sim/m68hc11/interp.c

   1 /* interp.c -- Simulator for Motorola 68HC11/68HC12
   2    Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #include "sim-main.h"
  22 #include "sim-assert.h"
  23 #include "sim-hw.h"
  24 #include "sim-options.h"
  25 #include "hw-tree.h"
  26 #include "hw-device.h"
  27 #include "hw-ports.h"
  28
  29 #ifndef MONITOR_BASE
  30 # define MONITOR_BASE (0x0C000)
  31 # define MONITOR_SIZE (0x04000)
  32 #endif
  33
  34 static void sim_get_info (SIM_DESC sd, char *cmd);
  35
  36
  37 char *interrupt_names[] = {
  38   "reset",
  39   "nmi",
  40   "int",
  41   NULL
  42 };
  43
  44 #ifndef INLINE
  45 #if defined(__GNUC__) && defined(__OPTIMIZE__)
  46 #define INLINE __inline__
  47 #else
  48 #define INLINE
  49 #endif
  50 #endif
  51
  52 struct sim_info_list
  53 {
  54   const char *name;
  55   const char *device;
  56 };
  57
  58 struct sim_info_list dev_list_68hc11[] = {
  59   {"cpu", "/m68hc11"},
  60   {"timer", "/m68hc11/m68hc11tim"},
  61   {"sio", "/m68hc11/m68hc11sio"},
  62   {"spi", "/m68hc11/m68hc11spi"},
  63   {"eeprom", "/m68hc11/m68hc11eepr"},
  64   {0, 0}
  65 };
  66
  67 struct sim_info_list dev_list_68hc12[] = {
  68   {"cpu", "/m68hc12"},
  69   {"timer", "/m68hc12/m68hc12tim"},
  70   {"sio", "/m68hc12/m68hc12sio"},
  71   {"spi", "/m68hc12/m68hc12spi"},
  72   {"eeprom", "/m68hc12/m68hc12eepr"},
  73   {0, 0}
  74 };
  75
  76 /* Cover function of sim_state_free to free the cpu buffers as well.  */
  77
  78 static void
  79 free_state (SIM_DESC sd)
  80 {
  81   if (STATE_MODULES (sd) != NULL)
  82     sim_module_uninstall (sd);
  83
  84   sim_state_free (sd);
  85 }
  86
  87 /* Give some information about the simulator.  */
  88 static void
  89 sim_get_info (SIM_DESC sd, char *cmd)
  90 {
  91   sim_cpu *cpu;
  92
  93   cpu = STATE_CPU (sd, 0);
  94   if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
  95     {
  96       int i;
  97       struct hw *hw_dev;
  98       struct sim_info_list *dev_list;
  99       const struct bfd_arch_info *arch;
 100
 101       arch = STATE_ARCHITECTURE (sd);
 102       cmd++;
 103
 104       if (arch->arch == bfd_arch_m68hc11)
 105         dev_list = dev_list_68hc11;
 106       else
 107         dev_list = dev_list_68hc12;
 108
 109       for (i = 0; dev_list[i].name; i++)
 110         if (strcmp (cmd, dev_list[i].name) == 0)
 111           break;
 112
 113       if (dev_list[i].name == 0)
 114         {
 115           sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
 116           sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
 117           return;
 118         }
 119       hw_dev = sim_hw_parse (sd, dev_list[i].device);
 120       if (hw_dev == 0)
 121         {
 122           sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
 123           return;
 124         }
 125       hw_ioctl (hw_dev, 23, 0);
 126       return;
 127     }
 128
 129   cpu_info (sd, cpu);
 130   interrupts_info (sd, &cpu->cpu_interrupts);
 131 }
 132
 133
 134 void
 135 sim_board_reset (SIM_DESC sd)
 136 {
 137   struct hw *hw_cpu;
 138   sim_cpu *cpu;
 139   const struct bfd_arch_info *arch;
 140   const char *cpu_type;
 141
 142   cpu = STATE_CPU (sd, 0);
 143   arch = STATE_ARCHITECTURE (sd);
 144
 145   /*  hw_cpu = sim_hw_parse (sd, "/"); */
 146   if (arch->arch == bfd_arch_m68hc11)
 147     {
 148       cpu->cpu_type = CPU_M6811;
 149       cpu_type = "/m68hc11";
 150     }
 151   else
 152     {
 153       cpu->cpu_type = CPU_M6812;
 154       cpu_type = "/m68hc12";
 155     }
 156
 157   hw_cpu = sim_hw_parse (sd, cpu_type);
 158   if (hw_cpu == 0)
 159     {
 160       sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
 161       return;
 162     }
 163
 164   cpu_reset (cpu);
 165   hw_port_event (hw_cpu, 3, 0);
 166   cpu_restart (cpu);
 167 }
 168
 169 int
 170 sim_hw_configure (SIM_DESC sd)
 171 {
 172   const struct bfd_arch_info *arch;
 173   struct hw *device_tree;
 174   sim_cpu *cpu;
 175
 176   arch = STATE_ARCHITECTURE (sd);
 177   if (arch == 0)
 178     return 0;
 179
 180   cpu = STATE_CPU (sd, 0);
 181   cpu->cpu_configured_arch = arch;
 182   device_tree = sim_hw_parse (sd, "/");
 183   if (arch->arch == bfd_arch_m68hc11)
 184     {
 185       cpu->cpu_interpretor = cpu_interp_m6811;
 186       if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
 187         {
 188           /* Allocate core managed memory */
 189
 190           /* the monitor  */
 191           sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
 192                            /* MONITOR_BASE, MONITOR_SIZE */
 193                            0x8000, M6811_RAM_LEVEL, 0x8000);
 194           sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
 195                            M6811_RAM_LEVEL);
 196           sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
 197         }
 198
 199       if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
 200         {
 201           sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
 202           sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
 203           sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
 204         }
 205       if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
 206         {
 207           /* M68hc11 Timer configuration. */
 208           sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
 209           sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
 210           sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
 211         }
 212
 213       /* Create the SPI device.  */
 214       if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
 215         {
 216           sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
 217           sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
 218         }
 219       if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
 220         {
 221           /* M68hc11 persistent ram configuration. */
 222           sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
 223           sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
 224           sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
 225           /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
 226         }
 227       if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
 228         {
 229           sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
 230           sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
 231         }
 232       sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
 233       sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
 234       sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
 235       sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
 236       cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
 237     }
 238   else
 239     {
 240       cpu->cpu_interpretor = cpu_interp_m6812;
 241       if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
 242         {
 243           /* Allocate core external memory.  */
 244           sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
 245                            0xC000, M6811_RAM_LEVEL, 0x4000);
 246           sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
 247                            M6811_RAM_LEVEL);
 248           sim_do_commandf (sd, "memory region 0x01000000@%d,0x100000",
 249                            M6811_RAM_LEVEL);
 250
 251           sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
 252           sim_hw_parse (sd, "/m68hc12/use_bank 1");
 253         }
 254
 255       if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
 256         {
 257           sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
 258           sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
 259           sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
 260         }
 261       if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
 262         {
 263           /* M68hc11 Timer configuration. */
 264           sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
 265           sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
 266           sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
 267         }
 268
 269       /* Create the SPI device.  */
 270       if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
 271         {
 272           sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
 273           sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
 274         }
 275       if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
 276         {
 277           /* M68hc11 persistent ram configuration. */
 278           sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
 279           sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
 280           sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
 281         }
 282       if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
 283         {
 284           sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
 285           sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
 286         }
 287
 288       sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
 289       sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
 290       sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
 291       sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
 292       cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
 293     }
 294   return 0;
 295 }
 296
 297 static int
 298 sim_prepare_for_program (SIM_DESC sd, struct _bfd* abfd)
 299 {
 300   sim_cpu *cpu;
 301
 302   cpu = STATE_CPU (sd, 0);
 303
 304   sim_hw_configure (sd);
 305   if (abfd != NULL)
 306     {
 307       cpu->cpu_elf_start = bfd_get_start_address (abfd);
 308     }
 309
 310   /* reset all state information */
 311   sim_board_reset (sd);
 312
 313   return SIM_RC_OK;
 314 }
 315
 316 SIM_DESC
 317 sim_open (SIM_OPEN_KIND kind, host_callback *callback,
 318           struct _bfd *abfd, char **argv)
 319 {
 320   SIM_DESC sd;
 321   sim_cpu *cpu;
 322
 323   sd = sim_state_alloc (kind, callback);
 324   cpu = STATE_CPU (sd, 0);
 325
 326   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 327
 328   /* for compatibility */
 329   current_alignment = NONSTRICT_ALIGNMENT;
 330   current_target_byte_order = BIG_ENDIAN;
 331
 332   cpu_initialize (sd, cpu);
 333
 334   cpu->cpu_use_elf_start = 1;
 335   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 336     {
 337       free_state (sd);
 338       return 0;
 339     }
 340
 341   /* getopt will print the error message so we just have to exit if this fails.
 342      FIXME: Hmmm...  in the case of gdb we need getopt to call
 343      print_filtered.  */
 344   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 345     {
 346       /* Uninstall the modules to avoid memory leaks,
 347          file descriptor leaks, etc.  */
 348       free_state (sd);
 349       return 0;
 350     }
 351
 352   /* Check for/establish the a reference program image.  */
 353   if (sim_analyze_program (sd,
 354                            (STATE_PROG_ARGV (sd) != NULL
 355                             ? *STATE_PROG_ARGV (sd)
 356                             : NULL), abfd) != SIM_RC_OK)
 357     {
 358       free_state (sd);
 359       return 0;
 360     }
 361
 362   /* Establish any remaining configuration options.  */
 363   if (sim_config (sd) != SIM_RC_OK)
 364     {
 365       free_state (sd);
 366       return 0;
 367     }
 368
 369   if (sim_post_argv_init (sd) != SIM_RC_OK)
 370     {
 371       /* Uninstall the modules to avoid memory leaks,
 372          file descriptor leaks, etc.  */
 373       free_state (sd);
 374       return 0;
 375     }
 376
 377   sim_hw_configure (sd);
 378
 379   /* Fudge our descriptor.  */
 380   return sd;
 381 }
 382
 383
 384 void
 385 sim_close (SIM_DESC sd, int quitting)
 386 {
 387   /* shut down modules */
 388   sim_module_uninstall (sd);
 389
 390   /* Ensure that any resources allocated through the callback
 391      mechanism are released: */
 392   sim_io_shutdown (sd);
 393
 394   /* FIXME - free SD */
 395   sim_state_free (sd);
 396   return;
 397 }
 398
 399 void
 400 sim_set_profile (int n)
 401 {
 402 }
 403
 404 void
 405 sim_set_profile_size (int n)
 406 {
 407 }
 408
 409 /* Generic implementation of sim_engine_run that works within the
 410    sim_engine setjmp/longjmp framework. */
 411
 412 void
 413 sim_engine_run (SIM_DESC sd,
 414                 int next_cpu_nr,        /* ignore */
 415                 int nr_cpus,    /* ignore */
 416                 int siggnal)    /* ignore */
 417 {
 418   sim_cpu *cpu;
 419
 420   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 421   cpu = STATE_CPU (sd, 0);
 422   while (1)
 423     {
 424       cpu_single_step (cpu);
 425
 426       /* process any events */
 427       if (sim_events_tickn (sd, cpu->cpu_current_cycle))
 428         {
 429           sim_events_process (sd);
 430         }
 431     }
 432 }
 433
 434 int
 435 sim_trace (SIM_DESC sd)
 436 {
 437   sim_resume (sd, 0, 0);
 438   return 1;
 439 }
 440
 441 void
 442 sim_info (SIM_DESC sd, int verbose)
 443 {
 444   const char *cpu_type;
 445   const struct bfd_arch_info *arch;
 446
 447   /* Nothing to do if there is no verbose flag set.  */
 448   if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
 449     return;
 450
 451   arch = STATE_ARCHITECTURE (sd);
 452   if (arch->arch == bfd_arch_m68hc11)
 453     cpu_type = "68HC11";
 454   else
 455     cpu_type = "68HC12";
 456
 457   sim_io_eprintf (sd, "Simulator info:\n");
 458   sim_io_eprintf (sd, "  CPU Motorola %s\n", cpu_type);
 459   sim_get_info (sd, 0);
 460   sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
 461 }
 462
 463 SIM_RC
 464 sim_create_inferior (SIM_DESC sd, struct _bfd *abfd,
 465                      char **argv, char **env)
 466 {
 467   return sim_prepare_for_program (sd, abfd);
 468 }
 469
 470
 471 void
 472 sim_set_callbacks (host_callback *p)
 473 {
 474   /*  m6811_callback = p; */
 475 }
 476
 477
 478 int
 479 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
 480 {
 481   sim_cpu *cpu;
 482   uint16 val;
 483   int size = 2;
 484
 485   cpu = STATE_CPU (sd, 0);
 486   switch (rn)
 487     {
 488     case A_REGNUM:
 489       val = cpu_get_a (cpu);
 490       size = 1;
 491       break;
 492
 493     case B_REGNUM:
 494       val = cpu_get_b (cpu);
 495       size = 1;
 496       break;
 497
 498     case D_REGNUM:
 499       val = cpu_get_d (cpu);
 500       break;
 501
 502     case X_REGNUM:
 503       val = cpu_get_x (cpu);
 504       break;
 505
 506     case Y_REGNUM:
 507       val = cpu_get_y (cpu);
 508       break;
 509
 510     case SP_REGNUM:
 511       val = cpu_get_sp (cpu);
 512       break;
 513
 514     case PC_REGNUM:
 515       val = cpu_get_pc (cpu);
 516       break;
 517
 518     case PSW_REGNUM:
 519       val = cpu_get_ccr (cpu);
 520       size = 1;
 521       break;
 522
 523     case PAGE_REGNUM:
 524       val = cpu_get_page (cpu);
 525       size = 1;
 526       break;
 527
 528     default:
 529       val = 0;
 530       break;
 531     }
 532   memory[0] = val >> 8;
 533   memory[1] = val & 0x0FF;
 534   return size;
 535 }
 536
 537 int
 538 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
 539 {
 540   uint16 val;
 541   sim_cpu *cpu;
 542
 543   cpu = STATE_CPU (sd, 0);
 544
 545   val = *memory++;
 546   if (length == 2)
 547     val = (val << 8) | *memory;
 548
 549   switch (rn)
 550     {
 551     case D_REGNUM:
 552       cpu_set_d (cpu, val);
 553       break;
 554
 555     case A_REGNUM:
 556       cpu_set_a (cpu, val);
 557       return 1;
 558
 559     case B_REGNUM:
 560       cpu_set_b (cpu, val);
 561       return 1;
 562
 563     case X_REGNUM:
 564       cpu_set_x (cpu, val);
 565       break;
 566
 567     case Y_REGNUM:
 568       cpu_set_y (cpu, val);
 569       break;
 570
 571     case SP_REGNUM:
 572       cpu_set_sp (cpu, val);
 573       break;
 574
 575     case PC_REGNUM:
 576       cpu_set_pc (cpu, val);
 577       break;
 578
 579     case PSW_REGNUM:
 580       cpu_set_ccr (cpu, val);
 581       return 1;
 582
 583     case PAGE_REGNUM:
 584       cpu_set_page (cpu, val);
 585       return 1;
 586
 587     default:
 588       break;
 589     }
 590
 591   return 2;
 592 }
 593
 594 void
 595 sim_size (int s)
 596 {
 597   ;
 598 }
 599
 600 void
 601 sim_do_command (SIM_DESC sd, char *cmd)
 602 {
 603   char *mm_cmd = "memory-map";
 604   char *int_cmd = "interrupt";
 605   sim_cpu *cpu;
 606
 607   cpu = STATE_CPU (sd, 0);
 608   /* Commands available from GDB:   */
 609   if (sim_args_command (sd, cmd) != SIM_RC_OK)
 610     {
 611       if (strncmp (cmd, "info", sizeof ("info") - 1) == 0)
 612         sim_get_info (sd, &cmd[4]);
 613       else if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
 614         sim_io_eprintf (sd,
 615                         "`memory-map' command replaced by `sim memory'\n");
 616       else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
 617         sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
 618       else
 619         sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
 620     }
 621
 622   /* If the architecture changed, re-configure.  */
 623   if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch)
 624     sim_hw_configure (sd);
 625 }
 626
 627 /* Halt the simulator after just one instruction */
 628
 629 static void
 630 has_stepped (SIM_DESC sd,
 631              void *data)
 632 {
 633   ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 634   sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP);
 635 }
 636
 637
 638 /* Generic resume - assumes the existance of sim_engine_run */
 639
 640 void
 641 sim_resume (SIM_DESC sd,
 642             int step,
 643             int siggnal)
 644 {
 645   sim_engine *engine = STATE_ENGINE (sd);
 646   jmp_buf buf;
 647   int jmpval;
 648
 649   ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 650
 651   /* we only want to be single stepping the simulator once */
 652   if (engine->stepper != NULL)
 653     {
 654       sim_events_deschedule (sd, engine->stepper);
 655       engine->stepper = NULL;
 656     }
 657   sim_module_resume (sd);
 658
 659   /* run/resume the simulator */
 660   engine->jmpbuf = &buf;
 661   jmpval = setjmp (buf);
 662   if (jmpval == sim_engine_start_jmpval
 663       || jmpval == sim_engine_restart_jmpval)
 664     {
 665       int last_cpu_nr = sim_engine_last_cpu_nr (sd);
 666       int next_cpu_nr = sim_engine_next_cpu_nr (sd);
 667       int nr_cpus = sim_engine_nr_cpus (sd);
 668
 669       sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus);
 670       if (next_cpu_nr >= nr_cpus)
 671         next_cpu_nr = 0;
 672
 673       /* Only deliver the siggnal ]sic] the first time through - don't
 674          re-deliver any siggnal during a restart. */
 675       if (jmpval == sim_engine_restart_jmpval)
 676         siggnal = 0;
 677
 678       /* Install the stepping event after having processed some
 679          pending events.  This is necessary for HC11/HC12 simulator
 680          because the tick counter is incremented by the number of cycles
 681          the instruction took.  Some pending ticks to process can still
 682          be recorded internally by the simulator and sim_events_preprocess
 683          will handle them.  If the stepping event is inserted before,
 684          these pending ticks will raise the event and the simulator will
 685          stop without having executed any instruction.  */
 686       if (step)
 687         engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd);
 688
 689 #ifdef SIM_CPU_EXCEPTION_RESUME
 690       {
 691         sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr);
 692         SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal);
 693       }
 694 #endif
 695
 696       sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal);
 697     }
 698   engine->jmpbuf = NULL;
 699
 700   sim_module_suspend (sd);
 701 }