sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2015 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #define SIM_HANDLES_LMA 1
  24
  25 #include "sim-basics.h"
  26 #include "sim-signal.h"
  27 #include "sim-base.h"
  28
  29 #include "bfd.h"
  30
  31 #include "opcode/m68hc11.h"
  32
  33 #include "gdb/callback.h"
  34 #include "gdb/remote-sim.h"
  35 #include "opcode/m68hc11.h"
  36 #include "sim-types.h"
  37
  38 typedef unsigned8 uint8;
  39 typedef unsigned16 uint16;
  40 typedef signed16 int16;
  41 typedef unsigned32 uint32;
  42 typedef signed32 int32;
  43 typedef unsigned64 uint64;
  44 typedef signed64 int64;
  45
  46 struct _sim_cpu;
  47
  48 #include "interrupts.h"
  49 #include <setjmp.h>
  50
  51 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  52    RAM.  IO registers are mapped over everything and the external RAM
  53    is last (ie, it can be hidden by everything above it in the list).  */
  54 enum m68hc11_map_level
  55 {
  56   M6811_IO_LEVEL,
  57   M6811_EEPROM_LEVEL,
  58   M6811_NVRAM_LEVEL,
  59   M6811_RAM_LEVEL
  60 };
  61
  62 enum cpu_type
  63 {
  64   CPU_M6811,
  65   CPU_M6812
  66 };
  67
  68 #define X_REGNUM        0
  69 #define D_REGNUM        1
  70 #define Y_REGNUM        2
  71 #define SP_REGNUM       3
  72 #define PC_REGNUM       4
  73 #define A_REGNUM        5
  74 #define B_REGNUM        6
  75 #define PSW_REGNUM      7
  76 #define PAGE_REGNUM     8
  77 #define Z_REGNUM        9
  78
  79 typedef struct m6811_regs {
  80     unsigned short      d;
  81     unsigned short      ix;
  82     unsigned short      iy;
  83     unsigned short      sp;
  84     unsigned short      pc;
  85     unsigned char       ccr;
  86   unsigned short      page;
  87 } m6811_regs;
  88
  89
  90 /* Description of 68HC11 IO registers.  Such description is only provided
  91    for the info command to display the current setting of IO registers
  92    from GDB.  */
  93 struct io_reg_desc
  94 {
  95   int        mask;
  96   const char *short_name;
  97   const char *long_name;
  98 };
  99 typedef struct io_reg_desc io_reg_desc;
 100
 101 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 102                                int mode);
 103 extern void print_io_byte (SIM_DESC sd, const char *name,
 104                            io_reg_desc *desc, uint8 val, uint16 addr);
 105 extern void print_io_word (SIM_DESC sd, const char *name,
 106                            io_reg_desc *desc, uint16 val, uint16 addr);
 107
 108
 109 /* List of special 68HC11&68HC12 instructions that are not handled by the
 110    'gencode.c' generator.  These complex instructions are implemented
 111    by 'cpu_special'.  */
 112 enum M6811_Special
 113 {
 114   /* 68HC11 instructions.  */
 115   M6811_DAA,
 116   M6811_EMUL_SYSCALL,
 117   M6811_ILLEGAL,
 118   M6811_RTI,
 119   M6811_STOP,
 120   M6811_SWI,
 121   M6811_TEST,
 122   M6811_WAI,
 123
 124   /* 68HC12 instructions.  */
 125   M6812_BGND,
 126   M6812_CALL,
 127   M6812_CALL_INDIRECT,
 128   M6812_IDIVS,
 129   M6812_EDIV,
 130   M6812_EDIVS,
 131   M6812_EMACS,
 132   M6812_EMUL,
 133   M6812_EMULS,
 134   M6812_ETBL,
 135   M6812_MEM,
 136   M6812_REV,
 137   M6812_REVW,
 138   M6812_RTC,
 139   M6812_RTI,
 140   M6812_WAV
 141 };
 142
 143 #define M6811_MAX_PORTS (0x03f+1)
 144 #define M6812_MAX_PORTS (0x3ff+1)
 145 #define MAX_PORTS       (M6812_MAX_PORTS)
 146
 147 struct _sim_cpu;
 148
 149 typedef void (* cpu_interp) (struct _sim_cpu*);
 150
 151 struct _sim_cpu {
 152   /* CPU registers.  */
 153   struct m6811_regs     cpu_regs;
 154
 155   /* CPU interrupts.  */
 156   struct interrupts     cpu_interrupts;
 157
 158   /* Pointer to the interpretor routine.  */
 159   cpu_interp            cpu_interpretor;
 160
 161   /* Pointer to the architecture currently configured in the simulator.  */
 162   const struct bfd_arch_info  *cpu_configured_arch;
 163
 164   /* CPU absolute cycle time.  The cycle time is updated after
 165      each instruction, by the number of cycles taken by the instruction.
 166      It is cleared only when reset occurs.  */
 167   signed64              cpu_absolute_cycle;
 168
 169   /* Number of cycles to increment after the current instruction.
 170      This is also the number of ticks for the generic event scheduler.  */
 171   uint8                 cpu_current_cycle;
 172   int                   cpu_emul_syscall;
 173   int                   cpu_is_initialized;
 174   int                   cpu_running;
 175   int                   cpu_check_memory;
 176   int                   cpu_stop_on_interrupt;
 177
 178   /* When this is set, start execution of program at address specified
 179      in the ELF header.  This is used for testing some programs that do not
 180      have an interrupt table linked with them.  Programs created during the
 181      GCC validation are like this. A normal 68HC11 does not behave like
 182      this (unless there is some OS or downloadable feature).  */
 183   int                   cpu_use_elf_start;
 184
 185   /* The starting address specified in ELF header.  */
 186   int                   cpu_elf_start;
 187
 188   uint16                cpu_insn_pc;
 189
 190   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 191      get the cycle time.  This is used for the timer rate and for the baud
 192      rate generation.  */
 193   unsigned long         cpu_frequency;
 194
 195   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 196   unsigned int          cpu_mode;
 197   const char*           cpu_start_mode;
 198
 199   /* The cpu being configured.  */
 200   enum cpu_type         cpu_type;
 201
 202   /* Initial value of the CONFIG register.  */
 203   uint8                 cpu_config;
 204   uint8                 cpu_use_local_config;
 205
 206   uint8                 ios[MAX_PORTS];
 207
 208   /* Memory bank parameters which describe how the memory bank window
 209      is mapped in memory and how to convert it in virtual address.  */
 210   uint16                bank_start;
 211   uint16                bank_end;
 212   address_word          bank_virtual;
 213   unsigned              bank_shift;
 214
 215
 216   struct hw            *hw_cpu;
 217
 218   /* ... base type ... */
 219   sim_cpu_base base;
 220 };
 221
 222 /* Returns the cpu absolute cycle time (A virtual counter incremented
 223    at each 68HC11 E clock).  */
 224 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
 225 #define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
 226 #define cpu_is_running(PROC)    ((PROC)->cpu_running)
 227
 228 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 229 #define cpu_get_io_base(PROC) \
 230         (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
 231 #define cpu_get_reg_base(PROC) \
 232         (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
 233
 234 /* Returns the different CPU registers.  */
 235 #define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
 236 #define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
 237 #define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
 238 #define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
 239 #define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
 240 #define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
 241 #define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
 242 #define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
 243 #define cpu_get_page(PROC)         ((PROC)->cpu_regs.page)
 244
 245 /* 68HC12 specific and Motorola internal registers.  */
 246 #define cpu_get_tmp3(PROC)         (0)
 247 #define cpu_get_tmp2(PROC)         (0)
 248
 249 #define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
 250 #define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
 251 #define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
 252 #define cpu_set_page(PROC,VAL)     (((PROC)->cpu_regs.page) = (VAL))
 253
 254 /* 68HC12 specific and Motorola internal registers.  */
 255 #define cpu_set_tmp3(PROC,VAL)     (0)
 256 #define cpu_set_tmp2(PROC,VAL)     (void) (0)
 257
 258 #if 0
 259 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 260 #define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
 261 #endif
 262
 263 #define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))
 264
 265 #define cpu_set_a(PROC,VAL)  \
 266       cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
 267 #define cpu_set_b(PROC,VAL)  \
 268       cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
 269
 270 #define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
 271 #define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
 272 #define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
 273 #define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
 274 #define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
 275 #define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
 276 #define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
 277 #define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
 278 #define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
 279
 280 #define cpu_set_ccr_flag(S,B,V) \
 281 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
 282
 283 #define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
 284 #define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
 285 #define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
 286 #define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
 287 #define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
 288 #define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
 289 #define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
 290 #define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
 291
 292 #undef inline
 293 #define inline static __inline__
 294
 295 extern void cpu_memory_exception (struct _sim_cpu *proc,
 296                                   SIM_SIGNAL excep,
 297                                   uint16 addr,
 298                                   const char *message);
 299
 300 inline address_word
 301 phys_to_virt (sim_cpu *cpu, address_word addr)
 302 {
 303   if (addr >= cpu->bank_start && addr < cpu->bank_end)
 304     return ((address_word) (addr - cpu->bank_start)
 305             + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
 306             + cpu->bank_virtual);
 307   else
 308     return (address_word) (addr);
 309 }
 310
 311 inline uint8
 312 memory_read8 (sim_cpu *cpu, uint16 addr)
 313 {
 314   uint8 val;
 315
 316   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 317     {
 318       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 319                             "Read error");
 320     }
 321   return val;
 322 }
 323
 324 inline void
 325 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 326 {
 327   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 328     {
 329       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 330                             "Write error");
 331     }
 332 }
 333
 334 inline uint16
 335 memory_read16 (sim_cpu *cpu, uint16 addr)
 336 {
 337   uint8 b[2];
 338
 339   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 340     {
 341       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 342                             "Read error");
 343     }
 344   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 345 }
 346
 347 inline void
 348 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 349 {
 350   uint8 b[2];
 351
 352   b[0] = val >> 8;
 353   b[1] = val;
 354   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 355     {
 356       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 357                             "Write error");
 358     }
 359 }
 360 extern void
 361 cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
 362
 363      inline void
 364 cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
 365 {
 366   cpu_set_ccr_V (proc, 0);
 367   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 368   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 369 }
 370
 371      inline void
 372 cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
 373 {
 374   cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
 375   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 376   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 377 }
 378
 379      inline void
 380 cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
 381 {
 382   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 383   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 384   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 385 }
 386
 387 inline void
 388 cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 389 {
 390   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 391   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 392   cpu_set_ccr_Z (proc, r == 0);
 393   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 394 }
 395
 396
 397 inline void
 398 cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 399 {
 400   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 401   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 402   cpu_set_ccr_Z (proc, r == 0);
 403   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 404 }
 405
 406 inline void
 407 cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 408 {
 409   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 410   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 411   cpu_set_ccr_Z (proc, r == 0);
 412   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 413 }
 414
 415 inline void
 416 cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 417 {
 418   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 419   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 420   cpu_set_ccr_Z (proc, r == 0);
 421   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 422 }
 423
 424 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 425 inline void
 426 cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
 427 {
 428   uint16 addr = proc->cpu_regs.sp;
 429
 430   memory_write8 (proc, addr, val);
 431   proc->cpu_regs.sp = addr - 1;
 432 }
 433
 434 inline void
 435 cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
 436 {
 437   uint16 addr = proc->cpu_regs.sp - 1;
 438
 439   memory_write16 (proc, addr, val);
 440   proc->cpu_regs.sp = addr - 1;
 441 }
 442
 443 inline uint8
 444 cpu_m68hc11_pop_uint8 (sim_cpu *proc)
 445 {
 446   uint16 addr = proc->cpu_regs.sp;
 447   uint8 val;
 448
 449   val = memory_read8 (proc, addr + 1);
 450   proc->cpu_regs.sp = addr + 1;
 451   return val;
 452 }
 453
 454 inline uint16
 455 cpu_m68hc11_pop_uint16 (sim_cpu *proc)
 456 {
 457   uint16 addr = proc->cpu_regs.sp;
 458   uint16 val;
 459
 460   val = memory_read16 (proc, addr + 1);
 461   proc->cpu_regs.sp = addr + 2;
 462   return val;
 463 }
 464
 465 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 466 inline void
 467 cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
 468 {
 469   uint16 addr = proc->cpu_regs.sp;
 470
 471   addr --;
 472   memory_write8 (proc, addr, val);
 473   proc->cpu_regs.sp = addr;
 474 }
 475
 476 inline void
 477 cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
 478 {
 479   uint16 addr = proc->cpu_regs.sp;
 480
 481   addr -= 2;
 482   memory_write16 (proc, addr, val);
 483   proc->cpu_regs.sp = addr;
 484 }
 485
 486 inline uint8
 487 cpu_m68hc12_pop_uint8 (sim_cpu *proc)
 488 {
 489   uint16 addr = proc->cpu_regs.sp;
 490   uint8 val;
 491
 492   val = memory_read8 (proc, addr);
 493   proc->cpu_regs.sp = addr + 1;
 494   return val;
 495 }
 496
 497 inline uint16
 498 cpu_m68hc12_pop_uint16 (sim_cpu *proc)
 499 {
 500   uint16 addr = proc->cpu_regs.sp;
 501   uint16 val;
 502
 503   val = memory_read16 (proc, addr);
 504   proc->cpu_regs.sp = addr + 2;
 505   return val;
 506 }
 507
 508 /* Fetch a 8/16 bit value and update the PC.  */
 509 inline uint8
 510 cpu_fetch8 (sim_cpu *proc)
 511 {
 512   uint16 addr = proc->cpu_regs.pc;
 513   uint8 val;
 514
 515   val = memory_read8 (proc, addr);
 516   proc->cpu_regs.pc = addr + 1;
 517   return val;
 518 }
 519
 520 inline uint16
 521 cpu_fetch16 (sim_cpu *proc)
 522 {
 523   uint16 addr = proc->cpu_regs.pc;
 524   uint16 val;
 525
 526   val = memory_read16 (proc, addr);
 527   proc->cpu_regs.pc = addr + 2;
 528   return val;
 529 }
 530
 531 extern void cpu_call (sim_cpu* proc, uint16 addr);
 532 extern void cpu_exg (sim_cpu* proc, uint8 code);
 533 extern void cpu_dbcc (sim_cpu* proc);
 534 extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
 535 extern void cpu_move8 (sim_cpu *proc, uint8 op);
 536 extern void cpu_move16 (sim_cpu *proc, uint8 op);
 537
 538 extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
 539 extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
 540 extern void cpu_push_all (sim_cpu *proc);
 541 extern void cpu_single_step (sim_cpu *proc);
 542
 543 extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
 544
 545 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 546
 547 /* Returns the address of a 68HC12 indexed operand.
 548    Pre and post modifications are handled on the source register.  */
 549 extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
 550
 551 extern void cpu_return (sim_cpu *cpu);
 552 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 553 extern int cpu_reset (sim_cpu *cpu);
 554 extern int cpu_restart (sim_cpu *cpu);
 555 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 556                               uint16 addr, const char *message, ...);
 557 extern void emul_os (int op, sim_cpu *cpu);
 558 extern void cpu_interp_m6811 (sim_cpu *cpu);
 559 extern void cpu_interp_m6812 (sim_cpu *cpu);
 560
 561 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 562                                       double ton, double toff,
 563                                       signed64 repeat);
 564 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 565 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 566                                  unsigned addr, uint8 val);
 567
 568 /* The current state of the processor; registers, memory, etc.  */
 569
 570 struct sim_state {
 571   sim_cpu        *cpu[MAX_NR_PROCESSORS];
 572   device         *devices;
 573   sim_state_base base;
 574 };
 575
 576 extern void sim_board_reset (SIM_DESC sd);
 577
 578 #define PRINT_TIME  0x01
 579 #define PRINT_CYCLE 0x02
 580 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
 581
 582 #endif
 583
 584