sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2021 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #define SIM_HAVE_COMMON_SIM_STATE
  24
  25 #include "sim-basics.h"
  26 #include "sim-signal.h"
  27 #include "sim-base.h"
  28
  29 #include "bfd.h"
  30
  31 #include "opcode/m68hc11.h"
  32
  33 #include "sim/callback.h"
  34 #include "sim/sim.h"
  35 #include "opcode/m68hc11.h"
  36 #include "sim-types.h"
  37
  38 typedef unsigned8 uint8;
  39 typedef unsigned16 uint16;
  40 typedef signed16 int16;
  41 typedef unsigned32 uint32;
  42 typedef signed32 int32;
  43 typedef unsigned64 uint64;
  44 typedef signed64 int64;
  45
  46 struct _sim_cpu;
  47
  48 #include "interrupts.h"
  49 #include <setjmp.h>
  50
  51 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  52    RAM.  IO registers are mapped over everything and the external RAM
  53    is last (ie, it can be hidden by everything above it in the list).  */
  54 enum m68hc11_map_level
  55 {
  56   M6811_IO_LEVEL,
  57   M6811_EEPROM_LEVEL,
  58   M6811_NVRAM_LEVEL,
  59   M6811_RAM_LEVEL
  60 };
  61
  62 enum cpu_type
  63 {
  64   CPU_M6811,
  65   CPU_M6812
  66 };
  67
  68 #define X_REGNUM        0
  69 #define D_REGNUM        1
  70 #define Y_REGNUM        2
  71 #define SP_REGNUM       3
  72 #define PC_REGNUM       4
  73 #define A_REGNUM        5
  74 #define B_REGNUM        6
  75 #define PSW_REGNUM      7
  76 #define PAGE_REGNUM     8
  77 #define Z_REGNUM        9
  78
  79 typedef struct m6811_regs {
  80     unsigned short      d;
  81     unsigned short      ix;
  82     unsigned short      iy;
  83     unsigned short      sp;
  84     unsigned short      pc;
  85     unsigned char       ccr;
  86   unsigned short      page;
  87 } m6811_regs;
  88
  89
  90 /* Description of 68HC11 IO registers.  Such description is only provided
  91    for the info command to display the current setting of IO registers
  92    from GDB.  */
  93 struct io_reg_desc
  94 {
  95   int        mask;
  96   const char *short_name;
  97   const char *long_name;
  98 };
  99 typedef struct io_reg_desc io_reg_desc;
 100
 101 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 102                                int mode);
 103 extern void print_io_byte (SIM_DESC sd, const char *name,
 104                            io_reg_desc *desc, uint8 val, uint16 addr);
 105 extern void print_io_word (SIM_DESC sd, const char *name,
 106                            io_reg_desc *desc, uint16 val, uint16 addr);
 107
 108
 109 /* List of special 68HC11&68HC12 instructions that are not handled by the
 110    'gencode.c' generator.  These complex instructions are implemented
 111    by 'cpu_special'.  */
 112 enum M6811_Special
 113 {
 114   /* 68HC11 instructions.  */
 115   M6811_DAA,
 116   M6811_EMUL_SYSCALL,
 117   M6811_ILLEGAL,
 118   M6811_RTI,
 119   M6811_STOP,
 120   M6811_SWI,
 121   M6811_TEST,
 122   M6811_WAI,
 123
 124   /* 68HC12 instructions.  */
 125   M6812_BGND,
 126   M6812_CALL,
 127   M6812_CALL_INDIRECT,
 128   M6812_IDIVS,
 129   M6812_EDIV,
 130   M6812_EDIVS,
 131   M6812_EMACS,
 132   M6812_EMUL,
 133   M6812_EMULS,
 134   M6812_ETBL,
 135   M6812_MEM,
 136   M6812_REV,
 137   M6812_REVW,
 138   M6812_RTC,
 139   M6812_RTI,
 140   M6812_WAV
 141 };
 142
 143 #define M6811_MAX_PORTS (0x03f+1)
 144 #define M6812_MAX_PORTS (0x3ff+1)
 145 #define MAX_PORTS       (M6812_MAX_PORTS)
 146
 147 struct _sim_cpu;
 148
 149 typedef void (* cpu_interp) (struct _sim_cpu*);
 150
 151 struct _sim_cpu {
 152   /* CPU registers.  */
 153   struct m6811_regs     cpu_regs;
 154
 155   /* CPU interrupts.  */
 156   struct interrupts     cpu_interrupts;
 157
 158   /* Pointer to the interpretor routine.  */
 159   cpu_interp            cpu_interpretor;
 160
 161   /* Pointer to the architecture currently configured in the simulator.  */
 162   const struct bfd_arch_info  *cpu_configured_arch;
 163
 164   /* CPU absolute cycle time.  The cycle time is updated after
 165      each instruction, by the number of cycles taken by the instruction.
 166      It is cleared only when reset occurs.  */
 167   signed64              cpu_absolute_cycle;
 168
 169   /* Number of cycles to increment after the current instruction.
 170      This is also the number of ticks for the generic event scheduler.  */
 171   uint8                 cpu_current_cycle;
 172   int                   cpu_emul_syscall;
 173   int                   cpu_is_initialized;
 174   int                   cpu_running;
 175   int                   cpu_check_memory;
 176   int                   cpu_stop_on_interrupt;
 177
 178   /* When this is set, start execution of program at address specified
 179      in the ELF header.  This is used for testing some programs that do not
 180      have an interrupt table linked with them.  Programs created during the
 181      GCC validation are like this. A normal 68HC11 does not behave like
 182      this (unless there is some OS or downloadable feature).  */
 183   int                   cpu_use_elf_start;
 184
 185   /* The starting address specified in ELF header.  */
 186   int                   cpu_elf_start;
 187
 188   uint16                cpu_insn_pc;
 189
 190   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 191      get the cycle time.  This is used for the timer rate and for the baud
 192      rate generation.  */
 193   unsigned long         cpu_frequency;
 194
 195   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 196   unsigned int          cpu_mode;
 197   const char*           cpu_start_mode;
 198
 199   /* The cpu being configured.  */
 200   enum cpu_type         cpu_type;
 201
 202   /* Initial value of the CONFIG register.  */
 203   uint8                 cpu_config;
 204   uint8                 cpu_use_local_config;
 205
 206   uint8                 ios[MAX_PORTS];
 207
 208   /* Memory bank parameters which describe how the memory bank window
 209      is mapped in memory and how to convert it in virtual address.  */
 210   uint16                bank_start;
 211   uint16                bank_end;
 212   address_word          bank_virtual;
 213   unsigned              bank_shift;
 214
 215
 216   struct hw            *hw_cpu;
 217
 218   /* ... base type ... */
 219   sim_cpu_base base;
 220 };
 221
 222 /* Returns the cpu absolute cycle time (A virtual counter incremented
 223    at each 68HC11 E clock).  */
 224 #define cpu_current_cycle(cpu)    ((cpu)->cpu_absolute_cycle)
 225 #define cpu_add_cycles(cpu, T)    ((cpu)->cpu_current_cycle += (signed64) (T))
 226 #define cpu_is_running(cpu)       ((cpu)->cpu_running)
 227
 228 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 229 #define cpu_get_io_base(cpu) \
 230   (((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
 231 #define cpu_get_reg_base(cpu) \
 232   (((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
 233
 234 /* Returns the different CPU registers.  */
 235 #define cpu_get_ccr(cpu)          ((cpu)->cpu_regs.ccr)
 236 #define cpu_get_pc(cpu)           ((cpu)->cpu_regs.pc)
 237 #define cpu_get_d(cpu)            ((cpu)->cpu_regs.d)
 238 #define cpu_get_x(cpu)            ((cpu)->cpu_regs.ix)
 239 #define cpu_get_y(cpu)            ((cpu)->cpu_regs.iy)
 240 #define cpu_get_sp(cpu)           ((cpu)->cpu_regs.sp)
 241 #define cpu_get_a(cpu)            (((cpu)->cpu_regs.d >> 8) & 0x0FF)
 242 #define cpu_get_b(cpu)            ((cpu)->cpu_regs.d & 0x0FF)
 243 #define cpu_get_page(cpu)         ((cpu)->cpu_regs.page)
 244
 245 /* 68HC12 specific and Motorola internal registers.  */
 246 #define cpu_get_tmp3(cpu)         (0)
 247 #define cpu_get_tmp2(cpu)         (0)
 248
 249 #define cpu_set_d(cpu, val)       ((cpu)->cpu_regs.d = (val))
 250 #define cpu_set_x(cpu, val)       ((cpu)->cpu_regs.ix = (val))
 251 #define cpu_set_y(cpu, val)       ((cpu)->cpu_regs.iy = (val))
 252 #define cpu_set_page(cpu, val)    ((cpu)->cpu_regs.page = (val))
 253
 254 /* 68HC12 specific and Motorola internal registers.  */
 255 #define cpu_set_tmp3(cpu, val)    (0)
 256 #define cpu_set_tmp2(cpu, val)    (void) (0)
 257
 258 #if 0
 259 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 260 #define cpu_set_sp(cpu, val)      ((cpu)->cpu_regs.sp = (val))
 261 #endif
 262
 263 #define cpu_set_pc(cpu, val)      ((cpu)->cpu_regs.pc = (val))
 264
 265 #define cpu_set_a(cpu, val)  \
 266   cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
 267 #define cpu_set_b(cpu, val)  \
 268   cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
 269
 270 #define cpu_set_ccr(cpu, val)     ((cpu)->cpu_regs.ccr = (val))
 271 #define cpu_get_ccr_H(cpu)        ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
 272 #define cpu_get_ccr_X(cpu)        ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
 273 #define cpu_get_ccr_S(cpu)        ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
 274 #define cpu_get_ccr_N(cpu)        ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
 275 #define cpu_get_ccr_V(cpu)        ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
 276 #define cpu_get_ccr_C(cpu)        ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
 277 #define cpu_get_ccr_Z(cpu)        ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
 278 #define cpu_get_ccr_I(cpu)        ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
 279
 280 #define cpu_set_ccr_flag(S, B, V) \
 281   cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
 282
 283 #define cpu_set_ccr_H(cpu, val)   cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
 284 #define cpu_set_ccr_X(cpu, val)   cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
 285 #define cpu_set_ccr_S(cpu, val)   cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
 286 #define cpu_set_ccr_N(cpu, val)   cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
 287 #define cpu_set_ccr_V(cpu, val)   cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
 288 #define cpu_set_ccr_C(cpu, val)   cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
 289 #define cpu_set_ccr_Z(cpu, val)   cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
 290 #define cpu_set_ccr_I(cpu, val)   cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
 291
 292 extern void cpu_memory_exception (sim_cpu *cpu,
 293                                   SIM_SIGNAL excep,
 294                                   uint16 addr,
 295                                   const char *message);
 296
 297 STATIC_INLINE address_word
 298 phys_to_virt (sim_cpu *cpu, address_word addr)
 299 {
 300   if (addr >= cpu->bank_start && addr < cpu->bank_end)
 301     return ((address_word) (addr - cpu->bank_start)
 302             + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
 303             + cpu->bank_virtual);
 304   else
 305     return (address_word) (addr);
 306 }
 307
 308 STATIC_INLINE uint8
 309 memory_read8 (sim_cpu *cpu, uint16 addr)
 310 {
 311   uint8 val;
 312
 313   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 314     {
 315       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 316                             "Read error");
 317     }
 318   return val;
 319 }
 320
 321 STATIC_INLINE void
 322 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 323 {
 324   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 325     {
 326       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 327                             "Write error");
 328     }
 329 }
 330
 331 STATIC_INLINE uint16
 332 memory_read16 (sim_cpu *cpu, uint16 addr)
 333 {
 334   uint8 b[2];
 335
 336   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 337     {
 338       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 339                             "Read error");
 340     }
 341   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 342 }
 343
 344 STATIC_INLINE void
 345 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 346 {
 347   uint8 b[2];
 348
 349   b[0] = val >> 8;
 350   b[1] = val;
 351   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 352     {
 353       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 354                             "Write error");
 355     }
 356 }
 357 extern void
 358 cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
 359
 360 STATIC_INLINE void
 361 cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
 362 {
 363   cpu_set_ccr_V (cpu, 0);
 364   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 365   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 366 }
 367
 368 STATIC_INLINE void
 369 cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
 370 {
 371   cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
 372   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 373   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 374 }
 375
 376 STATIC_INLINE void
 377 cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
 378 {
 379   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 380   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 381   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 382 }
 383
 384 STATIC_INLINE void
 385 cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 386 {
 387   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 388   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 389   cpu_set_ccr_Z (cpu, r == 0);
 390   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 391 }
 392
 393
 394 STATIC_INLINE void
 395 cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 396 {
 397   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 398   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 399   cpu_set_ccr_Z (cpu, r == 0);
 400   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 401 }
 402
 403 STATIC_INLINE void
 404 cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 405 {
 406   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 407   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 408   cpu_set_ccr_Z (cpu, r == 0);
 409   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 410 }
 411
 412 STATIC_INLINE void
 413 cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 414 {
 415   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 416   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 417   cpu_set_ccr_Z (cpu, r == 0);
 418   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 419 }
 420
 421 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 422 STATIC_INLINE void
 423 cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
 424 {
 425   uint16 addr = cpu->cpu_regs.sp;
 426
 427   memory_write8 (cpu, addr, val);
 428   cpu->cpu_regs.sp = addr - 1;
 429 }
 430
 431 STATIC_INLINE void
 432 cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
 433 {
 434   uint16 addr = cpu->cpu_regs.sp - 1;
 435
 436   memory_write16 (cpu, addr, val);
 437   cpu->cpu_regs.sp = addr - 1;
 438 }
 439
 440 STATIC_INLINE uint8
 441 cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
 442 {
 443   uint16 addr = cpu->cpu_regs.sp;
 444   uint8 val;
 445
 446   val = memory_read8 (cpu, addr + 1);
 447   cpu->cpu_regs.sp = addr + 1;
 448   return val;
 449 }
 450
 451 STATIC_INLINE uint16
 452 cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
 453 {
 454   uint16 addr = cpu->cpu_regs.sp;
 455   uint16 val;
 456
 457   val = memory_read16 (cpu, addr + 1);
 458   cpu->cpu_regs.sp = addr + 2;
 459   return val;
 460 }
 461
 462 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 463 STATIC_INLINE void
 464 cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
 465 {
 466   uint16 addr = cpu->cpu_regs.sp;
 467
 468   addr --;
 469   memory_write8 (cpu, addr, val);
 470   cpu->cpu_regs.sp = addr;
 471 }
 472
 473 STATIC_INLINE void
 474 cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
 475 {
 476   uint16 addr = cpu->cpu_regs.sp;
 477
 478   addr -= 2;
 479   memory_write16 (cpu, addr, val);
 480   cpu->cpu_regs.sp = addr;
 481 }
 482
 483 STATIC_INLINE uint8
 484 cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
 485 {
 486   uint16 addr = cpu->cpu_regs.sp;
 487   uint8 val;
 488
 489   val = memory_read8 (cpu, addr);
 490   cpu->cpu_regs.sp = addr + 1;
 491   return val;
 492 }
 493
 494 STATIC_INLINE uint16
 495 cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
 496 {
 497   uint16 addr = cpu->cpu_regs.sp;
 498   uint16 val;
 499
 500   val = memory_read16 (cpu, addr);
 501   cpu->cpu_regs.sp = addr + 2;
 502   return val;
 503 }
 504
 505 /* Fetch a 8/16 bit value and update the PC.  */
 506 STATIC_INLINE uint8
 507 cpu_fetch8 (sim_cpu *cpu)
 508 {
 509   uint16 addr = cpu->cpu_regs.pc;
 510   uint8 val;
 511
 512   val = memory_read8 (cpu, addr);
 513   cpu->cpu_regs.pc = addr + 1;
 514   return val;
 515 }
 516
 517 STATIC_INLINE uint16
 518 cpu_fetch16 (sim_cpu *cpu)
 519 {
 520   uint16 addr = cpu->cpu_regs.pc;
 521   uint16 val;
 522
 523   val = memory_read16 (cpu, addr);
 524   cpu->cpu_regs.pc = addr + 2;
 525   return val;
 526 }
 527
 528 extern void cpu_call (sim_cpu *cpu, uint16 addr);
 529 extern void cpu_exg (sim_cpu *cpu, uint8 code);
 530 extern void cpu_dbcc (sim_cpu *cpu);
 531 extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
 532 extern void cpu_move8 (sim_cpu *cpu, uint8 op);
 533 extern void cpu_move16 (sim_cpu *cpu, uint8 op);
 534
 535 extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
 536 extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
 537 extern void cpu_push_all (sim_cpu *cpu);
 538 extern void cpu_single_step (sim_cpu *cpu);
 539
 540 extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
 541
 542 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 543
 544 /* Returns the address of a 68HC12 indexed operand.
 545    Pre and post modifications are handled on the source register.  */
 546 extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
 547
 548 extern void cpu_return (sim_cpu *cpu);
 549 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 550 extern int cpu_reset (sim_cpu *cpu);
 551 extern int cpu_restart (sim_cpu *cpu);
 552 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 553                               uint16 addr, const char *message, ...);
 554 extern void emul_os (int op, sim_cpu *cpu);
 555 extern void cpu_interp_m6811 (sim_cpu *cpu);
 556 extern void cpu_interp_m6812 (sim_cpu *cpu);
 557
 558 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 559                                       double ton, double toff,
 560                                       signed64 repeat);
 561 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 562 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 563                                  unsigned addr, uint8 val);
 564
 565 extern void sim_board_reset (SIM_DESC sd);
 566
 567 #define PRINT_TIME  0x01
 568 #define PRINT_CYCLE 0x02
 569 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
 570
 571 #endif
 572
 573