1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2007
3 Free Software Foundation, Inc.
4 Written by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License along
19 with this program; if not, write to the Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #define WITH_MODULO_MEMORY 1
26 #define WITH_WATCHPOINTS 1
27 #define SIM_HANDLES_LMA 1
29 #include "sim-basics.h"
31 typedef address_word sim_cia
;
33 #include "sim-signal.h"
38 #include "opcode/m68hc11.h"
40 #include "gdb/callback.h"
41 #include "gdb/remote-sim.h"
42 #include "opcode/m68hc11.h"
43 #include "sim-types.h"
45 typedef unsigned8 uint8
;
46 typedef unsigned16 uint16
;
47 typedef signed16 int16
;
48 typedef unsigned32 uint32
;
49 typedef signed32 int32
;
50 typedef unsigned64 uint64
;
51 typedef signed64 int64
;
55 #include "interrupts.h"
58 /* Specifies the level of mapping for the IO, EEprom, nvram and external
59 RAM. IO registers are mapped over everything and the external RAM
60 is last (ie, it can be hidden by everything above it in the list). */
61 enum m68hc11_map_level
86 typedef struct m6811_regs
{
97 /* Description of 68HC11 IO registers. Such description is only provided
98 for the info command to display the current setting of IO registers
103 const char *short_name
;
104 const char *long_name
;
106 typedef struct io_reg_desc io_reg_desc
;
108 extern void print_io_reg_desc (SIM_DESC sd
, io_reg_desc
*desc
, int val
,
110 extern void print_io_byte (SIM_DESC sd
, const char *name
,
111 io_reg_desc
*desc
, uint8 val
, uint16 addr
);
112 extern void print_io_word (SIM_DESC sd
, const char *name
,
113 io_reg_desc
*desc
, uint16 val
, uint16 addr
);
116 /* List of special 68HC11&68HC12 instructions that are not handled by the
117 'gencode.c' generator. These complex instructions are implemented
121 /* 68HC11 instructions. */
131 /* 68HC12 instructions. */
150 #define M6811_MAX_PORTS (0x03f+1)
151 #define M6812_MAX_PORTS (0x3ff+1)
152 #define MAX_PORTS (M6812_MAX_PORTS)
156 typedef void (* cpu_interp
) (struct _sim_cpu
*);
160 struct m6811_regs cpu_regs
;
162 /* CPU interrupts. */
163 struct interrupts cpu_interrupts
;
165 /* Pointer to the interpretor routine. */
166 cpu_interp cpu_interpretor
;
168 /* Pointer to the architecture currently configured in the simulator. */
169 const struct bfd_arch_info
*cpu_configured_arch
;
171 /* CPU absolute cycle time. The cycle time is updated after
172 each instruction, by the number of cycles taken by the instruction.
173 It is cleared only when reset occurs. */
174 signed64 cpu_absolute_cycle
;
176 /* Number of cycles to increment after the current instruction.
177 This is also the number of ticks for the generic event scheduler. */
178 uint8 cpu_current_cycle
;
179 int cpu_emul_syscall
;
180 int cpu_is_initialized
;
182 int cpu_check_memory
;
183 int cpu_stop_on_interrupt
;
185 /* When this is set, start execution of program at address specified
186 in the ELF header. This is used for testing some programs that do not
187 have an interrupt table linked with them. Programs created during the
188 GCC validation are like this. A normal 68HC11 does not behave like
189 this (unless there is some OS or downloadable feature). */
190 int cpu_use_elf_start
;
192 /* The starting address specified in ELF header. */
197 /* CPU frequency. This is the quartz frequency. It is divided by 4 to
198 get the cycle time. This is used for the timer rate and for the baud
200 unsigned long cpu_frequency
;
202 /* The mode in which the CPU is configured (MODA and MODB pins). */
203 unsigned int cpu_mode
;
204 const char* cpu_start_mode
;
206 /* The cpu being configured. */
207 enum cpu_type cpu_type
;
209 /* Initial value of the CONFIG register. */
211 uint8 cpu_use_local_config
;
213 uint8 ios
[MAX_PORTS
];
215 /* Memory bank parameters which describe how the memory bank window
216 is mapped in memory and how to convert it in virtual address. */
219 address_word bank_virtual
;
225 /* ... base type ... */
229 /* Returns the cpu absolute cycle time (A virtual counter incremented
230 at each 68HC11 E clock). */
231 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
232 #define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
233 #define cpu_is_running(PROC) ((PROC)->cpu_running)
235 /* Get the IO/RAM base addresses depending on the M6811_INIT register. */
236 #define cpu_get_io_base(PROC) \
237 (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
238 #define cpu_get_reg_base(PROC) \
239 (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
241 /* Returns the different CPU registers. */
242 #define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
243 #define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
244 #define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
245 #define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
246 #define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
247 #define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
248 #define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
249 #define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
250 #define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
252 /* 68HC12 specific and Motorola internal registers. */
253 #define cpu_get_tmp3(PROC) (0)
254 #define cpu_get_tmp2(PROC) (0)
256 #define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
257 #define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
258 #define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
259 #define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
261 /* 68HC12 specific and Motorola internal registers. */
262 #define cpu_set_tmp3(PROC,VAL) (0)
263 #define cpu_set_tmp2(PROC,VAL) (void) (0)
266 /* This is a function in m68hc11_sim.c to keep track of the frame. */
267 #define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
270 #define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
272 #define cpu_set_a(PROC,VAL) \
273 cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
274 #define cpu_set_b(PROC,VAL) \
275 cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
277 #define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
278 #define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
279 #define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
280 #define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
281 #define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
282 #define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
283 #define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
284 #define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
285 #define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
287 #define cpu_set_ccr_flag(S,B,V) \
288 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
290 #define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
291 #define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
292 #define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
293 #define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
294 #define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
295 #define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
296 #define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
297 #define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
300 #define inline static __inline__
302 extern void cpu_memory_exception (struct _sim_cpu
*proc
,
305 const char *message
);
308 phys_to_virt (sim_cpu
*cpu
, address_word addr
)
310 if (addr
>= cpu
->bank_start
&& addr
< cpu
->bank_end
)
311 return ((address_word
) (addr
- cpu
->bank_start
)
312 + (((address_word
) cpu
->cpu_regs
.page
) << cpu
->bank_shift
)
313 + cpu
->bank_virtual
);
315 return (address_word
) (addr
);
319 memory_read8 (sim_cpu
*cpu
, uint16 addr
)
323 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
325 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
332 memory_write8 (sim_cpu
*cpu
, uint16 addr
, uint8 val
)
334 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
336 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
342 memory_read16 (sim_cpu
*cpu
, uint16 addr
)
346 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
348 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
351 return (((uint16
) (b
[0])) << 8) | ((uint16
) b
[1]);
355 memory_write16 (sim_cpu
*cpu
, uint16 addr
, uint16 val
)
361 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
363 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
368 cpu_ccr_update_tst8 (sim_cpu
*proc
, uint8 val
);
371 cpu_ccr_update_tst16 (sim_cpu
*proc
, uint16 val
)
373 cpu_set_ccr_V (proc
, 0);
374 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
375 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
379 cpu_ccr_update_shift8 (sim_cpu
*proc
, uint8 val
)
381 cpu_set_ccr_N (proc
, val
& 0x80 ? 1 : 0);
382 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
383 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
387 cpu_ccr_update_shift16 (sim_cpu
*proc
, uint16 val
)
389 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
390 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
391 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
395 cpu_ccr_update_add8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
397 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x80 ? 1 : 0);
398 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80 ? 1 : 0);
399 cpu_set_ccr_Z (proc
, r
== 0);
400 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
405 cpu_ccr_update_sub8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
407 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x80 ? 1 : 0);
408 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80 ? 1 : 0);
409 cpu_set_ccr_Z (proc
, r
== 0);
410 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
414 cpu_ccr_update_add16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
416 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x8000 ? 1 : 0);
417 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x8000 ? 1 : 0);
418 cpu_set_ccr_Z (proc
, r
== 0);
419 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
423 cpu_ccr_update_sub16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
425 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x8000 ? 1 : 0);
426 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x8000 ? 1 : 0);
427 cpu_set_ccr_Z (proc
, r
== 0);
428 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
431 /* Push and pop instructions for 68HC11 (next-available stack mode). */
433 cpu_m68hc11_push_uint8 (sim_cpu
*proc
, uint8 val
)
435 uint16 addr
= proc
->cpu_regs
.sp
;
437 memory_write8 (proc
, addr
, val
);
438 proc
->cpu_regs
.sp
= addr
- 1;
442 cpu_m68hc11_push_uint16 (sim_cpu
*proc
, uint16 val
)
444 uint16 addr
= proc
->cpu_regs
.sp
- 1;
446 memory_write16 (proc
, addr
, val
);
447 proc
->cpu_regs
.sp
= addr
- 1;
451 cpu_m68hc11_pop_uint8 (sim_cpu
*proc
)
453 uint16 addr
= proc
->cpu_regs
.sp
;
456 val
= memory_read8 (proc
, addr
+ 1);
457 proc
->cpu_regs
.sp
= addr
+ 1;
462 cpu_m68hc11_pop_uint16 (sim_cpu
*proc
)
464 uint16 addr
= proc
->cpu_regs
.sp
;
467 val
= memory_read16 (proc
, addr
+ 1);
468 proc
->cpu_regs
.sp
= addr
+ 2;
472 /* Push and pop instructions for 68HC12 (last-used stack mode). */
474 cpu_m68hc12_push_uint8 (sim_cpu
*proc
, uint8 val
)
476 uint16 addr
= proc
->cpu_regs
.sp
;
479 memory_write8 (proc
, addr
, val
);
480 proc
->cpu_regs
.sp
= addr
;
484 cpu_m68hc12_push_uint16 (sim_cpu
*proc
, uint16 val
)
486 uint16 addr
= proc
->cpu_regs
.sp
;
489 memory_write16 (proc
, addr
, val
);
490 proc
->cpu_regs
.sp
= addr
;
494 cpu_m68hc12_pop_uint8 (sim_cpu
*proc
)
496 uint16 addr
= proc
->cpu_regs
.sp
;
499 val
= memory_read8 (proc
, addr
);
500 proc
->cpu_regs
.sp
= addr
+ 1;
505 cpu_m68hc12_pop_uint16 (sim_cpu
*proc
)
507 uint16 addr
= proc
->cpu_regs
.sp
;
510 val
= memory_read16 (proc
, addr
);
511 proc
->cpu_regs
.sp
= addr
+ 2;
515 /* Fetch a 8/16 bit value and update the PC. */
517 cpu_fetch8 (sim_cpu
*proc
)
519 uint16 addr
= proc
->cpu_regs
.pc
;
522 val
= memory_read8 (proc
, addr
);
523 proc
->cpu_regs
.pc
= addr
+ 1;
528 cpu_fetch16 (sim_cpu
*proc
)
530 uint16 addr
= proc
->cpu_regs
.pc
;
533 val
= memory_read16 (proc
, addr
);
534 proc
->cpu_regs
.pc
= addr
+ 2;
538 extern void cpu_call (sim_cpu
* proc
, uint16 addr
);
539 extern void cpu_exg (sim_cpu
* proc
, uint8 code
);
540 extern void cpu_dbcc (sim_cpu
* proc
);
541 extern void cpu_special (sim_cpu
*proc
, enum M6811_Special special
);
542 extern void cpu_move8 (sim_cpu
*proc
, uint8 op
);
543 extern void cpu_move16 (sim_cpu
*proc
, uint8 op
);
545 extern uint16
cpu_fetch_relbranch (sim_cpu
*proc
);
546 extern uint16
cpu_fetch_relbranch16 (sim_cpu
*proc
);
547 extern void cpu_push_all (sim_cpu
*proc
);
548 extern void cpu_single_step (sim_cpu
*proc
);
550 extern void cpu_info (SIM_DESC sd
, sim_cpu
*proc
);
552 extern int cpu_initialize (SIM_DESC sd
, sim_cpu
*cpu
);
554 /* Returns the address of a 68HC12 indexed operand.
555 Pre and post modifications are handled on the source register. */
556 extern uint16
cpu_get_indexed_operand_addr (sim_cpu
* cpu
, int restrict
);
558 extern void cpu_return (sim_cpu
*cpu
);
559 extern void cpu_set_sp (sim_cpu
*cpu
, uint16 val
);
560 extern int cpu_reset (sim_cpu
*cpu
);
561 extern int cpu_restart (sim_cpu
*cpu
);
562 extern void sim_memory_error (sim_cpu
*cpu
, SIM_SIGNAL excep
,
563 uint16 addr
, const char *message
, ...);
564 extern void emul_os (int op
, sim_cpu
*cpu
);
565 extern void cpu_interp_m6811 (sim_cpu
*cpu
);
566 extern void cpu_interp_m6812 (sim_cpu
*cpu
);
568 extern int m68hc11cpu_set_oscillator (SIM_DESC sd
, const char *port
,
569 double ton
, double toff
,
571 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd
, const char *port
);
572 extern void m68hc11cpu_set_port (struct hw
*me
, sim_cpu
*cpu
,
573 unsigned addr
, uint8 val
);
575 /* The current state of the processor; registers, memory, etc. */
577 #define CIA_GET(CPU) (cpu_get_pc (CPU))
578 #define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL)))
581 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
583 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
587 sim_cpu cpu
[MAX_NR_PROCESSORS
];
592 extern void sim_set_profile (int n
);
593 extern void sim_set_profile_size (int n
);
594 extern void sim_board_reset (SIM_DESC sd
);
596 #define PRINT_TIME 0x01
597 #define PRINT_CYCLE 0x02
598 extern const char *cycle_to_string (sim_cpu
*cpu
, signed64 t
, int flags
);