sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2022 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #include "sim-basics.h"
  24 #include "sim-base.h"
  25
  26 #include "bfd.h"
  27
  28 #include "opcode/m68hc11.h"
  29
  30 #include "sim/sim.h"
  31 #include "opcode/m68hc11.h"
  32 #include "sim-signal.h"
  33 #include "sim-types.h"
  34
  35 #include "interrupts.h"
  36 #include <setjmp.h>
  37
  38 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  39    RAM.  IO registers are mapped over everything and the external RAM
  40    is last (ie, it can be hidden by everything above it in the list).  */
  41 enum m68hc11_map_level
  42 {
  43   M6811_IO_LEVEL,
  44   M6811_EEPROM_LEVEL,
  45   M6811_NVRAM_LEVEL,
  46   M6811_RAM_LEVEL
  47 };
  48
  49 enum cpu_type
  50 {
  51   CPU_M6811,
  52   CPU_M6812
  53 };
  54
  55 #define X_REGNUM        0
  56 #define D_REGNUM        1
  57 #define Y_REGNUM        2
  58 #define SP_REGNUM       3
  59 #define PC_REGNUM       4
  60 #define A_REGNUM        5
  61 #define B_REGNUM        6
  62 #define PSW_REGNUM      7
  63 #define PAGE_REGNUM     8
  64 #define Z_REGNUM        9
  65
  66 typedef struct m6811_regs {
  67     unsigned short      d;
  68     unsigned short      ix;
  69     unsigned short      iy;
  70     unsigned short      sp;
  71     unsigned short      pc;
  72     unsigned char       ccr;
  73   unsigned short      page;
  74 } m6811_regs;
  75
  76
  77 /* Description of 68HC11 IO registers.  Such description is only provided
  78    for the info command to display the current setting of IO registers
  79    from GDB.  */
  80 struct io_reg_desc
  81 {
  82   int        mask;
  83   const char *short_name;
  84   const char *long_name;
  85 };
  86 typedef struct io_reg_desc io_reg_desc;
  87
  88 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
  89                                int mode);
  90 extern void print_io_byte (SIM_DESC sd, const char *name,
  91                            io_reg_desc *desc, uint8_t val, uint16_t addr);
  92 extern void print_io_word (SIM_DESC sd, const char *name,
  93                            io_reg_desc *desc, uint16_t val, uint16_t addr);
  94
  95
  96 /* List of special 68HC11&68HC12 instructions that are not handled by the
  97    'gencode.c' generator.  These complex instructions are implemented
  98    by 'cpu_special'.  */
  99 enum M6811_Special
 100 {
 101   /* 68HC11 instructions.  */
 102   M6811_DAA,
 103   M6811_EMUL_SYSCALL,
 104   M6811_ILLEGAL,
 105   M6811_RTI,
 106   M6811_STOP,
 107   M6811_SWI,
 108   M6811_TEST,
 109   M6811_WAI,
 110
 111   /* 68HC12 instructions.  */
 112   M6812_BGND,
 113   M6812_CALL,
 114   M6812_CALL_INDIRECT,
 115   M6812_IDIVS,
 116   M6812_EDIV,
 117   M6812_EDIVS,
 118   M6812_EMACS,
 119   M6812_EMUL,
 120   M6812_EMULS,
 121   M6812_ETBL,
 122   M6812_MEM,
 123   M6812_REV,
 124   M6812_REVW,
 125   M6812_RTC,
 126   M6812_RTI,
 127   M6812_WAV
 128 };
 129
 130 #define M6811_MAX_PORTS (0x03f+1)
 131 #define M6812_MAX_PORTS (0x3ff+1)
 132 #define MAX_PORTS       (M6812_MAX_PORTS)
 133
 134 typedef void (* cpu_interp) (sim_cpu *);
 135
 136 struct m68hc11_sim_cpu {
 137   /* CPU registers.  */
 138   struct m6811_regs     cpu_regs;
 139
 140   /* CPU interrupts.  */
 141   struct interrupts     cpu_interrupts;
 142
 143   /* Pointer to the interpretor routine.  */
 144   cpu_interp            cpu_interpretor;
 145
 146   /* Pointer to the architecture currently configured in the simulator.  */
 147   const struct bfd_arch_info  *cpu_configured_arch;
 148
 149   /* CPU absolute cycle time.  The cycle time is updated after
 150      each instruction, by the number of cycles taken by the instruction.
 151      It is cleared only when reset occurs.  */
 152   int64_t              cpu_absolute_cycle;
 153
 154   /* Number of cycles to increment after the current instruction.
 155      This is also the number of ticks for the generic event scheduler.  */
 156   uint8_t                 cpu_current_cycle;
 157   int                   cpu_emul_syscall;
 158   int                   cpu_is_initialized;
 159   int                   cpu_running;
 160   int                   cpu_check_memory;
 161   int                   cpu_stop_on_interrupt;
 162
 163   /* When this is set, start execution of program at address specified
 164      in the ELF header.  This is used for testing some programs that do not
 165      have an interrupt table linked with them.  Programs created during the
 166      GCC validation are like this. A normal 68HC11 does not behave like
 167      this (unless there is some OS or downloadable feature).  */
 168   int                   cpu_use_elf_start;
 169
 170   /* The starting address specified in ELF header.  */
 171   int                   cpu_elf_start;
 172
 173   uint16_t                cpu_insn_pc;
 174
 175   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 176      get the cycle time.  This is used for the timer rate and for the baud
 177      rate generation.  */
 178   unsigned long         cpu_frequency;
 179
 180   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 181   unsigned int          cpu_mode;
 182   const char*           cpu_start_mode;
 183
 184   /* The cpu being configured.  */
 185   enum cpu_type         cpu_type;
 186
 187   /* Initial value of the CONFIG register.  */
 188   uint8_t                 cpu_config;
 189   uint8_t                 cpu_use_local_config;
 190
 191   uint8_t                 ios[MAX_PORTS];
 192
 193   /* Memory bank parameters which describe how the memory bank window
 194      is mapped in memory and how to convert it in virtual address.  */
 195   uint16_t                bank_start;
 196   uint16_t                bank_end;
 197   address_word          bank_virtual;
 198   unsigned              bank_shift;
 199
 200
 201   struct hw            *hw_cpu;
 202 };
 203 #define M68HC11_SIM_CPU(cpu) ((struct m68hc11_sim_cpu *) CPU_ARCH_DATA (cpu))
 204
 205 /* Returns the cpu absolute cycle time (A virtual counter incremented
 206    at each 68HC11 E clock).  */
 207 #define cpu_current_cycle(cpu)    (M68HC11_SIM_CPU (cpu)->cpu_absolute_cycle)
 208 #define cpu_add_cycles(cpu, T)    (M68HC11_SIM_CPU (cpu)->cpu_current_cycle += (int64_t) (T))
 209 #define cpu_is_running(cpu)       (M68HC11_SIM_CPU (cpu)->cpu_running)
 210
 211 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 212 #define cpu_get_io_base(cpu) \
 213   (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
 214 #define cpu_get_reg_base(cpu) \
 215   (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
 216
 217 /* Returns the different CPU registers.  */
 218 #define cpu_get_ccr(cpu)          (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr)
 219 #define cpu_get_pc(cpu)           (M68HC11_SIM_CPU (cpu)->cpu_regs.pc)
 220 #define cpu_get_d(cpu)            (M68HC11_SIM_CPU (cpu)->cpu_regs.d)
 221 #define cpu_get_x(cpu)            (M68HC11_SIM_CPU (cpu)->cpu_regs.ix)
 222 #define cpu_get_y(cpu)            (M68HC11_SIM_CPU (cpu)->cpu_regs.iy)
 223 #define cpu_get_sp(cpu)           (M68HC11_SIM_CPU (cpu)->cpu_regs.sp)
 224 #define cpu_get_a(cpu)            ((M68HC11_SIM_CPU (cpu)->cpu_regs.d >> 8) & 0x0FF)
 225 #define cpu_get_b(cpu)            (M68HC11_SIM_CPU (cpu)->cpu_regs.d & 0x0FF)
 226 #define cpu_get_page(cpu)         (M68HC11_SIM_CPU (cpu)->cpu_regs.page)
 227
 228 /* 68HC12 specific and Motorola internal registers.  */
 229 #define cpu_get_tmp3(cpu)         (0)
 230 #define cpu_get_tmp2(cpu)         (0)
 231
 232 #define cpu_set_d(cpu, val)       (M68HC11_SIM_CPU (cpu)->cpu_regs.d = (val))
 233 #define cpu_set_x(cpu, val)       (M68HC11_SIM_CPU (cpu)->cpu_regs.ix = (val))
 234 #define cpu_set_y(cpu, val)       (M68HC11_SIM_CPU (cpu)->cpu_regs.iy = (val))
 235 #define cpu_set_page(cpu, val)    (M68HC11_SIM_CPU (cpu)->cpu_regs.page = (val))
 236
 237 /* 68HC12 specific and Motorola internal registers.  */
 238 #define cpu_set_tmp3(cpu, val)    (0)
 239 #define cpu_set_tmp2(cpu, val)    (void) (0)
 240
 241 #if 0
 242 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 243 #define cpu_set_sp(cpu, val)      (M68HC11_SIM_CPU (cpu)->cpu_regs.sp = (val))
 244 #endif
 245
 246 #define cpu_set_pc(cpu, val)      (M68HC11_SIM_CPU (cpu)->cpu_regs.pc = (val))
 247
 248 #define cpu_set_a(cpu, val)  \
 249   cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
 250 #define cpu_set_b(cpu, val)  \
 251   cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
 252
 253 #define cpu_set_ccr(cpu, val)     (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr = (val))
 254 #define cpu_get_ccr_H(cpu)        ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
 255 #define cpu_get_ccr_X(cpu)        ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
 256 #define cpu_get_ccr_S(cpu)        ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
 257 #define cpu_get_ccr_N(cpu)        ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
 258 #define cpu_get_ccr_V(cpu)        ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
 259 #define cpu_get_ccr_C(cpu)        ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
 260 #define cpu_get_ccr_Z(cpu)        ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
 261 #define cpu_get_ccr_I(cpu)        ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
 262
 263 #define cpu_set_ccr_flag(S, B, V) \
 264   cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
 265
 266 #define cpu_set_ccr_H(cpu, val)   cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
 267 #define cpu_set_ccr_X(cpu, val)   cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
 268 #define cpu_set_ccr_S(cpu, val)   cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
 269 #define cpu_set_ccr_N(cpu, val)   cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
 270 #define cpu_set_ccr_V(cpu, val)   cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
 271 #define cpu_set_ccr_C(cpu, val)   cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
 272 #define cpu_set_ccr_Z(cpu, val)   cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
 273 #define cpu_set_ccr_I(cpu, val)   cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
 274
 275 extern void cpu_memory_exception (sim_cpu *cpu,
 276                                   SIM_SIGNAL excep,
 277                                   uint16_t addr,
 278                                   const char *message);
 279
 280 STATIC_INLINE UNUSED address_word
 281 phys_to_virt (sim_cpu *cpu, address_word addr)
 282 {
 283   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 284
 285   if (addr >= m68hc11_cpu->bank_start && addr < m68hc11_cpu->bank_end)
 286     return ((address_word) (addr - m68hc11_cpu->bank_start)
 287             + (((address_word) m68hc11_cpu->cpu_regs.page) << m68hc11_cpu->bank_shift)
 288             + m68hc11_cpu->bank_virtual);
 289   else
 290     return (address_word) (addr);
 291 }
 292
 293 STATIC_INLINE UNUSED uint8_t
 294 memory_read8 (sim_cpu *cpu, uint16_t addr)
 295 {
 296   uint8_t val;
 297
 298   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 299     {
 300       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 301                             "Read error");
 302     }
 303   return val;
 304 }
 305
 306 STATIC_INLINE UNUSED void
 307 memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val)
 308 {
 309   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 310     {
 311       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 312                             "Write error");
 313     }
 314 }
 315
 316 STATIC_INLINE UNUSED uint16_t
 317 memory_read16 (sim_cpu *cpu, uint16_t addr)
 318 {
 319   uint8_t b[2];
 320
 321   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 322     {
 323       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 324                             "Read error");
 325     }
 326   return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]);
 327 }
 328
 329 STATIC_INLINE UNUSED void
 330 memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val)
 331 {
 332   uint8_t b[2];
 333
 334   b[0] = val >> 8;
 335   b[1] = val;
 336   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 337     {
 338       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 339                             "Write error");
 340     }
 341 }
 342 extern void
 343 cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val);
 344
 345 STATIC_INLINE UNUSED void
 346 cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val)
 347 {
 348   cpu_set_ccr_V (cpu, 0);
 349   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 350   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 351 }
 352
 353 STATIC_INLINE UNUSED void
 354 cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val)
 355 {
 356   cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
 357   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 358   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 359 }
 360
 361 STATIC_INLINE UNUSED void
 362 cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val)
 363 {
 364   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 365   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 366   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 367 }
 368
 369 STATIC_INLINE UNUSED void
 370 cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
 371 {
 372   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 373   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 374   cpu_set_ccr_Z (cpu, r == 0);
 375   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 376 }
 377
 378
 379 STATIC_INLINE UNUSED void
 380 cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
 381 {
 382   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 383   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 384   cpu_set_ccr_Z (cpu, r == 0);
 385   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 386 }
 387
 388 STATIC_INLINE UNUSED void
 389 cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
 390 {
 391   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 392   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 393   cpu_set_ccr_Z (cpu, r == 0);
 394   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 395 }
 396
 397 STATIC_INLINE UNUSED void
 398 cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
 399 {
 400   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 401   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 402   cpu_set_ccr_Z (cpu, r == 0);
 403   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 404 }
 405
 406 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 407 STATIC_INLINE UNUSED void
 408 cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val)
 409 {
 410   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 411   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 412
 413   memory_write8 (cpu, addr, val);
 414   m68hc11_cpu->cpu_regs.sp = addr - 1;
 415 }
 416
 417 STATIC_INLINE UNUSED void
 418 cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val)
 419 {
 420   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 421   uint16_t addr = m68hc11_cpu->cpu_regs.sp - 1;
 422
 423   memory_write16 (cpu, addr, val);
 424   m68hc11_cpu->cpu_regs.sp = addr - 1;
 425 }
 426
 427 STATIC_INLINE UNUSED uint8_t
 428 cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
 429 {
 430   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 431   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 432   uint8_t val;
 433
 434   val = memory_read8 (cpu, addr + 1);
 435   m68hc11_cpu->cpu_regs.sp = addr + 1;
 436   return val;
 437 }
 438
 439 STATIC_INLINE UNUSED uint16_t
 440 cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
 441 {
 442   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 443   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 444   uint16_t val;
 445
 446   val = memory_read16 (cpu, addr + 1);
 447   m68hc11_cpu->cpu_regs.sp = addr + 2;
 448   return val;
 449 }
 450
 451 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 452 STATIC_INLINE UNUSED void
 453 cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val)
 454 {
 455   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 456   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 457
 458   addr --;
 459   memory_write8 (cpu, addr, val);
 460   m68hc11_cpu->cpu_regs.sp = addr;
 461 }
 462
 463 STATIC_INLINE UNUSED void
 464 cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val)
 465 {
 466   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 467   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 468
 469   addr -= 2;
 470   memory_write16 (cpu, addr, val);
 471   m68hc11_cpu->cpu_regs.sp = addr;
 472 }
 473
 474 STATIC_INLINE UNUSED uint8_t
 475 cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
 476 {
 477   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 478   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 479   uint8_t val;
 480
 481   val = memory_read8 (cpu, addr);
 482   m68hc11_cpu->cpu_regs.sp = addr + 1;
 483   return val;
 484 }
 485
 486 STATIC_INLINE UNUSED uint16_t
 487 cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
 488 {
 489   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 490   uint16_t addr = m68hc11_cpu->cpu_regs.sp;
 491   uint16_t val;
 492
 493   val = memory_read16 (cpu, addr);
 494   m68hc11_cpu->cpu_regs.sp = addr + 2;
 495   return val;
 496 }
 497
 498 /* Fetch a 8/16 bit value and update the PC.  */
 499 STATIC_INLINE UNUSED uint8_t
 500 cpu_fetch8 (sim_cpu *cpu)
 501 {
 502   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 503   uint16_t addr = m68hc11_cpu->cpu_regs.pc;
 504   uint8_t val;
 505
 506   val = memory_read8 (cpu, addr);
 507   m68hc11_cpu->cpu_regs.pc = addr + 1;
 508   return val;
 509 }
 510
 511 STATIC_INLINE UNUSED uint16_t
 512 cpu_fetch16 (sim_cpu *cpu)
 513 {
 514   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 515   uint16_t addr = m68hc11_cpu->cpu_regs.pc;
 516   uint16_t val;
 517
 518   val = memory_read16 (cpu, addr);
 519   m68hc11_cpu->cpu_regs.pc = addr + 2;
 520   return val;
 521 }
 522
 523 extern void cpu_call (sim_cpu *cpu, uint16_t addr);
 524 extern void cpu_exg (sim_cpu *cpu, uint8_t code);
 525 extern void cpu_dbcc (sim_cpu *cpu);
 526 extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
 527 extern void cpu_move8 (sim_cpu *cpu, uint8_t op);
 528 extern void cpu_move16 (sim_cpu *cpu, uint8_t op);
 529
 530 extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu);
 531 extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu);
 532 extern void cpu_push_all (sim_cpu *cpu);
 533 extern void cpu_single_step (sim_cpu *cpu);
 534
 535 extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
 536
 537 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 538
 539 /* Returns the address of a 68HC12 indexed operand.
 540    Pre and post modifications are handled on the source register.  */
 541 extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
 542
 543 extern void cpu_return (sim_cpu *cpu);
 544 extern void cpu_set_sp (sim_cpu *cpu, uint16_t val);
 545 extern int cpu_reset (sim_cpu *cpu);
 546 extern int cpu_restart (sim_cpu *cpu);
 547 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 548                               uint16_t addr, const char *message, ...)
 549   ATTRIBUTE_PRINTF (4, 5);
 550 extern void emul_os (int op, sim_cpu *cpu);
 551 extern void cpu_interp_m6811 (sim_cpu *cpu);
 552 extern void cpu_interp_m6812 (sim_cpu *cpu);
 553
 554 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 555                                       double ton, double toff,
 556                                       int64_t repeat);
 557 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 558 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 559                                  unsigned addr, uint8_t val);
 560
 561 extern void sim_board_reset (SIM_DESC sd);
 562
 563 #define PRINT_TIME  0x01
 564 #define PRINT_CYCLE 0x02
 565 extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags);
 566
 567 #endif
 568
 569