sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11
   2    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@worldnet.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef _SIM_MAIN_H
  22 #define _SIM_MAIN_H
  23
  24 #define WITH_MODULO_MEMORY 1
  25 #define WITH_WATCHPOINTS 1
  26 #define SIM_HANDLES_LMA 1
  27
  28 #include "sim-basics.h"
  29
  30 typedef address_word sim_cia;
  31
  32 #include "sim-signal.h"
  33 #include "sim-base.h"
  34
  35 #include "bfd.h"
  36
  37 #include "opcode/m68hc11.h"
  38
  39 #include "callback.h"
  40 #include "remote-sim.h"
  41 #include "opcode/m68hc11.h"
  42 #include "sim-types.h"
  43
  44 typedef unsigned8 uint8;
  45 typedef unsigned16 uint16;
  46 typedef signed16 int16;
  47 typedef unsigned32 uint32;
  48 typedef signed32 int32;
  49 typedef unsigned64 uint64;
  50 typedef signed64 int64;
  51
  52 struct _sim_cpu;
  53
  54 #include "interrupts.h"
  55 #include <setjmp.h>
  56
  57 #define X_REGNUM        0
  58 #define D_REGNUM        1
  59 #define Y_REGNUM        2
  60 #define SP_REGNUM       3
  61 #define PC_REGNUM       4
  62 #define A_REGNUM        5
  63 #define B_REGNUM        6
  64 #define PSW_REGNUM      7
  65 #define Z_REGNUM        8
  66 #define FP_REGNUM       9
  67 #define TMP_REGNUM     10
  68 #define ZS_REGNUM      11
  69 #define XY_REGNUM      12
  70 #define ZD1_REGNUM     13
  71 #define ZD32_REGNUM    (ZD1_REGNUM+31)
  72
  73 #define FIRST_SOFT_REGNUM (Z_REGNUM)
  74 #define MAX_SOFT_REG      (ZD32_REGNUM - Z_REGNUM + 1)
  75
  76 typedef struct m6811_regs {
  77     unsigned short      d;
  78     unsigned short      ix;
  79     unsigned short      iy;
  80     unsigned short      sp;
  81     unsigned short      pc;
  82     unsigned char       ccr;
  83 } m6811_regs;
  84
  85
  86 /* Description of 68HC11 IO registers.  Such description is only provided
  87    for the info command to display the current setting of IO registers
  88    from GDB.  */
  89 struct io_reg_desc
  90 {
  91   int        mask;
  92   const char *short_name;
  93   const char *long_name;
  94 };
  95 typedef struct io_reg_desc io_reg_desc;
  96
  97 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
  98                                int mode);
  99 extern void print_io_byte (SIM_DESC sd, const char *name,
 100                            io_reg_desc *desc, uint8 val, uint16 addr);
 101
 102
 103 /* List of special 68HC11 instructions that are not handled by the
 104    'gencode.c' generator.  These complex instructions are implemented
 105    by 'cpu_special'.  */
 106 enum M6811_Special
 107 {
 108   M6811_RTI,
 109   M6811_WAI,
 110   M6811_SWI,
 111   M6811_TEST,
 112   M6811_ILLEGAL,
 113   M6811_EMUL_SYSCALL
 114 };
 115
 116 #define CPU_POP 1
 117 #define CPU_PUSH 2
 118
 119 #define MAX_PORTS 0x40
 120
 121 /* Tentative to keep track of the stack frame.
 122    The frame is updated each time a call or a return are made.
 123    We also have to take into account changes of stack pointer
 124    (either thread switch or longjmp).  */
 125 struct cpu_frame
 126 {
 127   struct cpu_frame *up;
 128   uint16 pc;
 129   uint16 sp_low;
 130   uint16 sp_high;
 131 };
 132
 133 /* Represents a list of frames (or a thread).  */
 134 struct cpu_frame_list
 135 {
 136   struct cpu_frame_list *next;
 137   struct cpu_frame_list *prev;
 138   struct cpu_frame      *frame;
 139 };
 140
 141 struct _sim_cpu {
 142   /* CPU registers.  */
 143   struct m6811_regs     cpu_regs;
 144
 145   /* CPU interrupts.  */
 146   struct interrupts     cpu_interrupts;
 147
 148   struct cpu_frame_list *cpu_frames;
 149   struct cpu_frame_list *cpu_current_frame;
 150   int                   cpu_need_update_frame;
 151
 152   /* CPU absolute cycle time.  The cycle time is updated after
 153      each instruction, by the number of cycles taken by the instruction.
 154      It is cleared only when reset occurs.  */
 155   signed64              cpu_absolute_cycle;
 156
 157   /* Number of cycles to increment after the current instruction.
 158      This is also the number of ticks for the generic event scheduler.  */
 159   uint8                 cpu_current_cycle;
 160   int                   cpu_emul_syscall;
 161   int                   cpu_is_initialized;
 162   int                   cpu_running;
 163   int                   cpu_check_memory;
 164   int                   cpu_stop_on_interrupt;
 165
 166   /* When this is set, start execution of program at address specified
 167      in the ELF header.  This is used for testing some programs that do not
 168      have an interrupt table linked with them.  Programs created during the
 169      GCC validation are like this. A normal 68HC11 does not behave like
 170      this (unless there is some OS or downloadable feature).  */
 171   int                   cpu_use_elf_start;
 172
 173   /* The starting address specified in ELF header.  */
 174   int                   cpu_elf_start;
 175
 176   uint16                cpu_insn_pc;
 177   unsigned short        cpu_nb_pseudo_regs;
 178   uint16                cpu_page0_reg[MAX_SOFT_REG];
 179
 180   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 181      get the cycle time.  This is used for the timer rate and for the baud
 182      rate generation.  */
 183   unsigned long         cpu_frequency;
 184
 185   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 186   unsigned int          cpu_mode;
 187
 188   /* Initial value of the CONFIG register.  */
 189   uint8                 cpu_config;
 190   uint8                 cpu_use_local_config;
 191
 192   uint8 ios[0x3F];
 193
 194   /* ... base type ... */
 195   sim_cpu_base base;
 196 };
 197
 198 /* Returns the cpu absolute cycle time (A virtual counter incremented
 199    at each 68HC11 E clock).  */
 200 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
 201 #define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
 202 #define cpu_is_running(PROC)    ((PROC)->cpu_running)
 203
 204 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 205 #define cpu_get_io_base(PROC) \
 206         (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
 207 #define cpu_get_reg_base(PROC) \
 208         (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
 209
 210 /* Returns the different CPU registers.  */
 211 #define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
 212 #define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
 213 #define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
 214 #define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
 215 #define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
 216 #define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
 217 #define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
 218 #define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
 219
 220 #define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
 221 #define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
 222 #define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
 223
 224 #if 0
 225 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 226 #define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
 227 #endif
 228
 229 #define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))
 230
 231 #define cpu_set_a(PROC,VAL)  \
 232       cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
 233 #define cpu_set_b(PROC,VAL)  \
 234       cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
 235
 236 #define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
 237 #define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
 238 #define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
 239 #define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
 240 #define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
 241 #define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
 242 #define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
 243 #define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
 244 #define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
 245
 246 #define cpu_set_ccr_flag(S,B,V) \
 247 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
 248
 249 #define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
 250 #define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
 251 #define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
 252 #define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
 253 #define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
 254 #define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
 255 #define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
 256 #define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
 257
 258 #undef inline
 259 #define inline static __inline__
 260
 261 extern void cpu_memory_exception (struct _sim_cpu *proc,
 262                                   SIM_SIGNAL excep,
 263                                   uint16 addr,
 264                                   const char *message);
 265
 266 inline uint8
 267 memory_read8 (sim_cpu *cpu, uint16 addr)
 268 {
 269   uint8 val;
 270
 271   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 272     {
 273       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 274                             "Read error");
 275     }
 276   return val;
 277 }
 278
 279 inline void
 280 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 281 {
 282   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 283     {
 284       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 285                             "Write error");
 286     }
 287 }
 288
 289 inline uint16
 290 memory_read16 (sim_cpu *cpu, uint16 addr)
 291 {
 292   uint8 b[2];
 293
 294   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 295     {
 296       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 297                             "Read error");
 298     }
 299   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 300 }
 301
 302 inline void
 303 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 304 {
 305   uint8 b[2];
 306
 307   b[0] = val >> 8;
 308   b[1] = val;
 309   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 310     {
 311       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 312                             "Write error");
 313     }
 314 }
 315 extern void
 316 cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
 317
 318      inline void
 319 cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
 320 {
 321   cpu_set_ccr_V (proc, 0);
 322   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 323   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 324 }
 325
 326      inline void
 327 cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
 328 {
 329   cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
 330   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 331   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 332 }
 333
 334      inline void
 335 cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
 336 {
 337   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 338   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 339   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 340 }
 341
 342 inline void
 343 cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 344 {
 345   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 346   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 347   cpu_set_ccr_Z (proc, r == 0);
 348   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 349 }
 350
 351
 352 inline void
 353 cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 354 {
 355   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 356   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 357   cpu_set_ccr_Z (proc, r == 0);
 358   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 359 }
 360
 361 inline void
 362 cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 363 {
 364   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 365   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 366   cpu_set_ccr_Z (proc, r == 0);
 367   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 368 }
 369
 370 inline void
 371 cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 372 {
 373   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 374   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 375   cpu_set_ccr_Z (proc, r == 0);
 376   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 377 }
 378
 379
 380 inline void
 381 cpu_push_uint8 (sim_cpu *proc, uint8 val)
 382 {
 383   uint16 addr = proc->cpu_regs.sp;
 384
 385   memory_write8 (proc, addr, val);
 386   proc->cpu_regs.sp = addr - 1;
 387   proc->cpu_need_update_frame |= CPU_PUSH;
 388 }
 389
 390 inline void
 391 cpu_push_uint16 (sim_cpu *proc, uint16 val)
 392 {
 393   uint16 addr = proc->cpu_regs.sp - 1;
 394
 395   memory_write16 (proc, addr, val);
 396   proc->cpu_regs.sp = addr - 1;
 397   proc->cpu_need_update_frame |= CPU_PUSH;
 398 }
 399
 400 inline uint8
 401 cpu_pop_uint8 (sim_cpu *proc)
 402 {
 403   uint16 addr = proc->cpu_regs.sp;
 404   uint8 val;
 405
 406   val = memory_read8 (proc, addr + 1);
 407   proc->cpu_regs.sp = addr + 1;
 408   proc->cpu_need_update_frame |= CPU_POP;
 409   return val;
 410 }
 411
 412 inline uint16
 413 cpu_pop_uint16 (sim_cpu *proc)
 414 {
 415   uint16 addr = proc->cpu_regs.sp;
 416   uint16 val;
 417
 418   val = memory_read16 (proc, addr + 1);
 419   proc->cpu_regs.sp = addr + 2;
 420   proc->cpu_need_update_frame |= CPU_POP;
 421   return val;
 422 }
 423
 424 inline uint8
 425 cpu_fetch8 (sim_cpu *proc)
 426 {
 427   uint16 addr = proc->cpu_regs.pc;
 428   uint8 val;
 429
 430   val = memory_read8 (proc, addr);
 431   proc->cpu_regs.pc = addr + 1;
 432   return val;
 433 }
 434
 435 inline uint16
 436 cpu_fetch16 (sim_cpu *proc)
 437 {
 438   uint16 addr = proc->cpu_regs.pc;
 439   uint16 val;
 440
 441   val = memory_read16 (proc, addr);
 442   proc->cpu_regs.pc = addr + 2;
 443   return val;
 444 }
 445
 446 extern void cpu_call (sim_cpu* proc, uint16 addr);
 447 extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
 448
 449 extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
 450 extern void cpu_push_all (sim_cpu *proc);
 451 extern void cpu_single_step (sim_cpu *proc);
 452
 453 extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
 454
 455 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 456
 457 extern void cpu_print_frame (SIM_DESC sd, sim_cpu *cpu);
 458 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 459 extern uint16 cpu_frame_reg (sim_cpu *cpu, uint16 rn);
 460 extern int cpu_reset (sim_cpu *cpu);
 461 extern int cpu_restart (sim_cpu *cpu);
 462 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 463                               uint16 addr, const char *message, ...);
 464 extern void emul_os (int op, sim_cpu *cpu);
 465 extern void cpu_interp (sim_cpu *cpu);
 466
 467 /* The current state of the processor; registers, memory, etc.  */
 468
 469 #define CIA_GET(CPU)      (cpu_get_pc (CPU))
 470 #define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))
 471
 472 #if (WITH_SMP)
 473 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 474 #else
 475 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 476 #endif
 477
 478 struct sim_state {
 479   sim_cpu        cpu[MAX_NR_PROCESSORS];
 480   device         *devices;
 481   sim_state_base base;
 482 };
 483
 484 extern void sim_set_profile (int n);
 485 extern void sim_set_profile_size (int n);
 486 extern void sim_board_reset (SIM_DESC sd);
 487
 488 #endif
 489
 490