sim/mcore/interp.c

   1 /* Simulator for Motorola's MCore processor
   2    Copyright (C) 1999-2024 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #include <signal.h>
  24 #include <stdlib.h>
  25 #include <string.h>
  26 #include <sys/param.h>
  27 #include <unistd.h>
  28 #include "bfd.h"
  29 #include "sim/callback.h"
  30 #include "libiberty.h"
  31 #include "sim/sim.h"
  32
  33 #include "sim-main.h"
  34 #include "sim-base.h"
  35 #include "sim-signal.h"
  36 #include "sim-syscall.h"
  37 #include "sim-options.h"
  38
  39 #include "target-newlib-syscall.h"
  40
  41 #include "mcore-sim.h"
  42
  43 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
  44
  45
  46 static unsigned long
  47 mcore_extract_unsigned_integer (const unsigned char *addr, int len)
  48 {
  49   unsigned long retval;
  50   unsigned char * p;
  51   unsigned char * startaddr = (unsigned char *)addr;
  52   unsigned char * endaddr = startaddr + len;
  53
  54   if (len > (int) sizeof (unsigned long))
  55     printf ("That operation is not available on integers of more than %zu bytes.",
  56             sizeof (unsigned long));
  57
  58   /* Start at the most significant end of the integer, and work towards
  59      the least significant.  */
  60   retval = 0;
  61
  62   if (! target_big_endian)
  63     {
  64       for (p = endaddr; p > startaddr;)
  65         retval = (retval << 8) | * -- p;
  66     }
  67   else
  68     {
  69       for (p = startaddr; p < endaddr;)
  70         retval = (retval << 8) | * p ++;
  71     }
  72
  73   return retval;
  74 }
  75
  76 static void
  77 mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
  78 {
  79   unsigned char * p;
  80   unsigned char * startaddr = (unsigned char *)addr;
  81   unsigned char * endaddr = startaddr + len;
  82
  83   if (! target_big_endian)
  84     {
  85       for (p = startaddr; p < endaddr;)
  86         {
  87           * p ++ = val & 0xff;
  88           val >>= 8;
  89         }
  90     }
  91   else
  92     {
  93       for (p = endaddr; p > startaddr;)
  94         {
  95           * -- p = val & 0xff;
  96           val >>= 8;
  97         }
  98     }
  99 }
 100
 101 static int memcycles = 1;
 102
 103 #define gr      MCORE_SIM_CPU (cpu)->active_gregs
 104 #define cr      MCORE_SIM_CPU (cpu)->regs.cregs
 105 #define sr      cr[0]
 106 #define vbr     cr[1]
 107 #define esr     cr[2]
 108 #define fsr     cr[3]
 109 #define epc     cr[4]
 110 #define fpc     cr[5]
 111 #define ss0     cr[6]
 112 #define ss1     cr[7]
 113 #define ss2     cr[8]
 114 #define ss3     cr[9]
 115 #define ss4     cr[10]
 116 #define gcr     cr[11]
 117 #define gsr     cr[12]
 118
 119 /* maniuplate the carry bit */
 120 #define C_ON()          (sr & 1)
 121 #define C_VALUE()       (sr & 1)
 122 #define C_OFF()         ((sr & 1) == 0)
 123 #define SET_C()         {sr |= 1;}
 124 #define CLR_C()         {sr &= 0xfffffffe;}
 125 #define NEW_C(v)        {CLR_C(); sr |= ((v) & 1);}
 126
 127 #define SR_AF()         ((sr >> 1) & 1)
 128 static void set_active_regs (SIM_CPU *cpu)
 129 {
 130   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
 131
 132   if (SR_AF())
 133     mcore_cpu->active_gregs = mcore_cpu->regs.alt_gregs;
 134   else
 135     mcore_cpu->active_gregs = mcore_cpu->regs.gregs;
 136 }
 137
 138 #define TRAPCODE        1       /* r1 holds which function we want */
 139 #define PARM1   2               /* first parameter  */
 140 #define PARM2   3
 141 #define PARM3   4
 142 #define PARM4   5
 143 #define RET1    2               /* register for return values. */
 144
 145 /* Default to a 8 Mbyte (== 2^23) memory space.  */
 146 #define DEFAULT_MEMORY_SIZE 0x800000
 147
 148 static void
 149 set_initial_gprs (SIM_CPU *cpu)
 150 {
 151   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
 152
 153   /* Set up machine just out of reset.  */
 154   CPU_PC_SET (cpu, 0);
 155   sr = 0;
 156
 157   /* Clean out the GPRs and alternate GPRs.  */
 158   memset (&mcore_cpu->regs.gregs, 0, sizeof(mcore_cpu->regs.gregs));
 159   memset (&mcore_cpu->regs.alt_gregs, 0, sizeof(mcore_cpu->regs.alt_gregs));
 160
 161   /* Make our register set point to the right place.  */
 162   set_active_regs (cpu);
 163
 164   /* ABI specifies initial values for these registers.  */
 165   gr[0] = DEFAULT_MEMORY_SIZE - 4;
 166
 167   /* dac fix, the stack address must be 8-byte aligned! */
 168   gr[0] = gr[0] - gr[0] % 8;
 169   gr[PARM1] = 0;
 170   gr[PARM2] = 0;
 171   gr[PARM3] = 0;
 172   gr[PARM4] = gr[0];
 173 }
 174
 175 /* Simulate a monitor trap.  */
 176
 177 static void
 178 handle_trap1 (SIM_DESC sd, SIM_CPU *cpu)
 179 {
 180   /* XXX: We don't pass back the actual errno value.  */
 181   gr[RET1] = sim_syscall (cpu, gr[TRAPCODE], gr[PARM1], gr[PARM2], gr[PARM3],
 182                           gr[PARM4]);
 183 }
 184
 185 static void
 186 process_stub (SIM_DESC sd, SIM_CPU *cpu, int what)
 187 {
 188   /* These values should match those in libgloss/mcore/syscalls.s.  */
 189   switch (what)
 190     {
 191     case 3:  /* _read */
 192     case 4:  /* _write */
 193     case 5:  /* _open */
 194     case 6:  /* _close */
 195     case 10: /* _unlink */
 196     case 19: /* _lseek */
 197     case 43: /* _times */
 198       gr[TRAPCODE] = what;
 199       handle_trap1 (sd, cpu);
 200       break;
 201
 202     default:
 203       if (STATE_VERBOSE_P (sd))
 204         fprintf (stderr, "Unhandled stub opcode: %d\n", what);
 205       break;
 206     }
 207 }
 208
 209 static void
 210 util (SIM_DESC sd, SIM_CPU *cpu, unsigned what)
 211 {
 212   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
 213
 214   switch (what)
 215     {
 216     case 0:     /* exit */
 217       sim_engine_halt (sd, cpu, NULL, mcore_cpu->regs.pc, sim_exited, gr[PARM1]);
 218       break;
 219
 220     case 1:     /* printf */
 221       if (STATE_VERBOSE_P (sd))
 222         fprintf (stderr, "WARNING: printf unimplemented\n");
 223       break;
 224
 225     case 2:     /* scanf */
 226       if (STATE_VERBOSE_P (sd))
 227         fprintf (stderr, "WARNING: scanf unimplemented\n");
 228       break;
 229
 230     case 3:     /* utime */
 231       gr[RET1] = mcore_cpu->insts;
 232       break;
 233
 234     case 0xFF:
 235       process_stub (sd, cpu, gr[1]);
 236       break;
 237
 238     default:
 239       if (STATE_VERBOSE_P (sd))
 240         fprintf (stderr, "Unhandled util code: %x\n", what);
 241       break;
 242     }
 243 }
 244
 245 /* For figuring out whether we carried; addc/subc use this. */
 246 static int
 247 iu_carry (unsigned long a, unsigned long b, int cin)
 248 {
 249   unsigned long x;
 250
 251   x = (a & 0xffff) + (b & 0xffff) + cin;
 252   x = (x >> 16) + (a >> 16) + (b >> 16);
 253   x >>= 16;
 254
 255   return (x != 0);
 256 }
 257
 258 /* TODO: Convert to common watchpoints.  */
 259 #undef WATCHFUNCTIONS
 260 #ifdef WATCHFUNCTIONS
 261
 262 #define MAXWL 80
 263 int32_t WL[MAXWL];
 264 char * WLstr[MAXWL];
 265
 266 int ENDWL=0;
 267 int WLincyc;
 268 int WLcyc[MAXWL];
 269 int WLcnts[MAXWL];
 270 int WLmax[MAXWL];
 271 int WLmin[MAXWL];
 272 int32_t WLendpc;
 273 int WLbcyc;
 274 int WLW;
 275 #endif
 276
 277 #define RD      (inst        & 0xF)
 278 #define RS      ((inst >> 4) & 0xF)
 279 #define RX      ((inst >> 8) & 0xF)
 280 #define IMM5    ((inst >> 4) & 0x1F)
 281 #define IMM4    ((inst) & 0xF)
 282
 283 #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X)
 284 #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X)
 285 #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X)
 286 #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
 287 #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
 288 #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
 289
 290 static int tracing = 0;
 291
 292 #define ILLEGAL() \
 293   sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL)
 294
 295 static void
 296 step_once (SIM_DESC sd, SIM_CPU *cpu)
 297 {
 298   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
 299   int needfetch;
 300   int32_t ibuf;
 301   int32_t pc;
 302   unsigned short inst;
 303   int memops;
 304   int bonus_cycles;
 305   int insts;
 306 #ifdef WATCHFUNCTIONS
 307   int w;
 308   int32_t WLhash;
 309 #endif
 310
 311   pc = CPU_PC_GET (cpu);
 312
 313   /* Fetch the initial instructions that we'll decode. */
 314   ibuf = rlat (pc & 0xFFFFFFFC);
 315   needfetch = 0;
 316
 317   memops = 0;
 318   bonus_cycles = 0;
 319   insts = 0;
 320
 321   /* make our register set point to the right place */
 322   set_active_regs (cpu);
 323
 324 #ifdef WATCHFUNCTIONS
 325   /* make a hash to speed exec loop, hope it's nonzero */
 326   WLhash = 0xFFFFFFFF;
 327
 328   for (w = 1; w <= ENDWL; w++)
 329     WLhash = WLhash & WL[w];
 330 #endif
 331
 332   /* TODO: Unindent this block.  */
 333     {
 334       insts ++;
 335
 336       if (pc & 02)
 337         {
 338           if (! target_big_endian)
 339             inst = ibuf >> 16;
 340           else
 341             inst = ibuf & 0xFFFF;
 342           needfetch = 1;
 343         }
 344       else
 345         {
 346           if (! target_big_endian)
 347             inst = ibuf & 0xFFFF;
 348           else
 349             inst = ibuf >> 16;
 350         }
 351
 352 #ifdef WATCHFUNCTIONS
 353       /* now scan list of watch addresses, if match, count it and
 354          note return address and count cycles until pc=return address */
 355
 356       if ((WLincyc == 1) && (pc == WLendpc))
 357         {
 358           int cycs = (mcore_cpu->cycles + (insts + bonus_cycles +
 359                                            (memops * memcycles)) - WLbcyc);
 360
 361           if (WLcnts[WLW] == 1)
 362             {
 363               WLmax[WLW] = cycs;
 364               WLmin[WLW] = cycs;
 365               WLcyc[WLW] = 0;
 366             }
 367
 368           if (cycs > WLmax[WLW])
 369             {
 370               WLmax[WLW] = cycs;
 371             }
 372
 373           if (cycs < WLmin[WLW])
 374             {
 375               WLmin[WLW] = cycs;
 376             }
 377
 378           WLcyc[WLW] += cycs;
 379           WLincyc = 0;
 380           WLendpc = 0;
 381         }
 382
 383       /* Optimize with a hash to speed loop.  */
 384       if (WLincyc == 0)
 385         {
 386           if ((WLhash == 0) || ((WLhash & pc) != 0))
 387             {
 388               for (w=1; w <= ENDWL; w++)
 389                 {
 390                   if (pc == WL[w])
 391                     {
 392                       WLcnts[w]++;
 393                       WLbcyc = mcore_cpu->cycles + insts
 394                         + bonus_cycles + (memops * memcycles);
 395                       WLendpc = gr[15];
 396                       WLincyc = 1;
 397                       WLW = w;
 398                       break;
 399                     }
 400                 }
 401             }
 402         }
 403 #endif
 404
 405       if (tracing)
 406         fprintf (stderr, "%.4x: inst = %.4x ", pc, inst);
 407
 408       pc += 2;
 409
 410       switch (inst >> 8)
 411         {
 412         case 0x00:
 413           switch RS
 414             {
 415             case 0x0:
 416               switch RD
 417                 {
 418                 case 0x0:                               /* bkpt */
 419                   pc -= 2;
 420                   sim_engine_halt (sd, cpu, NULL, pc - 2,
 421                                    sim_stopped, SIM_SIGTRAP);
 422                   break;
 423
 424                 case 0x1:                               /* sync */
 425                   break;
 426
 427                 case 0x2:                               /* rte */
 428                   pc = epc;
 429                   sr = esr;
 430                   needfetch = 1;
 431
 432                   set_active_regs (cpu);
 433                   break;
 434
 435                 case 0x3:                               /* rfi */
 436                   pc = fpc;
 437                   sr = fsr;
 438                   needfetch = 1;
 439
 440                   set_active_regs (cpu);
 441                   break;
 442
 443                 case 0x4:                               /* stop */
 444                   if (STATE_VERBOSE_P (sd))
 445                     fprintf (stderr, "WARNING: stop unimplemented\n");
 446                   break;
 447
 448                 case 0x5:                               /* wait */
 449                   if (STATE_VERBOSE_P (sd))
 450                     fprintf (stderr, "WARNING: wait unimplemented\n");
 451                   break;
 452
 453                 case 0x6:                               /* doze */
 454                   if (STATE_VERBOSE_P (sd))
 455                     fprintf (stderr, "WARNING: doze unimplemented\n");
 456                   break;
 457
 458                 case 0x7:
 459                   ILLEGAL ();                           /* illegal */
 460                   break;
 461
 462                 case 0x8:                               /* trap 0 */
 463                 case 0xA:                               /* trap 2 */
 464                 case 0xB:                               /* trap 3 */
 465                   sim_engine_halt (sd, cpu, NULL, pc,
 466                                    sim_stopped, SIM_SIGTRAP);
 467                   break;
 468
 469                 case 0xC:                               /* trap 4 */
 470                 case 0xD:                               /* trap 5 */
 471                 case 0xE:                               /* trap 6 */
 472                   ILLEGAL ();                           /* illegal */
 473                   break;
 474
 475                 case 0xF:                               /* trap 7 */
 476                   sim_engine_halt (sd, cpu, NULL, pc,   /* integer div-by-0 */
 477                                    sim_stopped, SIM_SIGTRAP);
 478                   break;
 479
 480                 case 0x9:                               /* trap 1 */
 481                   handle_trap1 (sd, cpu);
 482                   break;
 483                 }
 484               break;
 485
 486             case 0x1:
 487               ILLEGAL ();                               /* illegal */
 488               break;
 489
 490             case 0x2:                                   /* mvc */
 491               gr[RD] = C_VALUE();
 492               break;
 493             case 0x3:                                   /* mvcv */
 494               gr[RD] = C_OFF();
 495               break;
 496             case 0x4:                                   /* ldq */
 497               {
 498                 int32_t addr = gr[RD];
 499                 int regno = 4;                  /* always r4-r7 */
 500
 501                 bonus_cycles++;
 502                 memops += 4;
 503                 do
 504                   {
 505                     gr[regno] = rlat (addr);
 506                     addr += 4;
 507                     regno++;
 508                   }
 509                 while ((regno&0x3) != 0);
 510               }
 511               break;
 512             case 0x5:                                   /* stq */
 513               {
 514                 int32_t addr = gr[RD];
 515                 int regno = 4;                  /* always r4-r7 */
 516
 517                 memops += 4;
 518                 bonus_cycles++;
 519                 do
 520                   {
 521                     wlat (addr, gr[regno]);
 522                     addr += 4;
 523                     regno++;
 524                   }
 525                 while ((regno & 0x3) != 0);
 526               }
 527               break;
 528             case 0x6:                                   /* ldm */
 529               {
 530                 int32_t addr = gr[0];
 531                 int regno = RD;
 532
 533                 /* bonus cycle is really only needed if
 534                    the next insn shifts the last reg loaded.
 535
 536                    bonus_cycles++;
 537                 */
 538                 memops += 16-regno;
 539                 while (regno <= 0xF)
 540                   {
 541                     gr[regno] = rlat (addr);
 542                     addr += 4;
 543                     regno++;
 544                   }
 545               }
 546               break;
 547             case 0x7:                                   /* stm */
 548               {
 549                 int32_t addr = gr[0];
 550                 int regno = RD;
 551
 552                 /* this should be removed! */
 553                 /*  bonus_cycles ++; */
 554
 555                 memops += 16 - regno;
 556                 while (regno <= 0xF)
 557                   {
 558                     wlat (addr, gr[regno]);
 559                     addr += 4;
 560                     regno++;
 561                   }
 562               }
 563               break;
 564
 565             case 0x8:                                   /* dect */
 566               gr[RD] -= C_VALUE();
 567               break;
 568             case 0x9:                                   /* decf */
 569               gr[RD] -= C_OFF();
 570               break;
 571             case 0xA:                                   /* inct */
 572               gr[RD] += C_VALUE();
 573               break;
 574             case 0xB:                                   /* incf */
 575               gr[RD] += C_OFF();
 576               break;
 577             case 0xC:                                   /* jmp */
 578               pc = gr[RD];
 579               if (tracing && RD == 15)
 580                 fprintf (stderr, "Func return, r2 = %xx, r3 = %x\n",
 581                          gr[2], gr[3]);
 582               bonus_cycles++;
 583               needfetch = 1;
 584               break;
 585             case 0xD:                                   /* jsr */
 586               gr[15] = pc;
 587               pc = gr[RD];
 588               bonus_cycles++;
 589               needfetch = 1;
 590               break;
 591             case 0xE:                                   /* ff1 */
 592               {
 593                 int32_t tmp, i;
 594                 tmp = gr[RD];
 595                 for (i = 0; !(tmp & 0x80000000) && i < 32; i++)
 596                   tmp <<= 1;
 597                 gr[RD] = i;
 598               }
 599               break;
 600             case 0xF:                                   /* brev */
 601               {
 602                 int32_t tmp;
 603                 tmp = gr[RD];
 604                 tmp = ((tmp & 0xaaaaaaaa) >>  1) | ((tmp & 0x55555555) <<  1);
 605                 tmp = ((tmp & 0xcccccccc) >>  2) | ((tmp & 0x33333333) <<  2);
 606                 tmp = ((tmp & 0xf0f0f0f0) >>  4) | ((tmp & 0x0f0f0f0f) <<  4);
 607                 tmp = ((tmp & 0xff00ff00) >>  8) | ((tmp & 0x00ff00ff) <<  8);
 608                 gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16);
 609               }
 610               break;
 611             }
 612           break;
 613         case 0x01:
 614           switch RS
 615             {
 616             case 0x0:                                   /* xtrb3 */
 617               gr[1] = (gr[RD]) & 0xFF;
 618               NEW_C (gr[RD] != 0);
 619               break;
 620             case 0x1:                                   /* xtrb2 */
 621               gr[1] = (gr[RD]>>8) & 0xFF;
 622               NEW_C (gr[RD] != 0);
 623               break;
 624             case 0x2:                                   /* xtrb1 */
 625               gr[1] = (gr[RD]>>16) & 0xFF;
 626               NEW_C (gr[RD] != 0);
 627               break;
 628             case 0x3:                                   /* xtrb0 */
 629               gr[1] = (gr[RD]>>24) & 0xFF;
 630               NEW_C (gr[RD] != 0);
 631               break;
 632             case 0x4:                                   /* zextb */
 633               gr[RD] &= 0x000000FF;
 634               break;
 635             case 0x5:                                   /* sextb */
 636               {
 637                 long tmp;
 638                 tmp = gr[RD];
 639                 tmp <<= (sizeof (tmp) * 8) - 8;
 640                 tmp >>= (sizeof (tmp) * 8) - 8;
 641                 gr[RD] = tmp;
 642               }
 643               break;
 644             case 0x6:                                   /* zexth */
 645               gr[RD] &= 0x0000FFFF;
 646               break;
 647             case 0x7:                                   /* sexth */
 648               {
 649                 long tmp;
 650                 tmp = gr[RD];
 651                 tmp <<= (sizeof (tmp) * 8) - 16;
 652                 tmp >>= (sizeof (tmp) * 8) - 16;
 653                 gr[RD] = tmp;
 654               }
 655               break;
 656             case 0x8:                                   /* declt */
 657               --gr[RD];
 658               NEW_C ((long)gr[RD] < 0);
 659               break;
 660             case 0x9:                                   /* tstnbz */
 661               {
 662                 int32_t tmp = gr[RD];
 663                 NEW_C ((tmp & 0xFF000000) != 0 &&
 664                        (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 &&
 665                        (tmp & 0x000000FF) != 0);
 666               }
 667               break;
 668             case 0xA:                                   /* decgt */
 669               --gr[RD];
 670               NEW_C ((long)gr[RD] > 0);
 671               break;
 672             case 0xB:                                   /* decne */
 673               --gr[RD];
 674               NEW_C ((long)gr[RD] != 0);
 675               break;
 676             case 0xC:                                   /* clrt */
 677               if (C_ON())
 678                 gr[RD] = 0;
 679               break;
 680             case 0xD:                                   /* clrf */
 681               if (C_OFF())
 682                 gr[RD] = 0;
 683               break;
 684             case 0xE:                                   /* abs */
 685               if (gr[RD] & 0x80000000)
 686                 gr[RD] = ~gr[RD] + 1;
 687               break;
 688             case 0xF:                                   /* not */
 689               gr[RD] = ~gr[RD];
 690               break;
 691             }
 692           break;
 693         case 0x02:                                      /* movt */
 694           if (C_ON())
 695             gr[RD] = gr[RS];
 696           break;
 697         case 0x03:                                      /* mult */
 698           /* consume 2 bits per cycle from rs, until rs is 0 */
 699           {
 700             unsigned int t = gr[RS];
 701             int ticks;
 702             for (ticks = 0; t != 0 ; t >>= 2)
 703               ticks++;
 704             bonus_cycles += ticks;
 705           }
 706           bonus_cycles += 2;  /* min. is 3, so add 2, plus ticks above */
 707           if (tracing)
 708             fprintf (stderr, "  mult %x by %x to give %x",
 709                      gr[RD], gr[RS], gr[RD] * gr[RS]);
 710           gr[RD] = gr[RD] * gr[RS];
 711           break;
 712         case 0x04:                                      /* loopt */
 713           if (C_ON())
 714             {
 715               pc += (IMM4 << 1) - 32;
 716               bonus_cycles ++;
 717               needfetch = 1;
 718             }
 719           --gr[RS];                             /* not RD! */
 720           NEW_C (((long)gr[RS]) > 0);
 721           break;
 722         case 0x05:                                      /* subu */
 723           gr[RD] -= gr[RS];
 724           break;
 725         case 0x06:                                      /* addc */
 726           {
 727             unsigned long tmp, a, b;
 728             a = gr[RD];
 729             b = gr[RS];
 730             gr[RD] = a + b + C_VALUE ();
 731             tmp = iu_carry (a, b, C_VALUE ());
 732             NEW_C (tmp);
 733           }
 734           break;
 735         case 0x07:                                      /* subc */
 736           {
 737             unsigned long tmp, a, b;
 738             a = gr[RD];
 739             b = gr[RS];
 740             gr[RD] = a - b + C_VALUE () - 1;
 741             tmp = iu_carry (a,~b, C_VALUE ());
 742             NEW_C (tmp);
 743           }
 744           break;
 745         case 0x08:                                      /* illegal */
 746         case 0x09:                                      /* illegal*/
 747           ILLEGAL ();
 748           break;
 749         case 0x0A:                                      /* movf */
 750           if (C_OFF())
 751             gr[RD] = gr[RS];
 752           break;
 753         case 0x0B:                                      /* lsr */
 754           {
 755             uint32_t dst, src;
 756             dst = gr[RD];
 757             src = gr[RS];
 758             /* We must not rely solely upon the native shift operations, since they
 759                may not match the M*Core's behaviour on boundary conditions.  */
 760             dst = src > 31 ? 0 : dst >> src;
 761             gr[RD] = dst;
 762           }
 763           break;
 764         case 0x0C:                                      /* cmphs */
 765           NEW_C ((unsigned long )gr[RD] >=
 766                  (unsigned long)gr[RS]);
 767           break;
 768         case 0x0D:                                      /* cmplt */
 769           NEW_C ((long)gr[RD] < (long)gr[RS]);
 770           break;
 771         case 0x0E:                                      /* tst */
 772           NEW_C ((gr[RD] & gr[RS]) != 0);
 773           break;
 774         case 0x0F:                                      /* cmpne */
 775           NEW_C (gr[RD] != gr[RS]);
 776           break;
 777         case 0x10: case 0x11:                           /* mfcr */
 778           {
 779             unsigned r;
 780             r = IMM5;
 781             if (r <= LAST_VALID_CREG)
 782               gr[RD] = cr[r];
 783             else
 784               ILLEGAL ();
 785           }
 786           break;
 787
 788         case 0x12:                                      /* mov */
 789           gr[RD] = gr[RS];
 790           if (tracing)
 791             fprintf (stderr, "MOV %x into reg %d", gr[RD], RD);
 792           break;
 793
 794         case 0x13:                                      /* bgenr */
 795           if (gr[RS] & 0x20)
 796             gr[RD] = 0;
 797           else
 798             gr[RD] = 1 << (gr[RS] & 0x1F);
 799           break;
 800
 801         case 0x14:                                      /* rsub */
 802           gr[RD] = gr[RS] - gr[RD];
 803           break;
 804
 805         case 0x15:                                      /* ixw */
 806           gr[RD] += gr[RS]<<2;
 807           break;
 808
 809         case 0x16:                                      /* and */
 810           gr[RD] &= gr[RS];
 811           break;
 812
 813         case 0x17:                                      /* xor */
 814           gr[RD] ^= gr[RS];
 815           break;
 816
 817         case 0x18: case 0x19:                           /* mtcr */
 818           {
 819             unsigned r;
 820             r = IMM5;
 821             if (r <= LAST_VALID_CREG)
 822               cr[r] = gr[RD];
 823             else
 824               ILLEGAL ();
 825
 826             /* we might have changed register sets... */
 827             set_active_regs (cpu);
 828           }
 829           break;
 830
 831         case 0x1A:                                      /* asr */
 832           /* We must not rely solely upon the native shift operations, since they
 833              may not match the M*Core's behaviour on boundary conditions.  */
 834           if (gr[RS] > 30)
 835             gr[RD] = ((long) gr[RD]) < 0 ? -1 : 0;
 836           else
 837             gr[RD] = (long) gr[RD] >> gr[RS];
 838           break;
 839
 840         case 0x1B:                                      /* lsl */
 841           /* We must not rely solely upon the native shift operations, since they
 842              may not match the M*Core's behaviour on boundary conditions.  */
 843           gr[RD] = gr[RS] > 31 ? 0 : gr[RD] << gr[RS];
 844           break;
 845
 846         case 0x1C:                                      /* addu */
 847           gr[RD] += gr[RS];
 848           break;
 849
 850         case 0x1D:                                      /* ixh */
 851           gr[RD] += gr[RS] << 1;
 852           break;
 853
 854         case 0x1E:                                      /* or */
 855           gr[RD] |= gr[RS];
 856           break;
 857
 858         case 0x1F:                                      /* andn */
 859           gr[RD] &= ~gr[RS];
 860           break;
 861         case 0x20: case 0x21:                           /* addi */
 862           gr[RD] =
 863             gr[RD] + (IMM5 + 1);
 864           break;
 865         case 0x22: case 0x23:                           /* cmplti */
 866           {
 867             int tmp = (IMM5 + 1);
 868             if (gr[RD] < tmp)
 869               {
 870                 SET_C();
 871               }
 872             else
 873               {
 874                 CLR_C();
 875               }
 876           }
 877           break;
 878         case 0x24: case 0x25:                           /* subi */
 879           gr[RD] =
 880             gr[RD] - (IMM5 + 1);
 881           break;
 882         case 0x26: case 0x27:                           /* illegal */
 883           ILLEGAL ();
 884           break;
 885         case 0x28: case 0x29:                           /* rsubi */
 886           gr[RD] =
 887             IMM5 - gr[RD];
 888           break;
 889         case 0x2A: case 0x2B:                           /* cmpnei */
 890           if (gr[RD] != IMM5)
 891             {
 892               SET_C();
 893             }
 894           else
 895             {
 896               CLR_C();
 897             }
 898           break;
 899
 900         case 0x2C: case 0x2D:                           /* bmaski, divu */
 901           {
 902             unsigned imm = IMM5;
 903
 904             if (imm == 1)
 905               {
 906                 int exe;
 907                 int rxnlz, r1nlz;
 908                 unsigned int rx, r1;
 909
 910                 rx = gr[RD];
 911                 r1 = gr[1];
 912                 exe = 0;
 913
 914                 /* unsigned divide */
 915                 gr[RD] = (int32_t) ((unsigned int) gr[RD] / (unsigned int)gr[1] );
 916
 917                 /* compute bonus_cycles for divu */
 918                 for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++)
 919                   r1 = r1 << 1;
 920
 921                 for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++)
 922                   rx = rx << 1;
 923
 924                 if (r1nlz < rxnlz)
 925                   exe += 4;
 926                 else
 927                   exe += 5 + r1nlz - rxnlz;
 928
 929                 if (exe >= (2 * memcycles - 1))
 930                   {
 931                     bonus_cycles += exe - (2 * memcycles) + 1;
 932                   }
 933               }
 934             else if (imm == 0 || imm >= 8)
 935               {
 936                 /* bmaski */
 937                 if (imm == 0)
 938                   gr[RD] = -1;
 939                 else
 940                   gr[RD] = (1 << imm) - 1;
 941               }
 942             else
 943               {
 944                 /* illegal */
 945                 ILLEGAL ();
 946               }
 947           }
 948           break;
 949         case 0x2E: case 0x2F:                           /* andi */
 950           gr[RD] = gr[RD] & IMM5;
 951           break;
 952         case 0x30: case 0x31:                           /* bclri */
 953           gr[RD] = gr[RD] & ~(1<<IMM5);
 954           break;
 955         case 0x32: case 0x33:                           /* bgeni, divs */
 956           {
 957             unsigned imm = IMM5;
 958             if (imm == 1)
 959               {
 960                 int exe,sc;
 961                 int rxnlz, r1nlz;
 962                 signed int rx, r1;
 963
 964                 /* compute bonus_cycles for divu */
 965                 rx = gr[RD];
 966                 r1 = gr[1];
 967                 exe = 0;
 968
 969                 if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0)))
 970                   sc = 1;
 971                 else
 972                   sc = 0;
 973
 974                 rx = abs (rx);
 975                 r1 = abs (r1);
 976
 977                 /* signed divide, general registers are of type int, so / op is OK */
 978                 gr[RD] = gr[RD] / gr[1];
 979
 980                 for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ )
 981                   r1 = r1 << 1;
 982
 983                 for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ )
 984                   rx = rx << 1;
 985
 986                 if (r1nlz < rxnlz)
 987                   exe += 5;
 988                 else
 989                   exe += 6 + r1nlz - rxnlz + sc;
 990
 991                 if (exe >= (2 * memcycles - 1))
 992                   {
 993                     bonus_cycles += exe - (2 * memcycles) + 1;
 994                   }
 995               }
 996             else if (imm >= 7)
 997               {
 998                 /* bgeni */
 999                 gr[RD] = (1 << IMM5);
1000               }
1001             else
1002               {
1003                 /* illegal */
1004                 ILLEGAL ();
1005               }
1006             break;
1007           }
1008         case 0x34: case 0x35:                           /* bseti */
1009           gr[RD] = gr[RD] | (1 << IMM5);
1010           break;
1011         case 0x36: case 0x37:                           /* btsti */
1012           NEW_C (gr[RD] >> IMM5);
1013           break;
1014         case 0x38: case 0x39:                           /* xsr, rotli */
1015           {
1016             unsigned imm = IMM5;
1017             uint32_t tmp = gr[RD];
1018             if (imm == 0)
1019               {
1020                 int32_t cbit;
1021                 cbit = C_VALUE();
1022                 NEW_C (tmp);
1023                 gr[RD] = (cbit << 31) | (tmp >> 1);
1024               }
1025             else
1026               gr[RD] = (tmp << imm) | (tmp >> (32 - imm));
1027           }
1028           break;
1029         case 0x3A: case 0x3B:                           /* asrc, asri */
1030           {
1031             unsigned imm = IMM5;
1032             long tmp = gr[RD];
1033             if (imm == 0)
1034               {
1035                 NEW_C (tmp);
1036                 gr[RD] = tmp >> 1;
1037               }
1038             else
1039               gr[RD] = tmp >> imm;
1040           }
1041           break;
1042         case 0x3C: case 0x3D:                           /* lslc, lsli */
1043           {
1044             unsigned imm = IMM5;
1045             unsigned long tmp = gr[RD];
1046             if (imm == 0)
1047               {
1048                 NEW_C (tmp >> 31);
1049                 gr[RD] = tmp << 1;
1050               }
1051             else
1052               gr[RD] = tmp << imm;
1053           }
1054           break;
1055         case 0x3E: case 0x3F:                           /* lsrc, lsri */
1056           {
1057             unsigned imm = IMM5;
1058             uint32_t tmp = gr[RD];
1059             if (imm == 0)
1060               {
1061                 NEW_C (tmp);
1062                 gr[RD] = tmp >> 1;
1063               }
1064             else
1065               gr[RD] = tmp >> imm;
1066           }
1067           break;
1068         case 0x40: case 0x41: case 0x42: case 0x43:
1069         case 0x44: case 0x45: case 0x46: case 0x47:
1070         case 0x48: case 0x49: case 0x4A: case 0x4B:
1071         case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1072           ILLEGAL ();
1073           break;
1074         case 0x50:
1075           util (sd, cpu, inst & 0xFF);
1076           break;
1077         case 0x51: case 0x52: case 0x53:
1078         case 0x54: case 0x55: case 0x56: case 0x57:
1079         case 0x58: case 0x59: case 0x5A: case 0x5B:
1080         case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1081           ILLEGAL ();
1082           break;
1083         case 0x60: case 0x61: case 0x62: case 0x63:     /* movi  */
1084         case 0x64: case 0x65: case 0x66: case 0x67:
1085           gr[RD] = (inst >> 4) & 0x7F;
1086           break;
1087         case 0x68: case 0x69: case 0x6A: case 0x6B:
1088         case 0x6C: case 0x6D: case 0x6E: case 0x6F:     /* illegal */
1089           ILLEGAL ();
1090           break;
1091         case 0x71: case 0x72: case 0x73:
1092         case 0x74: case 0x75: case 0x76: case 0x77:
1093         case 0x78: case 0x79: case 0x7A: case 0x7B:
1094         case 0x7C: case 0x7D: case 0x7E:                /* lrw */
1095           gr[RX] =  rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
1096           if (tracing)
1097             fprintf (stderr, "LRW of 0x%x from 0x%x to reg %d",
1098                      rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC),
1099                      (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX);
1100           memops++;
1101           break;
1102         case 0x7F:                                      /* jsri */
1103           gr[15] = pc;
1104           if (tracing)
1105             fprintf (stderr,
1106                      "func call: r2 = %x r3 = %x r4 = %x r5 = %x r6 = %x r7 = %x\n",
1107                      gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]);
1108           ATTRIBUTE_FALLTHROUGH;
1109         case 0x70:                                      /* jmpi */
1110           pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
1111           memops++;
1112           bonus_cycles++;
1113           needfetch = 1;
1114           break;
1115
1116         case 0x80: case 0x81: case 0x82: case 0x83:
1117         case 0x84: case 0x85: case 0x86: case 0x87:
1118         case 0x88: case 0x89: case 0x8A: case 0x8B:
1119         case 0x8C: case 0x8D: case 0x8E: case 0x8F:     /* ld */
1120           gr[RX] = rlat (gr[RD] + ((inst >> 2) & 0x003C));
1121           if (tracing)
1122             fprintf (stderr, "load reg %d from 0x%x with 0x%x",
1123                      RX,
1124                      gr[RD] + ((inst >> 2) & 0x003C), gr[RX]);
1125           memops++;
1126           break;
1127         case 0x90: case 0x91: case 0x92: case 0x93:
1128         case 0x94: case 0x95: case 0x96: case 0x97:
1129         case 0x98: case 0x99: case 0x9A: case 0x9B:
1130         case 0x9C: case 0x9D: case 0x9E: case 0x9F:     /* st */
1131           wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]);
1132           if (tracing)
1133             fprintf (stderr, "store reg %d (containing 0x%x) to 0x%x",
1134                      RX, gr[RX],
1135                      gr[RD] + ((inst >> 2) & 0x003C));
1136           memops++;
1137           break;
1138         case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1139         case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1140         case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1141         case 0xAC: case 0xAD: case 0xAE: case 0xAF:     /* ld.b */
1142           gr[RX] = rbat (gr[RD] + RS);
1143           memops++;
1144           break;
1145         case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1146         case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1147         case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1148         case 0xBC: case 0xBD: case 0xBE: case 0xBF:     /* st.b */
1149           wbat (gr[RD] + RS, gr[RX]);
1150           memops++;
1151           break;
1152         case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1153         case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1154         case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1155         case 0xCC: case 0xCD: case 0xCE: case 0xCF:     /* ld.h */
1156           gr[RX] = rhat (gr[RD] + ((inst >> 3) & 0x001E));
1157           memops++;
1158           break;
1159         case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1160         case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1161         case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1162         case 0xDC: case 0xDD: case 0xDE: case 0xDF:     /* st.h */
1163           what (gr[RD] + ((inst >> 3) & 0x001E), gr[RX]);
1164           memops++;
1165           break;
1166         case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1167         case 0xEC: case 0xED: case 0xEE: case 0xEF:     /* bf */
1168           if (C_OFF())
1169             {
1170               int disp;
1171               disp = inst & 0x03FF;
1172               if (inst & 0x0400)
1173                 disp |= 0xFFFFFC00;
1174               pc += disp<<1;
1175               bonus_cycles++;
1176               needfetch = 1;
1177             }
1178           break;
1179         case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1180         case 0xE4: case 0xE5: case 0xE6: case 0xE7:     /* bt */
1181           if (C_ON())
1182             {
1183               int disp;
1184               disp = inst & 0x03FF;
1185               if (inst & 0x0400)
1186                 disp |= 0xFFFFFC00;
1187               pc += disp<<1;
1188               bonus_cycles++;
1189               needfetch = 1;
1190             }
1191           break;
1192
1193         case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1194         case 0xFC: case 0xFD: case 0xFE: case 0xFF:     /* bsr */
1195           gr[15] = pc;
1196           ATTRIBUTE_FALLTHROUGH;
1197         case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1198         case 0xF4: case 0xF5: case 0xF6: case 0xF7:     /* br */
1199           {
1200             int disp;
1201             disp = inst & 0x03FF;
1202             if (inst & 0x0400)
1203               disp |= 0xFFFFFC00;
1204             pc += disp<<1;
1205             bonus_cycles++;
1206             needfetch = 1;
1207           }
1208           break;
1209
1210         }
1211
1212       if (tracing)
1213         fprintf (stderr, "\n");
1214
1215       if (needfetch)
1216         {
1217           ibuf = rlat (pc & 0xFFFFFFFC);
1218           needfetch = 0;
1219         }
1220     }
1221
1222   /* Hide away the things we've cached while executing.  */
1223   CPU_PC_SET (cpu, pc);
1224   mcore_cpu->insts += insts;            /* instructions done ... */
1225   mcore_cpu->cycles += insts;           /* and each takes a cycle */
1226   mcore_cpu->cycles += bonus_cycles;    /* and extra cycles for branches */
1227   mcore_cpu->cycles += memops * memcycles;      /* and memop cycle delays */
1228 }
1229
1230 void
1231 sim_engine_run (SIM_DESC sd,
1232                 int next_cpu_nr,  /* ignore  */
1233                 int nr_cpus,      /* ignore  */
1234                 int siggnal)      /* ignore  */
1235 {
1236   sim_cpu *cpu;
1237
1238   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1239
1240   cpu = STATE_CPU (sd, 0);
1241
1242   while (1)
1243     {
1244       step_once (sd, cpu);
1245       if (sim_events_tick (sd))
1246         sim_events_process (sd);
1247     }
1248 }
1249
1250 static int
1251 mcore_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
1252 {
1253   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
1254
1255   if (rn < NUM_MCORE_REGS && rn >= 0)
1256     {
1257       if (length == 4)
1258         {
1259           long ival;
1260
1261           /* misalignment safe */
1262           ival = mcore_extract_unsigned_integer (memory, 4);
1263           mcore_cpu->asints[rn] = ival;
1264         }
1265
1266       return 4;
1267     }
1268   else
1269     return 0;
1270 }
1271
1272 static int
1273 mcore_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
1274 {
1275   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
1276
1277   if (rn < NUM_MCORE_REGS && rn >= 0)
1278     {
1279       if (length == 4)
1280         {
1281           long ival = mcore_cpu->asints[rn];
1282
1283           /* misalignment-safe */
1284           mcore_store_unsigned_integer (memory, 4, ival);
1285         }
1286
1287       return 4;
1288     }
1289   else
1290     return 0;
1291 }
1292
1293 void
1294 sim_info (SIM_DESC sd, bool verbose)
1295 {
1296   SIM_CPU *cpu = STATE_CPU (sd, 0);
1297   struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
1298 #ifdef WATCHFUNCTIONS
1299   int w, wcyc;
1300 #endif
1301   double virttime = mcore_cpu->cycles / 36.0e6;
1302   host_callback *callback = STATE_CALLBACK (sd);
1303
1304   callback->printf_filtered (callback, "\n\n# instructions executed  %10d\n",
1305                              mcore_cpu->insts);
1306   callback->printf_filtered (callback, "# cycles                 %10d\n",
1307                              mcore_cpu->cycles);
1308   callback->printf_filtered (callback, "# pipeline stalls        %10d\n",
1309                              mcore_cpu->stalls);
1310   callback->printf_filtered (callback, "# virtual time taken     %10.4f\n",
1311                              virttime);
1312
1313 #ifdef WATCHFUNCTIONS
1314   callback->printf_filtered (callback, "\nNumber of watched functions: %d\n",
1315                              ENDWL);
1316
1317   wcyc = 0;
1318
1319   for (w = 1; w <= ENDWL; w++)
1320     {
1321       callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]);
1322       callback->printf_filtered (callback, "  calls = %d, cycles = %d\n",
1323                                  WLcnts[w],WLcyc[w]);
1324
1325       if (WLcnts[w] != 0)
1326         callback->printf_filtered (callback,
1327                                    "  maxcpc = %d, mincpc = %d, avecpc = %d\n",
1328                                    WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]);
1329       wcyc += WLcyc[w];
1330     }
1331
1332   callback->printf_filtered (callback,
1333                              "Total cycles for watched functions: %d\n",wcyc);
1334 #endif
1335 }
1336
1337 static sim_cia
1338 mcore_pc_get (sim_cpu *cpu)
1339 {
1340   return MCORE_SIM_CPU (cpu)->regs.pc;
1341 }
1342
1343 static void
1344 mcore_pc_set (sim_cpu *cpu, sim_cia pc)
1345 {
1346   MCORE_SIM_CPU (cpu)->regs.pc = pc;
1347 }
1348
1349 static void
1350 free_state (SIM_DESC sd)
1351 {
1352   if (STATE_MODULES (sd) != NULL)
1353     sim_module_uninstall (sd);
1354   sim_cpu_free_all (sd);
1355   sim_state_free (sd);
1356 }
1357
1358 SIM_DESC
1359 sim_open (SIM_OPEN_KIND kind, host_callback *cb,
1360           struct bfd *abfd, char * const *argv)
1361 {
1362   int i;
1363   SIM_DESC sd = sim_state_alloc (kind, cb);
1364   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1365
1366   /* Set default options before parsing user options.  */
1367   cb->syscall_map = cb_mcore_syscall_map;
1368
1369   /* The cpu data is kept in a separately allocated chunk of memory.  */
1370   if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct mcore_sim_cpu))
1371       != SIM_RC_OK)
1372     {
1373       free_state (sd);
1374       return 0;
1375     }
1376
1377   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1378     {
1379       free_state (sd);
1380       return 0;
1381     }
1382
1383   /* The parser will print an error message for us, so we silently return.  */
1384   if (sim_parse_args (sd, argv) != SIM_RC_OK)
1385     {
1386       free_state (sd);
1387       return 0;
1388     }
1389
1390   /* Check for/establish the a reference program image.  */
1391   if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
1392     {
1393       free_state (sd);
1394       return 0;
1395     }
1396
1397   /* Configure/verify the target byte order and other runtime
1398      configuration options.  */
1399   if (sim_config (sd) != SIM_RC_OK)
1400     {
1401       sim_module_uninstall (sd);
1402       return 0;
1403     }
1404
1405   if (sim_post_argv_init (sd) != SIM_RC_OK)
1406     {
1407       /* Uninstall the modules to avoid memory leaks,
1408          file descriptor leaks, etc.  */
1409       sim_module_uninstall (sd);
1410       return 0;
1411     }
1412
1413   /* CPU specific initialization.  */
1414   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1415     {
1416       SIM_CPU *cpu = STATE_CPU (sd, i);
1417
1418       CPU_REG_FETCH (cpu) = mcore_reg_fetch;
1419       CPU_REG_STORE (cpu) = mcore_reg_store;
1420       CPU_PC_FETCH (cpu) = mcore_pc_get;
1421       CPU_PC_STORE (cpu) = mcore_pc_set;
1422
1423       set_initial_gprs (cpu);   /* Reset the GPR registers.  */
1424     }
1425
1426   /* Default to a 8 Mbyte (== 2^23) memory space.  */
1427   sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE);
1428
1429   return sd;
1430 }
1431
1432 SIM_RC
1433 sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd,
1434                      char * const *argv, char * const *env)
1435 {
1436   SIM_CPU *cpu = STATE_CPU (sd, 0);
1437   char * const *avp;
1438   int nargs = 0;
1439   int nenv = 0;
1440   int s_length;
1441   int l;
1442   unsigned long strings;
1443   unsigned long pointers;
1444   unsigned long hi_stack;
1445
1446
1447   /* Set the initial register set.  */
1448   set_initial_gprs (cpu);
1449
1450   hi_stack = DEFAULT_MEMORY_SIZE - 4;
1451   CPU_PC_SET (cpu, bfd_get_start_address (prog_bfd));
1452
1453   /* Calculate the argument and environment strings.  */
1454   s_length = 0;
1455   nargs = 0;
1456   avp = argv;
1457   while (avp && *avp)
1458     {
1459       l = strlen (*avp) + 1;    /* include the null */
1460       s_length += (l + 3) & ~3; /* make it a 4 byte boundary */
1461       nargs++; avp++;
1462     }
1463
1464   nenv = 0;
1465   avp = env;
1466   while (avp && *avp)
1467     {
1468       l = strlen (*avp) + 1;    /* include the null */
1469       s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */
1470       nenv++; avp++;
1471     }
1472
1473   /* Claim some memory for the pointers and strings. */
1474   pointers = hi_stack - sizeof(int32_t) * (nenv+1+nargs+1);
1475   pointers &= ~3;               /* must be 4-byte aligned */
1476   gr[0] = pointers;
1477
1478   strings = gr[0] - s_length;
1479   strings &= ~3;                /* want to make it 4-byte aligned */
1480   gr[0] = strings;
1481   /* dac fix, the stack address must be 8-byte aligned! */
1482   gr[0] = gr[0] - gr[0] % 8;
1483
1484   /* Loop through the arguments and fill them in.  */
1485   gr[PARM1] = nargs;
1486   if (nargs == 0)
1487     {
1488       /* No strings to fill in.  */
1489       gr[PARM2] = 0;
1490     }
1491   else
1492     {
1493       gr[PARM2] = pointers;
1494       avp = argv;
1495       while (avp && *avp)
1496         {
1497           /* Save where we're putting it.  */
1498           wlat (pointers, strings);
1499
1500           /* Copy the string.  */
1501           l = strlen (* avp) + 1;
1502           sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l);
1503
1504           /* Bump the pointers.  */
1505           avp++;
1506           pointers += 4;
1507           strings += l+1;
1508         }
1509
1510       /* A null to finish the list.  */
1511       wlat (pointers, 0);
1512       pointers += 4;
1513     }
1514
1515   /* Now do the environment pointers.  */
1516   if (nenv == 0)
1517     {
1518       /* No strings to fill in.  */
1519       gr[PARM3] = 0;
1520     }
1521   else
1522     {
1523       gr[PARM3] = pointers;
1524       avp = env;
1525
1526       while (avp && *avp)
1527         {
1528           /* Save where we're putting it.  */
1529           wlat (pointers, strings);
1530
1531           /* Copy the string.  */
1532           l = strlen (* avp) + 1;
1533           sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l);
1534
1535           /* Bump the pointers.  */
1536           avp++;
1537           pointers += 4;
1538           strings += l+1;
1539         }
1540
1541       /* A null to finish the list.  */
1542       wlat (pointers, 0);
1543       pointers += 4;
1544     }
1545
1546   return SIM_RC_OK;
1547 }