]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/mcore/interp.c
1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 1999-2023 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
26 #include <sys/param.h>
29 #include "sim/callback.h"
30 #include "libiberty.h"
35 #include "sim-signal.h"
36 #include "sim-syscall.h"
37 #include "sim-options.h"
39 #include "target-newlib-syscall.h"
41 #include "mcore-sim.h"
43 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
47 mcore_extract_unsigned_integer (const unsigned char *addr
, int len
)
51 unsigned char * startaddr
= (unsigned char *)addr
;
52 unsigned char * endaddr
= startaddr
+ len
;
54 if (len
> (int) sizeof (unsigned long))
55 printf ("That operation is not available on integers of more than %zu bytes.",
56 sizeof (unsigned long));
58 /* Start at the most significant end of the integer, and work towards
59 the least significant. */
62 if (! target_big_endian
)
64 for (p
= endaddr
; p
> startaddr
;)
65 retval
= (retval
<< 8) | * -- p
;
69 for (p
= startaddr
; p
< endaddr
;)
70 retval
= (retval
<< 8) | * p
++;
77 mcore_store_unsigned_integer (unsigned char *addr
, int len
, unsigned long val
)
80 unsigned char * startaddr
= (unsigned char *)addr
;
81 unsigned char * endaddr
= startaddr
+ len
;
83 if (! target_big_endian
)
85 for (p
= startaddr
; p
< endaddr
;)
93 for (p
= endaddr
; p
> startaddr
;)
101 static int memcycles
= 1;
103 #define gr MCORE_SIM_CPU (cpu)->active_gregs
104 #define cr MCORE_SIM_CPU (cpu)->regs.cregs
119 /* maniuplate the carry bit */
120 #define C_ON() (sr & 1)
121 #define C_VALUE() (sr & 1)
122 #define C_OFF() ((sr & 1) == 0)
123 #define SET_C() {sr |= 1;}
124 #define CLR_C() {sr &= 0xfffffffe;}
125 #define NEW_C(v) {CLR_C(); sr |= ((v) & 1);}
127 #define SR_AF() ((sr >> 1) & 1)
128 static void set_active_regs (SIM_CPU
*cpu
)
130 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
133 mcore_cpu
->active_gregs
= mcore_cpu
->regs
.alt_gregs
;
135 mcore_cpu
->active_gregs
= mcore_cpu
->regs
.gregs
;
138 #define TRAPCODE 1 /* r1 holds which function we want */
139 #define PARM1 2 /* first parameter */
143 #define RET1 2 /* register for return values. */
145 /* Default to a 8 Mbyte (== 2^23) memory space. */
146 #define DEFAULT_MEMORY_SIZE 0x800000
149 set_initial_gprs (SIM_CPU
*cpu
)
151 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
153 /* Set up machine just out of reset. */
157 /* Clean out the GPRs and alternate GPRs. */
158 memset (&mcore_cpu
->regs
.gregs
, 0, sizeof(mcore_cpu
->regs
.gregs
));
159 memset (&mcore_cpu
->regs
.alt_gregs
, 0, sizeof(mcore_cpu
->regs
.alt_gregs
));
161 /* Make our register set point to the right place. */
162 set_active_regs (cpu
);
164 /* ABI specifies initial values for these registers. */
165 gr
[0] = DEFAULT_MEMORY_SIZE
- 4;
167 /* dac fix, the stack address must be 8-byte aligned! */
168 gr
[0] = gr
[0] - gr
[0] % 8;
175 /* Simulate a monitor trap. */
178 handle_trap1 (SIM_DESC sd
, SIM_CPU
*cpu
)
180 /* XXX: We don't pass back the actual errno value. */
181 gr
[RET1
] = sim_syscall (cpu
, gr
[TRAPCODE
], gr
[PARM1
], gr
[PARM2
], gr
[PARM3
],
186 process_stub (SIM_DESC sd
, SIM_CPU
*cpu
, int what
)
188 /* These values should match those in libgloss/mcore/syscalls.s. */
195 case 10: /* _unlink */
196 case 19: /* _lseek */
197 case 43: /* _times */
199 handle_trap1 (sd
, cpu
);
203 if (STATE_VERBOSE_P (sd
))
204 fprintf (stderr
, "Unhandled stub opcode: %d\n", what
);
210 util (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned what
)
212 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
217 sim_engine_halt (sd
, cpu
, NULL
, mcore_cpu
->regs
.pc
, sim_exited
, gr
[PARM1
]);
221 if (STATE_VERBOSE_P (sd
))
222 fprintf (stderr
, "WARNING: printf unimplemented\n");
226 if (STATE_VERBOSE_P (sd
))
227 fprintf (stderr
, "WARNING: scanf unimplemented\n");
231 gr
[RET1
] = mcore_cpu
->insts
;
235 process_stub (sd
, cpu
, gr
[1]);
239 if (STATE_VERBOSE_P (sd
))
240 fprintf (stderr
, "Unhandled util code: %x\n", what
);
245 /* For figuring out whether we carried; addc/subc use this. */
247 iu_carry (unsigned long a
, unsigned long b
, int cin
)
251 x
= (a
& 0xffff) + (b
& 0xffff) + cin
;
252 x
= (x
>> 16) + (a
>> 16) + (b
>> 16);
258 /* TODO: Convert to common watchpoints. */
259 #undef WATCHFUNCTIONS
260 #ifdef WATCHFUNCTIONS
277 #define RD (inst & 0xF)
278 #define RS ((inst >> 4) & 0xF)
279 #define RX ((inst >> 8) & 0xF)
280 #define IMM5 ((inst >> 4) & 0x1F)
281 #define IMM4 ((inst) & 0xF)
283 #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X)
284 #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X)
285 #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X)
286 #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
287 #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
288 #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
290 static int tracing
= 0;
293 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL)
296 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
298 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
308 #ifdef WATCHFUNCTIONS
312 pc
= CPU_PC_GET (cpu
);
314 /* Fetch the initial instructions that we'll decode. */
315 ibuf
= rlat (pc
& 0xFFFFFFFC);
322 /* make our register set point to the right place */
323 set_active_regs (cpu
);
325 #ifdef WATCHFUNCTIONS
326 /* make a hash to speed exec loop, hope it's nonzero */
329 for (w
= 1; w
<= ENDWL
; w
++)
330 WLhash
= WLhash
& WL
[w
];
333 /* TODO: Unindent this block. */
341 if (! target_big_endian
)
344 inst
= ibuf
& 0xFFFF;
349 if (! target_big_endian
)
350 inst
= ibuf
& 0xFFFF;
355 #ifdef WATCHFUNCTIONS
356 /* now scan list of watch addresses, if match, count it and
357 note return address and count cycles until pc=return address */
359 if ((WLincyc
== 1) && (pc
== WLendpc
))
361 cycs
= (mcore_cpu
->cycles
+ (insts
+ bonus_cycles
+
362 (memops
* memcycles
)) - WLbcyc
);
364 if (WLcnts
[WLW
] == 1)
371 if (cycs
> WLmax
[WLW
])
376 if (cycs
< WLmin
[WLW
])
386 /* Optimize with a hash to speed loop. */
389 if ((WLhash
== 0) || ((WLhash
& pc
) != 0))
391 for (w
=1; w
<= ENDWL
; w
++)
396 WLbcyc
= mcore_cpu
->cycles
+ insts
397 + bonus_cycles
+ (memops
* memcycles
);
409 fprintf (stderr
, "%.4x: inst = %.4x ", pc
, inst
);
425 sim_engine_halt (sd
, cpu
, NULL
, pc
- 2,
426 sim_stopped
, SIM_SIGTRAP
);
437 set_active_regs (cpu
);
445 set_active_regs (cpu
);
449 if (STATE_VERBOSE_P (sd
))
450 fprintf (stderr
, "WARNING: stop unimplemented\n");
454 if (STATE_VERBOSE_P (sd
))
455 fprintf (stderr
, "WARNING: wait unimplemented\n");
459 if (STATE_VERBOSE_P (sd
))
460 fprintf (stderr
, "WARNING: doze unimplemented\n");
464 ILLEGAL (); /* illegal */
467 case 0x8: /* trap 0 */
468 case 0xA: /* trap 2 */
469 case 0xB: /* trap 3 */
470 sim_engine_halt (sd
, cpu
, NULL
, pc
,
471 sim_stopped
, SIM_SIGTRAP
);
474 case 0xC: /* trap 4 */
475 case 0xD: /* trap 5 */
476 case 0xE: /* trap 6 */
477 ILLEGAL (); /* illegal */
480 case 0xF: /* trap 7 */
481 sim_engine_halt (sd
, cpu
, NULL
, pc
, /* integer div-by-0 */
482 sim_stopped
, SIM_SIGTRAP
);
485 case 0x9: /* trap 1 */
486 handle_trap1 (sd
, cpu
);
492 ILLEGAL (); /* illegal */
503 int32_t addr
= gr
[RD
];
504 int regno
= 4; /* always r4-r7 */
510 gr
[regno
] = rlat (addr
);
514 while ((regno
&0x3) != 0);
519 int32_t addr
= gr
[RD
];
520 int regno
= 4; /* always r4-r7 */
526 wlat (addr
, gr
[regno
]);
530 while ((regno
& 0x3) != 0);
535 int32_t addr
= gr
[0];
538 /* bonus cycle is really only needed if
539 the next insn shifts the last reg loaded.
546 gr
[regno
] = rlat (addr
);
554 int32_t addr
= gr
[0];
557 /* this should be removed! */
558 /* bonus_cycles ++; */
560 memops
+= 16 - regno
;
563 wlat (addr
, gr
[regno
]);
584 if (tracing
&& RD
== 15)
585 fprintf (stderr
, "Func return, r2 = %xx, r3 = %x\n",
600 for (i
= 0; !(tmp
& 0x80000000) && i
< 32; i
++)
609 tmp
= ((tmp
& 0xaaaaaaaa) >> 1) | ((tmp
& 0x55555555) << 1);
610 tmp
= ((tmp
& 0xcccccccc) >> 2) | ((tmp
& 0x33333333) << 2);
611 tmp
= ((tmp
& 0xf0f0f0f0) >> 4) | ((tmp
& 0x0f0f0f0f) << 4);
612 tmp
= ((tmp
& 0xff00ff00) >> 8) | ((tmp
& 0x00ff00ff) << 8);
613 gr
[RD
] = ((tmp
& 0xffff0000) >> 16) | ((tmp
& 0x0000ffff) << 16);
621 case 0x0: /* xtrb3 */
622 gr
[1] = (gr
[RD
]) & 0xFF;
625 case 0x1: /* xtrb2 */
626 gr
[1] = (gr
[RD
]>>8) & 0xFF;
629 case 0x2: /* xtrb1 */
630 gr
[1] = (gr
[RD
]>>16) & 0xFF;
633 case 0x3: /* xtrb0 */
634 gr
[1] = (gr
[RD
]>>24) & 0xFF;
637 case 0x4: /* zextb */
638 gr
[RD
] &= 0x000000FF;
640 case 0x5: /* sextb */
649 case 0x6: /* zexth */
650 gr
[RD
] &= 0x0000FFFF;
652 case 0x7: /* sexth */
661 case 0x8: /* declt */
663 NEW_C ((long)gr
[RD
] < 0);
665 case 0x9: /* tstnbz */
667 int32_t tmp
= gr
[RD
];
668 NEW_C ((tmp
& 0xFF000000) != 0 &&
669 (tmp
& 0x00FF0000) != 0 && (tmp
& 0x0000FF00) != 0 &&
670 (tmp
& 0x000000FF) != 0);
673 case 0xA: /* decgt */
675 NEW_C ((long)gr
[RD
] > 0);
677 case 0xB: /* decne */
679 NEW_C ((long)gr
[RD
] != 0);
690 if (gr
[RD
] & 0x80000000)
691 gr
[RD
] = ~gr
[RD
] + 1;
698 case 0x02: /* movt */
702 case 0x03: /* mult */
703 /* consume 2 bits per cycle from rs, until rs is 0 */
705 unsigned int t
= gr
[RS
];
707 for (ticks
= 0; t
!= 0 ; t
>>= 2)
709 bonus_cycles
+= ticks
;
711 bonus_cycles
+= 2; /* min. is 3, so add 2, plus ticks above */
713 fprintf (stderr
, " mult %x by %x to give %x",
714 gr
[RD
], gr
[RS
], gr
[RD
] * gr
[RS
]);
715 gr
[RD
] = gr
[RD
] * gr
[RS
];
717 case 0x04: /* loopt */
720 pc
+= (IMM4
<< 1) - 32;
724 --gr
[RS
]; /* not RD! */
725 NEW_C (((long)gr
[RS
]) > 0);
727 case 0x05: /* subu */
730 case 0x06: /* addc */
732 unsigned long tmp
, a
, b
;
735 gr
[RD
] = a
+ b
+ C_VALUE ();
736 tmp
= iu_carry (a
, b
, C_VALUE ());
740 case 0x07: /* subc */
742 unsigned long tmp
, a
, b
;
745 gr
[RD
] = a
- b
+ C_VALUE () - 1;
746 tmp
= iu_carry (a
,~b
, C_VALUE ());
750 case 0x08: /* illegal */
751 case 0x09: /* illegal*/
754 case 0x0A: /* movf */
760 unsigned long dst
, src
;
763 /* We must not rely solely upon the native shift operations, since they
764 may not match the M*Core's behaviour on boundary conditions. */
765 dst
= src
> 31 ? 0 : dst
>> src
;
769 case 0x0C: /* cmphs */
770 NEW_C ((unsigned long )gr
[RD
] >=
771 (unsigned long)gr
[RS
]);
773 case 0x0D: /* cmplt */
774 NEW_C ((long)gr
[RD
] < (long)gr
[RS
]);
777 NEW_C ((gr
[RD
] & gr
[RS
]) != 0);
779 case 0x0F: /* cmpne */
780 NEW_C (gr
[RD
] != gr
[RS
]);
782 case 0x10: case 0x11: /* mfcr */
786 if (r
<= LAST_VALID_CREG
)
796 fprintf (stderr
, "MOV %x into reg %d", gr
[RD
], RD
);
799 case 0x13: /* bgenr */
803 gr
[RD
] = 1 << (gr
[RS
] & 0x1F);
806 case 0x14: /* rsub */
807 gr
[RD
] = gr
[RS
] - gr
[RD
];
822 case 0x18: case 0x19: /* mtcr */
826 if (r
<= LAST_VALID_CREG
)
831 /* we might have changed register sets... */
832 set_active_regs (cpu
);
837 /* We must not rely solely upon the native shift operations, since they
838 may not match the M*Core's behaviour on boundary conditions. */
840 gr
[RD
] = ((long) gr
[RD
]) < 0 ? -1 : 0;
842 gr
[RD
] = (long) gr
[RD
] >> gr
[RS
];
846 /* We must not rely solely upon the native shift operations, since they
847 may not match the M*Core's behaviour on boundary conditions. */
848 gr
[RD
] = gr
[RS
] > 31 ? 0 : gr
[RD
] << gr
[RS
];
851 case 0x1C: /* addu */
856 gr
[RD
] += gr
[RS
] << 1;
863 case 0x1F: /* andn */
866 case 0x20: case 0x21: /* addi */
870 case 0x22: case 0x23: /* cmplti */
872 int tmp
= (IMM5
+ 1);
883 case 0x24: case 0x25: /* subi */
887 case 0x26: case 0x27: /* illegal */
890 case 0x28: case 0x29: /* rsubi */
894 case 0x2A: case 0x2B: /* cmpnei */
905 case 0x2C: case 0x2D: /* bmaski, divu */
919 /* unsigned divide */
920 gr
[RD
] = (int32_t) ((unsigned int) gr
[RD
] / (unsigned int)gr
[1] );
922 /* compute bonus_cycles for divu */
923 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32); r1nlz
++)
926 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32); rxnlz
++)
932 exe
+= 5 + r1nlz
- rxnlz
;
934 if (exe
>= (2 * memcycles
- 1))
936 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
939 else if (imm
== 0 || imm
>= 8)
945 gr
[RD
] = (1 << imm
) - 1;
954 case 0x2E: case 0x2F: /* andi */
955 gr
[RD
] = gr
[RD
] & IMM5
;
957 case 0x30: case 0x31: /* bclri */
958 gr
[RD
] = gr
[RD
] & ~(1<<IMM5
);
960 case 0x32: case 0x33: /* bgeni, divs */
969 /* compute bonus_cycles for divu */
974 if (((rx
< 0) && (r1
> 0)) || ((rx
>= 0) && (r1
< 0)))
982 /* signed divide, general registers are of type int, so / op is OK */
983 gr
[RD
] = gr
[RD
] / gr
[1];
985 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32) ; r1nlz
++ )
988 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32) ; rxnlz
++ )
994 exe
+= 6 + r1nlz
- rxnlz
+ sc
;
996 if (exe
>= (2 * memcycles
- 1))
998 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
1004 gr
[RD
] = (1 << IMM5
);
1013 case 0x34: case 0x35: /* bseti */
1014 gr
[RD
] = gr
[RD
] | (1 << IMM5
);
1016 case 0x36: case 0x37: /* btsti */
1017 NEW_C (gr
[RD
] >> IMM5
);
1019 case 0x38: case 0x39: /* xsr, rotli */
1021 unsigned imm
= IMM5
;
1022 unsigned long tmp
= gr
[RD
];
1028 gr
[RD
] = (cbit
<< 31) | (tmp
>> 1);
1031 gr
[RD
] = (tmp
<< imm
) | (tmp
>> (32 - imm
));
1034 case 0x3A: case 0x3B: /* asrc, asri */
1036 unsigned imm
= IMM5
;
1044 gr
[RD
] = tmp
>> imm
;
1047 case 0x3C: case 0x3D: /* lslc, lsli */
1049 unsigned imm
= IMM5
;
1050 unsigned long tmp
= gr
[RD
];
1057 gr
[RD
] = tmp
<< imm
;
1060 case 0x3E: case 0x3F: /* lsrc, lsri */
1062 unsigned imm
= IMM5
;
1063 unsigned long tmp
= gr
[RD
];
1070 gr
[RD
] = tmp
>> imm
;
1073 case 0x40: case 0x41: case 0x42: case 0x43:
1074 case 0x44: case 0x45: case 0x46: case 0x47:
1075 case 0x48: case 0x49: case 0x4A: case 0x4B:
1076 case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1080 util (sd
, cpu
, inst
& 0xFF);
1082 case 0x51: case 0x52: case 0x53:
1083 case 0x54: case 0x55: case 0x56: case 0x57:
1084 case 0x58: case 0x59: case 0x5A: case 0x5B:
1085 case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1088 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */
1089 case 0x64: case 0x65: case 0x66: case 0x67:
1090 gr
[RD
] = (inst
>> 4) & 0x7F;
1092 case 0x68: case 0x69: case 0x6A: case 0x6B:
1093 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */
1096 case 0x71: case 0x72: case 0x73:
1097 case 0x74: case 0x75: case 0x76: case 0x77:
1098 case 0x78: case 0x79: case 0x7A: case 0x7B:
1099 case 0x7C: case 0x7D: case 0x7E: /* lrw */
1100 gr
[RX
] = rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1102 fprintf (stderr
, "LRW of 0x%x from 0x%x to reg %d",
1103 rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC),
1104 (pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC, RX
);
1107 case 0x7F: /* jsri */
1111 "func call: r2 = %x r3 = %x r4 = %x r5 = %x r6 = %x r7 = %x\n",
1112 gr
[2], gr
[3], gr
[4], gr
[5], gr
[6], gr
[7]);
1113 case 0x70: /* jmpi */
1114 pc
= rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1120 case 0x80: case 0x81: case 0x82: case 0x83:
1121 case 0x84: case 0x85: case 0x86: case 0x87:
1122 case 0x88: case 0x89: case 0x8A: case 0x8B:
1123 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */
1124 gr
[RX
] = rlat (gr
[RD
] + ((inst
>> 2) & 0x003C));
1126 fprintf (stderr
, "load reg %d from 0x%x with 0x%x",
1128 gr
[RD
] + ((inst
>> 2) & 0x003C), gr
[RX
]);
1131 case 0x90: case 0x91: case 0x92: case 0x93:
1132 case 0x94: case 0x95: case 0x96: case 0x97:
1133 case 0x98: case 0x99: case 0x9A: case 0x9B:
1134 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */
1135 wlat (gr
[RD
] + ((inst
>> 2) & 0x003C), gr
[RX
]);
1137 fprintf (stderr
, "store reg %d (containing 0x%x) to 0x%x",
1139 gr
[RD
] + ((inst
>> 2) & 0x003C));
1142 case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1143 case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1144 case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1145 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */
1146 gr
[RX
] = rbat (gr
[RD
] + RS
);
1149 case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1150 case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1151 case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1152 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */
1153 wbat (gr
[RD
] + RS
, gr
[RX
]);
1156 case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1157 case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1158 case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1159 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */
1160 gr
[RX
] = rhat (gr
[RD
] + ((inst
>> 3) & 0x001E));
1163 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1164 case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1165 case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1166 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */
1167 what (gr
[RD
] + ((inst
>> 3) & 0x001E), gr
[RX
]);
1170 case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1171 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */
1175 disp
= inst
& 0x03FF;
1183 case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1184 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */
1188 disp
= inst
& 0x03FF;
1197 case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1198 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */
1200 case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1201 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */
1204 disp
= inst
& 0x03FF;
1216 fprintf (stderr
, "\n");
1220 ibuf
= rlat (pc
& 0xFFFFFFFC);
1225 /* Hide away the things we've cached while executing. */
1226 CPU_PC_SET (cpu
, pc
);
1227 mcore_cpu
->insts
+= insts
; /* instructions done ... */
1228 mcore_cpu
->cycles
+= insts
; /* and each takes a cycle */
1229 mcore_cpu
->cycles
+= bonus_cycles
; /* and extra cycles for branches */
1230 mcore_cpu
->cycles
+= memops
* memcycles
; /* and memop cycle delays */
1234 sim_engine_run (SIM_DESC sd
,
1235 int next_cpu_nr
, /* ignore */
1236 int nr_cpus
, /* ignore */
1237 int siggnal
) /* ignore */
1241 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1243 cpu
= STATE_CPU (sd
, 0);
1247 step_once (sd
, cpu
);
1248 if (sim_events_tick (sd
))
1249 sim_events_process (sd
);
1254 mcore_reg_store (SIM_CPU
*cpu
, int rn
, const void *memory
, int length
)
1256 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
1258 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1264 /* misalignment safe */
1265 ival
= mcore_extract_unsigned_integer (memory
, 4);
1266 mcore_cpu
->asints
[rn
] = ival
;
1276 mcore_reg_fetch (SIM_CPU
*cpu
, int rn
, void *memory
, int length
)
1278 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
1280 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1284 long ival
= mcore_cpu
->asints
[rn
];
1286 /* misalignment-safe */
1287 mcore_store_unsigned_integer (memory
, 4, ival
);
1297 sim_info (SIM_DESC sd
, int verbose
)
1299 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1300 struct mcore_sim_cpu
*mcore_cpu
= MCORE_SIM_CPU (cpu
);
1301 #ifdef WATCHFUNCTIONS
1304 double virttime
= mcore_cpu
->cycles
/ 36.0e6
;
1305 host_callback
*callback
= STATE_CALLBACK (sd
);
1307 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
1309 callback
->printf_filtered (callback
, "# cycles %10d\n",
1311 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
1313 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
1316 #ifdef WATCHFUNCTIONS
1317 callback
->printf_filtered (callback
, "\nNumber of watched functions: %d\n",
1322 for (w
= 1; w
<= ENDWL
; w
++)
1324 callback
->printf_filtered (callback
, "WL = %s %8x\n",WLstr
[w
],WL
[w
]);
1325 callback
->printf_filtered (callback
, " calls = %d, cycles = %d\n",
1326 WLcnts
[w
],WLcyc
[w
]);
1329 callback
->printf_filtered (callback
,
1330 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
1331 WLmax
[w
],WLmin
[w
],WLcyc
[w
]/WLcnts
[w
]);
1335 callback
->printf_filtered (callback
,
1336 "Total cycles for watched functions: %d\n",wcyc
);
1341 mcore_pc_get (sim_cpu
*cpu
)
1343 return MCORE_SIM_CPU (cpu
)->regs
.pc
;
1347 mcore_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1349 MCORE_SIM_CPU (cpu
)->regs
.pc
= pc
;
1353 free_state (SIM_DESC sd
)
1355 if (STATE_MODULES (sd
) != NULL
)
1356 sim_module_uninstall (sd
);
1357 sim_cpu_free_all (sd
);
1358 sim_state_free (sd
);
1362 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
1363 struct bfd
*abfd
, char * const *argv
)
1366 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1367 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1369 /* Set default options before parsing user options. */
1370 cb
->syscall_map
= cb_mcore_syscall_map
;
1372 /* The cpu data is kept in a separately allocated chunk of memory. */
1373 if (sim_cpu_alloc_all_extra (sd
, 0, sizeof (struct mcore_sim_cpu
))
1380 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1386 /* The parser will print an error message for us, so we silently return. */
1387 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1393 /* Check for/establish the a reference program image. */
1394 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
1400 /* Configure/verify the target byte order and other runtime
1401 configuration options. */
1402 if (sim_config (sd
) != SIM_RC_OK
)
1404 sim_module_uninstall (sd
);
1408 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1410 /* Uninstall the modules to avoid memory leaks,
1411 file descriptor leaks, etc. */
1412 sim_module_uninstall (sd
);
1416 /* CPU specific initialization. */
1417 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1419 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1421 CPU_REG_FETCH (cpu
) = mcore_reg_fetch
;
1422 CPU_REG_STORE (cpu
) = mcore_reg_store
;
1423 CPU_PC_FETCH (cpu
) = mcore_pc_get
;
1424 CPU_PC_STORE (cpu
) = mcore_pc_set
;
1426 set_initial_gprs (cpu
); /* Reset the GPR registers. */
1429 /* Default to a 8 Mbyte (== 2^23) memory space. */
1430 sim_do_commandf (sd
, "memory-size %#x", DEFAULT_MEMORY_SIZE
);
1436 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
1437 char * const *argv
, char * const *env
)
1439 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1445 unsigned long strings
;
1446 unsigned long pointers
;
1447 unsigned long hi_stack
;
1450 /* Set the initial register set. */
1451 set_initial_gprs (cpu
);
1453 hi_stack
= DEFAULT_MEMORY_SIZE
- 4;
1454 CPU_PC_SET (cpu
, bfd_get_start_address (prog_bfd
));
1456 /* Calculate the argument and environment strings. */
1462 l
= strlen (*avp
) + 1; /* include the null */
1463 s_length
+= (l
+ 3) & ~3; /* make it a 4 byte boundary */
1471 l
= strlen (*avp
) + 1; /* include the null */
1472 s_length
+= (l
+ 3) & ~ 3;/* make it a 4 byte boundary */
1476 /* Claim some memory for the pointers and strings. */
1477 pointers
= hi_stack
- sizeof(int32_t) * (nenv
+1+nargs
+1);
1478 pointers
&= ~3; /* must be 4-byte aligned */
1481 strings
= gr
[0] - s_length
;
1482 strings
&= ~3; /* want to make it 4-byte aligned */
1484 /* dac fix, the stack address must be 8-byte aligned! */
1485 gr
[0] = gr
[0] - gr
[0] % 8;
1487 /* Loop through the arguments and fill them in. */
1491 /* No strings to fill in. */
1496 gr
[PARM2
] = pointers
;
1500 /* Save where we're putting it. */
1501 wlat (pointers
, strings
);
1503 /* Copy the string. */
1504 l
= strlen (* avp
) + 1;
1505 sim_core_write_buffer (sd
, cpu
, write_map
, *avp
, strings
, l
);
1507 /* Bump the pointers. */
1513 /* A null to finish the list. */
1518 /* Now do the environment pointers. */
1521 /* No strings to fill in. */
1526 gr
[PARM3
] = pointers
;
1531 /* Save where we're putting it. */
1532 wlat (pointers
, strings
);
1534 /* Copy the string. */
1535 l
= strlen (* avp
) + 1;
1536 sim_core_write_buffer (sd
, cpu
, write_map
, *avp
, strings
, l
);
1538 /* Bump the pointers. */
1544 /* A null to finish the list. */