sim/mips/ChangeLog

   1 2011-07-05  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * interp.c (sim_do_command): Delete.
   4
   5 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
   8         (tx3904sio_fifo_reset): Likewise.
   9         * interp.c (sim_monitor): Likewise.
  10
  11 2010-04-14  Mike Frysinger  <vapier@gentoo.org>
  12
  13         * interp.c (sim_write): Add const to buffer arg.
  14
  15 2010-01-18  Masaki Muranaka  <monaka@monami-software.com>  (tiny change)
  16
  17         * interp.c: Don't include sysdep.h
  18
  19 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  20
  21         * configure: Regenerate.
  22
  23 2009-08-22  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  24
  25         * config.in: Regenerate.
  26         * configure: Likewise.
  27
  28         * configure: Regenerate.
  29
  30 2008-07-11  Hans-Peter Nilsson  <hp@axis.com>
  31
  32         * configure: Regenerate to track ../common/common.m4 changes.
  33         * config.in: Ditto.
  34
  35 2008-06-06  Vladimir Prus  <vladimir@codesourcery.com>
  36             Daniel Jacobowitz  <dan@codesourcery.com>
  37             Joseph Myers  <joseph@codesourcery.com>
  38
  39         * configure: Regenerate.
  40
  41 2007-10-22  Richard Sandiford  <rsandifo@nildram.co.uk>
  42
  43         * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
  44         that unconditionally allows fmt_ps.
  45         (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
  46         (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
  47         (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
  48         filter from 64,f to 32,f.
  49         (PREFX): Change filter from 64 to 32.
  50         (LDXC1, LUXC1): Provide separate mips32r2 implementations
  51         that use do_load_double instead of do_load.  Make both LUXC1
  52         versions unpredictable if SizeFGR () != 64.
  53         (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
  54         instead of do_store.  Remove unused variable.  Make both SUXC1
  55         versions unpredictable if SizeFGR () != 64.
  56
  57 2007-10-07  Richard Sandiford  <rsandifo@nildram.co.uk>
  58
  59         * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
  60         (sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
  61         shifts for that case.
  62
  63 2007-09-04  Nick Clifton  <nickc@redhat.com>
  64
  65         * interp.c (options enum): Add OPTION_INFO_MEMORY.
  66         (display_mem_info): New static variable.
  67         (mips_option_handler): Handle OPTION_INFO_MEMORY.
  68         (mips_options): Add info-memory and memory-info.
  69         (sim_open): After processing the command line and board
  70         specification, check display_mem_info.  If it is set then
  71         call the real handler for the --memory-info command line
  72         switch.
  73
  74 2007-08-24  Joel Brobecker  <brobecker@adacore.com>
  75
  76         * configure.ac: Change license of multi-run.c to GPL version 3.
  77         * configure: Regenerate.
  78
  79 2007-06-28  Richard Sandiford  <richard@codesourcery.com>
  80
  81         * configure.ac, configure: Revert last patch.
  82
  83 2007-06-26  Richard Sandiford  <richard@codesourcery.com>
  84
  85         * configure.ac (sim_mipsisa3264_configs): New variable.
  86         (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
  87         every configuration support all four targets, using the triplet to
  88         determine the default.
  89         * configure: Regenerate.
  90
  91 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
  92
  93         * Makefile.in (m16run.o): New rule.
  94
  95 2007-05-15  Thiemo Seufer  <ths@mips.com>
  96
  97         * mips3264r2.igen (DSHD): Fix compile warning.
  98
  99 2007-05-14  Thiemo Seufer  <ths@mips.com>
 100
 101         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
 102         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
 103         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
 104         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
 105         for mips32r2.
 106
 107 2007-03-01  Thiemo Seufer  <ths@mips.com>
 108
 109         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
 110         and mips64.
 111
 112 2007-02-20  Thiemo Seufer  <ths@mips.com>
 113
 114         * dsp.igen: Update copyright notice.
 115         * dsp2.igen: Fix copyright notice.
 116
 117 2007-02-20  Thiemo Seufer  <ths@mips.com>
 118             Chao-Ying Fu  <fu@mips.com>
 119
 120         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
 121         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 122         Add dsp2 to sim_igen_machine.
 123         * configure: Regenerate.
 124         * dsp.igen (do_ph_op): Add MUL support when op = 2.
 125         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
 126         (mulq_rs.ph): Use do_ph_mulq.
 127         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
 128         * mips.igen: Add dsp2 model and include dsp2.igen.
 129         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
 130         for *mips32r2, *mips64r2, *dsp.
 131         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
 132         for *mips32r2, *mips64r2, *dsp2.
 133         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
 134
 135 2007-02-19  Thiemo Seufer  <ths@mips.com>
 136             Nigel Stephens  <nigel@mips.com>
 137
 138         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
 139         jumps with hazard barrier.
 140
 141 2007-02-19  Thiemo Seufer  <ths@mips.com>
 142             Nigel Stephens  <nigel@mips.com>
 143
 144         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
 145         after each call to sim_io_write.
 146
 147 2007-02-19  Thiemo Seufer  <ths@mips.com>
 148             Nigel Stephens  <nigel@mips.com>
 149
 150         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
 151         supported by this simulator.
 152         (decode_coproc): Recognise additional CP0 Config registers
 153         correctly.
 154
 155 2007-02-19  Thiemo Seufer  <ths@mips.com>
 156             Nigel Stephens  <nigel@mips.com>
 157             David Ung  <davidu@mips.com>
 158
 159         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
 160         uninterpreted formats. If fmt is one of the uninterpreted types
 161         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
 162         fmt_word, and fmt_uninterpreted_64 like fmt_long.
 163         (store_fpr): When writing an invalid odd register, set the
 164         matching even register to fmt_unknown, not the following register.
 165         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
 166         the the memory window at offset 0 set by --memory-size command
 167         line option.
 168         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
 169         point register.
 170         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
 171         register.
 172         (sim_monitor): When returning the memory size to the MIPS
 173         application, use the value in STATE_MEM_SIZE, not an arbitrary
 174         hardcoded value.
 175         (cop_lw): Don' mess around with FPR_STATE, just pass
 176         fmt_uninterpreted_32 to StoreFPR.
 177         (cop_sw): Similarly.
 178         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
 179         (cop_sd): Similarly.
 180         * mips.igen (not_word_value): Single version for mips32, mips64
 181         and mips16.
 182
 183 2007-02-19  Thiemo Seufer <ths@mips.com>
 184             Nigel Stephens  <nigel@mips.com>
 185
 186         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
 187         MBytes.
 188
 189 2007-02-17  Thiemo Seufer  <ths@mips.com>
 190
 191         * configure.ac (mips*-sde-elf*): Move in front of generic machine
 192         configuration.
 193         * configure: Regenerate.
 194
 195 2007-02-17  Thiemo Seufer  <ths@mips.com>
 196
 197         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 198         Add mdmx to sim_igen_machine.
 199         (mipsisa64*-*-*): Likewise. Remove dsp.
 200         (mipsisa32*-*-*): Remove dsp.
 201         * configure: Regenerate.
 202
 203 2007-02-13  Thiemo Seufer  <ths@mips.com>
 204
 205         * configure.ac: Add mips*-sde-elf* target.
 206         * configure: Regenerate.
 207
 208 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 209
 210         * acconfig.h: Remove.
 211         * config.in, configure: Regenerate.
 212
 213 2006-11-07  Thiemo Seufer  <ths@mips.com>
 214
 215         * dsp.igen (do_w_op): Fix compiler warning.
 216
 217 2006-08-29  Thiemo Seufer  <ths@mips.com>
 218             David Ung  <davidu@mips.com>
 219
 220         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 221         sim_igen_machine.
 222         * configure: Regenerate.
 223         * mips.igen (model): Add smartmips.
 224         (MADDU): Increment ACX if carry.
 225         (do_mult): Clear ACX.
 226         (ROR,RORV): Add smartmips.
 227         (include): Include smartmips.igen.
 228         * sim-main.h (ACX): Set to REGISTERS[89].
 229         * smartmips.igen: New file.
 230
 231 2006-08-29  Thiemo Seufer  <ths@mips.com>
 232             David Ung  <davidu@mips.com>
 233
 234         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 235         mips3264r2.igen. Add missing dependency rules.
 236         * m16e.igen: Support for mips16e save/restore instructions.
 237
 238 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 239
 240         * configure: Regenerated.
 241
 242 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 243
 244         * configure: Regenerated.
 245
 246 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 247
 248         * configure: Regenerated.
 249
 250 2006-05-15 Chao-ying Fu  <fu@mips.com>
 251
 252         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 253
 254 2006-04-18  Nick Clifton  <nickc@redhat.com>
 255
 256         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 257         statement.
 258
 259 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 260
 261         * configure: Regenerate.
 262
 263 2005-12-14  Chao-ying Fu  <fu@mips.com>
 264
 265         * Makefile.in (SIM_OBJS): Add dsp.o.
 266         (dsp.o): New dependency.
 267         (IGEN_INCLUDE): Add dsp.igen.
 268         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 269         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 270         * configure: Regenerate.
 271         * mips.igen: Add dsp model and include dsp.igen.
 272         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 273         because these instructions are extended in DSP ASE.
 274         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 275         adding 6 DSP accumulator registers and 1 DSP control register.
 276         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 277         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 278         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 279         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 280         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 281         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 282         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 283         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 284         DSPCR_CCOND_SMASK): New define.
 285         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 286         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 287
 288 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 289
 290         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 291
 292 2005-06-16  David Ung  <davidu@mips.com>
 293             Nigel Stephens  <nigel@mips.com>
 294
 295         * mips.igen: New mips16e model and include m16e.igen.
 296         (check_u64): Add mips16e tag.
 297         * m16e.igen: New file for MIPS16e instructions.
 298         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 299         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 300         models.
 301         * configure: Regenerate.
 302
 303 2005-05-26  David Ung  <davidu@mips.com>
 304
 305         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 306         tags to all instructions which are applicable to the new ISAs.
 307         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 308         vr.igen.
 309         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 310         instructions.
 311         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 312         to mips.igen.
 313         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 314         * configure: Regenerate.
 315
 316 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 317
 318         * configure: Regenerate.
 319
 320 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 321
 322         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 323         explicit call to AC_CONFIG_HEADER.
 324         * configure: Regenerate.
 325
 326 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 327
 328         * configure.ac: Update to use ../common/common.m4.
 329         * configure: Re-generate.
 330
 331 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 332
 333         * configure: Regenerated to track ../common/aclocal.m4 changes.
 334
 335 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 336
 337         * configure.ac: Rename configure.in, require autoconf 2.59.
 338         * configure: Re-generate.
 339
 340 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 341
 342         * configure: Regenerate for ../common/aclocal.m4 update.
 343
 344 2004-09-24  Monika Chaddha  <monika@acmet.com>
 345
 346         Committed by Andrew Cagney.
 347         * m16.igen (CMP, CMPI): Fix assembler.
 348
 349 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 350
 351         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 352         * configure: Regenerate.
 353
 354 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 355
 356         * configure.in (sim_m16_machine): Include mipsIII.
 357         * configure: Regenerate.
 358
 359 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 360
 361         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 362         from COP0_BADVADDR.
 363         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 364
 365 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 366
 367         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 368
 369 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 370
 371         * mips.igen (check_fmt): Remove.
 372         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 373         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 374         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 375         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 376         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 377         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 378         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 379         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 380         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 381         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 382
 383 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * sb1.igen (check_sbx): New function.
 386         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 387
 388 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 389             Richard Sandiford  <rsandifo@redhat.com>
 390
 391         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 392         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 393         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 394         separate implementations for mipsIV and mipsV.  Use new macros to
 395         determine whether the restrictions apply.
 396
 397 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 398
 399         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 400         (check_mult_hilo): Improve comments.
 401         (check_div_hilo): Likewise.  Also, fork off a new version
 402         to handle mips32/mips64 (since there are no hazards to check
 403         in MIPS32/MIPS64).
 404
 405 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 406
 407         * mips.igen (do_dmultx): Fix check for negative operands.
 408
 409 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 410
 411         * Makefile.in (SHELL): Make sure this is defined.
 412         (various): Use $(SHELL) whenever we invoke move-if-change.
 413
 414 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 415
 416         * cp1.c: Tweak attribution slightly.
 417         * cp1.h: Likewise.
 418         * mdmx.c: Likewise.
 419         * mdmx.igen: Likewise.
 420         * mips3d.igen: Likewise.
 421         * sb1.igen: Likewise.
 422
 423 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 424
 425         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 426         unsigned operands.
 427
 428 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 429
 430         * interp.c (sim_open): Rename _bfd to bfd.
 431         (sim_create_inferior): Ditto.
 432
 433 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 434
 435         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 436
 437 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 438
 439         * mips.igen (EI, DI): Remove.
 440
 441 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 442
 443         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 444
 445 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 446             Andrew Cagney  <ac131313@redhat.com>
 447             Gavin Romig-Koch  <gavin@redhat.com>
 448             Graydon Hoare  <graydon@redhat.com>
 449             Aldy Hernandez  <aldyh@redhat.com>
 450             Dave Brolley  <brolley@redhat.com>
 451             Chris Demetriou  <cgd@broadcom.com>
 452
 453         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 454         (sim_mach_default): New variable.
 455         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 456         Add a new simulator generator, MULTI.
 457         * configure: Regenerate.
 458         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 459         (multi-run.o): New dependency.
 460         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 461         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 462         (tmp-multi): Combine them.
 463         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 464         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 465         (distclean-extra): New rule.
 466         * sim-main.h: Include bfd.h.
 467         (MIPS_MACH): New macro.
 468         * mips.igen (vr4120, vr5400, vr5500): New models.
 469         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 470         * vr.igen: Replace with new version.
 471
 472 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 473
 474         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 475         * configure: Regenerate.
 476
 477 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 478
 479         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 480         * mips.igen: Remove all invocations of check_branch_bug and
 481         mark_branch_bug.
 482
 483 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 484
 485         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 486
 487 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 488
 489         * mips.igen (do_load_double, do_store_double): New functions.
 490         (LDC1, SDC1): Rename to...
 491         (LDC1b, SDC1b): respectively.
 492         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 493
 494 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 495
 496         * cp1.c (fp_recip2): Modify initialization expression so that
 497         GCC will recognize it as constant.
 498
 499 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 500
 501         * mdmx.c (SD_): Delete.
 502         (Unpredictable): Re-define, for now, to directly invoke
 503         unpredictable_action().
 504         (mdmx_acc_op): Fix error in .ob immediate handling.
 505
 506 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 507
 508         * interp.c (sim_firmware_command): Initialize `address'.
 509
 510 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 511
 512         * configure: Regenerated to track ../common/aclocal.m4 changes.
 513
 514 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 515             Ed Satterthwaite  <ehs@broadcom.com>
 516
 517         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 518         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 519         * mips.igen: Include mips3d.igen.
 520         (mips3d): New model name for MIPS-3D ASE instructions.
 521         (CVT.W.fmt): Don't use this instruction for word (source) format
 522         instructions.
 523         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 524         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 525         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 526         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 527         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 528         (RSquareRoot1, RSquareRoot2): New macros.
 529         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 530         (fp_rsqrt2): New functions.
 531         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 532         * configure: Regenerate.
 533
 534 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 535             Ed Satterthwaite  <ehs@broadcom.com>
 536
 537         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 538         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 539         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 540         (convert): Note that this function is not used for paired-single
 541         format conversions.
 542         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 543         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 544         (check_fmt_p): Enable paired-single support.
 545         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 546         (PUU.PS): New instructions.
 547         (CVT.S.fmt): Don't use this instruction for paired-single format
 548         destinations.
 549         * sim-main.h (FP_formats): New value 'fmt_ps.'
 550         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 551         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 552
 553 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 554
 555         * mips.igen: Fix formatting of function calls in
 556         many FP operations.
 557
 558 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 559
 560         * mips.igen (MOVN, MOVZ): Trace result.
 561         (TNEI): Print "tnei" as the opcode name in traces.
 562         (CEIL.W): Add disassembly string for traces.
 563         (RSQRT.fmt): Make location of disassembly string consistent
 564         with other instructions.
 565
 566 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 567
 568         * mips.igen (X): Delete unused function.
 569
 570 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 571
 572         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 573
 574 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 575             Ed Satterthwaite  <ehs@broadcom.com>
 576
 577         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 578         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 579         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 580         (fp_nmsub): New prototypes.
 581         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 582         (NegMultiplySub): New defines.
 583         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 584         (MADD.D, MADD.S): Replace with...
 585         (MADD.fmt): New instruction.
 586         (MSUB.D, MSUB.S): Replace with...
 587         (MSUB.fmt): New instruction.
 588         (NMADD.D, NMADD.S): Replace with...
 589         (NMADD.fmt): New instruction.
 590         (NMSUB.D, MSUB.S): Replace with...
 591         (NMSUB.fmt): New instruction.
 592
 593 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 594             Ed Satterthwaite  <ehs@broadcom.com>
 595
 596         * cp1.c: Fix more comment spelling and formatting.
 597         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 598         (denorm_mode): New function.
 599         (fpu_unary, fpu_binary): Round results after operation, collect
 600         status from rounding operations, and update the FCSR.
 601         (convert): Collect status from integer conversions and rounding
 602         operations, and update the FCSR.  Adjust NaN values that result
 603         from conversions.  Convert to use sim_io_eprintf rather than
 604         fprintf, and remove some debugging code.
 605         * cp1.h (fenr_FS): New define.
 606
 607 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 608
 609         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 610         rounding mode to sim FP rounding mode flag conversion code into...
 611         (rounding_mode): New function.
 612
 613 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 614
 615         * cp1.c: Clean up formatting of a few comments.
 616         (value_fpr): Reformat switch statement.
 617
 618 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 619             Ed Satterthwaite  <ehs@broadcom.com>
 620
 621         * cp1.h: New file.
 622         * sim-main.h: Include cp1.h.
 623         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 624         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 625         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 626         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 627         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 628         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 629         * cp1.c: Don't include sim-fpu.h; already included by
 630         sim-main.h.  Clean up formatting of some comments.
 631         (NaN, Equal, Less): Remove.
 632         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 633         (fp_cmp): New functions.
 634         * mips.igen (do_c_cond_fmt): Remove.
 635         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 636         Compare.  Add result tracing.
 637         (CxC1): Remove, replace with...
 638         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 639         (DMxC1): Remove, replace with...
 640         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 641         (MxC1): Remove, replace with...
 642         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 643
 644 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 645
 646         * sim-main.h (FGRIDX): Remove, replace all uses with...
 647         (FGR_BASE): New macro.
 648         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 649         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 650         (NR_FGR, FGR): Likewise.
 651         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 652         * mips.igen: Likewise.
 653
 654 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 655
 656         * cp1.c: Add an FSF Copyright notice to this file.
 657
 658 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 659             Ed Satterthwaite  <ehs@broadcom.com>
 660
 661         * cp1.c (Infinity): Remove.
 662         * sim-main.h (Infinity): Likewise.
 663
 664         * cp1.c (fp_unary, fp_binary): New functions.
 665         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 666         (fp_sqrt): New functions, implemented in terms of the above.
 667         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 668         (Recip, SquareRoot): Remove (replaced by functions above).
 669         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 670         (fp_recip, fp_sqrt): New prototypes.
 671         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 672         (Recip, SquareRoot): Replace prototypes with #defines which
 673         invoke the functions above.
 674
 675 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 676
 677         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 678         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 679         file, remove PARAMS from prototypes.
 680         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 681         simulator state arguments.
 682         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 683         pass simulator state arguments.
 684         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 685         (store_fpr, convert): Remove 'sd' argument.
 686         (value_fpr): Likewise.  Convert to use 'SD' instead.
 687
 688 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 689
 690         * cp1.c (Min, Max): Remove #if 0'd functions.
 691         * sim-main.h (Min, Max): Remove.
 692
 693 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 694
 695         * cp1.c: fix formatting of switch case and default labels.
 696         * interp.c: Likewise.
 697         * sim-main.c: Likewise.
 698
 699 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 700
 701         * cp1.c: Clean up comments which describe FP formats.
 702          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 703
 704 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 705             Ed Satterthwaite  <ehs@broadcom.com>
 706
 707         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 708         Broadcom SiByte SB-1 processor configurations.
 709         * configure: Regenerate.
 710         * sb1.igen: New file.
 711         * mips.igen: Include sb1.igen.
 712         (sb1): New model.
 713         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 714         * mdmx.igen: Add "sb1" model to all appropriate functions and
 715         instructions.
 716         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 717         (ob_func, ob_acc): Reference the above.
 718         (qh_acc): Adjust to keep the same size as ob_acc.
 719         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 720         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 721
 722 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 723
 724         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 725
 726 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 727             Ed Satterthwaite  <ehs@broadcom.com>
 728
 729         * mips.igen (mdmx): New (pseudo-)model.
 730         * mdmx.c, mdmx.igen: New files.
 731         * Makefile.in (SIM_OBJS): Add mdmx.o.
 732         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 733         New typedefs.
 734         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 735         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 736         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 737         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 738         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 739         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 740         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 741         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 742         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 743         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 744         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 745         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 746         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 747         (qh_fmtsel): New macros.
 748         (_sim_cpu): New member "acc".
 749         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 750         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 751
 752 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 753
 754         * interp.c: Use 'deprecated' rather than 'depreciated.'
 755         * sim-main.h: Likewise.
 756
 757 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 758
 759         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 760         which wouldn't compile anyway.
 761         * sim-main.h (unpredictable_action): New function prototype.
 762         (Unpredictable): Define to call igen function unpredictable().
 763         (NotWordValue): New macro to call igen function not_word_value().
 764         (UndefinedResult): Remove.
 765         * interp.c (undefined_result): Remove.
 766         (unpredictable_action): New function.
 767         * mips.igen (not_word_value, unpredictable): New functions.
 768         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 769         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 770         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 771         NotWordValue() to check for unpredictable inputs, then
 772         Unpredictable() to handle them.
 773
 774 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 775
 776         * mips.igen: Fix formatting of calls to Unpredictable().
 777
 778 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 779
 780         * interp.c (sim_open): Revert previous change.
 781
 782 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 783
 784         * interp.c (sim_open): Disable chunk of code that wrote code in
 785         vector table entries.
 786
 787 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 788
 789         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 790         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 791         unused definitions.
 792
 793 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 794
 795         * cp1.c: Fix many formatting issues.
 796
 797 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 798
 799         * cp1.c (fpu_format_name): New function to replace...
 800         (DOFMT): This.  Delete, and update all callers.
 801         (fpu_rounding_mode_name): New function to replace...
 802         (RMMODE): This.  Delete, and update all callers.
 803
 804 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 805
 806         * interp.c: Move FPU support routines from here to...
 807         * cp1.c: Here.  New file.
 808         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 809         (cp1.o): New target.
 810
 811 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 812
 813         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 814         * mips.igen (mips32, mips64): New models, add to all instructions
 815         and functions as appropriate.
 816         (loadstore_ea, check_u64): New variant for model mips64.
 817         (check_fmt_p): New variant for models mipsV and mips64, remove
 818         mipsV model marking fro other variant.
 819         (SLL) Rename to...
 820         (SLLa) this.
 821         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 822         for mips32 and mips64.
 823         (DCLO, DCLZ): New instructions for mips64.
 824
 825 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 826
 827         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 828         immediate or code as a hex value with the "%#lx" format.
 829         (ANDI): Likewise, and fix printed instruction name.
 830
 831 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 832
 833         * sim-main.h (UndefinedResult, Unpredictable): New macros
 834         which currently do nothing.
 835
 836 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 837
 838         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 839         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 840         (status_CU3): New definitions.
 841
 842         * sim-main.h (ExceptionCause): Add new values for MIPS32
 843         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 844         for DebugBreakPoint and NMIReset to note their status in
 845         MIPS32 and MIPS64.
 846         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 847         (SignalExceptionCacheErr): New exception macros.
 848
 849 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 850
 851         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 852         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 853         is always enabled.
 854         (SignalExceptionCoProcessorUnusable): Take as argument the
 855         unusable coprocessor number.
 856
 857 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 858
 859         * mips.igen: Fix formatting of all SignalException calls.
 860
 861 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 862
 863         * sim-main.h (SIGNEXTEND): Remove.
 864
 865 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 866
 867         * mips.igen: Remove gencode comment from top of file, fix
 868         spelling in another comment.
 869
 870 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 871
 872         * mips.igen (check_fmt, check_fmt_p): New functions to check
 873         whether specific floating point formats are usable.
 874         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 875         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 876         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 877         Use the new functions.
 878         (do_c_cond_fmt): Remove format checks...
 879         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 880
 881 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 882
 883         * mips.igen: Fix formatting of check_fpu calls.
 884
 885 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 886
 887         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 888
 889 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 890
 891         * mips.igen: Remove whitespace at end of lines.
 892
 893 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 894
 895         * mips.igen (loadstore_ea): New function to do effective
 896         address calculations.
 897         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 898         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 899         CACHE): Use loadstore_ea to do effective address computations.
 900
 901 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 902
 903         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 904         * mips.igen (LL, CxC1, MxC1): Likewise.
 905
 906 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 907
 908         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 909         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 910         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 911         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 912         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 913         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 914         Don't split opcode fields by hand, use the opcode field values
 915         provided by igen.
 916
 917 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 918
 919         * mips.igen (do_divu): Fix spacing.
 920
 921         * mips.igen (do_dsllv): Move to be right before DSLLV,
 922         to match the rest of the do_<shift> functions.
 923
 924 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 925
 926         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 927         DSRL32, do_dsrlv): Trace inputs and results.
 928
 929 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 930
 931         * mips.igen (CACHE): Provide instruction-printing string.
 932
 933         * interp.c (signal_exception): Comment tokens after #endif.
 934
 935 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 936
 937         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 938         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 939         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 940         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 941         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 942         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 943         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 944         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 945
 946 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 947
 948         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 949         instruction-printing string.
 950         (LWU): Use '64' as the filter flag.
 951
 952 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 953
 954         * mips.igen (SDXC1): Fix instruction-printing string.
 955
 956 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 957
 958         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 959         filter flags "32,f".
 960
 961 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 962
 963         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 964         as the filter flag.
 965
 966 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 967
 968         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 969         add a comma) so that it more closely match the MIPS ISA
 970         documentation opcode partitioning.
 971         (PREF): Put useful names on opcode fields, and include
 972         instruction-printing string.
 973
 974 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 975
 976         * mips.igen (check_u64): New function which in the future will
 977         check whether 64-bit instructions are usable and signal an
 978         exception if not.  Currently a no-op.
 979         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 980         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 981         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 982         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 983
 984         * mips.igen (check_fpu): New function which in the future will
 985         check whether FPU instructions are usable and signal an exception
 986         if not.  Currently a no-op.
 987         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 988         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 989         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 990         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 991         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 992         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 993         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 994         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 995
 996 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 997
 998         * mips.igen (do_load_left, do_load_right): Move to be immediately
 999         following do_load.
1000         (do_store_left, do_store_right): Move to be immediately following
1001         do_store.
1002
1003 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1004
1005         * mips.igen (mipsV): New model name.  Also, add it to
1006         all instructions and functions where it is appropriate.
1007
1008 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
1009
1010         * mips.igen: For all functions and instructions, list model
1011         names that support that instruction one per line.
1012
1013 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1014
1015         * mips.igen: Add some additional comments about supported
1016         models, and about which instructions go where.
1017         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1018         order as is used in the rest of the file.
1019
1020 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1021
1022         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1023         indicating that ALU32_END or ALU64_END are there to check
1024         for overflow.
1025         (DADD): Likewise, but also remove previous comment about
1026         overflow checking.
1027
1028 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1029
1030         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1031         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1032         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1033         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1034         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1035         fields (i.e., add and move commas) so that they more closely
1036         match the MIPS ISA documentation opcode partitioning.
1037
1038 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1039
1040         * mips.igen (ADDI): Print immediate value.
1041         (BREAK): Print code.
1042         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1043         (SLL): Print "nop" specially, and don't run the code
1044         that does the shift for the "nop" case.
1045
1046 2001-11-17  Fred Fish  <fnf@redhat.com>
1047
1048         * sim-main.h (float_operation): Move enum declaration outside
1049         of _sim_cpu struct declaration.
1050
1051 2001-04-12  Jim Blandy  <jimb@redhat.com>
1052
1053         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1054         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
1055         set of the FCSR.
1056         * sim-main.h (COCIDX): Remove definition; this isn't supported by
1057         PENDING_FILL, and you can get the intended effect gracefully by
1058         calling PENDING_SCHED directly.
1059
1060 2001-02-23  Ben Elliston  <bje@redhat.com>
1061
1062         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1063         already defined elsewhere.
1064
1065 2001-02-19  Ben Elliston  <bje@redhat.com>
1066
1067         * sim-main.h (sim_monitor): Return an int.
1068         * interp.c (sim_monitor): Add return values.
1069         (signal_exception): Handle error conditions from sim_monitor.
1070
1071 2001-02-08  Ben Elliston  <bje@redhat.com>
1072
1073         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1074         (store_memory): Likewise, pass cia to sim_core_write*.
1075
1076 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
1077
1078         On advice from Chris G. Demetriou <cgd@sibyte.com>:
1079         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1080
1081 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1082
1083         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1084         * Makefile.in: Don't delete *.igen when cleaning directory.
1085
1086 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1087
1088         * m16.igen (break): Call SignalException not sim_engine_halt.
1089
1090 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1091
1092         From Jason Eckhardt:
1093         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1094
1095 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1096
1097         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1098
1099 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1100
1101         * mips.igen (do_dmultx): Fix typo.
1102
1103 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1104
1105         * configure: Regenerated to track ../common/aclocal.m4 changes.
1106
1107 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1108
1109         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1110
1111 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1112
1113         * sim-main.h (GPR_CLEAR): Define macro.
1114
1115 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1116
1117         * interp.c (decode_coproc): Output long using %lx and not %s.
1118
1119 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1120
1121         * interp.c (sim_open): Sort & extend dummy memory regions for
1122         --board=jmr3904 for eCos.
1123
1124 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1125
1126         * configure: Regenerated.
1127
1128 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1129
1130         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1131         calls, conditional on the simulator being in verbose mode.
1132
1133 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1134
1135         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1136         cache don't get ReservedInstruction traps.
1137
1138 1999-11-29  Mark Salter  <msalter@cygnus.com>
1139
1140         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1141         to clear status bits in sdisr register. This is how the hardware works.
1142
1143         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1144         being used by cygmon.
1145
1146 1999-11-11  Andrew Haley  <aph@cygnus.com>
1147
1148         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1149         instructions.
1150
1151 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1152
1153         * mips.igen (MULT): Correct previous mis-applied patch.
1154
1155 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1156
1157         * mips.igen (delayslot32): Handle sequence like
1158         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1159         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1160         (MULT): Actually pass the third register...
1161
1162 1999-09-03  Mark Salter  <msalter@cygnus.com>
1163
1164         * interp.c (sim_open): Added more memory aliases for additional
1165         hardware being touched by cygmon on jmr3904 board.
1166
1167 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1168
1169         * configure: Regenerated to track ../common/aclocal.m4 changes.
1170
1171 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1172
1173         * interp.c (sim_store_register): Handle case where client - GDB -
1174         specifies that a 4 byte register is 8 bytes in size.
1175         (sim_fetch_register): Ditto.
1176
1177 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1178
1179         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1180         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1181         (idt_monitor_base): Base address for IDT monitor traps.
1182         (pmon_monitor_base): Ditto for PMON.
1183         (lsipmon_monitor_base): Ditto for LSI PMON.
1184         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1185         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1186         (sim_firmware_command): New function.
1187         (mips_option_handler): Call it for OPTION_FIRMWARE.
1188         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1189         option was given, add no monitor by default.  Add BREAK hooks only if
1190         monitors are also there.
1191
1192 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1193
1194         * interp.c (sim_monitor): Flush output before reading input.
1195
1196 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1197
1198         * tconfig.in (SIM_HANDLES_LMA): Always define.
1199
1200 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1201
1202         From Mark Salter <msalter@cygnus.com>:
1203         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1204         (sim_open): Add setup for BSP board.
1205
1206 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1207
1208         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1209         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1210         them as unimplemented.
1211
1212 1999-05-08  Felix Lee  <flee@cygnus.com>
1213
1214         * configure: Regenerated to track ../common/aclocal.m4 changes.
1215
1216 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1217
1218         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1219
1220 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1221
1222         * configure.in: Any mips64vr5*-*-* target should have
1223         -DTARGET_ENABLE_FR=1.
1224         (default_endian): Any mips64vr*el-*-* target should default to
1225         LITTLE_ENDIAN.
1226         * configure: Re-generate.
1227
1228 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1229
1230         * mips.igen (ldl): Extend from _16_, not 32.
1231
1232 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1233
1234         * interp.c (sim_store_register): Force registers written to by GDB
1235         into an un-interpreted state.
1236
1237 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1238
1239         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1240         CPU, start periodic background I/O polls.
1241         (tx3904sio_poll): New function: periodic I/O poller.
1242
1243 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1244
1245         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1246
1247 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1248
1249         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1250         case statement.
1251
1252 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1253
1254         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1255         (load_word): Call SIM_CORE_SIGNAL hook on error.
1256         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1257         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1258         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1259         * sim-main.h (COP0_BADVADDR): Define.
1260         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1261         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1262         (_sim_cpu): Add exc_* fields to store register value snapshots.
1263         * mips.igen (*): Replace memory-related SignalException* calls
1264         with references to SIM_CORE_SIGNAL hook.
1265
1266         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1267         fix.
1268         * sim-main.c (*): Minor warning cleanups.
1269
1270 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1271
1272         * m16.igen (DADDIU5): Correct type-o.
1273
1274 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1275
1276         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1277         variables.
1278
1279 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1280
1281         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1282         to include path.
1283         (interp.o): Add dependency on itable.h
1284         (oengine.c, gencode): Delete remaining references.
1285         (BUILT_SRC_FROM_GEN): Clean up.
1286
1287 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1288
1289         * vr4run.c: New.
1290         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1291         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1292         tmp-run-hack) : New.
1293         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1294         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1295         Drop the "64" qualifier to get the HACK generator working.
1296         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1297         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1298         qualifier to get the hack generator working.
1299         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1300         (DSLL): Use do_dsll.
1301         (DSLLV): Use do_dsllv.
1302         (DSRA): Use do_dsra.
1303         (DSRL): Use do_dsrl.
1304         (DSRLV): Use do_dsrlv.
1305         (BC1): Move *vr4100 to get the HACK generator working.
1306         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1307         get the HACK generator working.
1308         (MACC) Rename to get the HACK generator working.
1309         (DMACC,MACCS,DMACCS): Add the 64.
1310
1311 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1312
1313         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1314         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1315
1316 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1317
1318     * mips/interp.c (DEBUG): Cleanups.
1319
1320 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1321
1322         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1323         (tx3904sio_tickle): fflush after a stdout character output.
1324
1325 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1326
1327         * interp.c (sim_close): Uninstall modules.
1328
1329 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * sim-main.h, interp.c (sim_monitor): Change to global
1332         function.
1333
1334 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1335
1336         * configure.in (vr4100): Only include vr4100 instructions in
1337         simulator.
1338         * configure: Re-generate.
1339         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1340
1341 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1342
1343         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1344         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1345         true alternative.
1346
1347         * configure.in (sim_default_gen, sim_use_gen): Replace with
1348         sim_gen.
1349         (--enable-sim-igen): Delete config option. Always using IGEN.
1350         * configure: Re-generate.
1351
1352         * Makefile.in (gencode): Kill, kill, kill.
1353         * gencode.c: Ditto.
1354
1355 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1356
1357         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1358         bit mips16 igen simulator.
1359         * configure: Re-generate.
1360
1361         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1362         as part of vr4100 ISA.
1363         * vr.igen: Mark all instructions as 64 bit only.
1364
1365 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1366
1367         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1368         Pacify GCC.
1369
1370 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1371
1372         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1373         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1374         * configure: Re-generate.
1375
1376         * m16.igen (BREAK): Define breakpoint instruction.
1377         (JALX32): Mark instruction as mips16 and not r3900.
1378         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1379
1380         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1381
1382 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1383
1384         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1385         insn as a debug breakpoint.
1386
1387         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1388         pending.slot_size.
1389         (PENDING_SCHED): Clean up trace statement.
1390         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1391         (PENDING_FILL): Delay write by only one cycle.
1392         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1393
1394         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1395         of pending writes.
1396         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1397         32 & 64.
1398         (pending_tick): Move incrementing of index to FOR statement.
1399         (pending_tick): Only update PENDING_OUT after a write has occured.
1400
1401         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1402         build simulator.
1403         * configure: Re-generate.
1404
1405         * interp.c (sim_engine_run OLD): Delete explicit call to
1406         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1407
1408 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1409
1410         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1411         interrupt level number to match changed SignalExceptionInterrupt
1412         macro.
1413
1414 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1415
1416         * interp.c: #include "itable.h" if WITH_IGEN.
1417         (get_insn_name): New function.
1418         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1419         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1420
1421 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1422
1423         * configure: Rebuilt to inhale new common/aclocal.m4.
1424
1425 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1426
1427         * dv-tx3904sio.c: Include sim-assert.h.
1428
1429 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1430
1431         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1432         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1433         Reorganize target-specific sim-hardware checks.
1434         * configure: rebuilt.
1435         * interp.c (sim_open): For tx39 target boards, set
1436         OPERATING_ENVIRONMENT, add tx3904sio devices.
1437         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1438         ROM executables.  Install dv-sockser into sim-modules list.
1439
1440         * dv-tx3904irc.c: Compiler warning clean-up.
1441         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1442         frequent hw-trace messages.
1443
1444 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1447
1448 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1449
1450         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1451
1452         * vr.igen: New file.
1453         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1454         * mips.igen: Define vr4100 model. Include vr.igen.
1455 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1456
1457         * mips.igen (check_mf_hilo): Correct check.
1458
1459 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1460
1461         * sim-main.h (interrupt_event): Add prototype.
1462
1463         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1464         register_ptr, register_value.
1465         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1466
1467         * sim-main.h (tracefh): Make extern.
1468
1469 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1470
1471         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1472         Reduce unnecessarily high timer event frequency.
1473         * dv-tx3904cpu.c: Ditto for interrupt event.
1474
1475 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1476
1477         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1478         to allay warnings.
1479         (interrupt_event): Made non-static.
1480
1481         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1482         interchange of configuration values for external vs. internal
1483         clock dividers.
1484
1485 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1486
1487         * mips.igen (BREAK): Moved code to here for
1488         simulator-reserved break instructions.
1489         * gencode.c (build_instruction): Ditto.
1490         * interp.c (signal_exception): Code moved from here.  Non-
1491         reserved instructions now use exception vector, rather
1492         than halting sim.
1493         * sim-main.h: Moved magic constants to here.
1494
1495 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1496
1497         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1498         register upon non-zero interrupt event level, clear upon zero
1499         event value.
1500         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1501         by passing zero event value.
1502         (*_io_{read,write}_buffer): Endianness fixes.
1503         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1504         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1505
1506         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1507         serial I/O and timer module at base address 0xFFFF0000.
1508
1509 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1510
1511         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1512         and BigEndianCPU.
1513
1514 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1515
1516         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1517         parts.
1518         * configure: Update.
1519
1520 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1521
1522         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1523         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1524         * configure.in: Include tx3904tmr in hw_device list.
1525         * configure: Rebuilt.
1526         * interp.c (sim_open): Instantiate three timer instances.
1527         Fix address typo of tx3904irc instance.
1528
1529 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1530
1531         * interp.c (signal_exception): SystemCall exception now uses
1532         the exception vector.
1533
1534 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1535
1536         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1537         to allay warnings.
1538
1539 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1540
1541         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1542
1543 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1544
1545         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1546
1547         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1548         sim-main.h. Declare a struct hw_descriptor instead of struct
1549         hw_device_descriptor.
1550
1551 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1552
1553         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1554         right bits and then re-align left hand bytes to correct byte
1555         lanes.  Fix incorrect computation in do_store_left when loading
1556         bytes from second word.
1557
1558 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1559
1560         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1561         * interp.c (sim_open): Only create a device tree when HW is
1562         enabled.
1563
1564         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1565         * interp.c (signal_exception): Ditto.
1566
1567 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1568
1569         * gencode.c: Mark BEGEZALL as LIKELY.
1570
1571 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1572
1573         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1574         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1575
1576 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1577
1578         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1579         modules.  Recognize TX39 target with "mips*tx39" pattern.
1580         * configure: Rebuilt.
1581         * sim-main.h (*): Added many macros defining bits in
1582         TX39 control registers.
1583         (SignalInterrupt): Send actual PC instead of NULL.
1584         (SignalNMIReset): New exception type.
1585         * interp.c (board): New variable for future use to identify
1586         a particular board being simulated.
1587         (mips_option_handler,mips_options): Added "--board" option.
1588         (interrupt_event): Send actual PC.
1589         (sim_open): Make memory layout conditional on board setting.
1590         (signal_exception): Initial implementation of hardware interrupt
1591         handling.  Accept another break instruction variant for simulator
1592         exit.
1593         (decode_coproc): Implement RFE instruction for TX39.
1594         (mips.igen): Decode RFE instruction as such.
1595         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1596         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1597         bbegin to implement memory map.
1598         * dv-tx3904cpu.c: New file.
1599         * dv-tx3904irc.c: New file.
1600
1601 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1602
1603         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1604
1605 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1606
1607         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1608         with calls to check_div_hilo.
1609
1610 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1611
1612         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1613         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1614         Add special r3900 version of do_mult_hilo.
1615         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1616         with calls to check_mult_hilo.
1617         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1618         with calls to check_div_hilo.
1619
1620 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1621
1622         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1623         Document a replacement.
1624
1625 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1626
1627         * interp.c (sim_monitor): Make mon_printf work.
1628
1629 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1630
1631         * sim-main.h (INSN_NAME): New arg `cpu'.
1632
1633 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1634
1635         * configure: Regenerated to track ../common/aclocal.m4 changes.
1636
1637 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1638
1639         * configure: Regenerated to track ../common/aclocal.m4 changes.
1640         * config.in: Ditto.
1641
1642 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1643
1644         * acconfig.h: New file.
1645         * configure.in: Reverted change of Apr 24; use sinclude again.
1646
1647 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1648
1649         * configure: Regenerated to track ../common/aclocal.m4 changes.
1650         * config.in: Ditto.
1651
1652 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1653
1654         * configure.in: Don't call sinclude.
1655
1656 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1657
1658         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1659
1660 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1661
1662         * mips.igen (ERET): Implement.
1663
1664         * interp.c (decode_coproc): Return sign-extended EPC.
1665
1666         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1667
1668         * interp.c (signal_exception): Do not ignore Trap.
1669         (signal_exception): On TRAP, restart at exception address.
1670         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1671         (signal_exception): Update.
1672         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1673         so that TRAP instructions are caught.
1674
1675 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1676
1677         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1678         contains HI/LO access history.
1679         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1680         (HIACCESS, LOACCESS): Delete, replace with
1681         (HIHISTORY, LOHISTORY): New macros.
1682         (CHECKHILO): Delete all, moved to mips.igen
1683
1684         * gencode.c (build_instruction): Do not generate checks for
1685         correct HI/LO register usage.
1686
1687         * interp.c (old_engine_run): Delete checks for correct HI/LO
1688         register usage.
1689
1690         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1691         check_mf_cycles): New functions.
1692         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1693         do_divu, domultx, do_mult, do_multu): Use.
1694
1695         * tx.igen ("madd", "maddu"): Use.
1696
1697 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1698
1699         * mips.igen (DSRAV): Use function do_dsrav.
1700         (SRAV): Use new function do_srav.
1701
1702         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1703         (B): Sign extend 11 bit immediate.
1704         (EXT-B*): Shift 16 bit immediate left by 1.
1705         (ADDIU*): Don't sign extend immediate value.
1706
1707 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1708
1709         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1710
1711         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1712         functions.
1713
1714         * mips.igen (delayslot32, nullify_next_insn): New functions.
1715         (m16.igen): Always include.
1716         (do_*): Add more tracing.
1717
1718         * m16.igen (delayslot16): Add NIA argument, could be called by a
1719         32 bit MIPS16 instruction.
1720
1721         * interp.c (ifetch16): Move function from here.
1722         * sim-main.c (ifetch16): To here.
1723
1724         * sim-main.c (ifetch16, ifetch32): Update to match current
1725         implementations of LH, LW.
1726         (signal_exception): Don't print out incorrect hex value of illegal
1727         instruction.
1728
1729 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1730
1731         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1732         instruction.
1733
1734         * m16.igen: Implement MIPS16 instructions.
1735
1736         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1737         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1738         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1739         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1740         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1741         bodies of corresponding code from 32 bit insn to these.  Also used
1742         by MIPS16 versions of functions.
1743
1744         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1745         (IMEM16): Drop NR argument from macro.
1746
1747 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1748
1749         * Makefile.in (SIM_OBJS): Add sim-main.o.
1750
1751         * sim-main.h (address_translation, load_memory, store_memory,
1752         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1753         as INLINE_SIM_MAIN.
1754         (pr_addr, pr_uword64): Declare.
1755         (sim-main.c): Include when H_REVEALS_MODULE_P.
1756
1757         * interp.c (address_translation, load_memory, store_memory,
1758         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1759         from here.
1760         * sim-main.c: To here. Fix compilation problems.
1761
1762         * configure.in: Enable inlining.
1763         * configure: Re-config.
1764
1765 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * configure: Regenerated to track ../common/aclocal.m4 changes.
1768
1769 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1770
1771         * mips.igen: Include tx.igen.
1772         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1773         * tx.igen: New file, contains MADD and MADDU.
1774
1775         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1776         the hardwired constant `7'.
1777         (store_memory): Ditto.
1778         (LOADDRMASK): Move definition to sim-main.h.
1779
1780         mips.igen (MTC0): Enable for r3900.
1781         (ADDU): Add trace.
1782
1783         mips.igen (do_load_byte): Delete.
1784         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1785         do_store_right): New functions.
1786         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1787
1788         configure.in: Let the tx39 use igen again.
1789         configure: Update.
1790
1791 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1792
1793         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1794         not an address sized quantity.  Return zero for cache sizes.
1795
1796 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1797
1798         * mips.igen (r3900): r3900 does not support 64 bit integer
1799         operations.
1800
1801 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1802
1803         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1804         than igen one.
1805         * configure : Rebuild.
1806
1807 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1808
1809         * configure: Regenerated to track ../common/aclocal.m4 changes.
1810
1811 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1812
1813         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1814
1815 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1816
1817         * configure: Regenerated to track ../common/aclocal.m4 changes.
1818         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1819
1820 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1821
1822         * configure: Regenerated to track ../common/aclocal.m4 changes.
1823
1824 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1825
1826         * interp.c (Max, Min): Comment out functions. Not yet used.
1827
1828 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1829
1830         * configure: Regenerated to track ../common/aclocal.m4 changes.
1831
1832 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1833
1834         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1835         configurable settings for stand-alone simulator.
1836
1837         * configure.in: Added X11 search, just in case.
1838
1839         * configure: Regenerated.
1840
1841 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1842
1843         * interp.c (sim_write, sim_read, load_memory, store_memory):
1844         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1845
1846 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1847
1848         * sim-main.h (GETFCC): Return an unsigned value.
1849
1850 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1851
1852         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1853         (DADD): Result destination is RD not RT.
1854
1855 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1856
1857         * sim-main.h (HIACCESS, LOACCESS): Always define.
1858
1859         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1860
1861         * interp.c (sim_info): Delete.
1862
1863 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1864
1865         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1866         (mips_option_handler): New argument `cpu'.
1867         (sim_open): Update call to sim_add_option_table.
1868
1869 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1870
1871         * mips.igen (CxC1): Add tracing.
1872
1873 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1874
1875         * sim-main.h (Max, Min): Declare.
1876
1877         * interp.c (Max, Min): New functions.
1878
1879         * mips.igen (BC1): Add tracing.
1880
1881 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1882
1883         * interp.c Added memory map for stack in vr4100
1884
1885 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1886
1887         * interp.c (load_memory): Add missing "break"'s.
1888
1889 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * interp.c (sim_store_register, sim_fetch_register): Pass in
1892         length parameter.  Return -1.
1893
1894 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1895
1896         * interp.c: Added hardware init hook, fixed warnings.
1897
1898 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1899
1900         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1901
1902 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1903
1904         * interp.c (ifetch16): New function.
1905
1906         * sim-main.h (IMEM32): Rename IMEM.
1907         (IMEM16_IMMED): Define.
1908         (IMEM16): Define.
1909         (DELAY_SLOT): Update.
1910
1911         * m16run.c (sim_engine_run): New file.
1912
1913         * m16.igen: All instructions except LB.
1914         (LB): Call do_load_byte.
1915         * mips.igen (do_load_byte): New function.
1916         (LB): Call do_load_byte.
1917
1918         * mips.igen: Move spec for insn bit size and high bit from here.
1919         * Makefile.in (tmp-igen, tmp-m16): To here.
1920
1921         * m16.dc: New file, decode mips16 instructions.
1922
1923         * Makefile.in (SIM_NO_ALL): Define.
1924         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1925
1926 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1927
1928         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1929         point unit to 32 bit registers.
1930         * configure: Re-generate.
1931
1932 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * configure.in (sim_use_gen): Make IGEN the default simulator
1935         generator for generic 32 and 64 bit mips targets.
1936         * configure: Re-generate.
1937
1938 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1939
1940         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1941         bitsize.
1942
1943         * interp.c (sim_fetch_register, sim_store_register): Read/write
1944         FGR from correct location.
1945         (sim_open): Set size of FGR's according to
1946         WITH_TARGET_FLOATING_POINT_BITSIZE.
1947
1948         * sim-main.h (FGR): Store floating point registers in a separate
1949         array.
1950
1951 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1952
1953         * configure: Regenerated to track ../common/aclocal.m4 changes.
1954
1955 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1956
1957         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1958
1959         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1960
1961         * interp.c (pending_tick): New function.  Deliver pending writes.
1962
1963         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1964         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1965         it can handle mixed sized quantites and single bits.
1966
1967 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1968
1969         * interp.c (oengine.h): Do not include when building with IGEN.
1970         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1971         (sim_info): Ditto for PROCESSOR_64BIT.
1972         (sim_monitor): Replace ut_reg with unsigned_word.
1973         (*): Ditto for t_reg.
1974         (LOADDRMASK): Define.
1975         (sim_open): Remove defunct check that host FP is IEEE compliant,
1976         using software to emulate floating point.
1977         (value_fpr, ...): Always compile, was conditional on HASFPU.
1978
1979 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1980
1981         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1982         size.
1983
1984         * interp.c (SD, CPU): Define.
1985         (mips_option_handler): Set flags in each CPU.
1986         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1987         (sim_close): Do not clear STATE, deleted anyway.
1988         (sim_write, sim_read): Assume CPU zero's vm should be used for
1989         data transfers.
1990         (sim_create_inferior): Set the PC for all processors.
1991         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1992         argument.
1993         (mips16_entry): Pass correct nr of args to store_word, load_word.
1994         (ColdReset): Cold reset all cpu's.
1995         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1996         (sim_monitor, load_memory, store_memory, signal_exception): Use
1997         `CPU' instead of STATE_CPU.
1998
1999
2000         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2001         SD or CPU_.
2002
2003         * sim-main.h (signal_exception): Add sim_cpu arg.
2004         (SignalException*): Pass both SD and CPU to signal_exception.
2005         * interp.c (signal_exception): Update.
2006
2007         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2008         Ditto
2009         (sync_operation, prefetch, cache_op, store_memory, load_memory,
2010         address_translation): Ditto
2011         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2012
2013 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2014
2015         * configure: Regenerated to track ../common/aclocal.m4 changes.
2016
2017 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2018
2019         * interp.c (sim_engine_run): Add `nr_cpus' argument.
2020
2021         * mips.igen (model): Map processor names onto BFD name.
2022
2023         * sim-main.h (CPU_CIA): Delete.
2024         (SET_CIA, GET_CIA): Define
2025
2026 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2027
2028         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2029         regiser.
2030
2031         * configure.in (default_endian): Configure a big-endian simulator
2032         by default.
2033         * configure: Re-generate.
2034
2035 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
2036
2037         * configure: Regenerated to track ../common/aclocal.m4 changes.
2038
2039 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
2040
2041         * interp.c (sim_monitor): Handle Densan monitor outbyte
2042         and inbyte functions.
2043
2044 1997-12-29  Felix Lee  <flee@cygnus.com>
2045
2046         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2047
2048 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
2049
2050         * Makefile.in (tmp-igen): Arrange for $zero to always be
2051         reset to zero after every instruction.
2052
2053 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2054
2055         * configure: Regenerated to track ../common/aclocal.m4 changes.
2056         * config.in: Ditto.
2057
2058 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
2059
2060         * mips.igen (MSUB): Fix to work like MADD.
2061         * gencode.c (MSUB): Similarly.
2062
2063 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
2064
2065         * configure: Regenerated to track ../common/aclocal.m4 changes.
2066
2067 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2068
2069         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2070
2071 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2072
2073         * sim-main.h (sim-fpu.h): Include.
2074
2075         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2076         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2077         using host independant sim_fpu module.
2078
2079 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2080
2081         * interp.c (signal_exception): Report internal errors with SIGABRT
2082         not SIGQUIT.
2083
2084         * sim-main.h (C0_CONFIG): New register.
2085         (signal.h): No longer include.
2086
2087         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2088
2089 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
2090
2091         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2092
2093 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2094
2095         * mips.igen: Tag vr5000 instructions.
2096         (ANDI): Was missing mipsIV model, fix assembler syntax.
2097         (do_c_cond_fmt): New function.
2098         (C.cond.fmt): Handle mips I-III which do not support CC field
2099         separatly.
2100         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2101         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2102         in IV3.2 spec.
2103         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2104         vr5000 which saves LO in a GPR separatly.
2105
2106         * configure.in (enable-sim-igen): For vr5000, select vr5000
2107         specific instructions.
2108         * configure: Re-generate.
2109
2110 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2111
2112         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2113
2114         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2115         fmt_uninterpreted_64 bit cases to switch.  Convert to
2116         fmt_formatted,
2117
2118         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2119
2120         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2121         as specified in IV3.2 spec.
2122         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2123
2124 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2125
2126         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2127         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2128         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2129         PENDING_FILL versions of instructions.  Simplify.
2130         (X): New function.
2131         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2132         instructions.
2133         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2134         a signed value.
2135         (MTHI, MFHI): Disable code checking HI-LO.
2136
2137         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2138         global.
2139         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2140
2141 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2142
2143         * gencode.c (build_mips16_operands): Replace IPC with cia.
2144
2145         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2146         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2147         IPC to `cia'.
2148         (UndefinedResult): Replace function with macro/function
2149         combination.
2150         (sim_engine_run): Don't save PC in IPC.
2151
2152         * sim-main.h (IPC): Delete.
2153
2154
2155         * interp.c (signal_exception, store_word, load_word,
2156         address_translation, load_memory, store_memory, cache_op,
2157         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2158         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2159         current instruction address - cia - argument.
2160         (sim_read, sim_write): Call address_translation directly.
2161         (sim_engine_run): Rename variable vaddr to cia.
2162         (signal_exception): Pass cia to sim_monitor
2163
2164         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2165         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2166         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2167
2168         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2169         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2170         SIM_ASSERT.
2171
2172         * interp.c (signal_exception): Pass restart address to
2173         sim_engine_restart.
2174
2175         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2176         idecode.o): Add dependency.
2177
2178         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2179         Delete definitions
2180         (DELAY_SLOT): Update NIA not PC with branch address.
2181         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2182
2183         * mips.igen: Use CIA not PC in branch calculations.
2184         (illegal): Call SignalException.
2185         (BEQ, ADDIU): Fix assembler.
2186
2187 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2188
2189         * m16.igen (JALX): Was missing.
2190
2191         * configure.in (enable-sim-igen): New configuration option.
2192         * configure: Re-generate.
2193
2194         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2195
2196         * interp.c (load_memory, store_memory): Delete parameter RAW.
2197         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2198         bypassing {load,store}_memory.
2199
2200         * sim-main.h (ByteSwapMem): Delete definition.
2201
2202         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2203
2204         * interp.c (sim_do_command, sim_commands): Delete mips specific
2205         commands.  Handled by module sim-options.
2206
2207         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2208         (WITH_MODULO_MEMORY): Define.
2209
2210         * interp.c (sim_info): Delete code printing memory size.
2211
2212         * interp.c (mips_size): Nee sim_size, delete function.
2213         (power2): Delete.
2214         (monitor, monitor_base, monitor_size): Delete global variables.
2215         (sim_open, sim_close): Delete code creating monitor and other
2216         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2217         manage memory regions.
2218         (load_memory, store_memory): Use sim-core for memory model.
2219
2220         * interp.c (address_translation): Delete all memory map code
2221         except line forcing 32 bit addresses.
2222
2223 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2224
2225         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2226         trace options.
2227
2228         * interp.c (logfh, logfile): Delete globals.
2229         (sim_open, sim_close): Delete code opening & closing log file.
2230         (mips_option_handler): Delete -l and -n options.
2231         (OPTION mips_options): Ditto.
2232
2233         * interp.c (OPTION mips_options): Rename option trace to dinero.
2234         (mips_option_handler): Update.
2235
2236 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2237
2238         * interp.c (fetch_str): New function.
2239         (sim_monitor): Rewrite using sim_read & sim_write.
2240         (sim_open): Check magic number.
2241         (sim_open): Write monitor vectors into memory using sim_write.
2242         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2243         (sim_read, sim_write): Simplify - transfer data one byte at a
2244         time.
2245         (load_memory, store_memory): Clarify meaning of parameter RAW.
2246
2247         * sim-main.h (isHOST): Defete definition.
2248         (isTARGET): Mark as depreciated.
2249         (address_translation): Delete parameter HOST.
2250
2251         * interp.c (address_translation): Delete parameter HOST.
2252
2253 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2254
2255         * mips.igen:
2256
2257         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2258         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2259
2260 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2261
2262         * mips.igen: Add model filter field to records.
2263
2264 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2265
2266         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2267
2268         interp.c (sim_engine_run): Do not compile function sim_engine_run
2269         when WITH_IGEN == 1.
2270
2271         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2272         target architecture.
2273
2274         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2275         igen. Replace with configuration variables sim_igen_flags /
2276         sim_m16_flags.
2277
2278         * m16.igen: New file.  Copy mips16 insns here.
2279         * mips.igen: From here.
2280
2281 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2282
2283         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2284         to top.
2285         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2286
2287 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2288
2289         * gencode.c (build_instruction): Follow sim_write's lead in using
2290         BigEndianMem instead of !ByteSwapMem.
2291
2292 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2293
2294         * configure.in (sim_gen): Dependent on target, select type of
2295         generator.  Always select old style generator.
2296
2297         configure: Re-generate.
2298
2299         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2300         targets.
2301         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2302         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2303         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2304         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2305         SIM_@sim_gen@_*, set by autoconf.
2306
2307 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2308
2309         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2310
2311         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2312         CURRENT_FLOATING_POINT instead.
2313
2314         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2315         (address_translation): Raise exception InstructionFetch when
2316         translation fails and isINSTRUCTION.
2317
2318         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2319         sim_engine_run): Change type of of vaddr and paddr to
2320         address_word.
2321         (address_translation, prefetch, load_memory, store_memory,
2322         cache_op): Change type of vAddr and pAddr to address_word.
2323
2324         * gencode.c (build_instruction): Change type of vaddr and paddr to
2325         address_word.
2326
2327 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2328
2329         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2330         macro to obtain result of ALU op.
2331
2332 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2333
2334         * interp.c (sim_info): Call profile_print.
2335
2336 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2337
2338         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2339
2340         * sim-main.h (WITH_PROFILE): Do not define, defined in
2341         common/sim-config.h.  Use sim-profile module.
2342         (simPROFILE): Delete defintion.
2343
2344         * interp.c (PROFILE): Delete definition.
2345         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2346         (sim_close): Delete code writing profile histogram.
2347         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2348         Delete.
2349         (sim_engine_run): Delete code profiling the PC.
2350
2351 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2352
2353         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2354
2355         * interp.c (sim_monitor): Make register pointers of type
2356         unsigned_word*.
2357
2358         * sim-main.h: Make registers of type unsigned_word not
2359         signed_word.
2360
2361 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2362
2363         * interp.c (sync_operation): Rename from SyncOperation, make
2364         global, add SD argument.
2365         (prefetch): Rename from Prefetch, make global, add SD argument.
2366         (decode_coproc): Make global.
2367
2368         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2369
2370         * gencode.c (build_instruction): Generate DecodeCoproc not
2371         decode_coproc calls.
2372
2373         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2374         (SizeFGR): Move to sim-main.h
2375         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2376         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2377         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2378         sim-main.h.
2379         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2380         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2381         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2382         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2383         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2384         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2385
2386         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2387         exception.
2388         (sim-alu.h): Include.
2389         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2390         (sim_cia): Typedef to instruction_address.
2391
2392 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2393
2394         * Makefile.in (interp.o): Rename generated file engine.c to
2395         oengine.c.
2396
2397         * interp.c: Update.
2398
2399 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2400
2401         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2402
2403 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2404
2405         * gencode.c (build_instruction): For "FPSQRT", output correct
2406         number of arguments to Recip.
2407
2408 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2409
2410         * Makefile.in (interp.o): Depends on sim-main.h
2411
2412         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2413
2414         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2415         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2416         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2417         STATE, DSSTATE): Define
2418         (GPR, FGRIDX, ..): Define.
2419
2420         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2421         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2422         (GPR, FGRIDX, ...): Delete macros.
2423
2424         * interp.c: Update names to match defines from sim-main.h
2425
2426 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2427
2428         * interp.c (sim_monitor): Add SD argument.
2429         (sim_warning): Delete.  Replace calls with calls to
2430         sim_io_eprintf.
2431         (sim_error): Delete. Replace calls with sim_io_error.
2432         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2433         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2434         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2435         argument.
2436         (mips_size): Rename from sim_size. Add SD argument.
2437
2438         * interp.c (simulator): Delete global variable.
2439         (callback): Delete global variable.
2440         (mips_option_handler, sim_open, sim_write, sim_read,
2441         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2442         sim_size,sim_monitor): Use sim_io_* not callback->*.
2443         (sim_open): ZALLOC simulator struct.
2444         (PROFILE): Do not define.
2445
2446 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2449         support.h with corresponding code.
2450
2451         * sim-main.h (word64, uword64), support.h: Move definition to
2452         sim-main.h.
2453         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2454
2455         * support.h: Delete
2456         * Makefile.in: Update dependencies
2457         * interp.c: Do not include.
2458
2459 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2460
2461         * interp.c (address_translation, load_memory, store_memory,
2462         cache_op): Rename to from AddressTranslation et.al., make global,
2463         add SD argument
2464
2465         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2466         CacheOp): Define.
2467
2468         * interp.c (SignalException): Rename to signal_exception, make
2469         global.
2470
2471         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2472
2473         * sim-main.h (SignalException, SignalExceptionInterrupt,
2474         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2475         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2476         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2477         Define.
2478
2479         * interp.c, support.h: Use.
2480
2481 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2482
2483         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2484         to value_fpr / store_fpr. Add SD argument.
2485         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2486         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2487
2488         * sim-main.h (ValueFPR, StoreFPR): Define.
2489
2490 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2491
2492         * interp.c (sim_engine_run): Check consistency between configure
2493         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2494         and HASFPU.
2495
2496         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2497         (mips_fpu): Configure WITH_FLOATING_POINT.
2498         (mips_endian): Configure WITH_TARGET_ENDIAN.
2499         * configure: Update.
2500
2501 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2502
2503         * configure: Regenerated to track ../common/aclocal.m4 changes.
2504
2505 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2506
2507         * configure: Regenerated.
2508
2509 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2510
2511         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2512
2513 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2514
2515         * gencode.c (print_igen_insn_models): Assume certain architectures
2516         include all mips* instructions.
2517         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2518         instruction.
2519
2520         * Makefile.in (tmp.igen): Add target. Generate igen input from
2521         gencode file.
2522
2523         * gencode.c (FEATURE_IGEN): Define.
2524         (main): Add --igen option.  Generate output in igen format.
2525         (process_instructions): Format output according to igen option.
2526         (print_igen_insn_format): New function.
2527         (print_igen_insn_models): New function.
2528         (process_instructions): Only issue warnings and ignore
2529         instructions when no FEATURE_IGEN.
2530
2531 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2532
2533         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2534         MIPS targets.
2535
2536 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2537
2538         * configure: Regenerated to track ../common/aclocal.m4 changes.
2539
2540 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2541
2542         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2543         SIM_RESERVED_BITS): Delete, moved to common.
2544         (SIM_EXTRA_CFLAGS): Update.
2545
2546 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2547
2548         * configure.in: Configure non-strict memory alignment.
2549         * configure: Regenerated to track ../common/aclocal.m4 changes.
2550
2551 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2552
2553         * configure: Regenerated to track ../common/aclocal.m4 changes.
2554
2555 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2556
2557         * gencode.c (SDBBP,DERET): Added (3900) insns.
2558         (RFE): Turn on for 3900.
2559         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2560         (dsstate): Made global.
2561         (SUBTARGET_R3900): Added.
2562         (CANCELDELAYSLOT): New.
2563         (SignalException): Ignore SystemCall rather than ignore and
2564         terminate.  Add DebugBreakPoint handling.
2565         (decode_coproc): New insns RFE, DERET; and new registers Debug
2566         and DEPC protected by SUBTARGET_R3900.
2567         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2568         bits explicitly.
2569         * Makefile.in,configure.in: Add mips subtarget option.
2570         * configure: Update.
2571
2572 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2573
2574         * gencode.c: Add r3900 (tx39).
2575
2576
2577 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2578
2579         * gencode.c (build_instruction): Don't need to subtract 4 for
2580         JALR, just 2.
2581
2582 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2583
2584         * interp.c: Correct some HASFPU problems.
2585
2586 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2587
2588         * configure: Regenerated to track ../common/aclocal.m4 changes.
2589
2590 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2591
2592         * interp.c (mips_options): Fix samples option short form, should
2593         be `x'.
2594
2595 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2596
2597         * interp.c (sim_info): Enable info code.  Was just returning.
2598
2599 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2600
2601         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2602         MFC0.
2603
2604 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2605
2606         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2607         constants.
2608         (build_instruction): Ditto for LL.
2609
2610 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2611
2612         * configure: Regenerated to track ../common/aclocal.m4 changes.
2613
2614 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2615
2616         * configure: Regenerated to track ../common/aclocal.m4 changes.
2617         * config.in: Ditto.
2618
2619 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2620
2621         * interp.c (sim_open): Add call to sim_analyze_program, update
2622         call to sim_config.
2623
2624 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2625
2626         * interp.c (sim_kill): Delete.
2627         (sim_create_inferior): Add ABFD argument. Set PC from same.
2628         (sim_load): Move code initializing trap handlers from here.
2629         (sim_open): To here.
2630         (sim_load): Delete, use sim-hload.c.
2631
2632         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2633
2634 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2635
2636         * configure: Regenerated to track ../common/aclocal.m4 changes.
2637         * config.in: Ditto.
2638
2639 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2640
2641         * interp.c (sim_open): Add ABFD argument.
2642         (sim_load): Move call to sim_config from here.
2643         (sim_open): To here.  Check return status.
2644
2645 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2646
2647         * gencode.c (build_instruction): Two arg MADD should
2648         not assign result to $0.
2649
2650 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2651
2652         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2653         * sim/mips/configure.in: Regenerate.
2654
2655 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2656
2657         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2658         signed8, unsigned8 et.al. types.
2659
2660         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2661         hosts when selecting subreg.
2662
2663 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2664
2665         * interp.c (sim_engine_run): Reset the ZERO register to zero
2666         regardless of FEATURE_WARN_ZERO.
2667         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2668
2669 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2670
2671         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2672         (SignalException): For BreakPoints ignore any mode bits and just
2673         save the PC.
2674         (SignalException): Always set the CAUSE register.
2675
2676 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2677
2678         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2679         exception has been taken.
2680
2681         * interp.c: Implement the ERET and mt/f sr instructions.
2682
2683 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2684
2685         * interp.c (SignalException): Don't bother restarting an
2686         interrupt.
2687
2688 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2689
2690         * interp.c (SignalException): Really take an interrupt.
2691         (interrupt_event): Only deliver interrupts when enabled.
2692
2693 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2694
2695         * interp.c (sim_info): Only print info when verbose.
2696         (sim_info) Use sim_io_printf for output.
2697
2698 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2699
2700         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2701         mips architectures.
2702
2703 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2704
2705         * interp.c (sim_do_command): Check for common commands if a
2706         simulator specific command fails.
2707
2708 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2709
2710         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2711         and simBE when DEBUG is defined.
2712
2713 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2714
2715         * interp.c (interrupt_event): New function.  Pass exception event
2716         onto exception handler.
2717
2718         * configure.in: Check for stdlib.h.
2719         * configure: Regenerate.
2720
2721         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2722         variable declaration.
2723         (build_instruction): Initialize memval1.
2724         (build_instruction): Add UNUSED attribute to byte, bigend,
2725         reverse.
2726         (build_operands): Ditto.
2727
2728         * interp.c: Fix GCC warnings.
2729         (sim_get_quit_code): Delete.
2730
2731         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2732         * Makefile.in: Ditto.
2733         * configure: Re-generate.
2734
2735         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2736
2737 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2738
2739         * interp.c (mips_option_handler): New function parse argumes using
2740         sim-options.
2741         (myname): Replace with STATE_MY_NAME.
2742         (sim_open): Delete check for host endianness - performed by
2743         sim_config.
2744         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2745         (sim_open): Move much of the initialization from here.
2746         (sim_load): To here.  After the image has been loaded and
2747         endianness set.
2748         (sim_open): Move ColdReset from here.
2749         (sim_create_inferior): To here.
2750         (sim_open): Make FP check less dependant on host endianness.
2751
2752         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2753         run.
2754         * interp.c (sim_set_callbacks): Delete.
2755
2756         * interp.c (membank, membank_base, membank_size): Replace with
2757         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2758         (sim_open): Remove call to callback->init. gdb/run do this.
2759
2760         * interp.c: Update
2761
2762         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2763
2764         * interp.c (big_endian_p): Delete, replaced by
2765         current_target_byte_order.
2766
2767 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2768
2769         * interp.c (host_read_long, host_read_word, host_swap_word,
2770         host_swap_long): Delete. Using common sim-endian.
2771         (sim_fetch_register, sim_store_register): Use H2T.
2772         (pipeline_ticks): Delete.  Handled by sim-events.
2773         (sim_info): Update.
2774         (sim_engine_run): Update.
2775
2776 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2777
2778         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2779         reason from here.
2780         (SignalException): To here. Signal using sim_engine_halt.
2781         (sim_stop_reason): Delete, moved to common.
2782
2783 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2784
2785         * interp.c (sim_open): Add callback argument.
2786         (sim_set_callbacks): Delete SIM_DESC argument.
2787         (sim_size): Ditto.
2788
2789 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2790
2791         * Makefile.in (SIM_OBJS): Add common modules.
2792
2793         * interp.c (sim_set_callbacks): Also set SD callback.
2794         (set_endianness, xfer_*, swap_*): Delete.
2795         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2796         Change to functions using sim-endian macros.
2797         (control_c, sim_stop): Delete, use common version.
2798         (simulate): Convert into.
2799         (sim_engine_run): This function.
2800         (sim_resume): Delete.
2801
2802         * interp.c (simulation): New variable - the simulator object.
2803         (sim_kind): Delete global - merged into simulation.
2804         (sim_load): Cleanup.  Move PC assignment from here.
2805         (sim_create_inferior): To here.
2806
2807         * sim-main.h: New file.
2808         * interp.c (sim-main.h): Include.
2809
2810 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2811
2812         * configure: Regenerated to track ../common/aclocal.m4 changes.
2813
2814 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2815
2816         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2817
2818 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2819
2820         * gencode.c (build_instruction): DIV instructions: check
2821         for division by zero and integer overflow before using
2822         host's division operation.
2823
2824 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2825
2826         * Makefile.in (SIM_OBJS): Add sim-load.o.
2827         * interp.c: #include bfd.h.
2828         (target_byte_order): Delete.
2829         (sim_kind, myname, big_endian_p): New static locals.
2830         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2831         after argument parsing.  Recognize -E arg, set endianness accordingly.
2832         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2833         load file into simulator.  Set PC from bfd.
2834         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2835         (set_endianness): Use big_endian_p instead of target_byte_order.
2836
2837 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2838
2839         * interp.c (sim_size): Delete prototype - conflicts with
2840         definition in remote-sim.h.  Correct definition.
2841
2842 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2843
2844         * configure: Regenerated to track ../common/aclocal.m4 changes.
2845         * config.in: Ditto.
2846
2847 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2848
2849         * interp.c (sim_open): New arg `kind'.
2850
2851         * configure: Regenerated to track ../common/aclocal.m4 changes.
2852
2853 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2854
2855         * configure: Regenerated to track ../common/aclocal.m4 changes.
2856
2857 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2858
2859         * interp.c (sim_open): Set optind to 0 before calling getopt.
2860
2861 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2862
2863         * configure: Regenerated to track ../common/aclocal.m4 changes.
2864
2865 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2866
2867         * interp.c : Replace uses of pr_addr with pr_uword64
2868         where the bit length is always 64 independent of SIM_ADDR.
2869         (pr_uword64) : added.
2870
2871 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2872
2873         * configure: Re-generate.
2874
2875 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2876
2877         * configure: Regenerate to track ../common/aclocal.m4 changes.
2878
2879 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2880
2881         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2882         in argv form.
2883         (other sim_*): New SIM_DESC argument.
2884
2885 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2886
2887         * interp.c: Fix printing of addresses for non-64-bit targets.
2888         (pr_addr): Add function to print address based on size.
2889
2890 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2891
2892         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2893
2894 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2895
2896         * gencode.c (build_mips16_operands): Correct computation of base
2897         address for extended PC relative instruction.
2898
2899 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2900
2901         * interp.c (mips16_entry): Add support for floating point cases.
2902         (SignalException): Pass floating point cases to mips16_entry.
2903         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2904         registers.
2905         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2906         or fmt_word.
2907         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2908         and then set the state to fmt_uninterpreted.
2909         (COP_SW): Temporarily set the state to fmt_word while calling
2910         ValueFPR.
2911
2912 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2913
2914         * gencode.c (build_instruction): The high order may be set in the
2915         comparison flags at any ISA level, not just ISA 4.
2916
2917 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2918
2919         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2920         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2921         * configure.in: sinclude ../common/aclocal.m4.
2922         * configure: Regenerated.
2923
2924 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2925
2926         * configure: Rebuild after change to aclocal.m4.
2927
2928 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2929
2930         * configure configure.in Makefile.in:  Update to new configure
2931         scheme which is more compatible with WinGDB builds.
2932         * configure.in:  Improve comment on how to run autoconf.
2933         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2934         * Makefile.in:  Use autoconf substitution to install common
2935         makefile fragment.
2936
2937 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2938
2939         * gencode.c (build_instruction): Use BigEndianCPU instead of
2940         ByteSwapMem.
2941
2942 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2943
2944         * interp.c (sim_monitor): Make output to stdout visible in
2945         wingdb's I/O log window.
2946
2947 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2948
2949         * support.h: Undo previous change to SIGTRAP
2950         and SIGQUIT values.
2951
2952 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2953
2954         * interp.c (store_word, load_word): New static functions.
2955         (mips16_entry): New static function.
2956         (SignalException): Look for mips16 entry and exit instructions.
2957         (simulate): Use the correct index when setting fpr_state after
2958         doing a pending move.
2959
2960 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2961
2962         * interp.c: Fix byte-swapping code throughout to work on
2963         both little- and big-endian hosts.
2964
2965 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2966
2967         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2968         with gdb/config/i386/xm-windows.h.
2969
2970 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2971
2972         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2973         that messes up arithmetic shifts.
2974
2975 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2976
2977         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2978         SIGTRAP and SIGQUIT for _WIN32.
2979
2980 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2981
2982         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2983         force a 64 bit multiplication.
2984         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2985         destination register is 0, since that is the default mips16 nop
2986         instruction.
2987
2988 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2989
2990         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2991         (build_endian_shift): Don't check proc64.
2992         (build_instruction): Always set memval to uword64.  Cast op2 to
2993         uword64 when shifting it left in memory instructions.  Always use
2994         the same code for stores--don't special case proc64.
2995
2996         * gencode.c (build_mips16_operands): Fix base PC value for PC
2997         relative operands.
2998         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2999         jal instruction.
3000         * interp.c (simJALDELAYSLOT): Define.
3001         (JALDELAYSLOT): Define.
3002         (INDELAYSLOT, INJALDELAYSLOT): Define.
3003         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3004
3005 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
3006
3007         * interp.c (sim_open): add flush_cache as a PMON routine
3008         (sim_monitor): handle flush_cache by ignoring it
3009
3010 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
3011
3012         * gencode.c (build_instruction): Use !ByteSwapMem instead of
3013         BigEndianMem.
3014         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3015         (BigEndianMem): Rename to ByteSwapMem and change sense.
3016         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3017         BigEndianMem references to !ByteSwapMem.
3018         (set_endianness): New function, with prototype.
3019         (sim_open): Call set_endianness.
3020         (sim_info): Use simBE instead of BigEndianMem.
3021         (xfer_direct_word, xfer_direct_long, swap_direct_word,
3022         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3023         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3024         ifdefs, keeping the prototype declaration.
3025         (swap_word): Rewrite correctly.
3026         (ColdReset): Delete references to CONFIG.  Delete endianness related
3027         code; moved to set_endianness.
3028
3029 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
3030
3031         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3032         * interp.c (CHECKHILO): Define away.
3033         (simSIGINT): New macro.
3034         (membank_size): Increase from 1MB to 2MB.
3035         (control_c): New function.
3036         (sim_resume): Rename parameter signal to signal_number.  Add local
3037         variable prev.  Call signal before and after simulate.
3038         (sim_stop_reason): Add simSIGINT support.
3039         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3040         functions always.
3041         (sim_warning): Delete call to SignalException.  Do call printf_filtered
3042         if logfh is NULL.
3043         (AddressTranslation): Add #ifdef DEBUG around debugging message and
3044         a call to sim_warning.
3045
3046 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
3047
3048         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3049         16 bit instructions.
3050
3051 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3052
3053         Add support for mips16 (16 bit MIPS implementation):
3054         * gencode.c (inst_type): Add mips16 instruction encoding types.
3055         (GETDATASIZEINSN): Define.
3056         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
3057         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
3058         mtlo.
3059         (MIPS16_DECODE): New table, for mips16 instructions.
3060         (bitmap_val): New static function.
3061         (struct mips16_op): Define.
3062         (mips16_op_table): New table, for mips16 operands.
3063         (build_mips16_operands): New static function.
3064         (process_instructions): If PC is odd, decode a mips16
3065         instruction.  Break out instruction handling into new
3066         build_instruction function.
3067         (build_instruction): New static function, broken out of
3068         process_instructions.  Check modifiers rather than flags for SHIFT
3069         bit count and m[ft]{hi,lo} direction.
3070         (usage): Pass program name to fprintf.
3071         (main): Remove unused variable this_option_optind.  Change
3072         ``*loptarg++'' to ``loptarg++''.
3073         (my_strtoul): Parenthesize && within ||.
3074         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3075         (simulate): If PC is odd, fetch a 16 bit instruction, and
3076         increment PC by 2 rather than 4.
3077         * configure.in: Add case for mips16*-*-*.
3078         * configure: Rebuild.
3079
3080 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
3081
3082         * interp.c: Allow -t to enable tracing in standalone simulator.
3083         Fix garbage output in trace file and error messages.
3084
3085 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
3086
3087         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3088         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3089         * configure.in: Simplify using macros in ../common/aclocal.m4.
3090         * configure: Regenerated.
3091         * tconfig.in: New file.
3092
3093 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3094
3095         * interp.c: Fix bugs in 64-bit port.
3096         Use ansi function declarations for msvc compiler.
3097         Initialize and test file pointer in trace code.
3098         Prevent duplicate definition of LAST_EMED_REGNUM.
3099
3100 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3101
3102         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3103
3104 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3105
3106         * interp.c (SignalException): Check for explicit terminating
3107         breakpoint value.
3108         * gencode.c: Pass instruction value through SignalException()
3109         calls for Trap, Breakpoint and Syscall.
3110
3111 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3112
3113         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3114         only used on those hosts that provide it.
3115         * configure.in: Add sqrt() to list of functions to be checked for.
3116         * config.in: Re-generated.
3117         * configure: Re-generated.
3118
3119 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3120
3121         * gencode.c (process_instructions): Call build_endian_shift when
3122         expanding STORE RIGHT, to fix swr.
3123         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3124         clear the high bits.
3125         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3126         Fix float to int conversions to produce signed values.
3127
3128 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3129
3130         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3131         (process_instructions): Correct handling of nor instruction.
3132         Correct shift count for 32 bit shift instructions. Correct sign
3133         extension for arithmetic shifts to not shift the number of bits in
3134         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3135         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3136         Fix madd.
3137         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3138         It's OK to have a mult follow a mult.  What's not OK is to have a
3139         mult follow an mfhi.
3140         (Convert): Comment out incorrect rounding code.
3141
3142 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3143
3144         * interp.c (sim_monitor): Improved monitor printf
3145         simulation. Tidied up simulator warnings, and added "--log" option
3146         for directing warning message output.
3147         * gencode.c: Use sim_warning() rather than WARNING macro.
3148
3149 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3150
3151         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3152         getopt1.o, rather than on gencode.c.  Link objects together.
3153         Don't link against -liberty.
3154         (gencode.o, getopt.o, getopt1.o): New targets.
3155         * gencode.c: Include <ctype.h> and "ansidecl.h".
3156         (AND): Undefine after including "ansidecl.h".
3157         (ULONG_MAX): Define if not defined.
3158         (OP_*): Don't define macros; now defined in opcode/mips.h.
3159         (main): Call my_strtoul rather than strtoul.
3160         (my_strtoul): New static function.
3161
3162 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3163
3164         * gencode.c (process_instructions):  Generate word64 and uword64
3165         instead of `long long' and `unsigned long long' data types.
3166         * interp.c:  #include sysdep.h to get signals, and define default
3167         for SIGBUS.
3168         * (Convert):  Work around for Visual-C++ compiler bug with type
3169         conversion.
3170         * support.h:  Make things compile under Visual-C++ by using
3171         __int64 instead of `long long'.  Change many refs to long long
3172         into word64/uword64 typedefs.
3173
3174 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3175
3176         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3177         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3178         (docdir): Removed.
3179         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3180         (AC_PROG_INSTALL): Added.
3181         (AC_PROG_CC): Moved to before configure.host call.
3182         * configure: Rebuilt.
3183
3184 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3185
3186         * configure.in: Define @SIMCONF@ depending on mips target.
3187         * configure: Rebuild.
3188         * Makefile.in (run): Add @SIMCONF@ to control simulator
3189         construction.
3190         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3191         * interp.c: Remove some debugging, provide more detailed error
3192         messages, update memory accesses to use LOADDRMASK.
3193
3194 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3195
3196         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3197         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3198         stamp-h.
3199         * configure: Rebuild.
3200         * config.in: New file, generated by autoheader.
3201         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3202         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3203         HAVE_ANINT and HAVE_AINT, as appropriate.
3204         * Makefile.in (run): Use @LIBS@ rather than -lm.
3205         (interp.o): Depend upon config.h.
3206         (Makefile): Just rebuild Makefile.
3207         (clean): Remove stamp-h.
3208         (mostlyclean): Make the same as clean, not as distclean.
3209         (config.h, stamp-h): New targets.
3210
3211 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3212
3213         * interp.c (ColdReset): Fix boolean test. Make all simulator
3214         globals static.
3215
3216 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3217
3218         * interp.c (xfer_direct_word, xfer_direct_long,
3219         swap_direct_word, swap_direct_long, xfer_big_word,
3220         xfer_big_long, xfer_little_word, xfer_little_long,
3221         swap_word,swap_long): Added.
3222         * interp.c (ColdReset): Provide function indirection to
3223         host<->simulated_target transfer routines.
3224         * interp.c (sim_store_register, sim_fetch_register): Updated to
3225         make use of indirected transfer routines.
3226
3227 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3228
3229         * gencode.c (process_instructions): Ensure FP ABS instruction
3230         recognised.
3231         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3232         system call support.
3233
3234 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3235
3236         * interp.c (sim_do_command): Complain if callback structure not
3237         initialised.
3238
3239 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3240
3241         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3242         support for Sun hosts.
3243         * Makefile.in (gencode): Ensure the host compiler and libraries
3244         used for cross-hosted build.
3245
3246 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3247
3248         * interp.c, gencode.c: Some more (TODO) tidying.
3249
3250 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3251
3252         * gencode.c, interp.c: Replaced explicit long long references with
3253         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3254         * support.h (SET64LO, SET64HI): Macros added.
3255
3256 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3257
3258         * configure: Regenerate with autoconf 2.7.
3259
3260 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3261
3262         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3263         * support.h: Remove superfluous "1" from #if.
3264         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3265
3266 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3267
3268         * interp.c (StoreFPR): Control UndefinedResult() call on
3269         WARN_RESULT manifest.
3270
3271 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3272
3273         * gencode.c: Tidied instruction decoding, and added FP instruction
3274         support.
3275
3276         * interp.c: Added dineroIII, and BSD profiling support. Also
3277         run-time FP handling.
3278
3279 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3280
3281         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3282         gencode.c, interp.c, support.h: created.