sim/mips/ChangeLog

   1 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
   4
   5 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * configure: Regenerate.
   8
   9 2021-01-30  Mike Frysinger  <vapier@gentoo.org>
  10
  11         * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
  12
  13 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  14
  15         * config.in, configure: Regenerate.
  16         * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
  17         and strings.h include.
  18
  19 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  20
  21         * configure: Regenerate.
  22
  23 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  24
  25         * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
  26         * configure: Regenerate.
  27
  28 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
  29
  30         * configure: Regenerate.
  31
  32 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
  33
  34         * configure: Regenerate.
  35
  36 2020-12-31  Pavel I. Kryukov  <kryukov@frtk.ru>  (tiny change)
  37
  38         *  sim-main.c: Include <stdlib.h>.
  39
  40 2020-12-14  Pavel I. Kryukov  <kryukov@frtk.ru>  (tiny change)
  41
  42         * cp1.c: Include <stdlib.h>.
  43
  44 2020-07-29  Simon Marchi  <simon.marchi@efficios.com>
  45
  46         * configure: Re-generate.
  47
  48 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  49
  50         * configure: Regenerate.
  51
  52 2016-11-11  Mike Frysinger  <vapier@gentoo.org>
  53
  54         PR sim/20808
  55         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
  56         and SD to sd.
  57
  58 2016-11-11  Mike Frysinger  <vapier@gentoo.org>
  59
  60         PR sim/20809
  61         * mips.igen (check_u64): Enable for `r3900'.
  62
  63 2016-02-05  Mike Frysinger  <vapier@gentoo.org>
  64
  65         * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
  66         STATE_PROG_BFD (sd).
  67         * configure: Regenerate.
  68
  69 2016-01-18  Andrew Bennett  <andrew.bennett@imgtec.com>
  70             Maciej W. Rozycki  <macro@imgtec.com>
  71
  72         PR sim/19441
  73         * micromips.igen (delayslot_micromips): Enable for `micromips32',
  74         `micromips64' and `micromipsdsp' only.
  75         (process_isa_mode): Enable for `micromips32' and `micromips64' only.
  76         (do_micromips_jalr, do_micromips_jal): Likewise.
  77         (compute_movep_src_reg): Likewise.
  78         (compute_andi16_imm): Likewise.
  79         (convert_fmt_micromips): Likewise.
  80         (convert_fmt_micromips_cvt_d): Likewise.
  81         (convert_fmt_micromips_cvt_s): Likewise.
  82         (FMT_MICROMIPS): Likewise.
  83         (FMT_MICROMIPS_CVT_D): Likewise.
  84         (FMT_MICROMIPS_CVT_S): Likewise.
  85
  86 2016-01-12  Mike Frysinger  <vapier@gentoo.org>
  87
  88         * interp.c: Include elf-bfd.h.
  89         (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
  90         ELFCLASS32.
  91
  92 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  93
  94         * config.in, configure: Regenerate.
  95
  96 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * configure: Regenerate.
  99
 100 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 101
 102         * configure: Regenerate.
 103
 104 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 105
 106         * configure: Regenerate.
 107
 108 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * configure: Regenerate.
 111
 112 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 113
 114         * configure.ac (SIM_AC_OPTION_SMP): Delete call.
 115         * configure: Regenerate.
 116
 117 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 118
 119         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 120         * configure: Regenerate.
 121
 122 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 123
 124         * configure: Regenerate.
 125
 126 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 127
 128         * configure: Regenerate.
 129
 130 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 131
 132         * config.in, configure: Regenerate.
 133
 134 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 135
 136         * interp.c (sim_open): Mark argv const.
 137         (sim_create_inferior): Mark argv and env const.
 138
 139 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 140
 141         * configure: Regenerate.
 142
 143 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 144
 145         * interp.c (sim_open): Update sim_parse_args comment.
 146
 147 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 148
 149         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 150         * configure: Regenerate.
 151
 152 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 153
 154         * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
 155         (default_endian): Likewise.  Change BIG_ENDIAN to BIG.
 156         * configure: Regenerate.
 157         * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
 158
 159 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 160
 161         * dv-tx3904cpu.c (CPU, SD): Delete.
 162
 163 2015-12-30  Mike Frysinger  <vapier@gentoo.org>
 164
 165         * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
 166         (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
 167         (sim_store_register): Rename to ...
 168         (mips_reg_store): ... this.  Delete local cpu var.
 169         Update sim_io_eprintf calls.
 170         (sim_fetch_register): Rename to ...
 171         (mips_reg_fetch): ... this.  Delete local cpu var.
 172         Update sim_io_eprintf calls.
 173
 174 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 175
 176         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 177
 178 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 179
 180         * config.in, configure: Regenerate.
 181
 182 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 183
 184         * interp.c (sim_write, sim_read): Delete.
 185         (store_word): Delete call to AddressTranslation and set paddr=vaddr.
 186         (load_word): Likewise.
 187         * micromips.igen (cache): Likewise.
 188         * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
 189         do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
 190         do_store_left, do_store_right, do_load_double, do_store_double):
 191         Likewise.
 192         (do_pref): Delete call to AddressTranslation and stub out Prefetch.
 193         (do_prefx): Likewise.
 194         * sim-main.c (address_translation, prefetch): Delete.
 195         (ifetch32, ifetch16): Delete call to AddressTranslation and set
 196         paddr=vaddr.
 197         * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
 198         address_translation, AddressTranslation, prefetch, Prefetch): Delete.
 199         (LoadMemory, StoreMemory): Delete CCA arg.
 200
 201 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 202
 203         * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
 204         * configure: Regenerated.
 205
 206 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 207
 208         * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
 209         * tconfig.h: Delete.
 210
 211 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 212
 213         * tconfig.h (SIM_HANDLES_LMA): Delete.
 214
 215 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 216
 217         * sim-main.h (WITH_WATCHPOINTS): Delete.
 218
 219 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 220
 221         * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
 222
 223 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 224
 225         * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
 226
 227 2015-12-15  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 228
 229         * micromips.igen (process_isa_mode): Fix left shift of negative
 230         value.
 231
 232 2015-11-17  Mike Frysinger  <vapier@gentoo.org>
 233
 234         * sim-main.h (WITH_MODULO_MEMORY): Delete.
 235
 236 2015-11-15  Mike Frysinger  <vapier@gentoo.org>
 237
 238         * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
 239
 240 2015-11-14  Mike Frysinger  <vapier@gentoo.org>
 241
 242         * interp.c (sim_close): Rename to ...
 243         (mips_sim_close): ... this.  Delete calls to sim_module_uninstall and
 244         sim_io_shutdown.
 245         * sim-main.h (mips_sim_close): Declare.
 246         (SIM_CLOSE_HOOK): Define.
 247
 248 2015-09-25  Andrew Bennett  <andrew.bennett@imgtec.com>
 249             Ali Lown  <ali.lown@imgtec.com>
 250
 251         * Makefile.in (tmp-micromips): New rule.
 252         (tmp-mach-multi): Add support for micromips.
 253         * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
 254         that works for both mips64 and micromips64.
 255         (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
 256         micromips32.
 257         Add build support for micromips.
 258         * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
 259         do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
 260         do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
 261         do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
 262         do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
 263         do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
 264         do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
 265         do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
 266         Refactored instruction code to use these functions.
 267         * dsp2.igen: Refactored instruction code to use the new functions.
 268         * interp.c (decode_coproc): Refactored to work with any instruction
 269         encoding.
 270         (isa_mode): New variable
 271         (RSVD_INSTRUCTION): Changed to 0x00000039.
 272         * m16.igen (BREAK16): Refactored instruction to use do_break16.
 273         (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
 274         * micromips.dc: New file.
 275         * micromips.igen: New file.
 276         * micromips16.dc: New file.
 277         * micromipsdsp.igen: New file.
 278         * micromipsrun.c: New file.
 279         * mips.igen (do_swc1): Changed to work with any instruction encoding.
 280         (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
 281         do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
 282         do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
 283         do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
 284         do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
 285         do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
 286         do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
 287         do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
 288         do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
 289         do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
 290         do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
 291         do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
 292         do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
 293         do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
 294         do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
 295         do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
 296         do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
 297         do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
 298         instructions.
 299         Refactored instruction code to use these functions.
 300         (RSVD): Changed to use new reserved instruction.
 301         (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
 302         check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
 303         do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
 304         do_store_double):  Added micromips32 and micromips64 models.
 305         Added include for micromips.igen and micromipsdsp.igen
 306         Add micromips32 and micromips64 models.
 307         (DecodeCoproc): Updated to use new macro definition.
 308         * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
 309         do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
 310         do_seb, do_seh do_rdhwr, do_wsbh): New functions.
 311         Refactored instruction code to use these functions.
 312         * sim-main.h (CP0_operation): New enum.
 313         (DecodeCoproc): Updated macro.
 314         (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
 315         MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
 316         MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
 317         ISA_MODE_MICROMIPS): New defines.
 318         (sim_state): Add isa_mode field.
 319
 320 2015-06-23  Mike Frysinger  <vapier@gentoo.org>
 321
 322         * configure: Regenerate.
 323
 324 2015-06-12  Mike Frysinger  <vapier@gentoo.org>
 325
 326         * configure.ac: Change configure.in to configure.ac.
 327         * configure: Regenerate.
 328
 329 2015-06-12  Mike Frysinger  <vapier@gentoo.org>
 330
 331         * configure: Regenerate.
 332
 333 2015-06-12  Mike Frysinger  <vapier@gentoo.org>
 334
 335         * interp.c [TRACE]: Delete.
 336         (TRACE): Change to WITH_TRACE_ANY_P.
 337         [!WITH_TRACE_ANY_P] (open_trace): Define.
 338         (mips_option_handler, open_trace, sim_close, dotrace):
 339         Change defined(TRACE) to WITH_TRACE_ANY_P.
 340         (sim_open): Delete TRACE ifdef check.
 341         * sim-main.c (load_memory): Delete TRACE ifdef check.
 342         (store_memory): Likewise.
 343         * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
 344         [!WITH_TRACE_ANY_P] (dotrace): Define.
 345
 346 2015-04-18  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
 349         comments.
 350
 351 2015-04-18  Mike Frysinger  <vapier@gentoo.org>
 352
 353         * sim-main.h (SIM_CPU): Delete.
 354
 355 2015-04-18  Mike Frysinger  <vapier@gentoo.org>
 356
 357         * sim-main.h (sim_cia): Delete.
 358
 359 2015-04-17  Mike Frysinger  <vapier@gentoo.org>
 360
 361         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
 362         PU_PC_GET.
 363         * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
 364         (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
 365         * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
 366         CIA_SET to CPU_PC_SET.
 367         * sim-main.h (CIA_GET, CIA_SET): Delete.
 368
 369 2015-04-15  Mike Frysinger  <vapier@gentoo.org>
 370
 371         * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
 372         * sim-main.h (STATE_CPU): Delete.
 373
 374 2015-04-13  Mike Frysinger  <vapier@gentoo.org>
 375
 376         * configure: Regenerate.
 377
 378 2015-04-13  Mike Frysinger  <vapier@gentoo.org>
 379
 380         * Makefile.in (SIM_OBJS): Add sim-cpu.o.
 381         * interp.c (mips_pc_get, mips_pc_set): New functions.
 382         (sim_open): Declare new local var i.  Call sim_cpu_alloc_all.
 383         Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
 384         (sim_pc_get): Delete.
 385         * sim-main.h (SIM_CPU): Define.
 386         (struct sim_state): Change cpu to an array of pointers.
 387         (STATE_CPU): Drop &.
 388
 389 2015-04-13  Mike Frysinger  <vapier@gentoo.org>
 390
 391         * interp.c (mips_option_handler, open_trace, sim_close,
 392         sim_write, sim_read, sim_store_register, sim_fetch_register,
 393         sim_create_inferior, pr_addr, pr_uword64): Convert old style
 394         prototypes.
 395         (sim_open): Convert old style prototype.  Change casts with
 396         sim_write to unsigned char *.
 397         (fetch_str): Change null to unsigned char, and change cast to
 398         unsigned char *.
 399         (sim_monitor): Change c & ch to unsigned char.  Change cast to
 400         unsigned char *.
 401
 402 2015-04-12  Mike Frysinger  <vapier@gentoo.org>
 403
 404         * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
 405
 406 2015-04-06  Mike Frysinger  <vapier@gentoo.org>
 407
 408         * Makefile.in (SIM_OBJS): Delete sim-engine.o.
 409
 410 2015-04-01  Mike Frysinger  <vapier@gentoo.org>
 411
 412         * tconfig.h (SIM_HAVE_PROFILE): Delete.
 413
 414 2015-03-31  Mike Frysinger  <vapier@gentoo.org>
 415
 416         * config.in, configure: Regenerate.
 417
 418 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
 419
 420         * interp.c (sim_pc_get): New function.
 421
 422 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
 423
 424         * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
 425         * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
 426
 427 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
 428
 429         * configure: Regenerate.
 430
 431 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
 432
 433         * configure: Regenerate.
 434
 435 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
 436
 437         * configure: Regenerate.
 438         * configure.ac (mips_extra_objs): Delete.
 439         * Makefile.in (MIPS_EXTRA_OBJS): Delete.
 440         (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
 441
 442 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
 443
 444         * configure: Regenerate.
 445         * configure.ac: Delete sim_hw checks for dv-sockser.
 446
 447 2015-03-16  Mike Frysinger  <vapier@gentoo.org>
 448
 449         * config.in, configure: Regenerate.
 450         * tconfig.in: Rename file ...
 451         * tconfig.h: ... here.
 452
 453 2015-03-15  Mike Frysinger  <vapier@gentoo.org>
 454
 455         * tconfig.in: Delete includes.
 456         [HAVE_DV_SOCKSER]: Delete.
 457
 458 2015-03-14  Mike Frysinger  <vapier@gentoo.org>
 459
 460         * Makefile.in (SIM_RUN_OBJS): Delete.
 461
 462 2015-03-14  Mike Frysinger  <vapier@gentoo.org>
 463
 464         * configure.ac (AC_CHECK_HEADERS): Delete.
 465         * aclocal.m4, configure: Regenerate.
 466
 467 2014-08-19  Alan Modra  <amodra@gmail.com>
 468
 469         * configure: Regenerate.
 470
 471 2014-08-15  Roland McGrath  <mcgrathr@google.com>
 472
 473         * configure: Regenerate.
 474         * config.in: Regenerate.
 475
 476 2014-03-04  Mike Frysinger  <vapier@gentoo.org>
 477
 478         * configure: Regenerate.
 479
 480 2013-09-23  Alan Modra  <amodra@gmail.com>
 481
 482         * configure: Regenerate.
 483
 484 2013-06-03  Mike Frysinger  <vapier@gentoo.org>
 485
 486         * aclocal.m4, configure: Regenerate.
 487
 488 2013-05-10  Freddie Chopin  <freddie_chopin@op.pl>
 489
 490         * configure: Rebuild.
 491
 492 2013-03-26  Mike Frysinger  <vapier@gentoo.org>
 493
 494         * configure: Regenerate.
 495
 496 2013-03-23  Joel Sherrill  <joel.sherrill@oarcorp.com>
 497
 498         * configure.ac: Address use of dv-sockser.o.
 499         * tconfig.in: Conditionalize use of dv_sockser_install.
 500         * configure: Regenerated.
 501         * config.in: Regenerated.
 502
 503 2012-10-04  Chao-ying Fu  <fu@mips.com>
 504             Steve Ellcey  <sellcey@mips.com>
 505
 506         * mips/mips3264r2.igen (rdhwr): New.
 507
 508 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
 509
 510         * configure.ac: Always link against dv-sockser.o.
 511         * configure: Regenerate.
 512
 513 2012-06-15  Joel Brobecker  <brobecker@adacore.com>
 514
 515         * config.in, configure: Regenerate.
 516
 517 2012-05-18  Nick Clifton  <nickc@redhat.com>
 518
 519         PR 14072
 520         * interp.c: Include config.h before system header files.
 521
 522 2012-03-24  Mike Frysinger  <vapier@gentoo.org>
 523
 524         * aclocal.m4, config.in, configure: Regenerate.
 525
 526 2011-12-03  Mike Frysinger  <vapier@gentoo.org>
 527
 528         * aclocal.m4: New file.
 529         * configure: Regenerate.
 530
 531 2011-10-19  Mike Frysinger  <vapier@gentoo.org>
 532
 533         * configure: Regenerate after common/acinclude.m4 update.
 534
 535 2011-10-17  Mike Frysinger  <vapier@gentoo.org>
 536
 537         * configure.ac: Change include to common/acinclude.m4.
 538
 539 2011-10-17  Mike Frysinger  <vapier@gentoo.org>
 540
 541         * configure.ac: Change AC_PREREQ to 2.64.  Delete AC_CONFIG_HEADER
 542         call.  Replace common.m4 include with SIM_AC_COMMON.
 543         * configure: Regenerate.
 544
 545 2011-07-08  Hans-Peter Nilsson  <hp@axis.com>
 546
 547         * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
 548         $(SIM_EXTRA_DEPS).
 549         (tmp-mach-multi): Exit early when igen fails.
 550
 551 2011-07-05  Mike Frysinger  <vapier@gentoo.org>
 552
 553         * interp.c (sim_do_command): Delete.
 554
 555 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 556
 557         * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
 558         (tx3904sio_fifo_reset): Likewise.
 559         * interp.c (sim_monitor): Likewise.
 560
 561 2010-04-14  Mike Frysinger  <vapier@gentoo.org>
 562
 563         * interp.c (sim_write): Add const to buffer arg.
 564
 565 2010-01-18  Masaki Muranaka  <monaka@monami-software.com>  (tiny change)
 566
 567         * interp.c: Don't include sysdep.h
 568
 569 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 570
 571         * configure: Regenerate.
 572
 573 2009-08-22  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 574
 575         * config.in: Regenerate.
 576         * configure: Likewise.
 577
 578         * configure: Regenerate.
 579
 580 2008-07-11  Hans-Peter Nilsson  <hp@axis.com>
 581
 582         * configure: Regenerate to track ../common/common.m4 changes.
 583         * config.in: Ditto.
 584
 585 2008-06-06  Vladimir Prus  <vladimir@codesourcery.com>
 586             Daniel Jacobowitz  <dan@codesourcery.com>
 587             Joseph Myers  <joseph@codesourcery.com>
 588
 589         * configure: Regenerate.
 590
 591 2007-10-22  Richard Sandiford  <rsandifo@nildram.co.uk>
 592
 593         * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
 594         that unconditionally allows fmt_ps.
 595         (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
 596         (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
 597         (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
 598         filter from 64,f to 32,f.
 599         (PREFX): Change filter from 64 to 32.
 600         (LDXC1, LUXC1): Provide separate mips32r2 implementations
 601         that use do_load_double instead of do_load.  Make both LUXC1
 602         versions unpredictable if SizeFGR () != 64.
 603         (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
 604         instead of do_store.  Remove unused variable.  Make both SUXC1
 605         versions unpredictable if SizeFGR () != 64.
 606
 607 2007-10-07  Richard Sandiford  <rsandifo@nildram.co.uk>
 608
 609         * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
 610         (sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
 611         shifts for that case.
 612
 613 2007-09-04  Nick Clifton  <nickc@redhat.com>
 614
 615         * interp.c (options enum): Add OPTION_INFO_MEMORY.
 616         (display_mem_info): New static variable.
 617         (mips_option_handler): Handle OPTION_INFO_MEMORY.
 618         (mips_options): Add info-memory and memory-info.
 619         (sim_open): After processing the command line and board
 620         specification, check display_mem_info.  If it is set then
 621         call the real handler for the --memory-info command line
 622         switch.
 623
 624 2007-08-24  Joel Brobecker  <brobecker@adacore.com>
 625
 626         * configure.ac: Change license of multi-run.c to GPL version 3.
 627         * configure: Regenerate.
 628
 629 2007-06-28  Richard Sandiford  <richard@codesourcery.com>
 630
 631         * configure.ac, configure: Revert last patch.
 632
 633 2007-06-26  Richard Sandiford  <richard@codesourcery.com>
 634
 635         * configure.ac (sim_mipsisa3264_configs): New variable.
 636         (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
 637         every configuration support all four targets, using the triplet to
 638         determine the default.
 639         * configure: Regenerate.
 640
 641 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
 642
 643         * Makefile.in (m16run.o): New rule.
 644
 645 2007-05-15  Thiemo Seufer  <ths@mips.com>
 646
 647         * mips3264r2.igen (DSHD): Fix compile warning.
 648
 649 2007-05-14  Thiemo Seufer  <ths@mips.com>
 650
 651         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
 652         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
 653         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
 654         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
 655         for mips32r2.
 656
 657 2007-03-01  Thiemo Seufer  <ths@mips.com>
 658
 659         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
 660         and mips64.
 661
 662 2007-02-20  Thiemo Seufer  <ths@mips.com>
 663
 664         * dsp.igen: Update copyright notice.
 665         * dsp2.igen: Fix copyright notice.
 666
 667 2007-02-20  Thiemo Seufer  <ths@mips.com>
 668             Chao-Ying Fu  <fu@mips.com>
 669
 670         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
 671         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 672         Add dsp2 to sim_igen_machine.
 673         * configure: Regenerate.
 674         * dsp.igen (do_ph_op): Add MUL support when op = 2.
 675         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
 676         (mulq_rs.ph): Use do_ph_mulq.
 677         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
 678         * mips.igen: Add dsp2 model and include dsp2.igen.
 679         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
 680         for *mips32r2, *mips64r2, *dsp.
 681         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
 682         for *mips32r2, *mips64r2, *dsp2.
 683         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
 684
 685 2007-02-19  Thiemo Seufer  <ths@mips.com>
 686             Nigel Stephens  <nigel@mips.com>
 687
 688         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
 689         jumps with hazard barrier.
 690
 691 2007-02-19  Thiemo Seufer  <ths@mips.com>
 692             Nigel Stephens  <nigel@mips.com>
 693
 694         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
 695         after each call to sim_io_write.
 696
 697 2007-02-19  Thiemo Seufer  <ths@mips.com>
 698             Nigel Stephens  <nigel@mips.com>
 699
 700         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
 701         supported by this simulator.
 702         (decode_coproc): Recognise additional CP0 Config registers
 703         correctly.
 704
 705 2007-02-19  Thiemo Seufer  <ths@mips.com>
 706             Nigel Stephens  <nigel@mips.com>
 707             David Ung  <davidu@mips.com>
 708
 709         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
 710         uninterpreted formats. If fmt is one of the uninterpreted types
 711         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
 712         fmt_word, and fmt_uninterpreted_64 like fmt_long.
 713         (store_fpr): When writing an invalid odd register, set the
 714         matching even register to fmt_unknown, not the following register.
 715         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
 716         the the memory window at offset 0 set by --memory-size command
 717         line option.
 718         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
 719         point register.
 720         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
 721         register.
 722         (sim_monitor): When returning the memory size to the MIPS
 723         application, use the value in STATE_MEM_SIZE, not an arbitrary
 724         hardcoded value.
 725         (cop_lw): Don' mess around with FPR_STATE, just pass
 726         fmt_uninterpreted_32 to StoreFPR.
 727         (cop_sw): Similarly.
 728         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
 729         (cop_sd): Similarly.
 730         * mips.igen (not_word_value): Single version for mips32, mips64
 731         and mips16.
 732
 733 2007-02-19  Thiemo Seufer <ths@mips.com>
 734             Nigel Stephens  <nigel@mips.com>
 735
 736         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
 737         MBytes.
 738
 739 2007-02-17  Thiemo Seufer  <ths@mips.com>
 740
 741         * configure.ac (mips*-sde-elf*): Move in front of generic machine
 742         configuration.
 743         * configure: Regenerate.
 744
 745 2007-02-17  Thiemo Seufer  <ths@mips.com>
 746
 747         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 748         Add mdmx to sim_igen_machine.
 749         (mipsisa64*-*-*): Likewise. Remove dsp.
 750         (mipsisa32*-*-*): Remove dsp.
 751         * configure: Regenerate.
 752
 753 2007-02-13  Thiemo Seufer  <ths@mips.com>
 754
 755         * configure.ac: Add mips*-sde-elf* target.
 756         * configure: Regenerate.
 757
 758 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 759
 760         * acconfig.h: Remove.
 761         * config.in, configure: Regenerate.
 762
 763 2006-11-07  Thiemo Seufer  <ths@mips.com>
 764
 765         * dsp.igen (do_w_op): Fix compiler warning.
 766
 767 2006-08-29  Thiemo Seufer  <ths@mips.com>
 768             David Ung  <davidu@mips.com>
 769
 770         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 771         sim_igen_machine.
 772         * configure: Regenerate.
 773         * mips.igen (model): Add smartmips.
 774         (MADDU): Increment ACX if carry.
 775         (do_mult): Clear ACX.
 776         (ROR,RORV): Add smartmips.
 777         (include): Include smartmips.igen.
 778         * sim-main.h (ACX): Set to REGISTERS[89].
 779         * smartmips.igen: New file.
 780
 781 2006-08-29  Thiemo Seufer  <ths@mips.com>
 782             David Ung  <davidu@mips.com>
 783
 784         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 785         mips3264r2.igen. Add missing dependency rules.
 786         * m16e.igen: Support for mips16e save/restore instructions.
 787
 788 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 789
 790         * configure: Regenerated.
 791
 792 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 793
 794         * configure: Regenerated.
 795
 796 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 797
 798         * configure: Regenerated.
 799
 800 2006-05-15 Chao-ying Fu  <fu@mips.com>
 801
 802         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 803
 804 2006-04-18  Nick Clifton  <nickc@redhat.com>
 805
 806         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 807         statement.
 808
 809 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 810
 811         * configure: Regenerate.
 812
 813 2005-12-14  Chao-ying Fu  <fu@mips.com>
 814
 815         * Makefile.in (SIM_OBJS): Add dsp.o.
 816         (dsp.o): New dependency.
 817         (IGEN_INCLUDE): Add dsp.igen.
 818         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 819         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 820         * configure: Regenerate.
 821         * mips.igen: Add dsp model and include dsp.igen.
 822         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 823         because these instructions are extended in DSP ASE.
 824         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 825         adding 6 DSP accumulator registers and 1 DSP control register.
 826         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 827         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 828         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 829         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 830         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 831         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 832         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 833         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 834         DSPCR_CCOND_SMASK): New define.
 835         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 836         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 837
 838 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 839
 840         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 841
 842 2005-06-16  David Ung  <davidu@mips.com>
 843             Nigel Stephens  <nigel@mips.com>
 844
 845         * mips.igen: New mips16e model and include m16e.igen.
 846         (check_u64): Add mips16e tag.
 847         * m16e.igen: New file for MIPS16e instructions.
 848         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 849         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 850         models.
 851         * configure: Regenerate.
 852
 853 2005-05-26  David Ung  <davidu@mips.com>
 854
 855         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 856         tags to all instructions which are applicable to the new ISAs.
 857         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 858         vr.igen.
 859         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 860         instructions.
 861         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 862         to mips.igen.
 863         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 864         * configure: Regenerate.
 865
 866 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 867
 868         * configure: Regenerate.
 869
 870 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 871
 872         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 873         explicit call to AC_CONFIG_HEADER.
 874         * configure: Regenerate.
 875
 876 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 877
 878         * configure.ac: Update to use ../common/common.m4.
 879         * configure: Re-generate.
 880
 881 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 882
 883         * configure: Regenerated to track ../common/aclocal.m4 changes.
 884
 885 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 886
 887         * configure.ac: Rename configure.in, require autoconf 2.59.
 888         * configure: Re-generate.
 889
 890 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 891
 892         * configure: Regenerate for ../common/aclocal.m4 update.
 893
 894 2004-09-24  Monika Chaddha  <monika@acmet.com>
 895
 896         Committed by Andrew Cagney.
 897         * m16.igen (CMP, CMPI): Fix assembler.
 898
 899 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 900
 901         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 902         * configure: Regenerate.
 903
 904 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 905
 906         * configure.in (sim_m16_machine): Include mipsIII.
 907         * configure: Regenerate.
 908
 909 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 910
 911         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 912         from COP0_BADVADDR.
 913         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 914
 915 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 916
 917         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 918
 919 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 920
 921         * mips.igen (check_fmt): Remove.
 922         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 923         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 924         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 925         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 926         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 927         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 928         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 929         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 930         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 931         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 932
 933 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 934
 935         * sb1.igen (check_sbx): New function.
 936         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 937
 938 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 939             Richard Sandiford  <rsandifo@redhat.com>
 940
 941         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 942         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 943         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 944         separate implementations for mipsIV and mipsV.  Use new macros to
 945         determine whether the restrictions apply.
 946
 947 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 948
 949         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 950         (check_mult_hilo): Improve comments.
 951         (check_div_hilo): Likewise.  Also, fork off a new version
 952         to handle mips32/mips64 (since there are no hazards to check
 953         in MIPS32/MIPS64).
 954
 955 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 956
 957         * mips.igen (do_dmultx): Fix check for negative operands.
 958
 959 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 960
 961         * Makefile.in (SHELL): Make sure this is defined.
 962         (various): Use $(SHELL) whenever we invoke move-if-change.
 963
 964 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 965
 966         * cp1.c: Tweak attribution slightly.
 967         * cp1.h: Likewise.
 968         * mdmx.c: Likewise.
 969         * mdmx.igen: Likewise.
 970         * mips3d.igen: Likewise.
 971         * sb1.igen: Likewise.
 972
 973 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 974
 975         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 976         unsigned operands.
 977
 978 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 979
 980         * interp.c (sim_open): Rename _bfd to bfd.
 981         (sim_create_inferior): Ditto.
 982
 983 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 984
 985         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 986
 987 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 988
 989         * mips.igen (EI, DI): Remove.
 990
 991 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 992
 993         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 994
 995 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 996             Andrew Cagney  <ac131313@redhat.com>
 997             Gavin Romig-Koch  <gavin@redhat.com>
 998             Graydon Hoare  <graydon@redhat.com>
 999             Aldy Hernandez  <aldyh@redhat.com>
1000             Dave Brolley  <brolley@redhat.com>
1001             Chris Demetriou  <cgd@broadcom.com>
1002
1003         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1004         (sim_mach_default): New variable.
1005         (mips64vr-*-*, mips64vrel-*-*): New configurations.
1006         Add a new simulator generator, MULTI.
1007         * configure: Regenerate.
1008         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1009         (multi-run.o): New dependency.
1010         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1011         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1012         (tmp-multi): Combine them.
1013         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
1014         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1015         (distclean-extra): New rule.
1016         * sim-main.h: Include bfd.h.
1017         (MIPS_MACH): New macro.
1018         * mips.igen (vr4120, vr5400, vr5500): New models.
1019         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1020         * vr.igen: Replace with new version.
1021
1022 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
1023
1024         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1025         * configure: Regenerate.
1026
1027 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
1028
1029         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1030         * mips.igen: Remove all invocations of check_branch_bug and
1031         mark_branch_bug.
1032
1033 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
1034
1035         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
1036
1037 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
1038
1039         * mips.igen (do_load_double, do_store_double): New functions.
1040         (LDC1, SDC1): Rename to...
1041         (LDC1b, SDC1b): respectively.
1042         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1043
1044 2002-07-29  Michael Snyder  <msnyder@redhat.com>
1045
1046         * cp1.c (fp_recip2): Modify initialization expression so that
1047         GCC will recognize it as constant.
1048
1049 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
1050
1051         * mdmx.c (SD_): Delete.
1052         (Unpredictable): Re-define, for now, to directly invoke
1053         unpredictable_action().
1054         (mdmx_acc_op): Fix error in .ob immediate handling.
1055
1056 2002-06-18  Andrew Cagney  <cagney@redhat.com>
1057
1058         * interp.c (sim_firmware_command): Initialize `address'.
1059
1060 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
1061
1062         * configure: Regenerated to track ../common/aclocal.m4 changes.
1063
1064 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
1065             Ed Satterthwaite  <ehs@broadcom.com>
1066
1067         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1068         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1069         * mips.igen: Include mips3d.igen.
1070         (mips3d): New model name for MIPS-3D ASE instructions.
1071         (CVT.W.fmt): Don't use this instruction for word (source) format
1072         instructions.
1073         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1074         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1075         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1076         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1077         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1078         (RSquareRoot1, RSquareRoot2): New macros.
1079         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1080         (fp_rsqrt2): New functions.
1081         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1082         * configure: Regenerate.
1083
1084 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
1085             Ed Satterthwaite  <ehs@broadcom.com>
1086
1087         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1088         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1089         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1090         (convert): Note that this function is not used for paired-single
1091         format conversions.
1092         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1093         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1094         (check_fmt_p): Enable paired-single support.
1095         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1096         (PUU.PS): New instructions.
1097         (CVT.S.fmt): Don't use this instruction for paired-single format
1098         destinations.
1099         * sim-main.h (FP_formats): New value 'fmt_ps.'
1100         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1101         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1102
1103 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
1104
1105         * mips.igen: Fix formatting of function calls in
1106         many FP operations.
1107
1108 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
1109
1110         * mips.igen (MOVN, MOVZ): Trace result.
1111         (TNEI): Print "tnei" as the opcode name in traces.
1112         (CEIL.W): Add disassembly string for traces.
1113         (RSQRT.fmt): Make location of disassembly string consistent
1114         with other instructions.
1115
1116 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
1117
1118         * mips.igen (X): Delete unused function.
1119
1120 2002-06-08  Andrew Cagney  <cagney@redhat.com>
1121
1122         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1123
1124 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1125             Ed Satterthwaite  <ehs@broadcom.com>
1126
1127         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1128         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1129         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1130         (fp_nmsub): New prototypes.
1131         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1132         (NegMultiplySub): New defines.
1133         * mips.igen (RSQRT.fmt): Use RSquareRoot().
1134         (MADD.D, MADD.S): Replace with...
1135         (MADD.fmt): New instruction.
1136         (MSUB.D, MSUB.S): Replace with...
1137         (MSUB.fmt): New instruction.
1138         (NMADD.D, NMADD.S): Replace with...
1139         (NMADD.fmt): New instruction.
1140         (NMSUB.D, MSUB.S): Replace with...
1141         (NMSUB.fmt): New instruction.
1142
1143 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1144             Ed Satterthwaite  <ehs@broadcom.com>
1145
1146         * cp1.c: Fix more comment spelling and formatting.
1147         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1148         (denorm_mode): New function.
1149         (fpu_unary, fpu_binary): Round results after operation, collect
1150         status from rounding operations, and update the FCSR.
1151         (convert): Collect status from integer conversions and rounding
1152         operations, and update the FCSR.  Adjust NaN values that result
1153         from conversions.  Convert to use sim_io_eprintf rather than
1154         fprintf, and remove some debugging code.
1155         * cp1.h (fenr_FS): New define.
1156
1157 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1158
1159         * cp1.c (convert): Remove unusable debugging code, and move MIPS
1160         rounding mode to sim FP rounding mode flag conversion code into...
1161         (rounding_mode): New function.
1162
1163 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1164
1165         * cp1.c: Clean up formatting of a few comments.
1166         (value_fpr): Reformat switch statement.
1167
1168 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
1169             Ed Satterthwaite  <ehs@broadcom.com>
1170
1171         * cp1.h: New file.
1172         * sim-main.h: Include cp1.h.
1173         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1174         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1175         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
1176         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1177         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1178         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1179         * cp1.c: Don't include sim-fpu.h; already included by
1180         sim-main.h.  Clean up formatting of some comments.
1181         (NaN, Equal, Less): Remove.
1182         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1183         (fp_cmp): New functions.
1184         * mips.igen (do_c_cond_fmt): Remove.
1185         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1186         Compare.  Add result tracing.
1187         (CxC1): Remove, replace with...
1188         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1189         (DMxC1): Remove, replace with...
1190         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
1191         (MxC1): Remove, replace with...
1192         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
1193
1194 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
1195
1196         * sim-main.h (FGRIDX): Remove, replace all uses with...
1197         (FGR_BASE): New macro.
1198         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1199         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1200         (NR_FGR, FGR): Likewise.
1201         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1202         * mips.igen: Likewise.
1203
1204 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
1205
1206         * cp1.c: Add an FSF Copyright notice to this file.
1207
1208 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
1209             Ed Satterthwaite  <ehs@broadcom.com>
1210
1211         * cp1.c (Infinity): Remove.
1212         * sim-main.h (Infinity): Likewise.
1213
1214         * cp1.c (fp_unary, fp_binary): New functions.
1215         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1216         (fp_sqrt): New functions, implemented in terms of the above.
1217         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1218         (Recip, SquareRoot): Remove (replaced by functions above).
1219         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1220         (fp_recip, fp_sqrt): New prototypes.
1221         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1222         (Recip, SquareRoot): Replace prototypes with #defines which
1223         invoke the functions above.
1224
1225 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1226
1227         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1228         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1229         file, remove PARAMS from prototypes.
1230         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
1231         simulator state arguments.
1232         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
1233         pass simulator state arguments.
1234         * cp1.c (SD): Redefine as CPU_STATE(cpu).
1235         (store_fpr, convert): Remove 'sd' argument.
1236         (value_fpr): Likewise.  Convert to use 'SD' instead.
1237
1238 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1239
1240         * cp1.c (Min, Max): Remove #if 0'd functions.
1241         * sim-main.h (Min, Max): Remove.
1242
1243 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1244
1245         * cp1.c: fix formatting of switch case and default labels.
1246         * interp.c: Likewise.
1247         * sim-main.c: Likewise.
1248
1249 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1250
1251         * cp1.c: Clean up comments which describe FP formats.
1252          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1253
1254 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1255             Ed Satterthwaite  <ehs@broadcom.com>
1256
1257         * configure.in (mipsisa64sb1*-*-*): New target for supporting
1258         Broadcom SiByte SB-1 processor configurations.
1259         * configure: Regenerate.
1260         * sb1.igen: New file.
1261         * mips.igen: Include sb1.igen.
1262         (sb1): New model.
1263         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1264         * mdmx.igen: Add "sb1" model to all appropriate functions and
1265         instructions.
1266         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1267         (ob_func, ob_acc): Reference the above.
1268         (qh_acc): Adjust to keep the same size as ob_acc.
1269         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1270         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1271
1272 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1273
1274         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1275
1276 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
1277             Ed Satterthwaite  <ehs@broadcom.com>
1278
1279         * mips.igen (mdmx): New (pseudo-)model.
1280         * mdmx.c, mdmx.igen: New files.
1281         * Makefile.in (SIM_OBJS): Add mdmx.o.
1282         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1283         New typedefs.
1284         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1285         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1286         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1287         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1288         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1289         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1290         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1291         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1292         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1293         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1294         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1295         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1296         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1297         (qh_fmtsel): New macros.
1298         (_sim_cpu): New member "acc".
1299         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1300         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1301
1302 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
1303
1304         * interp.c: Use 'deprecated' rather than 'depreciated.'
1305         * sim-main.h: Likewise.
1306
1307 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
1308
1309         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1310         which wouldn't compile anyway.
1311         * sim-main.h (unpredictable_action): New function prototype.
1312         (Unpredictable): Define to call igen function unpredictable().
1313         (NotWordValue): New macro to call igen function not_word_value().
1314         (UndefinedResult): Remove.
1315         * interp.c (undefined_result): Remove.
1316         (unpredictable_action): New function.
1317         * mips.igen (not_word_value, unpredictable): New functions.
1318         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1319         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1320         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1321         NotWordValue() to check for unpredictable inputs, then
1322         Unpredictable() to handle them.
1323
1324 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
1325
1326         * mips.igen: Fix formatting of calls to Unpredictable().
1327
1328 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
1329
1330         * interp.c (sim_open): Revert previous change.
1331
1332 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
1333
1334         * interp.c (sim_open): Disable chunk of code that wrote code in
1335         vector table entries.
1336
1337 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
1338
1339         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1340         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1341         unused definitions.
1342
1343 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
1344
1345         * cp1.c: Fix many formatting issues.
1346
1347 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
1348
1349         * cp1.c (fpu_format_name): New function to replace...
1350         (DOFMT): This.  Delete, and update all callers.
1351         (fpu_rounding_mode_name): New function to replace...
1352         (RMMODE): This.  Delete, and update all callers.
1353
1354 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
1355
1356         * interp.c: Move FPU support routines from here to...
1357         * cp1.c: Here.  New file.
1358         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1359         (cp1.o): New target.
1360
1361 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
1362
1363         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1364         * mips.igen (mips32, mips64): New models, add to all instructions
1365         and functions as appropriate.
1366         (loadstore_ea, check_u64): New variant for model mips64.
1367         (check_fmt_p): New variant for models mipsV and mips64, remove
1368         mipsV model marking fro other variant.
1369         (SLL) Rename to...
1370         (SLLa) this.
1371         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1372         for mips32 and mips64.
1373         (DCLO, DCLZ): New instructions for mips64.
1374
1375 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
1376
1377         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1378         immediate or code as a hex value with the "%#lx" format.
1379         (ANDI): Likewise, and fix printed instruction name.
1380
1381 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1382
1383         * sim-main.h (UndefinedResult, Unpredictable): New macros
1384         which currently do nothing.
1385
1386 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1387
1388         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1389         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1390         (status_CU3): New definitions.
1391
1392         * sim-main.h (ExceptionCause): Add new values for MIPS32
1393         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
1394         for DebugBreakPoint and NMIReset to note their status in
1395         MIPS32 and MIPS64.
1396         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1397         (SignalExceptionCacheErr): New exception macros.
1398
1399 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1400
1401         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1402         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1403         is always enabled.
1404         (SignalExceptionCoProcessorUnusable): Take as argument the
1405         unusable coprocessor number.
1406
1407 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1408
1409         * mips.igen: Fix formatting of all SignalException calls.
1410
1411 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1412
1413         * sim-main.h (SIGNEXTEND): Remove.
1414
1415 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
1416
1417         * mips.igen: Remove gencode comment from top of file, fix
1418         spelling in another comment.
1419
1420 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
1421
1422         * mips.igen (check_fmt, check_fmt_p): New functions to check
1423         whether specific floating point formats are usable.
1424         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1425         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1426         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1427         Use the new functions.
1428         (do_c_cond_fmt): Remove format checks...
1429         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1430
1431 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1432
1433         * mips.igen: Fix formatting of check_fpu calls.
1434
1435 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1436
1437         * mips.igen (FLOOR.L.fmt): Store correct destination register.
1438
1439 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1440
1441         * mips.igen: Remove whitespace at end of lines.
1442
1443 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1444
1445         * mips.igen (loadstore_ea): New function to do effective
1446         address calculations.
1447         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1448         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1449         CACHE): Use loadstore_ea to do effective address computations.
1450
1451 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1452
1453         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1454         * mips.igen (LL, CxC1, MxC1): Likewise.
1455
1456 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1457
1458         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1459         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1460         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1461         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1462         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1463         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1464         Don't split opcode fields by hand, use the opcode field values
1465         provided by igen.
1466
1467 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1468
1469         * mips.igen (do_divu): Fix spacing.
1470
1471         * mips.igen (do_dsllv): Move to be right before DSLLV,
1472         to match the rest of the do_<shift> functions.
1473
1474 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1475
1476         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1477         DSRL32, do_dsrlv): Trace inputs and results.
1478
1479 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1480
1481         * mips.igen (CACHE): Provide instruction-printing string.
1482
1483         * interp.c (signal_exception): Comment tokens after #endif.
1484
1485 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1486
1487         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1488         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1489         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1490         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1491         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1492         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1493         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1494         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1495
1496 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1497
1498         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1499         instruction-printing string.
1500         (LWU): Use '64' as the filter flag.
1501
1502 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1503
1504         * mips.igen (SDXC1): Fix instruction-printing string.
1505
1506 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1507
1508         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1509         filter flags "32,f".
1510
1511 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1512
1513         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1514         as the filter flag.
1515
1516 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1517
1518         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1519         add a comma) so that it more closely match the MIPS ISA
1520         documentation opcode partitioning.
1521         (PREF): Put useful names on opcode fields, and include
1522         instruction-printing string.
1523
1524 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1525
1526         * mips.igen (check_u64): New function which in the future will
1527         check whether 64-bit instructions are usable and signal an
1528         exception if not.  Currently a no-op.
1529         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1530         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1531         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1532         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1533
1534         * mips.igen (check_fpu): New function which in the future will
1535         check whether FPU instructions are usable and signal an exception
1536         if not.  Currently a no-op.
1537         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1538         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1539         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1540         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1541         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1542         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1543         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1544         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1545
1546 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1547
1548         * mips.igen (do_load_left, do_load_right): Move to be immediately
1549         following do_load.
1550         (do_store_left, do_store_right): Move to be immediately following
1551         do_store.
1552
1553 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1554
1555         * mips.igen (mipsV): New model name.  Also, add it to
1556         all instructions and functions where it is appropriate.
1557
1558 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
1559
1560         * mips.igen: For all functions and instructions, list model
1561         names that support that instruction one per line.
1562
1563 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1564
1565         * mips.igen: Add some additional comments about supported
1566         models, and about which instructions go where.
1567         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1568         order as is used in the rest of the file.
1569
1570 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1571
1572         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1573         indicating that ALU32_END or ALU64_END are there to check
1574         for overflow.
1575         (DADD): Likewise, but also remove previous comment about
1576         overflow checking.
1577
1578 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1579
1580         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1581         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1582         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1583         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1584         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1585         fields (i.e., add and move commas) so that they more closely
1586         match the MIPS ISA documentation opcode partitioning.
1587
1588 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1589
1590         * mips.igen (ADDI): Print immediate value.
1591         (BREAK): Print code.
1592         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1593         (SLL): Print "nop" specially, and don't run the code
1594         that does the shift for the "nop" case.
1595
1596 2001-11-17  Fred Fish  <fnf@redhat.com>
1597
1598         * sim-main.h (float_operation): Move enum declaration outside
1599         of _sim_cpu struct declaration.
1600
1601 2001-04-12  Jim Blandy  <jimb@redhat.com>
1602
1603         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1604         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
1605         set of the FCSR.
1606         * sim-main.h (COCIDX): Remove definition; this isn't supported by
1607         PENDING_FILL, and you can get the intended effect gracefully by
1608         calling PENDING_SCHED directly.
1609
1610 2001-02-23  Ben Elliston  <bje@redhat.com>
1611
1612         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1613         already defined elsewhere.
1614
1615 2001-02-19  Ben Elliston  <bje@redhat.com>
1616
1617         * sim-main.h (sim_monitor): Return an int.
1618         * interp.c (sim_monitor): Add return values.
1619         (signal_exception): Handle error conditions from sim_monitor.
1620
1621 2001-02-08  Ben Elliston  <bje@redhat.com>
1622
1623         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1624         (store_memory): Likewise, pass cia to sim_core_write*.
1625
1626 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
1627
1628         On advice from Chris G. Demetriou <cgd@sibyte.com>:
1629         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1630
1631 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1632
1633         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1634         * Makefile.in: Don't delete *.igen when cleaning directory.
1635
1636 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1637
1638         * m16.igen (break): Call SignalException not sim_engine_halt.
1639
1640 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1641
1642         From Jason Eckhardt:
1643         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1644
1645 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1646
1647         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1648
1649 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1650
1651         * mips.igen (do_dmultx): Fix typo.
1652
1653 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * configure: Regenerated to track ../common/aclocal.m4 changes.
1656
1657 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1658
1659         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1660
1661 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1662
1663         * sim-main.h (GPR_CLEAR): Define macro.
1664
1665 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1666
1667         * interp.c (decode_coproc): Output long using %lx and not %s.
1668
1669 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1670
1671         * interp.c (sim_open): Sort & extend dummy memory regions for
1672         --board=jmr3904 for eCos.
1673
1674 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1675
1676         * configure: Regenerated.
1677
1678 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1679
1680         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1681         calls, conditional on the simulator being in verbose mode.
1682
1683 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1684
1685         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1686         cache don't get ReservedInstruction traps.
1687
1688 1999-11-29  Mark Salter  <msalter@cygnus.com>
1689
1690         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1691         to clear status bits in sdisr register. This is how the hardware works.
1692
1693         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1694         being used by cygmon.
1695
1696 1999-11-11  Andrew Haley  <aph@cygnus.com>
1697
1698         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1699         instructions.
1700
1701 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1702
1703         * mips.igen (MULT): Correct previous mis-applied patch.
1704
1705 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1706
1707         * mips.igen (delayslot32): Handle sequence like
1708         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1709         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1710         (MULT): Actually pass the third register...
1711
1712 1999-09-03  Mark Salter  <msalter@cygnus.com>
1713
1714         * interp.c (sim_open): Added more memory aliases for additional
1715         hardware being touched by cygmon on jmr3904 board.
1716
1717 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1718
1719         * configure: Regenerated to track ../common/aclocal.m4 changes.
1720
1721 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1722
1723         * interp.c (sim_store_register): Handle case where client - GDB -
1724         specifies that a 4 byte register is 8 bytes in size.
1725         (sim_fetch_register): Ditto.
1726
1727 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1728
1729         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1730         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1731         (idt_monitor_base): Base address for IDT monitor traps.
1732         (pmon_monitor_base): Ditto for PMON.
1733         (lsipmon_monitor_base): Ditto for LSI PMON.
1734         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1735         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1736         (sim_firmware_command): New function.
1737         (mips_option_handler): Call it for OPTION_FIRMWARE.
1738         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1739         option was given, add no monitor by default.  Add BREAK hooks only if
1740         monitors are also there.
1741
1742 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1743
1744         * interp.c (sim_monitor): Flush output before reading input.
1745
1746 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1747
1748         * tconfig.in (SIM_HANDLES_LMA): Always define.
1749
1750 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1751
1752         From Mark Salter <msalter@cygnus.com>:
1753         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1754         (sim_open): Add setup for BSP board.
1755
1756 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1757
1758         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1759         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1760         them as unimplemented.
1761
1762 1999-05-08  Felix Lee  <flee@cygnus.com>
1763
1764         * configure: Regenerated to track ../common/aclocal.m4 changes.
1765
1766 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1767
1768         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1769
1770 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1771
1772         * configure.in: Any mips64vr5*-*-* target should have
1773         -DTARGET_ENABLE_FR=1.
1774         (default_endian): Any mips64vr*el-*-* target should default to
1775         LITTLE_ENDIAN.
1776         * configure: Re-generate.
1777
1778 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1779
1780         * mips.igen (ldl): Extend from _16_, not 32.
1781
1782 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1783
1784         * interp.c (sim_store_register): Force registers written to by GDB
1785         into an un-interpreted state.
1786
1787 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1788
1789         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1790         CPU, start periodic background I/O polls.
1791         (tx3904sio_poll): New function: periodic I/O poller.
1792
1793 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1794
1795         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1796
1797 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1798
1799         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1800         case statement.
1801
1802 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1803
1804         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1805         (load_word): Call SIM_CORE_SIGNAL hook on error.
1806         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1807         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1808         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1809         * sim-main.h (COP0_BADVADDR): Define.
1810         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1811         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1812         (_sim_cpu): Add exc_* fields to store register value snapshots.
1813         * mips.igen (*): Replace memory-related SignalException* calls
1814         with references to SIM_CORE_SIGNAL hook.
1815
1816         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1817         fix.
1818         * sim-main.c (*): Minor warning cleanups.
1819
1820 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1821
1822         * m16.igen (DADDIU5): Correct type-o.
1823
1824 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1825
1826         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1827         variables.
1828
1829 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1830
1831         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1832         to include path.
1833         (interp.o): Add dependency on itable.h
1834         (oengine.c, gencode): Delete remaining references.
1835         (BUILT_SRC_FROM_GEN): Clean up.
1836
1837 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1838
1839         * vr4run.c: New.
1840         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1841         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1842         tmp-run-hack) : New.
1843         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1844         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1845         Drop the "64" qualifier to get the HACK generator working.
1846         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1847         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1848         qualifier to get the hack generator working.
1849         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1850         (DSLL): Use do_dsll.
1851         (DSLLV): Use do_dsllv.
1852         (DSRA): Use do_dsra.
1853         (DSRL): Use do_dsrl.
1854         (DSRLV): Use do_dsrlv.
1855         (BC1): Move *vr4100 to get the HACK generator working.
1856         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1857         get the HACK generator working.
1858         (MACC) Rename to get the HACK generator working.
1859         (DMACC,MACCS,DMACCS): Add the 64.
1860
1861 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1862
1863         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1864         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1865
1866 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1867
1868     * mips/interp.c (DEBUG): Cleanups.
1869
1870 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1871
1872         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1873         (tx3904sio_tickle): fflush after a stdout character output.
1874
1875 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1876
1877         * interp.c (sim_close): Uninstall modules.
1878
1879 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1880
1881         * sim-main.h, interp.c (sim_monitor): Change to global
1882         function.
1883
1884 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1885
1886         * configure.in (vr4100): Only include vr4100 instructions in
1887         simulator.
1888         * configure: Re-generate.
1889         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1890
1891 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1892
1893         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1894         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1895         true alternative.
1896
1897         * configure.in (sim_default_gen, sim_use_gen): Replace with
1898         sim_gen.
1899         (--enable-sim-igen): Delete config option. Always using IGEN.
1900         * configure: Re-generate.
1901
1902         * Makefile.in (gencode): Kill, kill, kill.
1903         * gencode.c: Ditto.
1904
1905 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1906
1907         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1908         bit mips16 igen simulator.
1909         * configure: Re-generate.
1910
1911         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1912         as part of vr4100 ISA.
1913         * vr.igen: Mark all instructions as 64 bit only.
1914
1915 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1916
1917         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1918         Pacify GCC.
1919
1920 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1921
1922         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1923         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1924         * configure: Re-generate.
1925
1926         * m16.igen (BREAK): Define breakpoint instruction.
1927         (JALX32): Mark instruction as mips16 and not r3900.
1928         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1929
1930         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1931
1932 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1935         insn as a debug breakpoint.
1936
1937         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1938         pending.slot_size.
1939         (PENDING_SCHED): Clean up trace statement.
1940         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1941         (PENDING_FILL): Delay write by only one cycle.
1942         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1943
1944         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1945         of pending writes.
1946         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1947         32 & 64.
1948         (pending_tick): Move incrementing of index to FOR statement.
1949         (pending_tick): Only update PENDING_OUT after a write has occured.
1950
1951         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1952         build simulator.
1953         * configure: Re-generate.
1954
1955         * interp.c (sim_engine_run OLD): Delete explicit call to
1956         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1957
1958 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1959
1960         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1961         interrupt level number to match changed SignalExceptionInterrupt
1962         macro.
1963
1964 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1965
1966         * interp.c: #include "itable.h" if WITH_IGEN.
1967         (get_insn_name): New function.
1968         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1969         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1970
1971 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1972
1973         * configure: Rebuilt to inhale new common/aclocal.m4.
1974
1975 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1976
1977         * dv-tx3904sio.c: Include sim-assert.h.
1978
1979 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1980
1981         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1982         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1983         Reorganize target-specific sim-hardware checks.
1984         * configure: rebuilt.
1985         * interp.c (sim_open): For tx39 target boards, set
1986         OPERATING_ENVIRONMENT, add tx3904sio devices.
1987         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1988         ROM executables.  Install dv-sockser into sim-modules list.
1989
1990         * dv-tx3904irc.c: Compiler warning clean-up.
1991         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1992         frequent hw-trace messages.
1993
1994 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1995
1996         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1997
1998 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1999
2000         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2001
2002         * vr.igen: New file.
2003         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2004         * mips.igen: Define vr4100 model. Include vr.igen.
2005 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
2006
2007         * mips.igen (check_mf_hilo): Correct check.
2008
2009 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2010
2011         * sim-main.h (interrupt_event): Add prototype.
2012
2013         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2014         register_ptr, register_value.
2015         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2016
2017         * sim-main.h (tracefh): Make extern.
2018
2019 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
2020
2021         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
2022         Reduce unnecessarily high timer event frequency.
2023         * dv-tx3904cpu.c: Ditto for interrupt event.
2024
2025 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
2026
2027         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2028         to allay warnings.
2029         (interrupt_event): Made non-static.
2030
2031         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2032         interchange of configuration values for external vs. internal
2033         clock dividers.
2034
2035 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
2036
2037         * mips.igen (BREAK): Moved code to here for
2038         simulator-reserved break instructions.
2039         * gencode.c (build_instruction): Ditto.
2040         * interp.c (signal_exception): Code moved from here.  Non-
2041         reserved instructions now use exception vector, rather
2042         than halting sim.
2043         * sim-main.h: Moved magic constants to here.
2044
2045 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
2046
2047         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2048         register upon non-zero interrupt event level, clear upon zero
2049         event value.
2050         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2051         by passing zero event value.
2052         (*_io_{read,write}_buffer): Endianness fixes.
2053         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2054         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2055
2056         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2057         serial I/O and timer module at base address 0xFFFF0000.
2058
2059 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
2060
2061         * mips.igen (SWC1) : Correct the handling of ReverseEndian
2062         and BigEndianCPU.
2063
2064 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
2065
2066         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2067         parts.
2068         * configure: Update.
2069
2070 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
2071
2072         * dv-tx3904tmr.c: New file - implements tx3904 timer.
2073         * dv-tx3904{irc,cpu}.c: Mild reformatting.
2074         * configure.in: Include tx3904tmr in hw_device list.
2075         * configure: Rebuilt.
2076         * interp.c (sim_open): Instantiate three timer instances.
2077         Fix address typo of tx3904irc instance.
2078
2079 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
2080
2081         * interp.c (signal_exception): SystemCall exception now uses
2082         the exception vector.
2083
2084 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
2085
2086         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2087         to allay warnings.
2088
2089 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2090
2091         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2092
2093 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2094
2095         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2096
2097         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2098         sim-main.h. Declare a struct hw_descriptor instead of struct
2099         hw_device_descriptor.
2100
2101 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2102
2103         * mips.igen (do_store_left, do_load_left): Compute nr of left and
2104         right bits and then re-align left hand bytes to correct byte
2105         lanes.  Fix incorrect computation in do_store_left when loading
2106         bytes from second word.
2107
2108 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2109
2110         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2111         * interp.c (sim_open): Only create a device tree when HW is
2112         enabled.
2113
2114         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2115         * interp.c (signal_exception): Ditto.
2116
2117 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
2118
2119         * gencode.c: Mark BEGEZALL as LIKELY.
2120
2121 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2122
2123         * sim-main.h (ALU32_END): Sign extend 32 bit results.
2124         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
2125
2126 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
2127
2128         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2129         modules.  Recognize TX39 target with "mips*tx39" pattern.
2130         * configure: Rebuilt.
2131         * sim-main.h (*): Added many macros defining bits in
2132         TX39 control registers.
2133         (SignalInterrupt): Send actual PC instead of NULL.
2134         (SignalNMIReset): New exception type.
2135         * interp.c (board): New variable for future use to identify
2136         a particular board being simulated.
2137         (mips_option_handler,mips_options): Added "--board" option.
2138         (interrupt_event): Send actual PC.
2139         (sim_open): Make memory layout conditional on board setting.
2140         (signal_exception): Initial implementation of hardware interrupt
2141         handling.  Accept another break instruction variant for simulator
2142         exit.
2143         (decode_coproc): Implement RFE instruction for TX39.
2144         (mips.igen): Decode RFE instruction as such.
2145         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2146         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2147         bbegin to implement memory map.
2148         * dv-tx3904cpu.c: New file.
2149         * dv-tx3904irc.c: New file.
2150
2151 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
2152
2153         * mips.igen (check_mt_hilo): Create a separate r3900 version.
2154
2155 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
2156
2157         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
2158         with calls to check_div_hilo.
2159
2160 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
2161
2162         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2163         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
2164         Add special r3900 version of do_mult_hilo.
2165         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2166         with calls to check_mult_hilo.
2167         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2168         with calls to check_div_hilo.
2169
2170 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2171
2172         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2173         Document a replacement.
2174
2175 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
2176
2177         * interp.c (sim_monitor): Make mon_printf work.
2178
2179 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
2180
2181         * sim-main.h (INSN_NAME): New arg `cpu'.
2182
2183 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
2184
2185         * configure: Regenerated to track ../common/aclocal.m4 changes.
2186
2187 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
2188
2189         * configure: Regenerated to track ../common/aclocal.m4 changes.
2190         * config.in: Ditto.
2191
2192 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
2193
2194         * acconfig.h: New file.
2195         * configure.in: Reverted change of Apr 24; use sinclude again.
2196
2197 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
2198
2199         * configure: Regenerated to track ../common/aclocal.m4 changes.
2200         * config.in: Ditto.
2201
2202 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
2203
2204         * configure.in: Don't call sinclude.
2205
2206 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
2207
2208         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2209
2210 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2211
2212         * mips.igen (ERET): Implement.
2213
2214         * interp.c (decode_coproc): Return sign-extended EPC.
2215
2216         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2217
2218         * interp.c (signal_exception): Do not ignore Trap.
2219         (signal_exception): On TRAP, restart at exception address.
2220         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2221         (signal_exception): Update.
2222         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2223         so that TRAP instructions are caught.
2224
2225 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2226
2227         * sim-main.h (struct hilo_access, struct hilo_history): Define,
2228         contains HI/LO access history.
2229         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2230         (HIACCESS, LOACCESS): Delete, replace with
2231         (HIHISTORY, LOHISTORY): New macros.
2232         (CHECKHILO): Delete all, moved to mips.igen
2233
2234         * gencode.c (build_instruction): Do not generate checks for
2235         correct HI/LO register usage.
2236
2237         * interp.c (old_engine_run): Delete checks for correct HI/LO
2238         register usage.
2239
2240         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2241         check_mf_cycles): New functions.
2242         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2243         do_divu, domultx, do_mult, do_multu): Use.
2244
2245         * tx.igen ("madd", "maddu"): Use.
2246
2247 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2248
2249         * mips.igen (DSRAV): Use function do_dsrav.
2250         (SRAV): Use new function do_srav.
2251
2252         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2253         (B): Sign extend 11 bit immediate.
2254         (EXT-B*): Shift 16 bit immediate left by 1.
2255         (ADDIU*): Don't sign extend immediate value.
2256
2257 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2258
2259         * m16run.c (sim_engine_run): Restore CIA after handling an event.
2260
2261         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2262         functions.
2263
2264         * mips.igen (delayslot32, nullify_next_insn): New functions.
2265         (m16.igen): Always include.
2266         (do_*): Add more tracing.
2267
2268         * m16.igen (delayslot16): Add NIA argument, could be called by a
2269         32 bit MIPS16 instruction.
2270
2271         * interp.c (ifetch16): Move function from here.
2272         * sim-main.c (ifetch16): To here.
2273
2274         * sim-main.c (ifetch16, ifetch32): Update to match current
2275         implementations of LH, LW.
2276         (signal_exception): Don't print out incorrect hex value of illegal
2277         instruction.
2278
2279 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2280
2281         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2282         instruction.
2283
2284         * m16.igen: Implement MIPS16 instructions.
2285
2286         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2287         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2288         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2289         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2290         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
2291         bodies of corresponding code from 32 bit insn to these.  Also used
2292         by MIPS16 versions of functions.
2293
2294         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2295         (IMEM16): Drop NR argument from macro.
2296
2297 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2298
2299         * Makefile.in (SIM_OBJS): Add sim-main.o.
2300
2301         * sim-main.h (address_translation, load_memory, store_memory,
2302         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2303         as INLINE_SIM_MAIN.
2304         (pr_addr, pr_uword64): Declare.
2305         (sim-main.c): Include when H_REVEALS_MODULE_P.
2306
2307         * interp.c (address_translation, load_memory, store_memory,
2308         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2309         from here.
2310         * sim-main.c: To here. Fix compilation problems.
2311
2312         * configure.in: Enable inlining.
2313         * configure: Re-config.
2314
2315 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2316
2317         * configure: Regenerated to track ../common/aclocal.m4 changes.
2318
2319 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2320
2321         * mips.igen: Include tx.igen.
2322         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2323         * tx.igen: New file, contains MADD and MADDU.
2324
2325         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2326         the hardwired constant `7'.
2327         (store_memory): Ditto.
2328         (LOADDRMASK): Move definition to sim-main.h.
2329
2330         mips.igen (MTC0): Enable for r3900.
2331         (ADDU): Add trace.
2332
2333         mips.igen (do_load_byte): Delete.
2334         (do_load, do_store, do_load_left, do_load_write, do_store_left,
2335         do_store_right): New functions.
2336         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2337
2338         configure.in: Let the tx39 use igen again.
2339         configure: Update.
2340
2341 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2342
2343         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2344         not an address sized quantity.  Return zero for cache sizes.
2345
2346 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2347
2348         * mips.igen (r3900): r3900 does not support 64 bit integer
2349         operations.
2350
2351 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
2352
2353         * configure.in (mipstx39*-*-*): Use gencode simulator rather
2354         than igen one.
2355         * configure : Rebuild.
2356
2357 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2358
2359         * configure: Regenerated to track ../common/aclocal.m4 changes.
2360
2361 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2362
2363         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2364
2365 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
2366
2367         * configure: Regenerated to track ../common/aclocal.m4 changes.
2368         * config.in: Regenerated to track ../common/aclocal.m4 changes.
2369
2370 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2371
2372         * configure: Regenerated to track ../common/aclocal.m4 changes.
2373
2374 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2375
2376         * interp.c (Max, Min): Comment out functions. Not yet used.
2377
2378 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2379
2380         * configure: Regenerated to track ../common/aclocal.m4 changes.
2381
2382 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
2383
2384         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2385         configurable settings for stand-alone simulator.
2386
2387         * configure.in: Added X11 search, just in case.
2388
2389         * configure: Regenerated.
2390
2391 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2392
2393         * interp.c (sim_write, sim_read, load_memory, store_memory):
2394         Replace sim_core_*_map with read_map, write_map, exec_map resp.
2395
2396 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2397
2398         * sim-main.h (GETFCC): Return an unsigned value.
2399
2400 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2401
2402         * mips.igen (DIV): Fix check for -1 / MIN_INT.
2403         (DADD): Result destination is RD not RT.
2404
2405 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2406
2407         * sim-main.h (HIACCESS, LOACCESS): Always define.
2408
2409         * mdmx.igen (Maxi, Mini): Rename Max, Min.
2410
2411         * interp.c (sim_info): Delete.
2412
2413 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
2414
2415         * interp.c (DECLARE_OPTION_HANDLER): Use it.
2416         (mips_option_handler): New argument `cpu'.
2417         (sim_open): Update call to sim_add_option_table.
2418
2419 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2420
2421         * mips.igen (CxC1): Add tracing.
2422
2423 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2424
2425         * sim-main.h (Max, Min): Declare.
2426
2427         * interp.c (Max, Min): New functions.
2428
2429         * mips.igen (BC1): Add tracing.
2430
2431 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
2432
2433         * interp.c Added memory map for stack in vr4100
2434
2435 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
2436
2437         * interp.c (load_memory): Add missing "break"'s.
2438
2439 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2440
2441         * interp.c (sim_store_register, sim_fetch_register): Pass in
2442         length parameter.  Return -1.
2443
2444 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
2445
2446         * interp.c: Added hardware init hook, fixed warnings.
2447
2448 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2449
2450         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2451
2452 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2453
2454         * interp.c (ifetch16): New function.
2455
2456         * sim-main.h (IMEM32): Rename IMEM.
2457         (IMEM16_IMMED): Define.
2458         (IMEM16): Define.
2459         (DELAY_SLOT): Update.
2460
2461         * m16run.c (sim_engine_run): New file.
2462
2463         * m16.igen: All instructions except LB.
2464         (LB): Call do_load_byte.
2465         * mips.igen (do_load_byte): New function.
2466         (LB): Call do_load_byte.
2467
2468         * mips.igen: Move spec for insn bit size and high bit from here.
2469         * Makefile.in (tmp-igen, tmp-m16): To here.
2470
2471         * m16.dc: New file, decode mips16 instructions.
2472
2473         * Makefile.in (SIM_NO_ALL): Define.
2474         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2475
2476 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2477
2478         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2479         point unit to 32 bit registers.
2480         * configure: Re-generate.
2481
2482 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2483
2484         * configure.in (sim_use_gen): Make IGEN the default simulator
2485         generator for generic 32 and 64 bit mips targets.
2486         * configure: Re-generate.
2487
2488 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2489
2490         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2491         bitsize.
2492
2493         * interp.c (sim_fetch_register, sim_store_register): Read/write
2494         FGR from correct location.
2495         (sim_open): Set size of FGR's according to
2496         WITH_TARGET_FLOATING_POINT_BITSIZE.
2497
2498         * sim-main.h (FGR): Store floating point registers in a separate
2499         array.
2500
2501 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2502
2503         * configure: Regenerated to track ../common/aclocal.m4 changes.
2504
2505 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2506
2507         * interp.c (ColdReset): Call PENDING_INVALIDATE.
2508
2509         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2510
2511         * interp.c (pending_tick): New function.  Deliver pending writes.
2512
2513         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2514         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2515         it can handle mixed sized quantites and single bits.
2516
2517 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2518
2519         * interp.c (oengine.h): Do not include when building with IGEN.
2520         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2521         (sim_info): Ditto for PROCESSOR_64BIT.
2522         (sim_monitor): Replace ut_reg with unsigned_word.
2523         (*): Ditto for t_reg.
2524         (LOADDRMASK): Define.
2525         (sim_open): Remove defunct check that host FP is IEEE compliant,
2526         using software to emulate floating point.
2527         (value_fpr, ...): Always compile, was conditional on HASFPU.
2528
2529 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2530
2531         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2532         size.
2533
2534         * interp.c (SD, CPU): Define.
2535         (mips_option_handler): Set flags in each CPU.
2536         (interrupt_event): Assume CPU 0 is the one being iterrupted.
2537         (sim_close): Do not clear STATE, deleted anyway.
2538         (sim_write, sim_read): Assume CPU zero's vm should be used for
2539         data transfers.
2540         (sim_create_inferior): Set the PC for all processors.
2541         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2542         argument.
2543         (mips16_entry): Pass correct nr of args to store_word, load_word.
2544         (ColdReset): Cold reset all cpu's.
2545         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2546         (sim_monitor, load_memory, store_memory, signal_exception): Use
2547         `CPU' instead of STATE_CPU.
2548
2549
2550         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2551         SD or CPU_.
2552
2553         * sim-main.h (signal_exception): Add sim_cpu arg.
2554         (SignalException*): Pass both SD and CPU to signal_exception.
2555         * interp.c (signal_exception): Update.
2556
2557         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2558         Ditto
2559         (sync_operation, prefetch, cache_op, store_memory, load_memory,
2560         address_translation): Ditto
2561         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2562
2563 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2564
2565         * configure: Regenerated to track ../common/aclocal.m4 changes.
2566
2567 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2568
2569         * interp.c (sim_engine_run): Add `nr_cpus' argument.
2570
2571         * mips.igen (model): Map processor names onto BFD name.
2572
2573         * sim-main.h (CPU_CIA): Delete.
2574         (SET_CIA, GET_CIA): Define
2575
2576 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2577
2578         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2579         regiser.
2580
2581         * configure.in (default_endian): Configure a big-endian simulator
2582         by default.
2583         * configure: Re-generate.
2584
2585 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
2586
2587         * configure: Regenerated to track ../common/aclocal.m4 changes.
2588
2589 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
2590
2591         * interp.c (sim_monitor): Handle Densan monitor outbyte
2592         and inbyte functions.
2593
2594 1997-12-29  Felix Lee  <flee@cygnus.com>
2595
2596         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2597
2598 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
2599
2600         * Makefile.in (tmp-igen): Arrange for $zero to always be
2601         reset to zero after every instruction.
2602
2603 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2604
2605         * configure: Regenerated to track ../common/aclocal.m4 changes.
2606         * config.in: Ditto.
2607
2608 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
2609
2610         * mips.igen (MSUB): Fix to work like MADD.
2611         * gencode.c (MSUB): Similarly.
2612
2613 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
2614
2615         * configure: Regenerated to track ../common/aclocal.m4 changes.
2616
2617 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2618
2619         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2620
2621 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2622
2623         * sim-main.h (sim-fpu.h): Include.
2624
2625         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2626         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2627         using host independant sim_fpu module.
2628
2629 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2630
2631         * interp.c (signal_exception): Report internal errors with SIGABRT
2632         not SIGQUIT.
2633
2634         * sim-main.h (C0_CONFIG): New register.
2635         (signal.h): No longer include.
2636
2637         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2638
2639 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
2640
2641         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2642
2643 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2644
2645         * mips.igen: Tag vr5000 instructions.
2646         (ANDI): Was missing mipsIV model, fix assembler syntax.
2647         (do_c_cond_fmt): New function.
2648         (C.cond.fmt): Handle mips I-III which do not support CC field
2649         separatly.
2650         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2651         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2652         in IV3.2 spec.
2653         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2654         vr5000 which saves LO in a GPR separatly.
2655
2656         * configure.in (enable-sim-igen): For vr5000, select vr5000
2657         specific instructions.
2658         * configure: Re-generate.
2659
2660 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2661
2662         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2663
2664         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2665         fmt_uninterpreted_64 bit cases to switch.  Convert to
2666         fmt_formatted,
2667
2668         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2669
2670         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2671         as specified in IV3.2 spec.
2672         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2673
2674 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2675
2676         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2677         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2678         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2679         PENDING_FILL versions of instructions.  Simplify.
2680         (X): New function.
2681         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2682         instructions.
2683         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2684         a signed value.
2685         (MTHI, MFHI): Disable code checking HI-LO.
2686
2687         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2688         global.
2689         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2690
2691 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2692
2693         * gencode.c (build_mips16_operands): Replace IPC with cia.
2694
2695         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2696         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2697         IPC to `cia'.
2698         (UndefinedResult): Replace function with macro/function
2699         combination.
2700         (sim_engine_run): Don't save PC in IPC.
2701
2702         * sim-main.h (IPC): Delete.
2703
2704
2705         * interp.c (signal_exception, store_word, load_word,
2706         address_translation, load_memory, store_memory, cache_op,
2707         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2708         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2709         current instruction address - cia - argument.
2710         (sim_read, sim_write): Call address_translation directly.
2711         (sim_engine_run): Rename variable vaddr to cia.
2712         (signal_exception): Pass cia to sim_monitor
2713
2714         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2715         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2716         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2717
2718         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2719         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2720         SIM_ASSERT.
2721
2722         * interp.c (signal_exception): Pass restart address to
2723         sim_engine_restart.
2724
2725         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2726         idecode.o): Add dependency.
2727
2728         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2729         Delete definitions
2730         (DELAY_SLOT): Update NIA not PC with branch address.
2731         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2732
2733         * mips.igen: Use CIA not PC in branch calculations.
2734         (illegal): Call SignalException.
2735         (BEQ, ADDIU): Fix assembler.
2736
2737 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2738
2739         * m16.igen (JALX): Was missing.
2740
2741         * configure.in (enable-sim-igen): New configuration option.
2742         * configure: Re-generate.
2743
2744         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2745
2746         * interp.c (load_memory, store_memory): Delete parameter RAW.
2747         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2748         bypassing {load,store}_memory.
2749
2750         * sim-main.h (ByteSwapMem): Delete definition.
2751
2752         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2753
2754         * interp.c (sim_do_command, sim_commands): Delete mips specific
2755         commands.  Handled by module sim-options.
2756
2757         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2758         (WITH_MODULO_MEMORY): Define.
2759
2760         * interp.c (sim_info): Delete code printing memory size.
2761
2762         * interp.c (mips_size): Nee sim_size, delete function.
2763         (power2): Delete.
2764         (monitor, monitor_base, monitor_size): Delete global variables.
2765         (sim_open, sim_close): Delete code creating monitor and other
2766         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2767         manage memory regions.
2768         (load_memory, store_memory): Use sim-core for memory model.
2769
2770         * interp.c (address_translation): Delete all memory map code
2771         except line forcing 32 bit addresses.
2772
2773 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2774
2775         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2776         trace options.
2777
2778         * interp.c (logfh, logfile): Delete globals.
2779         (sim_open, sim_close): Delete code opening & closing log file.
2780         (mips_option_handler): Delete -l and -n options.
2781         (OPTION mips_options): Ditto.
2782
2783         * interp.c (OPTION mips_options): Rename option trace to dinero.
2784         (mips_option_handler): Update.
2785
2786 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2787
2788         * interp.c (fetch_str): New function.
2789         (sim_monitor): Rewrite using sim_read & sim_write.
2790         (sim_open): Check magic number.
2791         (sim_open): Write monitor vectors into memory using sim_write.
2792         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2793         (sim_read, sim_write): Simplify - transfer data one byte at a
2794         time.
2795         (load_memory, store_memory): Clarify meaning of parameter RAW.
2796
2797         * sim-main.h (isHOST): Defete definition.
2798         (isTARGET): Mark as depreciated.
2799         (address_translation): Delete parameter HOST.
2800
2801         * interp.c (address_translation): Delete parameter HOST.
2802
2803 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2804
2805         * mips.igen:
2806
2807         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2808         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2809
2810 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2811
2812         * mips.igen: Add model filter field to records.
2813
2814 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2815
2816         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2817
2818         interp.c (sim_engine_run): Do not compile function sim_engine_run
2819         when WITH_IGEN == 1.
2820
2821         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2822         target architecture.
2823
2824         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2825         igen. Replace with configuration variables sim_igen_flags /
2826         sim_m16_flags.
2827
2828         * m16.igen: New file.  Copy mips16 insns here.
2829         * mips.igen: From here.
2830
2831 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2832
2833         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2834         to top.
2835         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2836
2837 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2838
2839         * gencode.c (build_instruction): Follow sim_write's lead in using
2840         BigEndianMem instead of !ByteSwapMem.
2841
2842 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2843
2844         * configure.in (sim_gen): Dependent on target, select type of
2845         generator.  Always select old style generator.
2846
2847         configure: Re-generate.
2848
2849         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2850         targets.
2851         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2852         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2853         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2854         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2855         SIM_@sim_gen@_*, set by autoconf.
2856
2857 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2858
2859         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2860
2861         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2862         CURRENT_FLOATING_POINT instead.
2863
2864         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2865         (address_translation): Raise exception InstructionFetch when
2866         translation fails and isINSTRUCTION.
2867
2868         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2869         sim_engine_run): Change type of of vaddr and paddr to
2870         address_word.
2871         (address_translation, prefetch, load_memory, store_memory,
2872         cache_op): Change type of vAddr and pAddr to address_word.
2873
2874         * gencode.c (build_instruction): Change type of vaddr and paddr to
2875         address_word.
2876
2877 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2878
2879         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2880         macro to obtain result of ALU op.
2881
2882 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2883
2884         * interp.c (sim_info): Call profile_print.
2885
2886 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2887
2888         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2889
2890         * sim-main.h (WITH_PROFILE): Do not define, defined in
2891         common/sim-config.h.  Use sim-profile module.
2892         (simPROFILE): Delete defintion.
2893
2894         * interp.c (PROFILE): Delete definition.
2895         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2896         (sim_close): Delete code writing profile histogram.
2897         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2898         Delete.
2899         (sim_engine_run): Delete code profiling the PC.
2900
2901 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2902
2903         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2904
2905         * interp.c (sim_monitor): Make register pointers of type
2906         unsigned_word*.
2907
2908         * sim-main.h: Make registers of type unsigned_word not
2909         signed_word.
2910
2911 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2912
2913         * interp.c (sync_operation): Rename from SyncOperation, make
2914         global, add SD argument.
2915         (prefetch): Rename from Prefetch, make global, add SD argument.
2916         (decode_coproc): Make global.
2917
2918         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2919
2920         * gencode.c (build_instruction): Generate DecodeCoproc not
2921         decode_coproc calls.
2922
2923         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2924         (SizeFGR): Move to sim-main.h
2925         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2926         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2927         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2928         sim-main.h.
2929         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2930         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2931         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2932         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2933         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2934         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2935
2936         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2937         exception.
2938         (sim-alu.h): Include.
2939         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2940         (sim_cia): Typedef to instruction_address.
2941
2942 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2943
2944         * Makefile.in (interp.o): Rename generated file engine.c to
2945         oengine.c.
2946
2947         * interp.c: Update.
2948
2949 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2950
2951         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2952
2953 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2954
2955         * gencode.c (build_instruction): For "FPSQRT", output correct
2956         number of arguments to Recip.
2957
2958 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2959
2960         * Makefile.in (interp.o): Depends on sim-main.h
2961
2962         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2963
2964         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2965         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2966         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2967         STATE, DSSTATE): Define
2968         (GPR, FGRIDX, ..): Define.
2969
2970         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2971         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2972         (GPR, FGRIDX, ...): Delete macros.
2973
2974         * interp.c: Update names to match defines from sim-main.h
2975
2976 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2977
2978         * interp.c (sim_monitor): Add SD argument.
2979         (sim_warning): Delete.  Replace calls with calls to
2980         sim_io_eprintf.
2981         (sim_error): Delete. Replace calls with sim_io_error.
2982         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2983         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2984         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2985         argument.
2986         (mips_size): Rename from sim_size. Add SD argument.
2987
2988         * interp.c (simulator): Delete global variable.
2989         (callback): Delete global variable.
2990         (mips_option_handler, sim_open, sim_write, sim_read,
2991         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2992         sim_size,sim_monitor): Use sim_io_* not callback->*.
2993         (sim_open): ZALLOC simulator struct.
2994         (PROFILE): Do not define.
2995
2996 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2997
2998         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2999         support.h with corresponding code.
3000
3001         * sim-main.h (word64, uword64), support.h: Move definition to
3002         sim-main.h.
3003         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3004
3005         * support.h: Delete
3006         * Makefile.in: Update dependencies
3007         * interp.c: Do not include.
3008
3009 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3010
3011         * interp.c (address_translation, load_memory, store_memory,
3012         cache_op): Rename to from AddressTranslation et.al., make global,
3013         add SD argument
3014
3015         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3016         CacheOp): Define.
3017
3018         * interp.c (SignalException): Rename to signal_exception, make
3019         global.
3020
3021         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
3022
3023         * sim-main.h (SignalException, SignalExceptionInterrupt,
3024         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3025         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3026         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3027         Define.
3028
3029         * interp.c, support.h: Use.
3030
3031 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3032
3033         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3034         to value_fpr / store_fpr. Add SD argument.
3035         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3036         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3037
3038         * sim-main.h (ValueFPR, StoreFPR): Define.
3039
3040 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3041
3042         * interp.c (sim_engine_run): Check consistency between configure
3043         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3044         and HASFPU.
3045
3046         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
3047         (mips_fpu): Configure WITH_FLOATING_POINT.
3048         (mips_endian): Configure WITH_TARGET_ENDIAN.
3049         * configure: Update.
3050
3051 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3052
3053         * configure: Regenerated to track ../common/aclocal.m4 changes.
3054
3055 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
3056
3057         * configure: Regenerated.
3058
3059 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
3060
3061         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3062
3063 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3064
3065         * gencode.c (print_igen_insn_models): Assume certain architectures
3066         include all mips* instructions.
3067         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3068         instruction.
3069
3070         * Makefile.in (tmp.igen): Add target. Generate igen input from
3071         gencode file.
3072
3073         * gencode.c (FEATURE_IGEN): Define.
3074         (main): Add --igen option.  Generate output in igen format.
3075         (process_instructions): Format output according to igen option.
3076         (print_igen_insn_format): New function.
3077         (print_igen_insn_models): New function.
3078         (process_instructions): Only issue warnings and ignore
3079         instructions when no FEATURE_IGEN.
3080
3081 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3082
3083         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3084         MIPS targets.
3085
3086 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3087
3088         * configure: Regenerated to track ../common/aclocal.m4 changes.
3089
3090 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3091
3092         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3093         SIM_RESERVED_BITS): Delete, moved to common.
3094         (SIM_EXTRA_CFLAGS): Update.
3095
3096 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3097
3098         * configure.in: Configure non-strict memory alignment.
3099         * configure: Regenerated to track ../common/aclocal.m4 changes.
3100
3101 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3102
3103         * configure: Regenerated to track ../common/aclocal.m4 changes.
3104
3105 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
3106
3107         * gencode.c (SDBBP,DERET): Added (3900) insns.
3108         (RFE): Turn on for 3900.
3109         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3110         (dsstate): Made global.
3111         (SUBTARGET_R3900): Added.
3112         (CANCELDELAYSLOT): New.
3113         (SignalException): Ignore SystemCall rather than ignore and
3114         terminate.  Add DebugBreakPoint handling.
3115         (decode_coproc): New insns RFE, DERET; and new registers Debug
3116         and DEPC protected by SUBTARGET_R3900.
3117         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3118         bits explicitly.
3119         * Makefile.in,configure.in: Add mips subtarget option.
3120         * configure: Update.
3121
3122 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
3123
3124         * gencode.c: Add r3900 (tx39).
3125
3126
3127 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
3128
3129         * gencode.c (build_instruction): Don't need to subtract 4 for
3130         JALR, just 2.
3131
3132 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
3133
3134         * interp.c: Correct some HASFPU problems.
3135
3136 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3137
3138         * configure: Regenerated to track ../common/aclocal.m4 changes.
3139
3140 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3141
3142         * interp.c (mips_options): Fix samples option short form, should
3143         be `x'.
3144
3145 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3146
3147         * interp.c (sim_info): Enable info code.  Was just returning.
3148
3149 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3150
3151         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3152         MFC0.
3153
3154 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3155
3156         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3157         constants.
3158         (build_instruction): Ditto for LL.
3159
3160 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
3161
3162         * configure: Regenerated to track ../common/aclocal.m4 changes.
3163
3164 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3165
3166         * configure: Regenerated to track ../common/aclocal.m4 changes.
3167         * config.in: Ditto.
3168
3169 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3170
3171         * interp.c (sim_open): Add call to sim_analyze_program, update
3172         call to sim_config.
3173
3174 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3175
3176         * interp.c (sim_kill): Delete.
3177         (sim_create_inferior): Add ABFD argument. Set PC from same.
3178         (sim_load): Move code initializing trap handlers from here.
3179         (sim_open): To here.
3180         (sim_load): Delete, use sim-hload.c.
3181
3182         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3183
3184 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3185
3186         * configure: Regenerated to track ../common/aclocal.m4 changes.
3187         * config.in: Ditto.
3188
3189 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3190
3191         * interp.c (sim_open): Add ABFD argument.
3192         (sim_load): Move call to sim_config from here.
3193         (sim_open): To here.  Check return status.
3194
3195 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
3196
3197         * gencode.c (build_instruction): Two arg MADD should
3198         not assign result to $0.
3199
3200 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
3201
3202         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3203         * sim/mips/configure.in: Regenerate.
3204
3205 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
3206
3207         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3208         signed8, unsigned8 et.al. types.
3209
3210         * interp.c (SUB_REG_FETCH): Handle both little and big endian
3211         hosts when selecting subreg.
3212
3213 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
3214
3215         * interp.c (sim_engine_run): Reset the ZERO register to zero
3216         regardless of FEATURE_WARN_ZERO.
3217         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3218
3219 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3220
3221         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3222         (SignalException): For BreakPoints ignore any mode bits and just
3223         save the PC.
3224         (SignalException): Always set the CAUSE register.
3225
3226 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3227
3228         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3229         exception has been taken.
3230
3231         * interp.c: Implement the ERET and mt/f sr instructions.
3232
3233 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3234
3235         * interp.c (SignalException): Don't bother restarting an
3236         interrupt.
3237
3238 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3239
3240         * interp.c (SignalException): Really take an interrupt.
3241         (interrupt_event): Only deliver interrupts when enabled.
3242
3243 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3244
3245         * interp.c (sim_info): Only print info when verbose.
3246         (sim_info) Use sim_io_printf for output.
3247
3248 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3249
3250         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3251         mips architectures.
3252
3253 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3254
3255         * interp.c (sim_do_command): Check for common commands if a
3256         simulator specific command fails.
3257
3258 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
3259
3260         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3261         and simBE when DEBUG is defined.
3262
3263 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3264
3265         * interp.c (interrupt_event): New function.  Pass exception event
3266         onto exception handler.
3267
3268         * configure.in: Check for stdlib.h.
3269         * configure: Regenerate.
3270
3271         * gencode.c (build_instruction): Add UNUSED attribute to tempS
3272         variable declaration.
3273         (build_instruction): Initialize memval1.
3274         (build_instruction): Add UNUSED attribute to byte, bigend,
3275         reverse.
3276         (build_operands): Ditto.
3277
3278         * interp.c: Fix GCC warnings.
3279         (sim_get_quit_code): Delete.
3280
3281         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3282         * Makefile.in: Ditto.
3283         * configure: Re-generate.
3284
3285         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3286
3287 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3288
3289         * interp.c (mips_option_handler): New function parse argumes using
3290         sim-options.
3291         (myname): Replace with STATE_MY_NAME.
3292         (sim_open): Delete check for host endianness - performed by
3293         sim_config.
3294         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3295         (sim_open): Move much of the initialization from here.
3296         (sim_load): To here.  After the image has been loaded and
3297         endianness set.
3298         (sim_open): Move ColdReset from here.
3299         (sim_create_inferior): To here.
3300         (sim_open): Make FP check less dependant on host endianness.
3301
3302         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3303         run.
3304         * interp.c (sim_set_callbacks): Delete.
3305
3306         * interp.c (membank, membank_base, membank_size): Replace with
3307         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3308         (sim_open): Remove call to callback->init. gdb/run do this.
3309
3310         * interp.c: Update
3311
3312         * sim-main.h (SIM_HAVE_FLATMEM): Define.
3313
3314         * interp.c (big_endian_p): Delete, replaced by
3315         current_target_byte_order.
3316
3317 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3318
3319         * interp.c (host_read_long, host_read_word, host_swap_word,
3320         host_swap_long): Delete. Using common sim-endian.
3321         (sim_fetch_register, sim_store_register): Use H2T.
3322         (pipeline_ticks): Delete.  Handled by sim-events.
3323         (sim_info): Update.
3324         (sim_engine_run): Update.
3325
3326 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3327
3328         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3329         reason from here.
3330         (SignalException): To here. Signal using sim_engine_halt.
3331         (sim_stop_reason): Delete, moved to common.
3332
3333 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
3334
3335         * interp.c (sim_open): Add callback argument.
3336         (sim_set_callbacks): Delete SIM_DESC argument.
3337         (sim_size): Ditto.
3338
3339 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3340
3341         * Makefile.in (SIM_OBJS): Add common modules.
3342
3343         * interp.c (sim_set_callbacks): Also set SD callback.
3344         (set_endianness, xfer_*, swap_*): Delete.
3345         (host_read_word, host_read_long, host_swap_word, host_swap_long):
3346         Change to functions using sim-endian macros.
3347         (control_c, sim_stop): Delete, use common version.
3348         (simulate): Convert into.
3349         (sim_engine_run): This function.
3350         (sim_resume): Delete.
3351
3352         * interp.c (simulation): New variable - the simulator object.
3353         (sim_kind): Delete global - merged into simulation.
3354         (sim_load): Cleanup.  Move PC assignment from here.
3355         (sim_create_inferior): To here.
3356
3357         * sim-main.h: New file.
3358         * interp.c (sim-main.h): Include.
3359
3360 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
3361
3362         * configure: Regenerated to track ../common/aclocal.m4 changes.
3363
3364 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
3365
3366         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3367
3368 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
3369
3370         * gencode.c (build_instruction): DIV instructions: check
3371         for division by zero and integer overflow before using
3372         host's division operation.
3373
3374 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
3375
3376         * Makefile.in (SIM_OBJS): Add sim-load.o.
3377         * interp.c: #include bfd.h.
3378         (target_byte_order): Delete.
3379         (sim_kind, myname, big_endian_p): New static locals.
3380         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
3381         after argument parsing.  Recognize -E arg, set endianness accordingly.
3382         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
3383         load file into simulator.  Set PC from bfd.
3384         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
3385         (set_endianness): Use big_endian_p instead of target_byte_order.
3386
3387 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3388
3389         * interp.c (sim_size): Delete prototype - conflicts with
3390         definition in remote-sim.h.  Correct definition.
3391
3392 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3393
3394         * configure: Regenerated to track ../common/aclocal.m4 changes.
3395         * config.in: Ditto.
3396
3397 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
3398
3399         * interp.c (sim_open): New arg `kind'.
3400
3401         * configure: Regenerated to track ../common/aclocal.m4 changes.
3402
3403 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3404
3405         * configure: Regenerated to track ../common/aclocal.m4 changes.
3406
3407 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
3408
3409         * interp.c (sim_open): Set optind to 0 before calling getopt.
3410
3411 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3412
3413         * configure: Regenerated to track ../common/aclocal.m4 changes.
3414
3415 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
3416
3417         * interp.c : Replace uses of pr_addr with pr_uword64
3418         where the bit length is always 64 independent of SIM_ADDR.
3419         (pr_uword64) : added.
3420
3421 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3422
3423         * configure: Re-generate.
3424
3425 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
3426
3427         * configure: Regenerate to track ../common/aclocal.m4 changes.
3428
3429 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
3430
3431         * interp.c (sim_open): New SIM_DESC result.  Argument is now
3432         in argv form.
3433         (other sim_*): New SIM_DESC argument.
3434
3435 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
3436
3437         * interp.c: Fix printing of addresses for non-64-bit targets.
3438         (pr_addr): Add function to print address based on size.
3439
3440 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
3441
3442         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3443
3444 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
3445
3446         * gencode.c (build_mips16_operands): Correct computation of base
3447         address for extended PC relative instruction.
3448
3449 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
3450
3451         * interp.c (mips16_entry): Add support for floating point cases.
3452         (SignalException): Pass floating point cases to mips16_entry.
3453         (ValueFPR): Don't restrict fmt_single and fmt_word to even
3454         registers.
3455         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
3456         or fmt_word.
3457         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3458         and then set the state to fmt_uninterpreted.
3459         (COP_SW): Temporarily set the state to fmt_word while calling
3460         ValueFPR.
3461
3462 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
3463
3464         * gencode.c (build_instruction): The high order may be set in the
3465         comparison flags at any ISA level, not just ISA 4.
3466
3467 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
3468
3469         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3470         COMMON_{PRE,POST}_CONFIG_FRAG instead.
3471         * configure.in: sinclude ../common/aclocal.m4.
3472         * configure: Regenerated.
3473
3474 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
3475
3476         * configure: Rebuild after change to aclocal.m4.
3477
3478 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
3479
3480         * configure configure.in Makefile.in:  Update to new configure
3481         scheme which is more compatible with WinGDB builds.
3482         * configure.in:  Improve comment on how to run autoconf.
3483         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
3484         * Makefile.in:  Use autoconf substitution to install common
3485         makefile fragment.
3486
3487 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
3488
3489         * gencode.c (build_instruction): Use BigEndianCPU instead of
3490         ByteSwapMem.
3491
3492 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
3493
3494         * interp.c (sim_monitor): Make output to stdout visible in
3495         wingdb's I/O log window.
3496
3497 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
3498
3499         * support.h: Undo previous change to SIGTRAP
3500         and SIGQUIT values.
3501
3502 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
3503
3504         * interp.c (store_word, load_word): New static functions.
3505         (mips16_entry): New static function.
3506         (SignalException): Look for mips16 entry and exit instructions.
3507         (simulate): Use the correct index when setting fpr_state after
3508         doing a pending move.
3509
3510 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
3511
3512         * interp.c: Fix byte-swapping code throughout to work on
3513         both little- and big-endian hosts.
3514
3515 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
3516
3517         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3518         with gdb/config/i386/xm-windows.h.
3519
3520 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
3521
3522         * gencode.c (build_instruction): Work around MSVC++ code gen bug
3523         that messes up arithmetic shifts.
3524
3525 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
3526
3527         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
3528         SIGTRAP and SIGQUIT for _WIN32.
3529
3530 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
3531
3532         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3533         force a 64 bit multiplication.
3534         (build_instruction) [OR]: In mips16 mode, don't do anything if the
3535         destination register is 0, since that is the default mips16 nop
3536         instruction.
3537
3538 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
3539
3540         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3541         (build_endian_shift): Don't check proc64.
3542         (build_instruction): Always set memval to uword64.  Cast op2 to
3543         uword64 when shifting it left in memory instructions.  Always use
3544         the same code for stores--don't special case proc64.
3545
3546         * gencode.c (build_mips16_operands): Fix base PC value for PC
3547         relative operands.
3548         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3549         jal instruction.
3550         * interp.c (simJALDELAYSLOT): Define.
3551         (JALDELAYSLOT): Define.
3552         (INDELAYSLOT, INJALDELAYSLOT): Define.
3553         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3554
3555 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
3556
3557         * interp.c (sim_open): add flush_cache as a PMON routine
3558         (sim_monitor): handle flush_cache by ignoring it
3559
3560 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
3561
3562         * gencode.c (build_instruction): Use !ByteSwapMem instead of
3563         BigEndianMem.
3564         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3565         (BigEndianMem): Rename to ByteSwapMem and change sense.
3566         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3567         BigEndianMem references to !ByteSwapMem.
3568         (set_endianness): New function, with prototype.
3569         (sim_open): Call set_endianness.
3570         (sim_info): Use simBE instead of BigEndianMem.
3571         (xfer_direct_word, xfer_direct_long, swap_direct_word,
3572         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3573         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3574         ifdefs, keeping the prototype declaration.
3575         (swap_word): Rewrite correctly.
3576         (ColdReset): Delete references to CONFIG.  Delete endianness related
3577         code; moved to set_endianness.
3578
3579 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
3580
3581         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3582         * interp.c (CHECKHILO): Define away.
3583         (simSIGINT): New macro.
3584         (membank_size): Increase from 1MB to 2MB.
3585         (control_c): New function.
3586         (sim_resume): Rename parameter signal to signal_number.  Add local
3587         variable prev.  Call signal before and after simulate.
3588         (sim_stop_reason): Add simSIGINT support.
3589         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3590         functions always.
3591         (sim_warning): Delete call to SignalException.  Do call printf_filtered
3592         if logfh is NULL.
3593         (AddressTranslation): Add #ifdef DEBUG around debugging message and
3594         a call to sim_warning.
3595
3596 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
3597
3598         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3599         16 bit instructions.
3600
3601 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3602
3603         Add support for mips16 (16 bit MIPS implementation):
3604         * gencode.c (inst_type): Add mips16 instruction encoding types.
3605         (GETDATASIZEINSN): Define.
3606         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
3607         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
3608         mtlo.
3609         (MIPS16_DECODE): New table, for mips16 instructions.
3610         (bitmap_val): New static function.
3611         (struct mips16_op): Define.
3612         (mips16_op_table): New table, for mips16 operands.
3613         (build_mips16_operands): New static function.
3614         (process_instructions): If PC is odd, decode a mips16
3615         instruction.  Break out instruction handling into new
3616         build_instruction function.
3617         (build_instruction): New static function, broken out of
3618         process_instructions.  Check modifiers rather than flags for SHIFT
3619         bit count and m[ft]{hi,lo} direction.
3620         (usage): Pass program name to fprintf.
3621         (main): Remove unused variable this_option_optind.  Change
3622         ``*loptarg++'' to ``loptarg++''.
3623         (my_strtoul): Parenthesize && within ||.
3624         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3625         (simulate): If PC is odd, fetch a 16 bit instruction, and
3626         increment PC by 2 rather than 4.
3627         * configure.in: Add case for mips16*-*-*.
3628         * configure: Rebuild.
3629
3630 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
3631
3632         * interp.c: Allow -t to enable tracing in standalone simulator.
3633         Fix garbage output in trace file and error messages.
3634
3635 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
3636
3637         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3638         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3639         * configure.in: Simplify using macros in ../common/aclocal.m4.
3640         * configure: Regenerated.
3641         * tconfig.in: New file.
3642
3643 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3644
3645         * interp.c: Fix bugs in 64-bit port.
3646         Use ansi function declarations for msvc compiler.
3647         Initialize and test file pointer in trace code.
3648         Prevent duplicate definition of LAST_EMED_REGNUM.
3649
3650 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3651
3652         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3653
3654 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3655
3656         * interp.c (SignalException): Check for explicit terminating
3657         breakpoint value.
3658         * gencode.c: Pass instruction value through SignalException()
3659         calls for Trap, Breakpoint and Syscall.
3660
3661 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3662
3663         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3664         only used on those hosts that provide it.
3665         * configure.in: Add sqrt() to list of functions to be checked for.
3666         * config.in: Re-generated.
3667         * configure: Re-generated.
3668
3669 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3670
3671         * gencode.c (process_instructions): Call build_endian_shift when
3672         expanding STORE RIGHT, to fix swr.
3673         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3674         clear the high bits.
3675         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3676         Fix float to int conversions to produce signed values.
3677
3678 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3679
3680         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3681         (process_instructions): Correct handling of nor instruction.
3682         Correct shift count for 32 bit shift instructions. Correct sign
3683         extension for arithmetic shifts to not shift the number of bits in
3684         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3685         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3686         Fix madd.
3687         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3688         It's OK to have a mult follow a mult.  What's not OK is to have a
3689         mult follow an mfhi.
3690         (Convert): Comment out incorrect rounding code.
3691
3692 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3693
3694         * interp.c (sim_monitor): Improved monitor printf
3695         simulation. Tidied up simulator warnings, and added "--log" option
3696         for directing warning message output.
3697         * gencode.c: Use sim_warning() rather than WARNING macro.
3698
3699 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3700
3701         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3702         getopt1.o, rather than on gencode.c.  Link objects together.
3703         Don't link against -liberty.
3704         (gencode.o, getopt.o, getopt1.o): New targets.
3705         * gencode.c: Include <ctype.h> and "ansidecl.h".
3706         (AND): Undefine after including "ansidecl.h".
3707         (ULONG_MAX): Define if not defined.
3708         (OP_*): Don't define macros; now defined in opcode/mips.h.
3709         (main): Call my_strtoul rather than strtoul.
3710         (my_strtoul): New static function.
3711
3712 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3713
3714         * gencode.c (process_instructions):  Generate word64 and uword64
3715         instead of `long long' and `unsigned long long' data types.
3716         * interp.c:  #include sysdep.h to get signals, and define default
3717         for SIGBUS.
3718         * (Convert):  Work around for Visual-C++ compiler bug with type
3719         conversion.
3720         * support.h:  Make things compile under Visual-C++ by using
3721         __int64 instead of `long long'.  Change many refs to long long
3722         into word64/uword64 typedefs.
3723
3724 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3725
3726         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3727         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3728         (docdir): Removed.
3729         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3730         (AC_PROG_INSTALL): Added.
3731         (AC_PROG_CC): Moved to before configure.host call.
3732         * configure: Rebuilt.
3733
3734 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3735
3736         * configure.in: Define @SIMCONF@ depending on mips target.
3737         * configure: Rebuild.
3738         * Makefile.in (run): Add @SIMCONF@ to control simulator
3739         construction.
3740         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3741         * interp.c: Remove some debugging, provide more detailed error
3742         messages, update memory accesses to use LOADDRMASK.
3743
3744 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3745
3746         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3747         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3748         stamp-h.
3749         * configure: Rebuild.
3750         * config.in: New file, generated by autoheader.
3751         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3752         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3753         HAVE_ANINT and HAVE_AINT, as appropriate.
3754         * Makefile.in (run): Use @LIBS@ rather than -lm.
3755         (interp.o): Depend upon config.h.
3756         (Makefile): Just rebuild Makefile.
3757         (clean): Remove stamp-h.
3758         (mostlyclean): Make the same as clean, not as distclean.
3759         (config.h, stamp-h): New targets.
3760
3761 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3762
3763         * interp.c (ColdReset): Fix boolean test. Make all simulator
3764         globals static.
3765
3766 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3767
3768         * interp.c (xfer_direct_word, xfer_direct_long,
3769         swap_direct_word, swap_direct_long, xfer_big_word,
3770         xfer_big_long, xfer_little_word, xfer_little_long,
3771         swap_word,swap_long): Added.
3772         * interp.c (ColdReset): Provide function indirection to
3773         host<->simulated_target transfer routines.
3774         * interp.c (sim_store_register, sim_fetch_register): Updated to
3775         make use of indirected transfer routines.
3776
3777 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3778
3779         * gencode.c (process_instructions): Ensure FP ABS instruction
3780         recognised.
3781         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3782         system call support.
3783
3784 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3785
3786         * interp.c (sim_do_command): Complain if callback structure not
3787         initialised.
3788
3789 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3790
3791         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3792         support for Sun hosts.
3793         * Makefile.in (gencode): Ensure the host compiler and libraries
3794         used for cross-hosted build.
3795
3796 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3797
3798         * interp.c, gencode.c: Some more (TODO) tidying.
3799
3800 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3801
3802         * gencode.c, interp.c: Replaced explicit long long references with
3803         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3804         * support.h (SET64LO, SET64HI): Macros added.
3805
3806 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3807
3808         * configure: Regenerate with autoconf 2.7.
3809
3810 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3811
3812         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3813         * support.h: Remove superfluous "1" from #if.
3814         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3815
3816 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3817
3818         * interp.c (StoreFPR): Control UndefinedResult() call on
3819         WARN_RESULT manifest.
3820
3821 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3822
3823         * gencode.c: Tidied instruction decoding, and added FP instruction
3824         support.
3825
3826         * interp.c: Added dineroIII, and BSD profiling support. Also
3827         run-time FP handling.
3828
3829 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3830
3831         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3832         gencode.c, interp.c, support.h: created.