sim/mips/ChangeLog

   1 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * configure: Regenerate.
   4
   5 2020-12-31  Pavel I. Kryukov  <kryukov@frtk.ru>  (tiny change)
   6
   7         *  sim-main.c: Include <stdlib.h>.
   8
   9 2020-12-14  Pavel I. Kryukov  <kryukov@frtk.ru>  (tiny change)
  10
  11         * cp1.c: Include <stdlib.h>.
  12
  13 2020-07-29  Simon Marchi  <simon.marchi@efficios.com>
  14
  15         * configure: Re-generate.
  16
  17 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  18
  19         * configure: Regenerate.
  20
  21 2016-11-11  Mike Frysinger  <vapier@gentoo.org>
  22
  23         PR sim/20808
  24         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
  25         and SD to sd.
  26
  27 2016-11-11  Mike Frysinger  <vapier@gentoo.org>
  28
  29         PR sim/20809
  30         * mips.igen (check_u64): Enable for `r3900'.
  31
  32 2016-02-05  Mike Frysinger  <vapier@gentoo.org>
  33
  34         * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
  35         STATE_PROG_BFD (sd).
  36         * configure: Regenerate.
  37
  38 2016-01-18  Andrew Bennett  <andrew.bennett@imgtec.com>
  39             Maciej W. Rozycki  <macro@imgtec.com>
  40
  41         PR sim/19441
  42         * micromips.igen (delayslot_micromips): Enable for `micromips32',
  43         `micromips64' and `micromipsdsp' only.
  44         (process_isa_mode): Enable for `micromips32' and `micromips64' only.
  45         (do_micromips_jalr, do_micromips_jal): Likewise.
  46         (compute_movep_src_reg): Likewise.
  47         (compute_andi16_imm): Likewise.
  48         (convert_fmt_micromips): Likewise.
  49         (convert_fmt_micromips_cvt_d): Likewise.
  50         (convert_fmt_micromips_cvt_s): Likewise.
  51         (FMT_MICROMIPS): Likewise.
  52         (FMT_MICROMIPS_CVT_D): Likewise.
  53         (FMT_MICROMIPS_CVT_S): Likewise.
  54
  55 2016-01-12  Mike Frysinger  <vapier@gentoo.org>
  56
  57         * interp.c: Include elf-bfd.h.
  58         (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
  59         ELFCLASS32.
  60
  61 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  62
  63         * config.in, configure: Regenerate.
  64
  65 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  66
  67         * configure: Regenerate.
  68
  69 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  70
  71         * configure: Regenerate.
  72
  73 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  74
  75         * configure: Regenerate.
  76
  77 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  78
  79         * configure: Regenerate.
  80
  81 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  82
  83         * configure.ac (SIM_AC_OPTION_SMP): Delete call.
  84         * configure: Regenerate.
  85
  86 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  87
  88         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
  89         * configure: Regenerate.
  90
  91 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  92
  93         * configure: Regenerate.
  94
  95 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
  96
  97         * configure: Regenerate.
  98
  99 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 100
 101         * config.in, configure: Regenerate.
 102
 103 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 104
 105         * interp.c (sim_open): Mark argv const.
 106         (sim_create_inferior): Mark argv and env const.
 107
 108 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * configure: Regenerate.
 111
 112 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 113
 114         * interp.c (sim_open): Update sim_parse_args comment.
 115
 116 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 117
 118         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 119         * configure: Regenerate.
 120
 121 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 122
 123         * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
 124         (default_endian): Likewise.  Change BIG_ENDIAN to BIG.
 125         * configure: Regenerate.
 126         * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
 127
 128 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 129
 130         * dv-tx3904cpu.c (CPU, SD): Delete.
 131
 132 2015-12-30  Mike Frysinger  <vapier@gentoo.org>
 133
 134         * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
 135         (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
 136         (sim_store_register): Rename to ...
 137         (mips_reg_store): ... this.  Delete local cpu var.
 138         Update sim_io_eprintf calls.
 139         (sim_fetch_register): Rename to ...
 140         (mips_reg_fetch): ... this.  Delete local cpu var.
 141         Update sim_io_eprintf calls.
 142
 143 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 144
 145         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 146
 147 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 148
 149         * config.in, configure: Regenerate.
 150
 151 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 152
 153         * interp.c (sim_write, sim_read): Delete.
 154         (store_word): Delete call to AddressTranslation and set paddr=vaddr.
 155         (load_word): Likewise.
 156         * micromips.igen (cache): Likewise.
 157         * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
 158         do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
 159         do_store_left, do_store_right, do_load_double, do_store_double):
 160         Likewise.
 161         (do_pref): Delete call to AddressTranslation and stub out Prefetch.
 162         (do_prefx): Likewise.
 163         * sim-main.c (address_translation, prefetch): Delete.
 164         (ifetch32, ifetch16): Delete call to AddressTranslation and set
 165         paddr=vaddr.
 166         * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
 167         address_translation, AddressTranslation, prefetch, Prefetch): Delete.
 168         (LoadMemory, StoreMemory): Delete CCA arg.
 169
 170 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 171
 172         * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
 173         * configure: Regenerated.
 174
 175 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 176
 177         * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
 178         * tconfig.h: Delete.
 179
 180 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 181
 182         * tconfig.h (SIM_HANDLES_LMA): Delete.
 183
 184 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 185
 186         * sim-main.h (WITH_WATCHPOINTS): Delete.
 187
 188 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 189
 190         * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
 191
 192 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 193
 194         * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
 195
 196 2015-12-15  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 197
 198         * micromips.igen (process_isa_mode): Fix left shift of negative
 199         value.
 200
 201 2015-11-17  Mike Frysinger  <vapier@gentoo.org>
 202
 203         * sim-main.h (WITH_MODULO_MEMORY): Delete.
 204
 205 2015-11-15  Mike Frysinger  <vapier@gentoo.org>
 206
 207         * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
 208
 209 2015-11-14  Mike Frysinger  <vapier@gentoo.org>
 210
 211         * interp.c (sim_close): Rename to ...
 212         (mips_sim_close): ... this.  Delete calls to sim_module_uninstall and
 213         sim_io_shutdown.
 214         * sim-main.h (mips_sim_close): Declare.
 215         (SIM_CLOSE_HOOK): Define.
 216
 217 2015-09-25  Andrew Bennett  <andrew.bennett@imgtec.com>
 218             Ali Lown  <ali.lown@imgtec.com>
 219
 220         * Makefile.in (tmp-micromips): New rule.
 221         (tmp-mach-multi): Add support for micromips.
 222         * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
 223         that works for both mips64 and micromips64.
 224         (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
 225         micromips32.
 226         Add build support for micromips.
 227         * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
 228         do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
 229         do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
 230         do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
 231         do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
 232         do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
 233         do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
 234         do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
 235         Refactored instruction code to use these functions.
 236         * dsp2.igen: Refactored instruction code to use the new functions.
 237         * interp.c (decode_coproc): Refactored to work with any instruction
 238         encoding.
 239         (isa_mode): New variable
 240         (RSVD_INSTRUCTION): Changed to 0x00000039.
 241         * m16.igen (BREAK16): Refactored instruction to use do_break16.
 242         (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
 243         * micromips.dc: New file.
 244         * micromips.igen: New file.
 245         * micromips16.dc: New file.
 246         * micromipsdsp.igen: New file.
 247         * micromipsrun.c: New file.
 248         * mips.igen (do_swc1): Changed to work with any instruction encoding.
 249         (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
 250         do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
 251         do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
 252         do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
 253         do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
 254         do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
 255         do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
 256         do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
 257         do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
 258         do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
 259         do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
 260         do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
 261         do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
 262         do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
 263         do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
 264         do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
 265         do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
 266         do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
 267         instructions.
 268         Refactored instruction code to use these functions.
 269         (RSVD): Changed to use new reserved instruction.
 270         (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
 271         check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
 272         do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
 273         do_store_double):  Added micromips32 and micromips64 models.
 274         Added include for micromips.igen and micromipsdsp.igen
 275         Add micromips32 and micromips64 models.
 276         (DecodeCoproc): Updated to use new macro definition.
 277         * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
 278         do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
 279         do_seb, do_seh do_rdhwr, do_wsbh): New functions.
 280         Refactored instruction code to use these functions.
 281         * sim-main.h (CP0_operation): New enum.
 282         (DecodeCoproc): Updated macro.
 283         (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
 284         MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
 285         MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
 286         ISA_MODE_MICROMIPS): New defines.
 287         (sim_state): Add isa_mode field.
 288
 289 2015-06-23  Mike Frysinger  <vapier@gentoo.org>
 290
 291         * configure: Regenerate.
 292
 293 2015-06-12  Mike Frysinger  <vapier@gentoo.org>
 294
 295         * configure.ac: Change configure.in to configure.ac.
 296         * configure: Regenerate.
 297
 298 2015-06-12  Mike Frysinger  <vapier@gentoo.org>
 299
 300         * configure: Regenerate.
 301
 302 2015-06-12  Mike Frysinger  <vapier@gentoo.org>
 303
 304         * interp.c [TRACE]: Delete.
 305         (TRACE): Change to WITH_TRACE_ANY_P.
 306         [!WITH_TRACE_ANY_P] (open_trace): Define.
 307         (mips_option_handler, open_trace, sim_close, dotrace):
 308         Change defined(TRACE) to WITH_TRACE_ANY_P.
 309         (sim_open): Delete TRACE ifdef check.
 310         * sim-main.c (load_memory): Delete TRACE ifdef check.
 311         (store_memory): Likewise.
 312         * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
 313         [!WITH_TRACE_ANY_P] (dotrace): Define.
 314
 315 2015-04-18  Mike Frysinger  <vapier@gentoo.org>
 316
 317         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
 318         comments.
 319
 320 2015-04-18  Mike Frysinger  <vapier@gentoo.org>
 321
 322         * sim-main.h (SIM_CPU): Delete.
 323
 324 2015-04-18  Mike Frysinger  <vapier@gentoo.org>
 325
 326         * sim-main.h (sim_cia): Delete.
 327
 328 2015-04-17  Mike Frysinger  <vapier@gentoo.org>
 329
 330         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
 331         PU_PC_GET.
 332         * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
 333         (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
 334         * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
 335         CIA_SET to CPU_PC_SET.
 336         * sim-main.h (CIA_GET, CIA_SET): Delete.
 337
 338 2015-04-15  Mike Frysinger  <vapier@gentoo.org>
 339
 340         * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
 341         * sim-main.h (STATE_CPU): Delete.
 342
 343 2015-04-13  Mike Frysinger  <vapier@gentoo.org>
 344
 345         * configure: Regenerate.
 346
 347 2015-04-13  Mike Frysinger  <vapier@gentoo.org>
 348
 349         * Makefile.in (SIM_OBJS): Add sim-cpu.o.
 350         * interp.c (mips_pc_get, mips_pc_set): New functions.
 351         (sim_open): Declare new local var i.  Call sim_cpu_alloc_all.
 352         Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
 353         (sim_pc_get): Delete.
 354         * sim-main.h (SIM_CPU): Define.
 355         (struct sim_state): Change cpu to an array of pointers.
 356         (STATE_CPU): Drop &.
 357
 358 2015-04-13  Mike Frysinger  <vapier@gentoo.org>
 359
 360         * interp.c (mips_option_handler, open_trace, sim_close,
 361         sim_write, sim_read, sim_store_register, sim_fetch_register,
 362         sim_create_inferior, pr_addr, pr_uword64): Convert old style
 363         prototypes.
 364         (sim_open): Convert old style prototype.  Change casts with
 365         sim_write to unsigned char *.
 366         (fetch_str): Change null to unsigned char, and change cast to
 367         unsigned char *.
 368         (sim_monitor): Change c & ch to unsigned char.  Change cast to
 369         unsigned char *.
 370
 371 2015-04-12  Mike Frysinger  <vapier@gentoo.org>
 372
 373         * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
 374
 375 2015-04-06  Mike Frysinger  <vapier@gentoo.org>
 376
 377         * Makefile.in (SIM_OBJS): Delete sim-engine.o.
 378
 379 2015-04-01  Mike Frysinger  <vapier@gentoo.org>
 380
 381         * tconfig.h (SIM_HAVE_PROFILE): Delete.
 382
 383 2015-03-31  Mike Frysinger  <vapier@gentoo.org>
 384
 385         * config.in, configure: Regenerate.
 386
 387 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
 388
 389         * interp.c (sim_pc_get): New function.
 390
 391 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
 392
 393         * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
 394         * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
 395
 396 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
 397
 398         * configure: Regenerate.
 399
 400 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
 401
 402         * configure: Regenerate.
 403
 404 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
 405
 406         * configure: Regenerate.
 407         * configure.ac (mips_extra_objs): Delete.
 408         * Makefile.in (MIPS_EXTRA_OBJS): Delete.
 409         (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
 410
 411 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
 412
 413         * configure: Regenerate.
 414         * configure.ac: Delete sim_hw checks for dv-sockser.
 415
 416 2015-03-16  Mike Frysinger  <vapier@gentoo.org>
 417
 418         * config.in, configure: Regenerate.
 419         * tconfig.in: Rename file ...
 420         * tconfig.h: ... here.
 421
 422 2015-03-15  Mike Frysinger  <vapier@gentoo.org>
 423
 424         * tconfig.in: Delete includes.
 425         [HAVE_DV_SOCKSER]: Delete.
 426
 427 2015-03-14  Mike Frysinger  <vapier@gentoo.org>
 428
 429         * Makefile.in (SIM_RUN_OBJS): Delete.
 430
 431 2015-03-14  Mike Frysinger  <vapier@gentoo.org>
 432
 433         * configure.ac (AC_CHECK_HEADERS): Delete.
 434         * aclocal.m4, configure: Regenerate.
 435
 436 2014-08-19  Alan Modra  <amodra@gmail.com>
 437
 438         * configure: Regenerate.
 439
 440 2014-08-15  Roland McGrath  <mcgrathr@google.com>
 441
 442         * configure: Regenerate.
 443         * config.in: Regenerate.
 444
 445 2014-03-04  Mike Frysinger  <vapier@gentoo.org>
 446
 447         * configure: Regenerate.
 448
 449 2013-09-23  Alan Modra  <amodra@gmail.com>
 450
 451         * configure: Regenerate.
 452
 453 2013-06-03  Mike Frysinger  <vapier@gentoo.org>
 454
 455         * aclocal.m4, configure: Regenerate.
 456
 457 2013-05-10  Freddie Chopin  <freddie_chopin@op.pl>
 458
 459         * configure: Rebuild.
 460
 461 2013-03-26  Mike Frysinger  <vapier@gentoo.org>
 462
 463         * configure: Regenerate.
 464
 465 2013-03-23  Joel Sherrill  <joel.sherrill@oarcorp.com>
 466
 467         * configure.ac: Address use of dv-sockser.o.
 468         * tconfig.in: Conditionalize use of dv_sockser_install.
 469         * configure: Regenerated.
 470         * config.in: Regenerated.
 471
 472 2012-10-04  Chao-ying Fu  <fu@mips.com>
 473             Steve Ellcey  <sellcey@mips.com>
 474
 475         * mips/mips3264r2.igen (rdhwr): New.
 476
 477 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
 478
 479         * configure.ac: Always link against dv-sockser.o.
 480         * configure: Regenerate.
 481
 482 2012-06-15  Joel Brobecker  <brobecker@adacore.com>
 483
 484         * config.in, configure: Regenerate.
 485
 486 2012-05-18  Nick Clifton  <nickc@redhat.com>
 487
 488         PR 14072
 489         * interp.c: Include config.h before system header files.
 490
 491 2012-03-24  Mike Frysinger  <vapier@gentoo.org>
 492
 493         * aclocal.m4, config.in, configure: Regenerate.
 494
 495 2011-12-03  Mike Frysinger  <vapier@gentoo.org>
 496
 497         * aclocal.m4: New file.
 498         * configure: Regenerate.
 499
 500 2011-10-19  Mike Frysinger  <vapier@gentoo.org>
 501
 502         * configure: Regenerate after common/acinclude.m4 update.
 503
 504 2011-10-17  Mike Frysinger  <vapier@gentoo.org>
 505
 506         * configure.ac: Change include to common/acinclude.m4.
 507
 508 2011-10-17  Mike Frysinger  <vapier@gentoo.org>
 509
 510         * configure.ac: Change AC_PREREQ to 2.64.  Delete AC_CONFIG_HEADER
 511         call.  Replace common.m4 include with SIM_AC_COMMON.
 512         * configure: Regenerate.
 513
 514 2011-07-08  Hans-Peter Nilsson  <hp@axis.com>
 515
 516         * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
 517         $(SIM_EXTRA_DEPS).
 518         (tmp-mach-multi): Exit early when igen fails.
 519
 520 2011-07-05  Mike Frysinger  <vapier@gentoo.org>
 521
 522         * interp.c (sim_do_command): Delete.
 523
 524 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 525
 526         * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
 527         (tx3904sio_fifo_reset): Likewise.
 528         * interp.c (sim_monitor): Likewise.
 529
 530 2010-04-14  Mike Frysinger  <vapier@gentoo.org>
 531
 532         * interp.c (sim_write): Add const to buffer arg.
 533
 534 2010-01-18  Masaki Muranaka  <monaka@monami-software.com>  (tiny change)
 535
 536         * interp.c: Don't include sysdep.h
 537
 538 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 539
 540         * configure: Regenerate.
 541
 542 2009-08-22  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 543
 544         * config.in: Regenerate.
 545         * configure: Likewise.
 546
 547         * configure: Regenerate.
 548
 549 2008-07-11  Hans-Peter Nilsson  <hp@axis.com>
 550
 551         * configure: Regenerate to track ../common/common.m4 changes.
 552         * config.in: Ditto.
 553
 554 2008-06-06  Vladimir Prus  <vladimir@codesourcery.com>
 555             Daniel Jacobowitz  <dan@codesourcery.com>
 556             Joseph Myers  <joseph@codesourcery.com>
 557
 558         * configure: Regenerate.
 559
 560 2007-10-22  Richard Sandiford  <rsandifo@nildram.co.uk>
 561
 562         * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
 563         that unconditionally allows fmt_ps.
 564         (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
 565         (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
 566         (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
 567         filter from 64,f to 32,f.
 568         (PREFX): Change filter from 64 to 32.
 569         (LDXC1, LUXC1): Provide separate mips32r2 implementations
 570         that use do_load_double instead of do_load.  Make both LUXC1
 571         versions unpredictable if SizeFGR () != 64.
 572         (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
 573         instead of do_store.  Remove unused variable.  Make both SUXC1
 574         versions unpredictable if SizeFGR () != 64.
 575
 576 2007-10-07  Richard Sandiford  <rsandifo@nildram.co.uk>
 577
 578         * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
 579         (sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
 580         shifts for that case.
 581
 582 2007-09-04  Nick Clifton  <nickc@redhat.com>
 583
 584         * interp.c (options enum): Add OPTION_INFO_MEMORY.
 585         (display_mem_info): New static variable.
 586         (mips_option_handler): Handle OPTION_INFO_MEMORY.
 587         (mips_options): Add info-memory and memory-info.
 588         (sim_open): After processing the command line and board
 589         specification, check display_mem_info.  If it is set then
 590         call the real handler for the --memory-info command line
 591         switch.
 592
 593 2007-08-24  Joel Brobecker  <brobecker@adacore.com>
 594
 595         * configure.ac: Change license of multi-run.c to GPL version 3.
 596         * configure: Regenerate.
 597
 598 2007-06-28  Richard Sandiford  <richard@codesourcery.com>
 599
 600         * configure.ac, configure: Revert last patch.
 601
 602 2007-06-26  Richard Sandiford  <richard@codesourcery.com>
 603
 604         * configure.ac (sim_mipsisa3264_configs): New variable.
 605         (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
 606         every configuration support all four targets, using the triplet to
 607         determine the default.
 608         * configure: Regenerate.
 609
 610 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
 611
 612         * Makefile.in (m16run.o): New rule.
 613
 614 2007-05-15  Thiemo Seufer  <ths@mips.com>
 615
 616         * mips3264r2.igen (DSHD): Fix compile warning.
 617
 618 2007-05-14  Thiemo Seufer  <ths@mips.com>
 619
 620         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
 621         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
 622         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
 623         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
 624         for mips32r2.
 625
 626 2007-03-01  Thiemo Seufer  <ths@mips.com>
 627
 628         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
 629         and mips64.
 630
 631 2007-02-20  Thiemo Seufer  <ths@mips.com>
 632
 633         * dsp.igen: Update copyright notice.
 634         * dsp2.igen: Fix copyright notice.
 635
 636 2007-02-20  Thiemo Seufer  <ths@mips.com>
 637             Chao-Ying Fu  <fu@mips.com>
 638
 639         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
 640         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 641         Add dsp2 to sim_igen_machine.
 642         * configure: Regenerate.
 643         * dsp.igen (do_ph_op): Add MUL support when op = 2.
 644         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
 645         (mulq_rs.ph): Use do_ph_mulq.
 646         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
 647         * mips.igen: Add dsp2 model and include dsp2.igen.
 648         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
 649         for *mips32r2, *mips64r2, *dsp.
 650         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
 651         for *mips32r2, *mips64r2, *dsp2.
 652         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
 653
 654 2007-02-19  Thiemo Seufer  <ths@mips.com>
 655             Nigel Stephens  <nigel@mips.com>
 656
 657         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
 658         jumps with hazard barrier.
 659
 660 2007-02-19  Thiemo Seufer  <ths@mips.com>
 661             Nigel Stephens  <nigel@mips.com>
 662
 663         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
 664         after each call to sim_io_write.
 665
 666 2007-02-19  Thiemo Seufer  <ths@mips.com>
 667             Nigel Stephens  <nigel@mips.com>
 668
 669         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
 670         supported by this simulator.
 671         (decode_coproc): Recognise additional CP0 Config registers
 672         correctly.
 673
 674 2007-02-19  Thiemo Seufer  <ths@mips.com>
 675             Nigel Stephens  <nigel@mips.com>
 676             David Ung  <davidu@mips.com>
 677
 678         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
 679         uninterpreted formats. If fmt is one of the uninterpreted types
 680         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
 681         fmt_word, and fmt_uninterpreted_64 like fmt_long.
 682         (store_fpr): When writing an invalid odd register, set the
 683         matching even register to fmt_unknown, not the following register.
 684         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
 685         the the memory window at offset 0 set by --memory-size command
 686         line option.
 687         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
 688         point register.
 689         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
 690         register.
 691         (sim_monitor): When returning the memory size to the MIPS
 692         application, use the value in STATE_MEM_SIZE, not an arbitrary
 693         hardcoded value.
 694         (cop_lw): Don' mess around with FPR_STATE, just pass
 695         fmt_uninterpreted_32 to StoreFPR.
 696         (cop_sw): Similarly.
 697         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
 698         (cop_sd): Similarly.
 699         * mips.igen (not_word_value): Single version for mips32, mips64
 700         and mips16.
 701
 702 2007-02-19  Thiemo Seufer <ths@mips.com>
 703             Nigel Stephens  <nigel@mips.com>
 704
 705         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
 706         MBytes.
 707
 708 2007-02-17  Thiemo Seufer  <ths@mips.com>
 709
 710         * configure.ac (mips*-sde-elf*): Move in front of generic machine
 711         configuration.
 712         * configure: Regenerate.
 713
 714 2007-02-17  Thiemo Seufer  <ths@mips.com>
 715
 716         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 717         Add mdmx to sim_igen_machine.
 718         (mipsisa64*-*-*): Likewise. Remove dsp.
 719         (mipsisa32*-*-*): Remove dsp.
 720         * configure: Regenerate.
 721
 722 2007-02-13  Thiemo Seufer  <ths@mips.com>
 723
 724         * configure.ac: Add mips*-sde-elf* target.
 725         * configure: Regenerate.
 726
 727 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 728
 729         * acconfig.h: Remove.
 730         * config.in, configure: Regenerate.
 731
 732 2006-11-07  Thiemo Seufer  <ths@mips.com>
 733
 734         * dsp.igen (do_w_op): Fix compiler warning.
 735
 736 2006-08-29  Thiemo Seufer  <ths@mips.com>
 737             David Ung  <davidu@mips.com>
 738
 739         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 740         sim_igen_machine.
 741         * configure: Regenerate.
 742         * mips.igen (model): Add smartmips.
 743         (MADDU): Increment ACX if carry.
 744         (do_mult): Clear ACX.
 745         (ROR,RORV): Add smartmips.
 746         (include): Include smartmips.igen.
 747         * sim-main.h (ACX): Set to REGISTERS[89].
 748         * smartmips.igen: New file.
 749
 750 2006-08-29  Thiemo Seufer  <ths@mips.com>
 751             David Ung  <davidu@mips.com>
 752
 753         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 754         mips3264r2.igen. Add missing dependency rules.
 755         * m16e.igen: Support for mips16e save/restore instructions.
 756
 757 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 758
 759         * configure: Regenerated.
 760
 761 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 762
 763         * configure: Regenerated.
 764
 765 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 766
 767         * configure: Regenerated.
 768
 769 2006-05-15 Chao-ying Fu  <fu@mips.com>
 770
 771         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 772
 773 2006-04-18  Nick Clifton  <nickc@redhat.com>
 774
 775         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 776         statement.
 777
 778 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 779
 780         * configure: Regenerate.
 781
 782 2005-12-14  Chao-ying Fu  <fu@mips.com>
 783
 784         * Makefile.in (SIM_OBJS): Add dsp.o.
 785         (dsp.o): New dependency.
 786         (IGEN_INCLUDE): Add dsp.igen.
 787         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 788         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 789         * configure: Regenerate.
 790         * mips.igen: Add dsp model and include dsp.igen.
 791         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 792         because these instructions are extended in DSP ASE.
 793         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 794         adding 6 DSP accumulator registers and 1 DSP control register.
 795         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 796         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 797         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 798         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 799         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 800         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 801         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 802         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 803         DSPCR_CCOND_SMASK): New define.
 804         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 805         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 806
 807 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 808
 809         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 810
 811 2005-06-16  David Ung  <davidu@mips.com>
 812             Nigel Stephens  <nigel@mips.com>
 813
 814         * mips.igen: New mips16e model and include m16e.igen.
 815         (check_u64): Add mips16e tag.
 816         * m16e.igen: New file for MIPS16e instructions.
 817         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 818         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 819         models.
 820         * configure: Regenerate.
 821
 822 2005-05-26  David Ung  <davidu@mips.com>
 823
 824         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 825         tags to all instructions which are applicable to the new ISAs.
 826         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 827         vr.igen.
 828         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 829         instructions.
 830         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 831         to mips.igen.
 832         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 833         * configure: Regenerate.
 834
 835 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 836
 837         * configure: Regenerate.
 838
 839 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 840
 841         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 842         explicit call to AC_CONFIG_HEADER.
 843         * configure: Regenerate.
 844
 845 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 846
 847         * configure.ac: Update to use ../common/common.m4.
 848         * configure: Re-generate.
 849
 850 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 851
 852         * configure: Regenerated to track ../common/aclocal.m4 changes.
 853
 854 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 855
 856         * configure.ac: Rename configure.in, require autoconf 2.59.
 857         * configure: Re-generate.
 858
 859 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 860
 861         * configure: Regenerate for ../common/aclocal.m4 update.
 862
 863 2004-09-24  Monika Chaddha  <monika@acmet.com>
 864
 865         Committed by Andrew Cagney.
 866         * m16.igen (CMP, CMPI): Fix assembler.
 867
 868 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 869
 870         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 871         * configure: Regenerate.
 872
 873 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 874
 875         * configure.in (sim_m16_machine): Include mipsIII.
 876         * configure: Regenerate.
 877
 878 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 879
 880         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 881         from COP0_BADVADDR.
 882         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 883
 884 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 885
 886         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 887
 888 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 889
 890         * mips.igen (check_fmt): Remove.
 891         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 892         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 893         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 894         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 895         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 896         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 897         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 898         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 899         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 900         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 901
 902 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 903
 904         * sb1.igen (check_sbx): New function.
 905         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 906
 907 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 908             Richard Sandiford  <rsandifo@redhat.com>
 909
 910         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 911         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 912         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 913         separate implementations for mipsIV and mipsV.  Use new macros to
 914         determine whether the restrictions apply.
 915
 916 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 917
 918         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 919         (check_mult_hilo): Improve comments.
 920         (check_div_hilo): Likewise.  Also, fork off a new version
 921         to handle mips32/mips64 (since there are no hazards to check
 922         in MIPS32/MIPS64).
 923
 924 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 925
 926         * mips.igen (do_dmultx): Fix check for negative operands.
 927
 928 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 929
 930         * Makefile.in (SHELL): Make sure this is defined.
 931         (various): Use $(SHELL) whenever we invoke move-if-change.
 932
 933 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 934
 935         * cp1.c: Tweak attribution slightly.
 936         * cp1.h: Likewise.
 937         * mdmx.c: Likewise.
 938         * mdmx.igen: Likewise.
 939         * mips3d.igen: Likewise.
 940         * sb1.igen: Likewise.
 941
 942 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 943
 944         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 945         unsigned operands.
 946
 947 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 948
 949         * interp.c (sim_open): Rename _bfd to bfd.
 950         (sim_create_inferior): Ditto.
 951
 952 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 953
 954         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 955
 956 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 957
 958         * mips.igen (EI, DI): Remove.
 959
 960 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 961
 962         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 963
 964 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 965             Andrew Cagney  <ac131313@redhat.com>
 966             Gavin Romig-Koch  <gavin@redhat.com>
 967             Graydon Hoare  <graydon@redhat.com>
 968             Aldy Hernandez  <aldyh@redhat.com>
 969             Dave Brolley  <brolley@redhat.com>
 970             Chris Demetriou  <cgd@broadcom.com>
 971
 972         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 973         (sim_mach_default): New variable.
 974         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 975         Add a new simulator generator, MULTI.
 976         * configure: Regenerate.
 977         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 978         (multi-run.o): New dependency.
 979         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 980         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 981         (tmp-multi): Combine them.
 982         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 983         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 984         (distclean-extra): New rule.
 985         * sim-main.h: Include bfd.h.
 986         (MIPS_MACH): New macro.
 987         * mips.igen (vr4120, vr5400, vr5500): New models.
 988         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 989         * vr.igen: Replace with new version.
 990
 991 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 992
 993         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 994         * configure: Regenerate.
 995
 996 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 997
 998         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 999         * mips.igen: Remove all invocations of check_branch_bug and
1000         mark_branch_bug.
1001
1002 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
1003
1004         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
1005
1006 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
1007
1008         * mips.igen (do_load_double, do_store_double): New functions.
1009         (LDC1, SDC1): Rename to...
1010         (LDC1b, SDC1b): respectively.
1011         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1012
1013 2002-07-29  Michael Snyder  <msnyder@redhat.com>
1014
1015         * cp1.c (fp_recip2): Modify initialization expression so that
1016         GCC will recognize it as constant.
1017
1018 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
1019
1020         * mdmx.c (SD_): Delete.
1021         (Unpredictable): Re-define, for now, to directly invoke
1022         unpredictable_action().
1023         (mdmx_acc_op): Fix error in .ob immediate handling.
1024
1025 2002-06-18  Andrew Cagney  <cagney@redhat.com>
1026
1027         * interp.c (sim_firmware_command): Initialize `address'.
1028
1029 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
1030
1031         * configure: Regenerated to track ../common/aclocal.m4 changes.
1032
1033 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
1034             Ed Satterthwaite  <ehs@broadcom.com>
1035
1036         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1037         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1038         * mips.igen: Include mips3d.igen.
1039         (mips3d): New model name for MIPS-3D ASE instructions.
1040         (CVT.W.fmt): Don't use this instruction for word (source) format
1041         instructions.
1042         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1043         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1044         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1045         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1046         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1047         (RSquareRoot1, RSquareRoot2): New macros.
1048         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1049         (fp_rsqrt2): New functions.
1050         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1051         * configure: Regenerate.
1052
1053 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
1054             Ed Satterthwaite  <ehs@broadcom.com>
1055
1056         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1057         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1058         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1059         (convert): Note that this function is not used for paired-single
1060         format conversions.
1061         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1062         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1063         (check_fmt_p): Enable paired-single support.
1064         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1065         (PUU.PS): New instructions.
1066         (CVT.S.fmt): Don't use this instruction for paired-single format
1067         destinations.
1068         * sim-main.h (FP_formats): New value 'fmt_ps.'
1069         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1070         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1071
1072 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
1073
1074         * mips.igen: Fix formatting of function calls in
1075         many FP operations.
1076
1077 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
1078
1079         * mips.igen (MOVN, MOVZ): Trace result.
1080         (TNEI): Print "tnei" as the opcode name in traces.
1081         (CEIL.W): Add disassembly string for traces.
1082         (RSQRT.fmt): Make location of disassembly string consistent
1083         with other instructions.
1084
1085 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
1086
1087         * mips.igen (X): Delete unused function.
1088
1089 2002-06-08  Andrew Cagney  <cagney@redhat.com>
1090
1091         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1092
1093 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1094             Ed Satterthwaite  <ehs@broadcom.com>
1095
1096         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1097         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1098         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1099         (fp_nmsub): New prototypes.
1100         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1101         (NegMultiplySub): New defines.
1102         * mips.igen (RSQRT.fmt): Use RSquareRoot().
1103         (MADD.D, MADD.S): Replace with...
1104         (MADD.fmt): New instruction.
1105         (MSUB.D, MSUB.S): Replace with...
1106         (MSUB.fmt): New instruction.
1107         (NMADD.D, NMADD.S): Replace with...
1108         (NMADD.fmt): New instruction.
1109         (NMSUB.D, MSUB.S): Replace with...
1110         (NMSUB.fmt): New instruction.
1111
1112 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1113             Ed Satterthwaite  <ehs@broadcom.com>
1114
1115         * cp1.c: Fix more comment spelling and formatting.
1116         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1117         (denorm_mode): New function.
1118         (fpu_unary, fpu_binary): Round results after operation, collect
1119         status from rounding operations, and update the FCSR.
1120         (convert): Collect status from integer conversions and rounding
1121         operations, and update the FCSR.  Adjust NaN values that result
1122         from conversions.  Convert to use sim_io_eprintf rather than
1123         fprintf, and remove some debugging code.
1124         * cp1.h (fenr_FS): New define.
1125
1126 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1127
1128         * cp1.c (convert): Remove unusable debugging code, and move MIPS
1129         rounding mode to sim FP rounding mode flag conversion code into...
1130         (rounding_mode): New function.
1131
1132 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
1133
1134         * cp1.c: Clean up formatting of a few comments.
1135         (value_fpr): Reformat switch statement.
1136
1137 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
1138             Ed Satterthwaite  <ehs@broadcom.com>
1139
1140         * cp1.h: New file.
1141         * sim-main.h: Include cp1.h.
1142         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1143         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1144         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
1145         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1146         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1147         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1148         * cp1.c: Don't include sim-fpu.h; already included by
1149         sim-main.h.  Clean up formatting of some comments.
1150         (NaN, Equal, Less): Remove.
1151         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1152         (fp_cmp): New functions.
1153         * mips.igen (do_c_cond_fmt): Remove.
1154         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1155         Compare.  Add result tracing.
1156         (CxC1): Remove, replace with...
1157         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1158         (DMxC1): Remove, replace with...
1159         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
1160         (MxC1): Remove, replace with...
1161         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
1162
1163 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
1164
1165         * sim-main.h (FGRIDX): Remove, replace all uses with...
1166         (FGR_BASE): New macro.
1167         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1168         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1169         (NR_FGR, FGR): Likewise.
1170         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1171         * mips.igen: Likewise.
1172
1173 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
1174
1175         * cp1.c: Add an FSF Copyright notice to this file.
1176
1177 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
1178             Ed Satterthwaite  <ehs@broadcom.com>
1179
1180         * cp1.c (Infinity): Remove.
1181         * sim-main.h (Infinity): Likewise.
1182
1183         * cp1.c (fp_unary, fp_binary): New functions.
1184         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1185         (fp_sqrt): New functions, implemented in terms of the above.
1186         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1187         (Recip, SquareRoot): Remove (replaced by functions above).
1188         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1189         (fp_recip, fp_sqrt): New prototypes.
1190         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1191         (Recip, SquareRoot): Replace prototypes with #defines which
1192         invoke the functions above.
1193
1194 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1195
1196         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1197         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1198         file, remove PARAMS from prototypes.
1199         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
1200         simulator state arguments.
1201         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
1202         pass simulator state arguments.
1203         * cp1.c (SD): Redefine as CPU_STATE(cpu).
1204         (store_fpr, convert): Remove 'sd' argument.
1205         (value_fpr): Likewise.  Convert to use 'SD' instead.
1206
1207 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1208
1209         * cp1.c (Min, Max): Remove #if 0'd functions.
1210         * sim-main.h (Min, Max): Remove.
1211
1212 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1213
1214         * cp1.c: fix formatting of switch case and default labels.
1215         * interp.c: Likewise.
1216         * sim-main.c: Likewise.
1217
1218 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1219
1220         * cp1.c: Clean up comments which describe FP formats.
1221          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1222
1223 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1224             Ed Satterthwaite  <ehs@broadcom.com>
1225
1226         * configure.in (mipsisa64sb1*-*-*): New target for supporting
1227         Broadcom SiByte SB-1 processor configurations.
1228         * configure: Regenerate.
1229         * sb1.igen: New file.
1230         * mips.igen: Include sb1.igen.
1231         (sb1): New model.
1232         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1233         * mdmx.igen: Add "sb1" model to all appropriate functions and
1234         instructions.
1235         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1236         (ob_func, ob_acc): Reference the above.
1237         (qh_acc): Adjust to keep the same size as ob_acc.
1238         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1239         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1240
1241 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
1242
1243         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1244
1245 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
1246             Ed Satterthwaite  <ehs@broadcom.com>
1247
1248         * mips.igen (mdmx): New (pseudo-)model.
1249         * mdmx.c, mdmx.igen: New files.
1250         * Makefile.in (SIM_OBJS): Add mdmx.o.
1251         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1252         New typedefs.
1253         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1254         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1255         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1256         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1257         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1258         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1259         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1260         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1261         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1262         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1263         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1264         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1265         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1266         (qh_fmtsel): New macros.
1267         (_sim_cpu): New member "acc".
1268         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1269         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1270
1271 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
1272
1273         * interp.c: Use 'deprecated' rather than 'depreciated.'
1274         * sim-main.h: Likewise.
1275
1276 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
1277
1278         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1279         which wouldn't compile anyway.
1280         * sim-main.h (unpredictable_action): New function prototype.
1281         (Unpredictable): Define to call igen function unpredictable().
1282         (NotWordValue): New macro to call igen function not_word_value().
1283         (UndefinedResult): Remove.
1284         * interp.c (undefined_result): Remove.
1285         (unpredictable_action): New function.
1286         * mips.igen (not_word_value, unpredictable): New functions.
1287         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1288         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1289         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1290         NotWordValue() to check for unpredictable inputs, then
1291         Unpredictable() to handle them.
1292
1293 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
1294
1295         * mips.igen: Fix formatting of calls to Unpredictable().
1296
1297 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
1298
1299         * interp.c (sim_open): Revert previous change.
1300
1301 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
1302
1303         * interp.c (sim_open): Disable chunk of code that wrote code in
1304         vector table entries.
1305
1306 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
1307
1308         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1309         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1310         unused definitions.
1311
1312 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
1313
1314         * cp1.c: Fix many formatting issues.
1315
1316 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
1317
1318         * cp1.c (fpu_format_name): New function to replace...
1319         (DOFMT): This.  Delete, and update all callers.
1320         (fpu_rounding_mode_name): New function to replace...
1321         (RMMODE): This.  Delete, and update all callers.
1322
1323 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
1324
1325         * interp.c: Move FPU support routines from here to...
1326         * cp1.c: Here.  New file.
1327         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1328         (cp1.o): New target.
1329
1330 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
1331
1332         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1333         * mips.igen (mips32, mips64): New models, add to all instructions
1334         and functions as appropriate.
1335         (loadstore_ea, check_u64): New variant for model mips64.
1336         (check_fmt_p): New variant for models mipsV and mips64, remove
1337         mipsV model marking fro other variant.
1338         (SLL) Rename to...
1339         (SLLa) this.
1340         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1341         for mips32 and mips64.
1342         (DCLO, DCLZ): New instructions for mips64.
1343
1344 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
1345
1346         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1347         immediate or code as a hex value with the "%#lx" format.
1348         (ANDI): Likewise, and fix printed instruction name.
1349
1350 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1351
1352         * sim-main.h (UndefinedResult, Unpredictable): New macros
1353         which currently do nothing.
1354
1355 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1356
1357         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1358         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1359         (status_CU3): New definitions.
1360
1361         * sim-main.h (ExceptionCause): Add new values for MIPS32
1362         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
1363         for DebugBreakPoint and NMIReset to note their status in
1364         MIPS32 and MIPS64.
1365         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1366         (SignalExceptionCacheErr): New exception macros.
1367
1368 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1369
1370         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1371         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1372         is always enabled.
1373         (SignalExceptionCoProcessorUnusable): Take as argument the
1374         unusable coprocessor number.
1375
1376 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1377
1378         * mips.igen: Fix formatting of all SignalException calls.
1379
1380 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
1381
1382         * sim-main.h (SIGNEXTEND): Remove.
1383
1384 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
1385
1386         * mips.igen: Remove gencode comment from top of file, fix
1387         spelling in another comment.
1388
1389 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
1390
1391         * mips.igen (check_fmt, check_fmt_p): New functions to check
1392         whether specific floating point formats are usable.
1393         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1394         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1395         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1396         Use the new functions.
1397         (do_c_cond_fmt): Remove format checks...
1398         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1399
1400 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1401
1402         * mips.igen: Fix formatting of check_fpu calls.
1403
1404 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1405
1406         * mips.igen (FLOOR.L.fmt): Store correct destination register.
1407
1408 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1409
1410         * mips.igen: Remove whitespace at end of lines.
1411
1412 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1413
1414         * mips.igen (loadstore_ea): New function to do effective
1415         address calculations.
1416         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1417         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1418         CACHE): Use loadstore_ea to do effective address computations.
1419
1420 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1421
1422         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1423         * mips.igen (LL, CxC1, MxC1): Likewise.
1424
1425 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1426
1427         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1428         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1429         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1430         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1431         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1432         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1433         Don't split opcode fields by hand, use the opcode field values
1434         provided by igen.
1435
1436 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1437
1438         * mips.igen (do_divu): Fix spacing.
1439
1440         * mips.igen (do_dsllv): Move to be right before DSLLV,
1441         to match the rest of the do_<shift> functions.
1442
1443 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1444
1445         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1446         DSRL32, do_dsrlv): Trace inputs and results.
1447
1448 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1449
1450         * mips.igen (CACHE): Provide instruction-printing string.
1451
1452         * interp.c (signal_exception): Comment tokens after #endif.
1453
1454 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1455
1456         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1457         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1458         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1459         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1460         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1461         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1462         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1463         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1464
1465 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1466
1467         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1468         instruction-printing string.
1469         (LWU): Use '64' as the filter flag.
1470
1471 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1472
1473         * mips.igen (SDXC1): Fix instruction-printing string.
1474
1475 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1476
1477         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1478         filter flags "32,f".
1479
1480 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1481
1482         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1483         as the filter flag.
1484
1485 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1486
1487         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1488         add a comma) so that it more closely match the MIPS ISA
1489         documentation opcode partitioning.
1490         (PREF): Put useful names on opcode fields, and include
1491         instruction-printing string.
1492
1493 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1494
1495         * mips.igen (check_u64): New function which in the future will
1496         check whether 64-bit instructions are usable and signal an
1497         exception if not.  Currently a no-op.
1498         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1499         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1500         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1501         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1502
1503         * mips.igen (check_fpu): New function which in the future will
1504         check whether FPU instructions are usable and signal an exception
1505         if not.  Currently a no-op.
1506         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1507         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1508         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1509         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1510         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1511         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1512         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1513         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1514
1515 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1516
1517         * mips.igen (do_load_left, do_load_right): Move to be immediately
1518         following do_load.
1519         (do_store_left, do_store_right): Move to be immediately following
1520         do_store.
1521
1522 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1523
1524         * mips.igen (mipsV): New model name.  Also, add it to
1525         all instructions and functions where it is appropriate.
1526
1527 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
1528
1529         * mips.igen: For all functions and instructions, list model
1530         names that support that instruction one per line.
1531
1532 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1533
1534         * mips.igen: Add some additional comments about supported
1535         models, and about which instructions go where.
1536         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1537         order as is used in the rest of the file.
1538
1539 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1540
1541         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1542         indicating that ALU32_END or ALU64_END are there to check
1543         for overflow.
1544         (DADD): Likewise, but also remove previous comment about
1545         overflow checking.
1546
1547 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1548
1549         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1550         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1551         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1552         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1553         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1554         fields (i.e., add and move commas) so that they more closely
1555         match the MIPS ISA documentation opcode partitioning.
1556
1557 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1558
1559         * mips.igen (ADDI): Print immediate value.
1560         (BREAK): Print code.
1561         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1562         (SLL): Print "nop" specially, and don't run the code
1563         that does the shift for the "nop" case.
1564
1565 2001-11-17  Fred Fish  <fnf@redhat.com>
1566
1567         * sim-main.h (float_operation): Move enum declaration outside
1568         of _sim_cpu struct declaration.
1569
1570 2001-04-12  Jim Blandy  <jimb@redhat.com>
1571
1572         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1573         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
1574         set of the FCSR.
1575         * sim-main.h (COCIDX): Remove definition; this isn't supported by
1576         PENDING_FILL, and you can get the intended effect gracefully by
1577         calling PENDING_SCHED directly.
1578
1579 2001-02-23  Ben Elliston  <bje@redhat.com>
1580
1581         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1582         already defined elsewhere.
1583
1584 2001-02-19  Ben Elliston  <bje@redhat.com>
1585
1586         * sim-main.h (sim_monitor): Return an int.
1587         * interp.c (sim_monitor): Add return values.
1588         (signal_exception): Handle error conditions from sim_monitor.
1589
1590 2001-02-08  Ben Elliston  <bje@redhat.com>
1591
1592         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1593         (store_memory): Likewise, pass cia to sim_core_write*.
1594
1595 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
1596
1597         On advice from Chris G. Demetriou <cgd@sibyte.com>:
1598         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1599
1600 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1601
1602         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1603         * Makefile.in: Don't delete *.igen when cleaning directory.
1604
1605 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1606
1607         * m16.igen (break): Call SignalException not sim_engine_halt.
1608
1609 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1610
1611         From Jason Eckhardt:
1612         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1613
1614 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1615
1616         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1617
1618 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1619
1620         * mips.igen (do_dmultx): Fix typo.
1621
1622 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1623
1624         * configure: Regenerated to track ../common/aclocal.m4 changes.
1625
1626 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1627
1628         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1629
1630 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1631
1632         * sim-main.h (GPR_CLEAR): Define macro.
1633
1634 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1635
1636         * interp.c (decode_coproc): Output long using %lx and not %s.
1637
1638 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1639
1640         * interp.c (sim_open): Sort & extend dummy memory regions for
1641         --board=jmr3904 for eCos.
1642
1643 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1644
1645         * configure: Regenerated.
1646
1647 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1648
1649         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1650         calls, conditional on the simulator being in verbose mode.
1651
1652 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1653
1654         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1655         cache don't get ReservedInstruction traps.
1656
1657 1999-11-29  Mark Salter  <msalter@cygnus.com>
1658
1659         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1660         to clear status bits in sdisr register. This is how the hardware works.
1661
1662         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1663         being used by cygmon.
1664
1665 1999-11-11  Andrew Haley  <aph@cygnus.com>
1666
1667         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1668         instructions.
1669
1670 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1671
1672         * mips.igen (MULT): Correct previous mis-applied patch.
1673
1674 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1675
1676         * mips.igen (delayslot32): Handle sequence like
1677         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1678         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1679         (MULT): Actually pass the third register...
1680
1681 1999-09-03  Mark Salter  <msalter@cygnus.com>
1682
1683         * interp.c (sim_open): Added more memory aliases for additional
1684         hardware being touched by cygmon on jmr3904 board.
1685
1686 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1687
1688         * configure: Regenerated to track ../common/aclocal.m4 changes.
1689
1690 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1691
1692         * interp.c (sim_store_register): Handle case where client - GDB -
1693         specifies that a 4 byte register is 8 bytes in size.
1694         (sim_fetch_register): Ditto.
1695
1696 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1697
1698         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1699         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1700         (idt_monitor_base): Base address for IDT monitor traps.
1701         (pmon_monitor_base): Ditto for PMON.
1702         (lsipmon_monitor_base): Ditto for LSI PMON.
1703         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1704         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1705         (sim_firmware_command): New function.
1706         (mips_option_handler): Call it for OPTION_FIRMWARE.
1707         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1708         option was given, add no monitor by default.  Add BREAK hooks only if
1709         monitors are also there.
1710
1711 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1712
1713         * interp.c (sim_monitor): Flush output before reading input.
1714
1715 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1716
1717         * tconfig.in (SIM_HANDLES_LMA): Always define.
1718
1719 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1720
1721         From Mark Salter <msalter@cygnus.com>:
1722         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1723         (sim_open): Add setup for BSP board.
1724
1725 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1726
1727         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1728         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1729         them as unimplemented.
1730
1731 1999-05-08  Felix Lee  <flee@cygnus.com>
1732
1733         * configure: Regenerated to track ../common/aclocal.m4 changes.
1734
1735 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1736
1737         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1738
1739 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1740
1741         * configure.in: Any mips64vr5*-*-* target should have
1742         -DTARGET_ENABLE_FR=1.
1743         (default_endian): Any mips64vr*el-*-* target should default to
1744         LITTLE_ENDIAN.
1745         * configure: Re-generate.
1746
1747 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1748
1749         * mips.igen (ldl): Extend from _16_, not 32.
1750
1751 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1752
1753         * interp.c (sim_store_register): Force registers written to by GDB
1754         into an un-interpreted state.
1755
1756 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1757
1758         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1759         CPU, start periodic background I/O polls.
1760         (tx3904sio_poll): New function: periodic I/O poller.
1761
1762 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1763
1764         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1765
1766 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1767
1768         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1769         case statement.
1770
1771 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1772
1773         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1774         (load_word): Call SIM_CORE_SIGNAL hook on error.
1775         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1776         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1777         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1778         * sim-main.h (COP0_BADVADDR): Define.
1779         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1780         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1781         (_sim_cpu): Add exc_* fields to store register value snapshots.
1782         * mips.igen (*): Replace memory-related SignalException* calls
1783         with references to SIM_CORE_SIGNAL hook.
1784
1785         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1786         fix.
1787         * sim-main.c (*): Minor warning cleanups.
1788
1789 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1790
1791         * m16.igen (DADDIU5): Correct type-o.
1792
1793 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1794
1795         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1796         variables.
1797
1798 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1799
1800         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1801         to include path.
1802         (interp.o): Add dependency on itable.h
1803         (oengine.c, gencode): Delete remaining references.
1804         (BUILT_SRC_FROM_GEN): Clean up.
1805
1806 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1807
1808         * vr4run.c: New.
1809         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1810         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1811         tmp-run-hack) : New.
1812         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1813         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1814         Drop the "64" qualifier to get the HACK generator working.
1815         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1816         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1817         qualifier to get the hack generator working.
1818         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1819         (DSLL): Use do_dsll.
1820         (DSLLV): Use do_dsllv.
1821         (DSRA): Use do_dsra.
1822         (DSRL): Use do_dsrl.
1823         (DSRLV): Use do_dsrlv.
1824         (BC1): Move *vr4100 to get the HACK generator working.
1825         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1826         get the HACK generator working.
1827         (MACC) Rename to get the HACK generator working.
1828         (DMACC,MACCS,DMACCS): Add the 64.
1829
1830 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1831
1832         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1833         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1834
1835 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1836
1837     * mips/interp.c (DEBUG): Cleanups.
1838
1839 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1840
1841         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1842         (tx3904sio_tickle): fflush after a stdout character output.
1843
1844 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1845
1846         * interp.c (sim_close): Uninstall modules.
1847
1848 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * sim-main.h, interp.c (sim_monitor): Change to global
1851         function.
1852
1853 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1854
1855         * configure.in (vr4100): Only include vr4100 instructions in
1856         simulator.
1857         * configure: Re-generate.
1858         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1859
1860 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1861
1862         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1863         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1864         true alternative.
1865
1866         * configure.in (sim_default_gen, sim_use_gen): Replace with
1867         sim_gen.
1868         (--enable-sim-igen): Delete config option. Always using IGEN.
1869         * configure: Re-generate.
1870
1871         * Makefile.in (gencode): Kill, kill, kill.
1872         * gencode.c: Ditto.
1873
1874 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1875
1876         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1877         bit mips16 igen simulator.
1878         * configure: Re-generate.
1879
1880         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1881         as part of vr4100 ISA.
1882         * vr.igen: Mark all instructions as 64 bit only.
1883
1884 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1885
1886         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1887         Pacify GCC.
1888
1889 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1892         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1893         * configure: Re-generate.
1894
1895         * m16.igen (BREAK): Define breakpoint instruction.
1896         (JALX32): Mark instruction as mips16 and not r3900.
1897         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1898
1899         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1900
1901 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1902
1903         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1904         insn as a debug breakpoint.
1905
1906         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1907         pending.slot_size.
1908         (PENDING_SCHED): Clean up trace statement.
1909         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1910         (PENDING_FILL): Delay write by only one cycle.
1911         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1912
1913         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1914         of pending writes.
1915         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1916         32 & 64.
1917         (pending_tick): Move incrementing of index to FOR statement.
1918         (pending_tick): Only update PENDING_OUT after a write has occured.
1919
1920         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1921         build simulator.
1922         * configure: Re-generate.
1923
1924         * interp.c (sim_engine_run OLD): Delete explicit call to
1925         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1926
1927 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1928
1929         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1930         interrupt level number to match changed SignalExceptionInterrupt
1931         macro.
1932
1933 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1934
1935         * interp.c: #include "itable.h" if WITH_IGEN.
1936         (get_insn_name): New function.
1937         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1938         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1939
1940 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1941
1942         * configure: Rebuilt to inhale new common/aclocal.m4.
1943
1944 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1945
1946         * dv-tx3904sio.c: Include sim-assert.h.
1947
1948 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1949
1950         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1951         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1952         Reorganize target-specific sim-hardware checks.
1953         * configure: rebuilt.
1954         * interp.c (sim_open): For tx39 target boards, set
1955         OPERATING_ENVIRONMENT, add tx3904sio devices.
1956         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1957         ROM executables.  Install dv-sockser into sim-modules list.
1958
1959         * dv-tx3904irc.c: Compiler warning clean-up.
1960         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1961         frequent hw-trace messages.
1962
1963 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1964
1965         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1966
1967 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1968
1969         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1970
1971         * vr.igen: New file.
1972         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1973         * mips.igen: Define vr4100 model. Include vr.igen.
1974 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1975
1976         * mips.igen (check_mf_hilo): Correct check.
1977
1978 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1979
1980         * sim-main.h (interrupt_event): Add prototype.
1981
1982         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1983         register_ptr, register_value.
1984         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1985
1986         * sim-main.h (tracefh): Make extern.
1987
1988 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1989
1990         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1991         Reduce unnecessarily high timer event frequency.
1992         * dv-tx3904cpu.c: Ditto for interrupt event.
1993
1994 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1995
1996         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1997         to allay warnings.
1998         (interrupt_event): Made non-static.
1999
2000         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2001         interchange of configuration values for external vs. internal
2002         clock dividers.
2003
2004 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
2005
2006         * mips.igen (BREAK): Moved code to here for
2007         simulator-reserved break instructions.
2008         * gencode.c (build_instruction): Ditto.
2009         * interp.c (signal_exception): Code moved from here.  Non-
2010         reserved instructions now use exception vector, rather
2011         than halting sim.
2012         * sim-main.h: Moved magic constants to here.
2013
2014 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
2015
2016         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2017         register upon non-zero interrupt event level, clear upon zero
2018         event value.
2019         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2020         by passing zero event value.
2021         (*_io_{read,write}_buffer): Endianness fixes.
2022         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2023         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2024
2025         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2026         serial I/O and timer module at base address 0xFFFF0000.
2027
2028 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
2029
2030         * mips.igen (SWC1) : Correct the handling of ReverseEndian
2031         and BigEndianCPU.
2032
2033 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
2034
2035         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2036         parts.
2037         * configure: Update.
2038
2039 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
2040
2041         * dv-tx3904tmr.c: New file - implements tx3904 timer.
2042         * dv-tx3904{irc,cpu}.c: Mild reformatting.
2043         * configure.in: Include tx3904tmr in hw_device list.
2044         * configure: Rebuilt.
2045         * interp.c (sim_open): Instantiate three timer instances.
2046         Fix address typo of tx3904irc instance.
2047
2048 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
2049
2050         * interp.c (signal_exception): SystemCall exception now uses
2051         the exception vector.
2052
2053 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
2054
2055         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2056         to allay warnings.
2057
2058 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2059
2060         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2061
2062 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2065
2066         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2067         sim-main.h. Declare a struct hw_descriptor instead of struct
2068         hw_device_descriptor.
2069
2070 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2071
2072         * mips.igen (do_store_left, do_load_left): Compute nr of left and
2073         right bits and then re-align left hand bytes to correct byte
2074         lanes.  Fix incorrect computation in do_store_left when loading
2075         bytes from second word.
2076
2077 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2078
2079         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2080         * interp.c (sim_open): Only create a device tree when HW is
2081         enabled.
2082
2083         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2084         * interp.c (signal_exception): Ditto.
2085
2086 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
2087
2088         * gencode.c: Mark BEGEZALL as LIKELY.
2089
2090 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2091
2092         * sim-main.h (ALU32_END): Sign extend 32 bit results.
2093         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
2094
2095 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
2096
2097         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2098         modules.  Recognize TX39 target with "mips*tx39" pattern.
2099         * configure: Rebuilt.
2100         * sim-main.h (*): Added many macros defining bits in
2101         TX39 control registers.
2102         (SignalInterrupt): Send actual PC instead of NULL.
2103         (SignalNMIReset): New exception type.
2104         * interp.c (board): New variable for future use to identify
2105         a particular board being simulated.
2106         (mips_option_handler,mips_options): Added "--board" option.
2107         (interrupt_event): Send actual PC.
2108         (sim_open): Make memory layout conditional on board setting.
2109         (signal_exception): Initial implementation of hardware interrupt
2110         handling.  Accept another break instruction variant for simulator
2111         exit.
2112         (decode_coproc): Implement RFE instruction for TX39.
2113         (mips.igen): Decode RFE instruction as such.
2114         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2115         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2116         bbegin to implement memory map.
2117         * dv-tx3904cpu.c: New file.
2118         * dv-tx3904irc.c: New file.
2119
2120 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
2121
2122         * mips.igen (check_mt_hilo): Create a separate r3900 version.
2123
2124 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
2125
2126         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
2127         with calls to check_div_hilo.
2128
2129 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
2130
2131         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2132         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
2133         Add special r3900 version of do_mult_hilo.
2134         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2135         with calls to check_mult_hilo.
2136         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2137         with calls to check_div_hilo.
2138
2139 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2140
2141         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2142         Document a replacement.
2143
2144 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
2145
2146         * interp.c (sim_monitor): Make mon_printf work.
2147
2148 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
2149
2150         * sim-main.h (INSN_NAME): New arg `cpu'.
2151
2152 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
2153
2154         * configure: Regenerated to track ../common/aclocal.m4 changes.
2155
2156 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
2157
2158         * configure: Regenerated to track ../common/aclocal.m4 changes.
2159         * config.in: Ditto.
2160
2161 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
2162
2163         * acconfig.h: New file.
2164         * configure.in: Reverted change of Apr 24; use sinclude again.
2165
2166 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
2167
2168         * configure: Regenerated to track ../common/aclocal.m4 changes.
2169         * config.in: Ditto.
2170
2171 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
2172
2173         * configure.in: Don't call sinclude.
2174
2175 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
2176
2177         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2178
2179 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2180
2181         * mips.igen (ERET): Implement.
2182
2183         * interp.c (decode_coproc): Return sign-extended EPC.
2184
2185         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2186
2187         * interp.c (signal_exception): Do not ignore Trap.
2188         (signal_exception): On TRAP, restart at exception address.
2189         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2190         (signal_exception): Update.
2191         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2192         so that TRAP instructions are caught.
2193
2194 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2195
2196         * sim-main.h (struct hilo_access, struct hilo_history): Define,
2197         contains HI/LO access history.
2198         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2199         (HIACCESS, LOACCESS): Delete, replace with
2200         (HIHISTORY, LOHISTORY): New macros.
2201         (CHECKHILO): Delete all, moved to mips.igen
2202
2203         * gencode.c (build_instruction): Do not generate checks for
2204         correct HI/LO register usage.
2205
2206         * interp.c (old_engine_run): Delete checks for correct HI/LO
2207         register usage.
2208
2209         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2210         check_mf_cycles): New functions.
2211         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2212         do_divu, domultx, do_mult, do_multu): Use.
2213
2214         * tx.igen ("madd", "maddu"): Use.
2215
2216 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2217
2218         * mips.igen (DSRAV): Use function do_dsrav.
2219         (SRAV): Use new function do_srav.
2220
2221         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2222         (B): Sign extend 11 bit immediate.
2223         (EXT-B*): Shift 16 bit immediate left by 1.
2224         (ADDIU*): Don't sign extend immediate value.
2225
2226 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2227
2228         * m16run.c (sim_engine_run): Restore CIA after handling an event.
2229
2230         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2231         functions.
2232
2233         * mips.igen (delayslot32, nullify_next_insn): New functions.
2234         (m16.igen): Always include.
2235         (do_*): Add more tracing.
2236
2237         * m16.igen (delayslot16): Add NIA argument, could be called by a
2238         32 bit MIPS16 instruction.
2239
2240         * interp.c (ifetch16): Move function from here.
2241         * sim-main.c (ifetch16): To here.
2242
2243         * sim-main.c (ifetch16, ifetch32): Update to match current
2244         implementations of LH, LW.
2245         (signal_exception): Don't print out incorrect hex value of illegal
2246         instruction.
2247
2248 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2249
2250         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2251         instruction.
2252
2253         * m16.igen: Implement MIPS16 instructions.
2254
2255         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2256         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2257         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2258         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2259         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
2260         bodies of corresponding code from 32 bit insn to these.  Also used
2261         by MIPS16 versions of functions.
2262
2263         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2264         (IMEM16): Drop NR argument from macro.
2265
2266 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2267
2268         * Makefile.in (SIM_OBJS): Add sim-main.o.
2269
2270         * sim-main.h (address_translation, load_memory, store_memory,
2271         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2272         as INLINE_SIM_MAIN.
2273         (pr_addr, pr_uword64): Declare.
2274         (sim-main.c): Include when H_REVEALS_MODULE_P.
2275
2276         * interp.c (address_translation, load_memory, store_memory,
2277         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2278         from here.
2279         * sim-main.c: To here. Fix compilation problems.
2280
2281         * configure.in: Enable inlining.
2282         * configure: Re-config.
2283
2284 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2285
2286         * configure: Regenerated to track ../common/aclocal.m4 changes.
2287
2288 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2289
2290         * mips.igen: Include tx.igen.
2291         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2292         * tx.igen: New file, contains MADD and MADDU.
2293
2294         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2295         the hardwired constant `7'.
2296         (store_memory): Ditto.
2297         (LOADDRMASK): Move definition to sim-main.h.
2298
2299         mips.igen (MTC0): Enable for r3900.
2300         (ADDU): Add trace.
2301
2302         mips.igen (do_load_byte): Delete.
2303         (do_load, do_store, do_load_left, do_load_write, do_store_left,
2304         do_store_right): New functions.
2305         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2306
2307         configure.in: Let the tx39 use igen again.
2308         configure: Update.
2309
2310 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2311
2312         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2313         not an address sized quantity.  Return zero for cache sizes.
2314
2315 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2316
2317         * mips.igen (r3900): r3900 does not support 64 bit integer
2318         operations.
2319
2320 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
2321
2322         * configure.in (mipstx39*-*-*): Use gencode simulator rather
2323         than igen one.
2324         * configure : Rebuild.
2325
2326 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2327
2328         * configure: Regenerated to track ../common/aclocal.m4 changes.
2329
2330 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2331
2332         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2333
2334 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
2335
2336         * configure: Regenerated to track ../common/aclocal.m4 changes.
2337         * config.in: Regenerated to track ../common/aclocal.m4 changes.
2338
2339 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2340
2341         * configure: Regenerated to track ../common/aclocal.m4 changes.
2342
2343 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2344
2345         * interp.c (Max, Min): Comment out functions. Not yet used.
2346
2347 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2348
2349         * configure: Regenerated to track ../common/aclocal.m4 changes.
2350
2351 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
2352
2353         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2354         configurable settings for stand-alone simulator.
2355
2356         * configure.in: Added X11 search, just in case.
2357
2358         * configure: Regenerated.
2359
2360 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2361
2362         * interp.c (sim_write, sim_read, load_memory, store_memory):
2363         Replace sim_core_*_map with read_map, write_map, exec_map resp.
2364
2365 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2366
2367         * sim-main.h (GETFCC): Return an unsigned value.
2368
2369 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2370
2371         * mips.igen (DIV): Fix check for -1 / MIN_INT.
2372         (DADD): Result destination is RD not RT.
2373
2374 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2375
2376         * sim-main.h (HIACCESS, LOACCESS): Always define.
2377
2378         * mdmx.igen (Maxi, Mini): Rename Max, Min.
2379
2380         * interp.c (sim_info): Delete.
2381
2382 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
2383
2384         * interp.c (DECLARE_OPTION_HANDLER): Use it.
2385         (mips_option_handler): New argument `cpu'.
2386         (sim_open): Update call to sim_add_option_table.
2387
2388 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2389
2390         * mips.igen (CxC1): Add tracing.
2391
2392 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2393
2394         * sim-main.h (Max, Min): Declare.
2395
2396         * interp.c (Max, Min): New functions.
2397
2398         * mips.igen (BC1): Add tracing.
2399
2400 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
2401
2402         * interp.c Added memory map for stack in vr4100
2403
2404 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
2405
2406         * interp.c (load_memory): Add missing "break"'s.
2407
2408 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2409
2410         * interp.c (sim_store_register, sim_fetch_register): Pass in
2411         length parameter.  Return -1.
2412
2413 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
2414
2415         * interp.c: Added hardware init hook, fixed warnings.
2416
2417 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2418
2419         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2420
2421 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2422
2423         * interp.c (ifetch16): New function.
2424
2425         * sim-main.h (IMEM32): Rename IMEM.
2426         (IMEM16_IMMED): Define.
2427         (IMEM16): Define.
2428         (DELAY_SLOT): Update.
2429
2430         * m16run.c (sim_engine_run): New file.
2431
2432         * m16.igen: All instructions except LB.
2433         (LB): Call do_load_byte.
2434         * mips.igen (do_load_byte): New function.
2435         (LB): Call do_load_byte.
2436
2437         * mips.igen: Move spec for insn bit size and high bit from here.
2438         * Makefile.in (tmp-igen, tmp-m16): To here.
2439
2440         * m16.dc: New file, decode mips16 instructions.
2441
2442         * Makefile.in (SIM_NO_ALL): Define.
2443         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2444
2445 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2446
2447         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2448         point unit to 32 bit registers.
2449         * configure: Re-generate.
2450
2451 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2452
2453         * configure.in (sim_use_gen): Make IGEN the default simulator
2454         generator for generic 32 and 64 bit mips targets.
2455         * configure: Re-generate.
2456
2457 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2458
2459         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2460         bitsize.
2461
2462         * interp.c (sim_fetch_register, sim_store_register): Read/write
2463         FGR from correct location.
2464         (sim_open): Set size of FGR's according to
2465         WITH_TARGET_FLOATING_POINT_BITSIZE.
2466
2467         * sim-main.h (FGR): Store floating point registers in a separate
2468         array.
2469
2470 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2471
2472         * configure: Regenerated to track ../common/aclocal.m4 changes.
2473
2474 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2475
2476         * interp.c (ColdReset): Call PENDING_INVALIDATE.
2477
2478         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2479
2480         * interp.c (pending_tick): New function.  Deliver pending writes.
2481
2482         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2483         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2484         it can handle mixed sized quantites and single bits.
2485
2486 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2487
2488         * interp.c (oengine.h): Do not include when building with IGEN.
2489         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2490         (sim_info): Ditto for PROCESSOR_64BIT.
2491         (sim_monitor): Replace ut_reg with unsigned_word.
2492         (*): Ditto for t_reg.
2493         (LOADDRMASK): Define.
2494         (sim_open): Remove defunct check that host FP is IEEE compliant,
2495         using software to emulate floating point.
2496         (value_fpr, ...): Always compile, was conditional on HASFPU.
2497
2498 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2499
2500         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2501         size.
2502
2503         * interp.c (SD, CPU): Define.
2504         (mips_option_handler): Set flags in each CPU.
2505         (interrupt_event): Assume CPU 0 is the one being iterrupted.
2506         (sim_close): Do not clear STATE, deleted anyway.
2507         (sim_write, sim_read): Assume CPU zero's vm should be used for
2508         data transfers.
2509         (sim_create_inferior): Set the PC for all processors.
2510         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2511         argument.
2512         (mips16_entry): Pass correct nr of args to store_word, load_word.
2513         (ColdReset): Cold reset all cpu's.
2514         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2515         (sim_monitor, load_memory, store_memory, signal_exception): Use
2516         `CPU' instead of STATE_CPU.
2517
2518
2519         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2520         SD or CPU_.
2521
2522         * sim-main.h (signal_exception): Add sim_cpu arg.
2523         (SignalException*): Pass both SD and CPU to signal_exception.
2524         * interp.c (signal_exception): Update.
2525
2526         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2527         Ditto
2528         (sync_operation, prefetch, cache_op, store_memory, load_memory,
2529         address_translation): Ditto
2530         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2531
2532 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2533
2534         * configure: Regenerated to track ../common/aclocal.m4 changes.
2535
2536 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2537
2538         * interp.c (sim_engine_run): Add `nr_cpus' argument.
2539
2540         * mips.igen (model): Map processor names onto BFD name.
2541
2542         * sim-main.h (CPU_CIA): Delete.
2543         (SET_CIA, GET_CIA): Define
2544
2545 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2546
2547         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2548         regiser.
2549
2550         * configure.in (default_endian): Configure a big-endian simulator
2551         by default.
2552         * configure: Re-generate.
2553
2554 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
2555
2556         * configure: Regenerated to track ../common/aclocal.m4 changes.
2557
2558 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
2559
2560         * interp.c (sim_monitor): Handle Densan monitor outbyte
2561         and inbyte functions.
2562
2563 1997-12-29  Felix Lee  <flee@cygnus.com>
2564
2565         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2566
2567 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
2568
2569         * Makefile.in (tmp-igen): Arrange for $zero to always be
2570         reset to zero after every instruction.
2571
2572 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2573
2574         * configure: Regenerated to track ../common/aclocal.m4 changes.
2575         * config.in: Ditto.
2576
2577 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
2578
2579         * mips.igen (MSUB): Fix to work like MADD.
2580         * gencode.c (MSUB): Similarly.
2581
2582 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
2583
2584         * configure: Regenerated to track ../common/aclocal.m4 changes.
2585
2586 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2587
2588         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2589
2590 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2591
2592         * sim-main.h (sim-fpu.h): Include.
2593
2594         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2595         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2596         using host independant sim_fpu module.
2597
2598 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2599
2600         * interp.c (signal_exception): Report internal errors with SIGABRT
2601         not SIGQUIT.
2602
2603         * sim-main.h (C0_CONFIG): New register.
2604         (signal.h): No longer include.
2605
2606         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2607
2608 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
2609
2610         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2611
2612 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2613
2614         * mips.igen: Tag vr5000 instructions.
2615         (ANDI): Was missing mipsIV model, fix assembler syntax.
2616         (do_c_cond_fmt): New function.
2617         (C.cond.fmt): Handle mips I-III which do not support CC field
2618         separatly.
2619         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2620         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2621         in IV3.2 spec.
2622         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2623         vr5000 which saves LO in a GPR separatly.
2624
2625         * configure.in (enable-sim-igen): For vr5000, select vr5000
2626         specific instructions.
2627         * configure: Re-generate.
2628
2629 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2630
2631         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2632
2633         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2634         fmt_uninterpreted_64 bit cases to switch.  Convert to
2635         fmt_formatted,
2636
2637         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2638
2639         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2640         as specified in IV3.2 spec.
2641         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2642
2643 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2644
2645         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2646         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2647         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2648         PENDING_FILL versions of instructions.  Simplify.
2649         (X): New function.
2650         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2651         instructions.
2652         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2653         a signed value.
2654         (MTHI, MFHI): Disable code checking HI-LO.
2655
2656         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2657         global.
2658         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2659
2660 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2661
2662         * gencode.c (build_mips16_operands): Replace IPC with cia.
2663
2664         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2665         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2666         IPC to `cia'.
2667         (UndefinedResult): Replace function with macro/function
2668         combination.
2669         (sim_engine_run): Don't save PC in IPC.
2670
2671         * sim-main.h (IPC): Delete.
2672
2673
2674         * interp.c (signal_exception, store_word, load_word,
2675         address_translation, load_memory, store_memory, cache_op,
2676         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2677         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2678         current instruction address - cia - argument.
2679         (sim_read, sim_write): Call address_translation directly.
2680         (sim_engine_run): Rename variable vaddr to cia.
2681         (signal_exception): Pass cia to sim_monitor
2682
2683         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2684         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2685         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2686
2687         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2688         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2689         SIM_ASSERT.
2690
2691         * interp.c (signal_exception): Pass restart address to
2692         sim_engine_restart.
2693
2694         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2695         idecode.o): Add dependency.
2696
2697         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2698         Delete definitions
2699         (DELAY_SLOT): Update NIA not PC with branch address.
2700         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2701
2702         * mips.igen: Use CIA not PC in branch calculations.
2703         (illegal): Call SignalException.
2704         (BEQ, ADDIU): Fix assembler.
2705
2706 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2707
2708         * m16.igen (JALX): Was missing.
2709
2710         * configure.in (enable-sim-igen): New configuration option.
2711         * configure: Re-generate.
2712
2713         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2714
2715         * interp.c (load_memory, store_memory): Delete parameter RAW.
2716         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2717         bypassing {load,store}_memory.
2718
2719         * sim-main.h (ByteSwapMem): Delete definition.
2720
2721         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2722
2723         * interp.c (sim_do_command, sim_commands): Delete mips specific
2724         commands.  Handled by module sim-options.
2725
2726         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2727         (WITH_MODULO_MEMORY): Define.
2728
2729         * interp.c (sim_info): Delete code printing memory size.
2730
2731         * interp.c (mips_size): Nee sim_size, delete function.
2732         (power2): Delete.
2733         (monitor, monitor_base, monitor_size): Delete global variables.
2734         (sim_open, sim_close): Delete code creating monitor and other
2735         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2736         manage memory regions.
2737         (load_memory, store_memory): Use sim-core for memory model.
2738
2739         * interp.c (address_translation): Delete all memory map code
2740         except line forcing 32 bit addresses.
2741
2742 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2743
2744         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2745         trace options.
2746
2747         * interp.c (logfh, logfile): Delete globals.
2748         (sim_open, sim_close): Delete code opening & closing log file.
2749         (mips_option_handler): Delete -l and -n options.
2750         (OPTION mips_options): Ditto.
2751
2752         * interp.c (OPTION mips_options): Rename option trace to dinero.
2753         (mips_option_handler): Update.
2754
2755 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2756
2757         * interp.c (fetch_str): New function.
2758         (sim_monitor): Rewrite using sim_read & sim_write.
2759         (sim_open): Check magic number.
2760         (sim_open): Write monitor vectors into memory using sim_write.
2761         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2762         (sim_read, sim_write): Simplify - transfer data one byte at a
2763         time.
2764         (load_memory, store_memory): Clarify meaning of parameter RAW.
2765
2766         * sim-main.h (isHOST): Defete definition.
2767         (isTARGET): Mark as depreciated.
2768         (address_translation): Delete parameter HOST.
2769
2770         * interp.c (address_translation): Delete parameter HOST.
2771
2772 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2773
2774         * mips.igen:
2775
2776         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2777         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2778
2779 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2780
2781         * mips.igen: Add model filter field to records.
2782
2783 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2784
2785         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2786
2787         interp.c (sim_engine_run): Do not compile function sim_engine_run
2788         when WITH_IGEN == 1.
2789
2790         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2791         target architecture.
2792
2793         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2794         igen. Replace with configuration variables sim_igen_flags /
2795         sim_m16_flags.
2796
2797         * m16.igen: New file.  Copy mips16 insns here.
2798         * mips.igen: From here.
2799
2800 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2801
2802         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2803         to top.
2804         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2805
2806 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2807
2808         * gencode.c (build_instruction): Follow sim_write's lead in using
2809         BigEndianMem instead of !ByteSwapMem.
2810
2811 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2812
2813         * configure.in (sim_gen): Dependent on target, select type of
2814         generator.  Always select old style generator.
2815
2816         configure: Re-generate.
2817
2818         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2819         targets.
2820         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2821         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2822         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2823         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2824         SIM_@sim_gen@_*, set by autoconf.
2825
2826 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2827
2828         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2829
2830         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2831         CURRENT_FLOATING_POINT instead.
2832
2833         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2834         (address_translation): Raise exception InstructionFetch when
2835         translation fails and isINSTRUCTION.
2836
2837         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2838         sim_engine_run): Change type of of vaddr and paddr to
2839         address_word.
2840         (address_translation, prefetch, load_memory, store_memory,
2841         cache_op): Change type of vAddr and pAddr to address_word.
2842
2843         * gencode.c (build_instruction): Change type of vaddr and paddr to
2844         address_word.
2845
2846 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2847
2848         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2849         macro to obtain result of ALU op.
2850
2851 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2852
2853         * interp.c (sim_info): Call profile_print.
2854
2855 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2856
2857         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2858
2859         * sim-main.h (WITH_PROFILE): Do not define, defined in
2860         common/sim-config.h.  Use sim-profile module.
2861         (simPROFILE): Delete defintion.
2862
2863         * interp.c (PROFILE): Delete definition.
2864         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2865         (sim_close): Delete code writing profile histogram.
2866         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2867         Delete.
2868         (sim_engine_run): Delete code profiling the PC.
2869
2870 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2871
2872         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2873
2874         * interp.c (sim_monitor): Make register pointers of type
2875         unsigned_word*.
2876
2877         * sim-main.h: Make registers of type unsigned_word not
2878         signed_word.
2879
2880 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2881
2882         * interp.c (sync_operation): Rename from SyncOperation, make
2883         global, add SD argument.
2884         (prefetch): Rename from Prefetch, make global, add SD argument.
2885         (decode_coproc): Make global.
2886
2887         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2888
2889         * gencode.c (build_instruction): Generate DecodeCoproc not
2890         decode_coproc calls.
2891
2892         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2893         (SizeFGR): Move to sim-main.h
2894         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2895         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2896         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2897         sim-main.h.
2898         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2899         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2900         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2901         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2902         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2903         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2904
2905         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2906         exception.
2907         (sim-alu.h): Include.
2908         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2909         (sim_cia): Typedef to instruction_address.
2910
2911 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2912
2913         * Makefile.in (interp.o): Rename generated file engine.c to
2914         oengine.c.
2915
2916         * interp.c: Update.
2917
2918 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2919
2920         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2921
2922 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2923
2924         * gencode.c (build_instruction): For "FPSQRT", output correct
2925         number of arguments to Recip.
2926
2927 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2928
2929         * Makefile.in (interp.o): Depends on sim-main.h
2930
2931         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2932
2933         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2934         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2935         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2936         STATE, DSSTATE): Define
2937         (GPR, FGRIDX, ..): Define.
2938
2939         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2940         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2941         (GPR, FGRIDX, ...): Delete macros.
2942
2943         * interp.c: Update names to match defines from sim-main.h
2944
2945 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2946
2947         * interp.c (sim_monitor): Add SD argument.
2948         (sim_warning): Delete.  Replace calls with calls to
2949         sim_io_eprintf.
2950         (sim_error): Delete. Replace calls with sim_io_error.
2951         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2952         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2953         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2954         argument.
2955         (mips_size): Rename from sim_size. Add SD argument.
2956
2957         * interp.c (simulator): Delete global variable.
2958         (callback): Delete global variable.
2959         (mips_option_handler, sim_open, sim_write, sim_read,
2960         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2961         sim_size,sim_monitor): Use sim_io_* not callback->*.
2962         (sim_open): ZALLOC simulator struct.
2963         (PROFILE): Do not define.
2964
2965 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2966
2967         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2968         support.h with corresponding code.
2969
2970         * sim-main.h (word64, uword64), support.h: Move definition to
2971         sim-main.h.
2972         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2973
2974         * support.h: Delete
2975         * Makefile.in: Update dependencies
2976         * interp.c: Do not include.
2977
2978 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2979
2980         * interp.c (address_translation, load_memory, store_memory,
2981         cache_op): Rename to from AddressTranslation et.al., make global,
2982         add SD argument
2983
2984         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2985         CacheOp): Define.
2986
2987         * interp.c (SignalException): Rename to signal_exception, make
2988         global.
2989
2990         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2991
2992         * sim-main.h (SignalException, SignalExceptionInterrupt,
2993         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2994         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2995         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2996         Define.
2997
2998         * interp.c, support.h: Use.
2999
3000 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3001
3002         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3003         to value_fpr / store_fpr. Add SD argument.
3004         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3005         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3006
3007         * sim-main.h (ValueFPR, StoreFPR): Define.
3008
3009 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3010
3011         * interp.c (sim_engine_run): Check consistency between configure
3012         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3013         and HASFPU.
3014
3015         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
3016         (mips_fpu): Configure WITH_FLOATING_POINT.
3017         (mips_endian): Configure WITH_TARGET_ENDIAN.
3018         * configure: Update.
3019
3020 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3021
3022         * configure: Regenerated to track ../common/aclocal.m4 changes.
3023
3024 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
3025
3026         * configure: Regenerated.
3027
3028 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
3029
3030         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3031
3032 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3033
3034         * gencode.c (print_igen_insn_models): Assume certain architectures
3035         include all mips* instructions.
3036         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3037         instruction.
3038
3039         * Makefile.in (tmp.igen): Add target. Generate igen input from
3040         gencode file.
3041
3042         * gencode.c (FEATURE_IGEN): Define.
3043         (main): Add --igen option.  Generate output in igen format.
3044         (process_instructions): Format output according to igen option.
3045         (print_igen_insn_format): New function.
3046         (print_igen_insn_models): New function.
3047         (process_instructions): Only issue warnings and ignore
3048         instructions when no FEATURE_IGEN.
3049
3050 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3051
3052         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3053         MIPS targets.
3054
3055 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3056
3057         * configure: Regenerated to track ../common/aclocal.m4 changes.
3058
3059 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3060
3061         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3062         SIM_RESERVED_BITS): Delete, moved to common.
3063         (SIM_EXTRA_CFLAGS): Update.
3064
3065 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3066
3067         * configure.in: Configure non-strict memory alignment.
3068         * configure: Regenerated to track ../common/aclocal.m4 changes.
3069
3070 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3071
3072         * configure: Regenerated to track ../common/aclocal.m4 changes.
3073
3074 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
3075
3076         * gencode.c (SDBBP,DERET): Added (3900) insns.
3077         (RFE): Turn on for 3900.
3078         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3079         (dsstate): Made global.
3080         (SUBTARGET_R3900): Added.
3081         (CANCELDELAYSLOT): New.
3082         (SignalException): Ignore SystemCall rather than ignore and
3083         terminate.  Add DebugBreakPoint handling.
3084         (decode_coproc): New insns RFE, DERET; and new registers Debug
3085         and DEPC protected by SUBTARGET_R3900.
3086         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3087         bits explicitly.
3088         * Makefile.in,configure.in: Add mips subtarget option.
3089         * configure: Update.
3090
3091 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
3092
3093         * gencode.c: Add r3900 (tx39).
3094
3095
3096 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
3097
3098         * gencode.c (build_instruction): Don't need to subtract 4 for
3099         JALR, just 2.
3100
3101 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
3102
3103         * interp.c: Correct some HASFPU problems.
3104
3105 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3106
3107         * configure: Regenerated to track ../common/aclocal.m4 changes.
3108
3109 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3110
3111         * interp.c (mips_options): Fix samples option short form, should
3112         be `x'.
3113
3114 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3115
3116         * interp.c (sim_info): Enable info code.  Was just returning.
3117
3118 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3119
3120         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3121         MFC0.
3122
3123 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3124
3125         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3126         constants.
3127         (build_instruction): Ditto for LL.
3128
3129 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
3130
3131         * configure: Regenerated to track ../common/aclocal.m4 changes.
3132
3133 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3134
3135         * configure: Regenerated to track ../common/aclocal.m4 changes.
3136         * config.in: Ditto.
3137
3138 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3139
3140         * interp.c (sim_open): Add call to sim_analyze_program, update
3141         call to sim_config.
3142
3143 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3144
3145         * interp.c (sim_kill): Delete.
3146         (sim_create_inferior): Add ABFD argument. Set PC from same.
3147         (sim_load): Move code initializing trap handlers from here.
3148         (sim_open): To here.
3149         (sim_load): Delete, use sim-hload.c.
3150
3151         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3152
3153 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3154
3155         * configure: Regenerated to track ../common/aclocal.m4 changes.
3156         * config.in: Ditto.
3157
3158 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3159
3160         * interp.c (sim_open): Add ABFD argument.
3161         (sim_load): Move call to sim_config from here.
3162         (sim_open): To here.  Check return status.
3163
3164 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
3165
3166         * gencode.c (build_instruction): Two arg MADD should
3167         not assign result to $0.
3168
3169 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
3170
3171         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3172         * sim/mips/configure.in: Regenerate.
3173
3174 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
3175
3176         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3177         signed8, unsigned8 et.al. types.
3178
3179         * interp.c (SUB_REG_FETCH): Handle both little and big endian
3180         hosts when selecting subreg.
3181
3182 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
3183
3184         * interp.c (sim_engine_run): Reset the ZERO register to zero
3185         regardless of FEATURE_WARN_ZERO.
3186         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3187
3188 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3189
3190         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3191         (SignalException): For BreakPoints ignore any mode bits and just
3192         save the PC.
3193         (SignalException): Always set the CAUSE register.
3194
3195 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3196
3197         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3198         exception has been taken.
3199
3200         * interp.c: Implement the ERET and mt/f sr instructions.
3201
3202 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3203
3204         * interp.c (SignalException): Don't bother restarting an
3205         interrupt.
3206
3207 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3208
3209         * interp.c (SignalException): Really take an interrupt.
3210         (interrupt_event): Only deliver interrupts when enabled.
3211
3212 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3213
3214         * interp.c (sim_info): Only print info when verbose.
3215         (sim_info) Use sim_io_printf for output.
3216
3217 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3218
3219         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3220         mips architectures.
3221
3222 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3223
3224         * interp.c (sim_do_command): Check for common commands if a
3225         simulator specific command fails.
3226
3227 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
3228
3229         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3230         and simBE when DEBUG is defined.
3231
3232 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3233
3234         * interp.c (interrupt_event): New function.  Pass exception event
3235         onto exception handler.
3236
3237         * configure.in: Check for stdlib.h.
3238         * configure: Regenerate.
3239
3240         * gencode.c (build_instruction): Add UNUSED attribute to tempS
3241         variable declaration.
3242         (build_instruction): Initialize memval1.
3243         (build_instruction): Add UNUSED attribute to byte, bigend,
3244         reverse.
3245         (build_operands): Ditto.
3246
3247         * interp.c: Fix GCC warnings.
3248         (sim_get_quit_code): Delete.
3249
3250         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3251         * Makefile.in: Ditto.
3252         * configure: Re-generate.
3253
3254         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3255
3256 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3257
3258         * interp.c (mips_option_handler): New function parse argumes using
3259         sim-options.
3260         (myname): Replace with STATE_MY_NAME.
3261         (sim_open): Delete check for host endianness - performed by
3262         sim_config.
3263         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3264         (sim_open): Move much of the initialization from here.
3265         (sim_load): To here.  After the image has been loaded and
3266         endianness set.
3267         (sim_open): Move ColdReset from here.
3268         (sim_create_inferior): To here.
3269         (sim_open): Make FP check less dependant on host endianness.
3270
3271         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3272         run.
3273         * interp.c (sim_set_callbacks): Delete.
3274
3275         * interp.c (membank, membank_base, membank_size): Replace with
3276         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3277         (sim_open): Remove call to callback->init. gdb/run do this.
3278
3279         * interp.c: Update
3280
3281         * sim-main.h (SIM_HAVE_FLATMEM): Define.
3282
3283         * interp.c (big_endian_p): Delete, replaced by
3284         current_target_byte_order.
3285
3286 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3287
3288         * interp.c (host_read_long, host_read_word, host_swap_word,
3289         host_swap_long): Delete. Using common sim-endian.
3290         (sim_fetch_register, sim_store_register): Use H2T.
3291         (pipeline_ticks): Delete.  Handled by sim-events.
3292         (sim_info): Update.
3293         (sim_engine_run): Update.
3294
3295 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3296
3297         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3298         reason from here.
3299         (SignalException): To here. Signal using sim_engine_halt.
3300         (sim_stop_reason): Delete, moved to common.
3301
3302 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
3303
3304         * interp.c (sim_open): Add callback argument.
3305         (sim_set_callbacks): Delete SIM_DESC argument.
3306         (sim_size): Ditto.
3307
3308 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3309
3310         * Makefile.in (SIM_OBJS): Add common modules.
3311
3312         * interp.c (sim_set_callbacks): Also set SD callback.
3313         (set_endianness, xfer_*, swap_*): Delete.
3314         (host_read_word, host_read_long, host_swap_word, host_swap_long):
3315         Change to functions using sim-endian macros.
3316         (control_c, sim_stop): Delete, use common version.
3317         (simulate): Convert into.
3318         (sim_engine_run): This function.
3319         (sim_resume): Delete.
3320
3321         * interp.c (simulation): New variable - the simulator object.
3322         (sim_kind): Delete global - merged into simulation.
3323         (sim_load): Cleanup.  Move PC assignment from here.
3324         (sim_create_inferior): To here.
3325
3326         * sim-main.h: New file.
3327         * interp.c (sim-main.h): Include.
3328
3329 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
3330
3331         * configure: Regenerated to track ../common/aclocal.m4 changes.
3332
3333 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
3334
3335         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3336
3337 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
3338
3339         * gencode.c (build_instruction): DIV instructions: check
3340         for division by zero and integer overflow before using
3341         host's division operation.
3342
3343 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
3344
3345         * Makefile.in (SIM_OBJS): Add sim-load.o.
3346         * interp.c: #include bfd.h.
3347         (target_byte_order): Delete.
3348         (sim_kind, myname, big_endian_p): New static locals.
3349         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
3350         after argument parsing.  Recognize -E arg, set endianness accordingly.
3351         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
3352         load file into simulator.  Set PC from bfd.
3353         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
3354         (set_endianness): Use big_endian_p instead of target_byte_order.
3355
3356 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
3357
3358         * interp.c (sim_size): Delete prototype - conflicts with
3359         definition in remote-sim.h.  Correct definition.
3360
3361 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3362
3363         * configure: Regenerated to track ../common/aclocal.m4 changes.
3364         * config.in: Ditto.
3365
3366 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
3367
3368         * interp.c (sim_open): New arg `kind'.
3369
3370         * configure: Regenerated to track ../common/aclocal.m4 changes.
3371
3372 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3373
3374         * configure: Regenerated to track ../common/aclocal.m4 changes.
3375
3376 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
3377
3378         * interp.c (sim_open): Set optind to 0 before calling getopt.
3379
3380 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3381
3382         * configure: Regenerated to track ../common/aclocal.m4 changes.
3383
3384 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
3385
3386         * interp.c : Replace uses of pr_addr with pr_uword64
3387         where the bit length is always 64 independent of SIM_ADDR.
3388         (pr_uword64) : added.
3389
3390 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3391
3392         * configure: Re-generate.
3393
3394 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
3395
3396         * configure: Regenerate to track ../common/aclocal.m4 changes.
3397
3398 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
3399
3400         * interp.c (sim_open): New SIM_DESC result.  Argument is now
3401         in argv form.
3402         (other sim_*): New SIM_DESC argument.
3403
3404 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
3405
3406         * interp.c: Fix printing of addresses for non-64-bit targets.
3407         (pr_addr): Add function to print address based on size.
3408
3409 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
3410
3411         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3412
3413 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
3414
3415         * gencode.c (build_mips16_operands): Correct computation of base
3416         address for extended PC relative instruction.
3417
3418 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
3419
3420         * interp.c (mips16_entry): Add support for floating point cases.
3421         (SignalException): Pass floating point cases to mips16_entry.
3422         (ValueFPR): Don't restrict fmt_single and fmt_word to even
3423         registers.
3424         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
3425         or fmt_word.
3426         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3427         and then set the state to fmt_uninterpreted.
3428         (COP_SW): Temporarily set the state to fmt_word while calling
3429         ValueFPR.
3430
3431 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
3432
3433         * gencode.c (build_instruction): The high order may be set in the
3434         comparison flags at any ISA level, not just ISA 4.
3435
3436 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
3437
3438         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3439         COMMON_{PRE,POST}_CONFIG_FRAG instead.
3440         * configure.in: sinclude ../common/aclocal.m4.
3441         * configure: Regenerated.
3442
3443 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
3444
3445         * configure: Rebuild after change to aclocal.m4.
3446
3447 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
3448
3449         * configure configure.in Makefile.in:  Update to new configure
3450         scheme which is more compatible with WinGDB builds.
3451         * configure.in:  Improve comment on how to run autoconf.
3452         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
3453         * Makefile.in:  Use autoconf substitution to install common
3454         makefile fragment.
3455
3456 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
3457
3458         * gencode.c (build_instruction): Use BigEndianCPU instead of
3459         ByteSwapMem.
3460
3461 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
3462
3463         * interp.c (sim_monitor): Make output to stdout visible in
3464         wingdb's I/O log window.
3465
3466 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
3467
3468         * support.h: Undo previous change to SIGTRAP
3469         and SIGQUIT values.
3470
3471 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
3472
3473         * interp.c (store_word, load_word): New static functions.
3474         (mips16_entry): New static function.
3475         (SignalException): Look for mips16 entry and exit instructions.
3476         (simulate): Use the correct index when setting fpr_state after
3477         doing a pending move.
3478
3479 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
3480
3481         * interp.c: Fix byte-swapping code throughout to work on
3482         both little- and big-endian hosts.
3483
3484 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
3485
3486         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3487         with gdb/config/i386/xm-windows.h.
3488
3489 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
3490
3491         * gencode.c (build_instruction): Work around MSVC++ code gen bug
3492         that messes up arithmetic shifts.
3493
3494 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
3495
3496         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
3497         SIGTRAP and SIGQUIT for _WIN32.
3498
3499 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
3500
3501         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3502         force a 64 bit multiplication.
3503         (build_instruction) [OR]: In mips16 mode, don't do anything if the
3504         destination register is 0, since that is the default mips16 nop
3505         instruction.
3506
3507 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
3508
3509         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3510         (build_endian_shift): Don't check proc64.
3511         (build_instruction): Always set memval to uword64.  Cast op2 to
3512         uword64 when shifting it left in memory instructions.  Always use
3513         the same code for stores--don't special case proc64.
3514
3515         * gencode.c (build_mips16_operands): Fix base PC value for PC
3516         relative operands.
3517         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3518         jal instruction.
3519         * interp.c (simJALDELAYSLOT): Define.
3520         (JALDELAYSLOT): Define.
3521         (INDELAYSLOT, INJALDELAYSLOT): Define.
3522         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3523
3524 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
3525
3526         * interp.c (sim_open): add flush_cache as a PMON routine
3527         (sim_monitor): handle flush_cache by ignoring it
3528
3529 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
3530
3531         * gencode.c (build_instruction): Use !ByteSwapMem instead of
3532         BigEndianMem.
3533         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3534         (BigEndianMem): Rename to ByteSwapMem and change sense.
3535         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3536         BigEndianMem references to !ByteSwapMem.
3537         (set_endianness): New function, with prototype.
3538         (sim_open): Call set_endianness.
3539         (sim_info): Use simBE instead of BigEndianMem.
3540         (xfer_direct_word, xfer_direct_long, swap_direct_word,
3541         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3542         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3543         ifdefs, keeping the prototype declaration.
3544         (swap_word): Rewrite correctly.
3545         (ColdReset): Delete references to CONFIG.  Delete endianness related
3546         code; moved to set_endianness.
3547
3548 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
3549
3550         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3551         * interp.c (CHECKHILO): Define away.
3552         (simSIGINT): New macro.
3553         (membank_size): Increase from 1MB to 2MB.
3554         (control_c): New function.
3555         (sim_resume): Rename parameter signal to signal_number.  Add local
3556         variable prev.  Call signal before and after simulate.
3557         (sim_stop_reason): Add simSIGINT support.
3558         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3559         functions always.
3560         (sim_warning): Delete call to SignalException.  Do call printf_filtered
3561         if logfh is NULL.
3562         (AddressTranslation): Add #ifdef DEBUG around debugging message and
3563         a call to sim_warning.
3564
3565 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
3566
3567         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3568         16 bit instructions.
3569
3570 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3571
3572         Add support for mips16 (16 bit MIPS implementation):
3573         * gencode.c (inst_type): Add mips16 instruction encoding types.
3574         (GETDATASIZEINSN): Define.
3575         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
3576         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
3577         mtlo.
3578         (MIPS16_DECODE): New table, for mips16 instructions.
3579         (bitmap_val): New static function.
3580         (struct mips16_op): Define.
3581         (mips16_op_table): New table, for mips16 operands.
3582         (build_mips16_operands): New static function.
3583         (process_instructions): If PC is odd, decode a mips16
3584         instruction.  Break out instruction handling into new
3585         build_instruction function.
3586         (build_instruction): New static function, broken out of
3587         process_instructions.  Check modifiers rather than flags for SHIFT
3588         bit count and m[ft]{hi,lo} direction.
3589         (usage): Pass program name to fprintf.
3590         (main): Remove unused variable this_option_optind.  Change
3591         ``*loptarg++'' to ``loptarg++''.
3592         (my_strtoul): Parenthesize && within ||.
3593         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3594         (simulate): If PC is odd, fetch a 16 bit instruction, and
3595         increment PC by 2 rather than 4.
3596         * configure.in: Add case for mips16*-*-*.
3597         * configure: Rebuild.
3598
3599 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
3600
3601         * interp.c: Allow -t to enable tracing in standalone simulator.
3602         Fix garbage output in trace file and error messages.
3603
3604 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
3605
3606         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3607         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3608         * configure.in: Simplify using macros in ../common/aclocal.m4.
3609         * configure: Regenerated.
3610         * tconfig.in: New file.
3611
3612 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3613
3614         * interp.c: Fix bugs in 64-bit port.
3615         Use ansi function declarations for msvc compiler.
3616         Initialize and test file pointer in trace code.
3617         Prevent duplicate definition of LAST_EMED_REGNUM.
3618
3619 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3620
3621         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3622
3623 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3624
3625         * interp.c (SignalException): Check for explicit terminating
3626         breakpoint value.
3627         * gencode.c: Pass instruction value through SignalException()
3628         calls for Trap, Breakpoint and Syscall.
3629
3630 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3631
3632         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3633         only used on those hosts that provide it.
3634         * configure.in: Add sqrt() to list of functions to be checked for.
3635         * config.in: Re-generated.
3636         * configure: Re-generated.
3637
3638 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3639
3640         * gencode.c (process_instructions): Call build_endian_shift when
3641         expanding STORE RIGHT, to fix swr.
3642         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3643         clear the high bits.
3644         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3645         Fix float to int conversions to produce signed values.
3646
3647 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3648
3649         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3650         (process_instructions): Correct handling of nor instruction.
3651         Correct shift count for 32 bit shift instructions. Correct sign
3652         extension for arithmetic shifts to not shift the number of bits in
3653         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3654         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3655         Fix madd.
3656         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3657         It's OK to have a mult follow a mult.  What's not OK is to have a
3658         mult follow an mfhi.
3659         (Convert): Comment out incorrect rounding code.
3660
3661 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3662
3663         * interp.c (sim_monitor): Improved monitor printf
3664         simulation. Tidied up simulator warnings, and added "--log" option
3665         for directing warning message output.
3666         * gencode.c: Use sim_warning() rather than WARNING macro.
3667
3668 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3669
3670         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3671         getopt1.o, rather than on gencode.c.  Link objects together.
3672         Don't link against -liberty.
3673         (gencode.o, getopt.o, getopt1.o): New targets.
3674         * gencode.c: Include <ctype.h> and "ansidecl.h".
3675         (AND): Undefine after including "ansidecl.h".
3676         (ULONG_MAX): Define if not defined.
3677         (OP_*): Don't define macros; now defined in opcode/mips.h.
3678         (main): Call my_strtoul rather than strtoul.
3679         (my_strtoul): New static function.
3680
3681 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3682
3683         * gencode.c (process_instructions):  Generate word64 and uword64
3684         instead of `long long' and `unsigned long long' data types.
3685         * interp.c:  #include sysdep.h to get signals, and define default
3686         for SIGBUS.
3687         * (Convert):  Work around for Visual-C++ compiler bug with type
3688         conversion.
3689         * support.h:  Make things compile under Visual-C++ by using
3690         __int64 instead of `long long'.  Change many refs to long long
3691         into word64/uword64 typedefs.
3692
3693 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3694
3695         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3696         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3697         (docdir): Removed.
3698         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3699         (AC_PROG_INSTALL): Added.
3700         (AC_PROG_CC): Moved to before configure.host call.
3701         * configure: Rebuilt.
3702
3703 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3704
3705         * configure.in: Define @SIMCONF@ depending on mips target.
3706         * configure: Rebuild.
3707         * Makefile.in (run): Add @SIMCONF@ to control simulator
3708         construction.
3709         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3710         * interp.c: Remove some debugging, provide more detailed error
3711         messages, update memory accesses to use LOADDRMASK.
3712
3713 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3714
3715         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3716         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3717         stamp-h.
3718         * configure: Rebuild.
3719         * config.in: New file, generated by autoheader.
3720         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3721         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3722         HAVE_ANINT and HAVE_AINT, as appropriate.
3723         * Makefile.in (run): Use @LIBS@ rather than -lm.
3724         (interp.o): Depend upon config.h.
3725         (Makefile): Just rebuild Makefile.
3726         (clean): Remove stamp-h.
3727         (mostlyclean): Make the same as clean, not as distclean.
3728         (config.h, stamp-h): New targets.
3729
3730 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3731
3732         * interp.c (ColdReset): Fix boolean test. Make all simulator
3733         globals static.
3734
3735 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3736
3737         * interp.c (xfer_direct_word, xfer_direct_long,
3738         swap_direct_word, swap_direct_long, xfer_big_word,
3739         xfer_big_long, xfer_little_word, xfer_little_long,
3740         swap_word,swap_long): Added.
3741         * interp.c (ColdReset): Provide function indirection to
3742         host<->simulated_target transfer routines.
3743         * interp.c (sim_store_register, sim_fetch_register): Updated to
3744         make use of indirected transfer routines.
3745
3746 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3747
3748         * gencode.c (process_instructions): Ensure FP ABS instruction
3749         recognised.
3750         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3751         system call support.
3752
3753 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3754
3755         * interp.c (sim_do_command): Complain if callback structure not
3756         initialised.
3757
3758 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3759
3760         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3761         support for Sun hosts.
3762         * Makefile.in (gencode): Ensure the host compiler and libraries
3763         used for cross-hosted build.
3764
3765 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3766
3767         * interp.c, gencode.c: Some more (TODO) tidying.
3768
3769 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3770
3771         * gencode.c, interp.c: Replaced explicit long long references with
3772         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3773         * support.h (SET64LO, SET64HI): Macros added.
3774
3775 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3776
3777         * configure: Regenerate with autoconf 2.7.
3778
3779 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3780
3781         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3782         * support.h: Remove superfluous "1" from #if.
3783         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3784
3785 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3786
3787         * interp.c (StoreFPR): Control UndefinedResult() call on
3788         WARN_RESULT manifest.
3789
3790 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3791
3792         * gencode.c: Tidied instruction decoding, and added FP instruction
3793         support.
3794
3795         * interp.c: Added dineroIII, and BSD profiling support. Also
3796         run-time FP handling.
3797
3798 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3799
3800         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3801         gencode.c, interp.c, support.h: created.