sim/mips/ChangeLog

   1 2006-04-18  Nick Clifton  <nickc@redhat.com>
   2
   3         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
   4         statement.
   5
   6 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
   7
   8         * configure: Regenerate.
   9
  10 2005-12-14  Chao-ying Fu  <fu@mips.com>
  11
  12         * Makefile.in (SIM_OBJS): Add dsp.o.
  13         (dsp.o): New dependency.
  14         (IGEN_INCLUDE): Add dsp.igen.
  15         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
  16         mipsisa64*-*-*): Add dsp to sim_igen_machine.
  17         * configure: Regenerate.
  18         * mips.igen: Add dsp model and include dsp.igen.
  19         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
  20         because these instructions are extended in DSP ASE.
  21         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
  22         adding 6 DSP accumulator registers and 1 DSP control register.
  23         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
  24         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
  25         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
  26         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
  27         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
  28         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
  29         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
  30         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
  31         DSPCR_CCOND_SMASK): New define.
  32         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
  33         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
  34
  35 2005-07-08  Ian Lance Taylor  <ian@airs.com>
  36
  37         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
  38
  39 2005-06-16  David Ung  <davidu@mips.com>
  40             Nigel Stephens  <nigel@mips.com>
  41
  42         * mips.igen: New mips16e model and include m16e.igen.
  43         (check_u64): Add mips16e tag.
  44         * m16e.igen: New file for MIPS16e instructions.
  45         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
  46         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
  47         models.
  48         * configure: Regenerate.
  49
  50 2005-05-26  David Ung  <davidu@mips.com>
  51
  52         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
  53         tags to all instructions which are applicable to the new ISAs.
  54         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
  55         vr.igen.
  56         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
  57         instructions.
  58         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
  59         to mips.igen.
  60         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
  61         * configure: Regenerate.
  62
  63 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
  64
  65         * configure: Regenerate.
  66
  67 2005-01-14  Andrew Cagney  <cagney@gnu.org>
  68
  69         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
  70         explicit call to AC_CONFIG_HEADER.
  71         * configure: Regenerate.
  72
  73 2005-01-12  Andrew Cagney  <cagney@gnu.org>
  74
  75         * configure.ac: Update to use ../common/common.m4.
  76         * configure: Re-generate.
  77
  78 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
  79
  80         * configure: Regenerated to track ../common/aclocal.m4 changes.
  81
  82 2005-01-07  Andrew Cagney  <cagney@gnu.org>
  83
  84         * configure.ac: Rename configure.in, require autoconf 2.59.
  85         * configure: Re-generate.
  86
  87 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
  88
  89         * configure: Regenerate for ../common/aclocal.m4 update.
  90
  91 2004-09-24  Monika Chaddha  <monika@acmet.com>
  92
  93         Committed by Andrew Cagney.
  94         * m16.igen (CMP, CMPI): Fix assembler.
  95
  96 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
  97
  98         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
  99         * configure: Regenerate.
 100
 101 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 102
 103         * configure.in (sim_m16_machine): Include mipsIII.
 104         * configure: Regenerate.
 105
 106 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 107
 108         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 109         from COP0_BADVADDR.
 110         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 111
 112 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 113
 114         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 115
 116 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 117
 118         * mips.igen (check_fmt): Remove.
 119         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 120         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 121         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 122         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 123         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 124         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 125         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 126         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 127         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 128         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 129
 130 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 131
 132         * sb1.igen (check_sbx): New function.
 133         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 134
 135 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 136             Richard Sandiford  <rsandifo@redhat.com>
 137
 138         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 139         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 140         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 141         separate implementations for mipsIV and mipsV.  Use new macros to
 142         determine whether the restrictions apply.
 143
 144 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 145
 146         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 147         (check_mult_hilo): Improve comments.
 148         (check_div_hilo): Likewise.  Also, fork off a new version
 149         to handle mips32/mips64 (since there are no hazards to check
 150         in MIPS32/MIPS64).
 151
 152 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 153
 154         * mips.igen (do_dmultx): Fix check for negative operands.
 155
 156 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 157
 158         * Makefile.in (SHELL): Make sure this is defined.
 159         (various): Use $(SHELL) whenever we invoke move-if-change.
 160
 161 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 162
 163         * cp1.c: Tweak attribution slightly.
 164         * cp1.h: Likewise.
 165         * mdmx.c: Likewise.
 166         * mdmx.igen: Likewise.
 167         * mips3d.igen: Likewise.
 168         * sb1.igen: Likewise.
 169
 170 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 171
 172         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 173         unsigned operands.
 174
 175 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 176
 177         * interp.c (sim_open): Rename _bfd to bfd.
 178         (sim_create_inferior): Ditto.
 179
 180 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 181
 182         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 183
 184 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 185
 186         * mips.igen (EI, DI): Remove.
 187
 188 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 189
 190         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 191
 192 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 193             Andrew Cagney  <ac131313@redhat.com>
 194             Gavin Romig-Koch  <gavin@redhat.com>
 195             Graydon Hoare  <graydon@redhat.com>
 196             Aldy Hernandez  <aldyh@redhat.com>
 197             Dave Brolley  <brolley@redhat.com>
 198             Chris Demetriou  <cgd@broadcom.com>
 199
 200         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 201         (sim_mach_default): New variable.
 202         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 203         Add a new simulator generator, MULTI.
 204         * configure: Regenerate.
 205         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 206         (multi-run.o): New dependency.
 207         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 208         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 209         (tmp-multi): Combine them.
 210         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 211         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 212         (distclean-extra): New rule.
 213         * sim-main.h: Include bfd.h.
 214         (MIPS_MACH): New macro.
 215         * mips.igen (vr4120, vr5400, vr5500): New models.
 216         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 217         * vr.igen: Replace with new version.
 218
 219 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 220
 221         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 222         * configure: Regenerate.
 223
 224 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 225
 226         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 227         * mips.igen: Remove all invocations of check_branch_bug and
 228         mark_branch_bug.
 229
 230 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 231
 232         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 233
 234 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 235
 236         * mips.igen (do_load_double, do_store_double): New functions.
 237         (LDC1, SDC1): Rename to...
 238         (LDC1b, SDC1b): respectively.
 239         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 240
 241 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 242
 243         * cp1.c (fp_recip2): Modify initialization expression so that
 244         GCC will recognize it as constant.
 245
 246 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 247
 248         * mdmx.c (SD_): Delete.
 249         (Unpredictable): Re-define, for now, to directly invoke
 250         unpredictable_action().
 251         (mdmx_acc_op): Fix error in .ob immediate handling.
 252
 253 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 254
 255         * interp.c (sim_firmware_command): Initialize `address'.
 256
 257 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 258
 259         * configure: Regenerated to track ../common/aclocal.m4 changes.
 260
 261 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 262             Ed Satterthwaite  <ehs@broadcom.com>
 263
 264         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 265         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 266         * mips.igen: Include mips3d.igen.
 267         (mips3d): New model name for MIPS-3D ASE instructions.
 268         (CVT.W.fmt): Don't use this instruction for word (source) format
 269         instructions.
 270         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 271         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 272         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 273         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 274         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 275         (RSquareRoot1, RSquareRoot2): New macros.
 276         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 277         (fp_rsqrt2): New functions.
 278         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 279         * configure: Regenerate.
 280
 281 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 282             Ed Satterthwaite  <ehs@broadcom.com>
 283
 284         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 285         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 286         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 287         (convert): Note that this function is not used for paired-single
 288         format conversions.
 289         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 290         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 291         (check_fmt_p): Enable paired-single support.
 292         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 293         (PUU.PS): New instructions.
 294         (CVT.S.fmt): Don't use this instruction for paired-single format
 295         destinations.
 296         * sim-main.h (FP_formats): New value 'fmt_ps.'
 297         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 298         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 299
 300 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 301
 302         * mips.igen: Fix formatting of function calls in
 303         many FP operations.
 304
 305 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 306
 307         * mips.igen (MOVN, MOVZ): Trace result.
 308         (TNEI): Print "tnei" as the opcode name in traces.
 309         (CEIL.W): Add disassembly string for traces.
 310         (RSQRT.fmt): Make location of disassembly string consistent
 311         with other instructions.
 312
 313 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 314
 315         * mips.igen (X): Delete unused function.
 316
 317 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 318
 319         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 320
 321 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 322             Ed Satterthwaite  <ehs@broadcom.com>
 323
 324         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 325         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 326         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 327         (fp_nmsub): New prototypes.
 328         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 329         (NegMultiplySub): New defines.
 330         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 331         (MADD.D, MADD.S): Replace with...
 332         (MADD.fmt): New instruction.
 333         (MSUB.D, MSUB.S): Replace with...
 334         (MSUB.fmt): New instruction.
 335         (NMADD.D, NMADD.S): Replace with...
 336         (NMADD.fmt): New instruction.
 337         (NMSUB.D, MSUB.S): Replace with...
 338         (NMSUB.fmt): New instruction.
 339
 340 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 341             Ed Satterthwaite  <ehs@broadcom.com>
 342
 343         * cp1.c: Fix more comment spelling and formatting.
 344         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 345         (denorm_mode): New function.
 346         (fpu_unary, fpu_binary): Round results after operation, collect
 347         status from rounding operations, and update the FCSR.
 348         (convert): Collect status from integer conversions and rounding
 349         operations, and update the FCSR.  Adjust NaN values that result
 350         from conversions.  Convert to use sim_io_eprintf rather than
 351         fprintf, and remove some debugging code.
 352         * cp1.h (fenr_FS): New define.
 353
 354 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 355
 356         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 357         rounding mode to sim FP rounding mode flag conversion code into...
 358         (rounding_mode): New function.
 359
 360 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 361
 362         * cp1.c: Clean up formatting of a few comments.
 363         (value_fpr): Reformat switch statement.
 364
 365 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 366             Ed Satterthwaite  <ehs@broadcom.com>
 367
 368         * cp1.h: New file.
 369         * sim-main.h: Include cp1.h.
 370         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 371         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 372         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 373         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 374         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 375         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 376         * cp1.c: Don't include sim-fpu.h; already included by
 377         sim-main.h.  Clean up formatting of some comments.
 378         (NaN, Equal, Less): Remove.
 379         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 380         (fp_cmp): New functions.
 381         * mips.igen (do_c_cond_fmt): Remove.
 382         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 383         Compare.  Add result tracing.
 384         (CxC1): Remove, replace with...
 385         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 386         (DMxC1): Remove, replace with...
 387         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 388         (MxC1): Remove, replace with...
 389         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 390
 391 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 392
 393         * sim-main.h (FGRIDX): Remove, replace all uses with...
 394         (FGR_BASE): New macro.
 395         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 396         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 397         (NR_FGR, FGR): Likewise.
 398         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 399         * mips.igen: Likewise.
 400
 401 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 402
 403         * cp1.c: Add an FSF Copyright notice to this file.
 404
 405 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 406             Ed Satterthwaite  <ehs@broadcom.com>
 407
 408         * cp1.c (Infinity): Remove.
 409         * sim-main.h (Infinity): Likewise.
 410
 411         * cp1.c (fp_unary, fp_binary): New functions.
 412         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 413         (fp_sqrt): New functions, implemented in terms of the above.
 414         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 415         (Recip, SquareRoot): Remove (replaced by functions above).
 416         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 417         (fp_recip, fp_sqrt): New prototypes.
 418         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 419         (Recip, SquareRoot): Replace prototypes with #defines which
 420         invoke the functions above.
 421
 422 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 423
 424         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 425         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 426         file, remove PARAMS from prototypes.
 427         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 428         simulator state arguments.
 429         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 430         pass simulator state arguments.
 431         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 432         (store_fpr, convert): Remove 'sd' argument.
 433         (value_fpr): Likewise.  Convert to use 'SD' instead.
 434
 435 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 436
 437         * cp1.c (Min, Max): Remove #if 0'd functions.
 438         * sim-main.h (Min, Max): Remove.
 439
 440 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 441
 442         * cp1.c: fix formatting of switch case and default labels.
 443         * interp.c: Likewise.
 444         * sim-main.c: Likewise.
 445
 446 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 447
 448         * cp1.c: Clean up comments which describe FP formats.
 449          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 450
 451 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 452             Ed Satterthwaite  <ehs@broadcom.com>
 453
 454         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 455         Broadcom SiByte SB-1 processor configurations.
 456         * configure: Regenerate.
 457         * sb1.igen: New file.
 458         * mips.igen: Include sb1.igen.
 459         (sb1): New model.
 460         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 461         * mdmx.igen: Add "sb1" model to all appropriate functions and
 462         instructions.
 463         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 464         (ob_func, ob_acc): Reference the above.
 465         (qh_acc): Adjust to keep the same size as ob_acc.
 466         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 467         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 468
 469 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 470
 471         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 472
 473 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 474             Ed Satterthwaite  <ehs@broadcom.com>
 475
 476         * mips.igen (mdmx): New (pseudo-)model.
 477         * mdmx.c, mdmx.igen: New files.
 478         * Makefile.in (SIM_OBJS): Add mdmx.o.
 479         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 480         New typedefs.
 481         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 482         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 483         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 484         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 485         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 486         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 487         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 488         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 489         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 490         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 491         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 492         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 493         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 494         (qh_fmtsel): New macros.
 495         (_sim_cpu): New member "acc".
 496         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 497         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 498
 499 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 500
 501         * interp.c: Use 'deprecated' rather than 'depreciated.'
 502         * sim-main.h: Likewise.
 503
 504 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 505
 506         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 507         which wouldn't compile anyway.
 508         * sim-main.h (unpredictable_action): New function prototype.
 509         (Unpredictable): Define to call igen function unpredictable().
 510         (NotWordValue): New macro to call igen function not_word_value().
 511         (UndefinedResult): Remove.
 512         * interp.c (undefined_result): Remove.
 513         (unpredictable_action): New function.
 514         * mips.igen (not_word_value, unpredictable): New functions.
 515         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 516         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 517         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 518         NotWordValue() to check for unpredictable inputs, then
 519         Unpredictable() to handle them.
 520
 521 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 522
 523         * mips.igen: Fix formatting of calls to Unpredictable().
 524
 525 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 526
 527         * interp.c (sim_open): Revert previous change.
 528
 529 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 530
 531         * interp.c (sim_open): Disable chunk of code that wrote code in
 532         vector table entries.
 533
 534 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 535
 536         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 537         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 538         unused definitions.
 539
 540 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 541
 542         * cp1.c: Fix many formatting issues.
 543
 544 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 545
 546         * cp1.c (fpu_format_name): New function to replace...
 547         (DOFMT): This.  Delete, and update all callers.
 548         (fpu_rounding_mode_name): New function to replace...
 549         (RMMODE): This.  Delete, and update all callers.
 550
 551 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 552
 553         * interp.c: Move FPU support routines from here to...
 554         * cp1.c: Here.  New file.
 555         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 556         (cp1.o): New target.
 557
 558 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 559
 560         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 561         * mips.igen (mips32, mips64): New models, add to all instructions
 562         and functions as appropriate.
 563         (loadstore_ea, check_u64): New variant for model mips64.
 564         (check_fmt_p): New variant for models mipsV and mips64, remove
 565         mipsV model marking fro other variant.
 566         (SLL) Rename to...
 567         (SLLa) this.
 568         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 569         for mips32 and mips64.
 570         (DCLO, DCLZ): New instructions for mips64.
 571
 572 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 573
 574         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 575         immediate or code as a hex value with the "%#lx" format.
 576         (ANDI): Likewise, and fix printed instruction name.
 577
 578 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 579
 580         * sim-main.h (UndefinedResult, Unpredictable): New macros
 581         which currently do nothing.
 582
 583 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 584
 585         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 586         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 587         (status_CU3): New definitions.
 588
 589         * sim-main.h (ExceptionCause): Add new values for MIPS32
 590         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 591         for DebugBreakPoint and NMIReset to note their status in
 592         MIPS32 and MIPS64.
 593         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 594         (SignalExceptionCacheErr): New exception macros.
 595
 596 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 597
 598         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 599         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 600         is always enabled.
 601         (SignalExceptionCoProcessorUnusable): Take as argument the
 602         unusable coprocessor number.
 603
 604 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 605
 606         * mips.igen: Fix formatting of all SignalException calls.
 607
 608 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 609
 610         * sim-main.h (SIGNEXTEND): Remove.
 611
 612 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 613
 614         * mips.igen: Remove gencode comment from top of file, fix
 615         spelling in another comment.
 616
 617 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 618
 619         * mips.igen (check_fmt, check_fmt_p): New functions to check
 620         whether specific floating point formats are usable.
 621         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 622         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 623         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 624         Use the new functions.
 625         (do_c_cond_fmt): Remove format checks...
 626         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 627
 628 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 629
 630         * mips.igen: Fix formatting of check_fpu calls.
 631
 632 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 633
 634         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 635
 636 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 637
 638         * mips.igen: Remove whitespace at end of lines.
 639
 640 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 641
 642         * mips.igen (loadstore_ea): New function to do effective
 643         address calculations.
 644         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 645         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 646         CACHE): Use loadstore_ea to do effective address computations.
 647
 648 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 649
 650         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 651         * mips.igen (LL, CxC1, MxC1): Likewise.
 652
 653 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 654
 655         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 656         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 657         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 658         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 659         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 660         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 661         Don't split opcode fields by hand, use the opcode field values
 662         provided by igen.
 663
 664 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 665
 666         * mips.igen (do_divu): Fix spacing.
 667
 668         * mips.igen (do_dsllv): Move to be right before DSLLV,
 669         to match the rest of the do_<shift> functions.
 670
 671 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 672
 673         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 674         DSRL32, do_dsrlv): Trace inputs and results.
 675
 676 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 677
 678         * mips.igen (CACHE): Provide instruction-printing string.
 679
 680         * interp.c (signal_exception): Comment tokens after #endif.
 681
 682 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 683
 684         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 685         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 686         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 687         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 688         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 689         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 690         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 691         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 692
 693 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 694
 695         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 696         instruction-printing string.
 697         (LWU): Use '64' as the filter flag.
 698
 699 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 700
 701         * mips.igen (SDXC1): Fix instruction-printing string.
 702
 703 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 704
 705         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 706         filter flags "32,f".
 707
 708 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 709
 710         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 711         as the filter flag.
 712
 713 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 714
 715         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 716         add a comma) so that it more closely match the MIPS ISA
 717         documentation opcode partitioning.
 718         (PREF): Put useful names on opcode fields, and include
 719         instruction-printing string.
 720
 721 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 722
 723         * mips.igen (check_u64): New function which in the future will
 724         check whether 64-bit instructions are usable and signal an
 725         exception if not.  Currently a no-op.
 726         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 727         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 728         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 729         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 730
 731         * mips.igen (check_fpu): New function which in the future will
 732         check whether FPU instructions are usable and signal an exception
 733         if not.  Currently a no-op.
 734         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 735         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 736         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 737         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 738         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 739         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 740         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 741         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 742
 743 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 744
 745         * mips.igen (do_load_left, do_load_right): Move to be immediately
 746         following do_load.
 747         (do_store_left, do_store_right): Move to be immediately following
 748         do_store.
 749
 750 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 751
 752         * mips.igen (mipsV): New model name.  Also, add it to
 753         all instructions and functions where it is appropriate.
 754
 755 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 756
 757         * mips.igen: For all functions and instructions, list model
 758         names that support that instruction one per line.
 759
 760 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 761
 762         * mips.igen: Add some additional comments about supported
 763         models, and about which instructions go where.
 764         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 765         order as is used in the rest of the file.
 766
 767 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 768
 769         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 770         indicating that ALU32_END or ALU64_END are there to check
 771         for overflow.
 772         (DADD): Likewise, but also remove previous comment about
 773         overflow checking.
 774
 775 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 776
 777         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 778         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 779         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 780         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 781         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 782         fields (i.e., add and move commas) so that they more closely
 783         match the MIPS ISA documentation opcode partitioning.
 784
 785 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 786
 787         * mips.igen (ADDI): Print immediate value.
 788         (BREAK): Print code.
 789         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 790         (SLL): Print "nop" specially, and don't run the code
 791         that does the shift for the "nop" case.
 792
 793 2001-11-17  Fred Fish  <fnf@redhat.com>
 794
 795         * sim-main.h (float_operation): Move enum declaration outside
 796         of _sim_cpu struct declaration.
 797
 798 2001-04-12  Jim Blandy  <jimb@redhat.com>
 799
 800         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 801         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 802         set of the FCSR.
 803         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 804         PENDING_FILL, and you can get the intended effect gracefully by
 805         calling PENDING_SCHED directly.
 806
 807 2001-02-23  Ben Elliston  <bje@redhat.com>
 808
 809         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 810         already defined elsewhere.
 811
 812 2001-02-19  Ben Elliston  <bje@redhat.com>
 813
 814         * sim-main.h (sim_monitor): Return an int.
 815         * interp.c (sim_monitor): Add return values.
 816         (signal_exception): Handle error conditions from sim_monitor.
 817
 818 2001-02-08  Ben Elliston  <bje@redhat.com>
 819
 820         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 821         (store_memory): Likewise, pass cia to sim_core_write*.
 822
 823 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 824
 825         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 826         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 827
 828 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 829
 830         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 831         * Makefile.in: Don't delete *.igen when cleaning directory.
 832
 833 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 834
 835         * m16.igen (break): Call SignalException not sim_engine_halt.
 836
 837 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 838
 839         From Jason Eckhardt:
 840         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 841
 842 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 843
 844         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 845
 846 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 847
 848         * mips.igen (do_dmultx): Fix typo.
 849
 850 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 851
 852         * configure: Regenerated to track ../common/aclocal.m4 changes.
 853
 854 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 855
 856         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 857
 858 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 859
 860         * sim-main.h (GPR_CLEAR): Define macro.
 861
 862 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 863
 864         * interp.c (decode_coproc): Output long using %lx and not %s.
 865
 866 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 867
 868         * interp.c (sim_open): Sort & extend dummy memory regions for
 869         --board=jmr3904 for eCos.
 870
 871 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 872
 873         * configure: Regenerated.
 874
 875 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 876
 877         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 878         calls, conditional on the simulator being in verbose mode.
 879
 880 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 881
 882         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 883         cache don't get ReservedInstruction traps.
 884
 885 1999-11-29  Mark Salter  <msalter@cygnus.com>
 886
 887         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 888         to clear status bits in sdisr register. This is how the hardware works.
 889
 890         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 891         being used by cygmon.
 892
 893 1999-11-11  Andrew Haley  <aph@cygnus.com>
 894
 895         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 896         instructions.
 897
 898 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 899
 900         * mips.igen (MULT): Correct previous mis-applied patch.
 901
 902 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 903
 904         * mips.igen (delayslot32): Handle sequence like
 905         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 906         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 907         (MULT): Actually pass the third register...
 908
 909 1999-09-03  Mark Salter  <msalter@cygnus.com>
 910
 911         * interp.c (sim_open): Added more memory aliases for additional
 912         hardware being touched by cygmon on jmr3904 board.
 913
 914 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 915
 916         * configure: Regenerated to track ../common/aclocal.m4 changes.
 917
 918 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 919
 920         * interp.c (sim_store_register): Handle case where client - GDB -
 921         specifies that a 4 byte register is 8 bytes in size.
 922         (sim_fetch_register): Ditto.
 923
 924 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 925
 926         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 927         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 928         (idt_monitor_base): Base address for IDT monitor traps.
 929         (pmon_monitor_base): Ditto for PMON.
 930         (lsipmon_monitor_base): Ditto for LSI PMON.
 931         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 932         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 933         (sim_firmware_command): New function.
 934         (mips_option_handler): Call it for OPTION_FIRMWARE.
 935         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 936         option was given, add no monitor by default.  Add BREAK hooks only if
 937         monitors are also there.
 938
 939 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 940
 941         * interp.c (sim_monitor): Flush output before reading input.
 942
 943 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 944
 945         * tconfig.in (SIM_HANDLES_LMA): Always define.
 946
 947 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 948
 949         From Mark Salter <msalter@cygnus.com>:
 950         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 951         (sim_open): Add setup for BSP board.
 952
 953 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 954
 955         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 956         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 957         them as unimplemented.
 958
 959 1999-05-08  Felix Lee  <flee@cygnus.com>
 960
 961         * configure: Regenerated to track ../common/aclocal.m4 changes.
 962
 963 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 964
 965         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 966
 967 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 968
 969         * configure.in: Any mips64vr5*-*-* target should have
 970         -DTARGET_ENABLE_FR=1.
 971         (default_endian): Any mips64vr*el-*-* target should default to
 972         LITTLE_ENDIAN.
 973         * configure: Re-generate.
 974
 975 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 976
 977         * mips.igen (ldl): Extend from _16_, not 32.
 978
 979 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 980
 981         * interp.c (sim_store_register): Force registers written to by GDB
 982         into an un-interpreted state.
 983
 984 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 985
 986         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 987         CPU, start periodic background I/O polls.
 988         (tx3904sio_poll): New function: periodic I/O poller.
 989
 990 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 991
 992         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 993
 994 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 995
 996         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 997         case statement.
 998
 999 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1000
1001         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1002         (load_word): Call SIM_CORE_SIGNAL hook on error.
1003         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1004         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1005         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1006         * sim-main.h (COP0_BADVADDR): Define.
1007         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1008         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1009         (_sim_cpu): Add exc_* fields to store register value snapshots.
1010         * mips.igen (*): Replace memory-related SignalException* calls
1011         with references to SIM_CORE_SIGNAL hook.
1012
1013         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1014         fix.
1015         * sim-main.c (*): Minor warning cleanups.
1016
1017 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1018
1019         * m16.igen (DADDIU5): Correct type-o.
1020
1021 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1022
1023         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1024         variables.
1025
1026 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1027
1028         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1029         to include path.
1030         (interp.o): Add dependency on itable.h
1031         (oengine.c, gencode): Delete remaining references.
1032         (BUILT_SRC_FROM_GEN): Clean up.
1033
1034 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1035
1036         * vr4run.c: New.
1037         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1038         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1039         tmp-run-hack) : New.
1040         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1041         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1042         Drop the "64" qualifier to get the HACK generator working.
1043         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1044         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1045         qualifier to get the hack generator working.
1046         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1047         (DSLL): Use do_dsll.
1048         (DSLLV): Use do_dsllv.
1049         (DSRA): Use do_dsra.
1050         (DSRL): Use do_dsrl.
1051         (DSRLV): Use do_dsrlv.
1052         (BC1): Move *vr4100 to get the HACK generator working.
1053         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1054         get the HACK generator working.
1055         (MACC) Rename to get the HACK generator working.
1056         (DMACC,MACCS,DMACCS): Add the 64.
1057
1058 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1059
1060         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1061         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1062
1063 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1064
1065     * mips/interp.c (DEBUG): Cleanups.
1066
1067 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1068
1069         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1070         (tx3904sio_tickle): fflush after a stdout character output.
1071
1072 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1073
1074         * interp.c (sim_close): Uninstall modules.
1075
1076 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1077
1078         * sim-main.h, interp.c (sim_monitor): Change to global
1079         function.
1080
1081 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1082
1083         * configure.in (vr4100): Only include vr4100 instructions in
1084         simulator.
1085         * configure: Re-generate.
1086         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1087
1088 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1089
1090         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1091         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1092         true alternative.
1093
1094         * configure.in (sim_default_gen, sim_use_gen): Replace with
1095         sim_gen.
1096         (--enable-sim-igen): Delete config option. Always using IGEN.
1097         * configure: Re-generate.
1098
1099         * Makefile.in (gencode): Kill, kill, kill.
1100         * gencode.c: Ditto.
1101
1102 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1103
1104         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1105         bit mips16 igen simulator.
1106         * configure: Re-generate.
1107
1108         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1109         as part of vr4100 ISA.
1110         * vr.igen: Mark all instructions as 64 bit only.
1111
1112 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1113
1114         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1115         Pacify GCC.
1116
1117 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1118
1119         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1120         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1121         * configure: Re-generate.
1122
1123         * m16.igen (BREAK): Define breakpoint instruction.
1124         (JALX32): Mark instruction as mips16 and not r3900.
1125         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1126
1127         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1128
1129 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1130
1131         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1132         insn as a debug breakpoint.
1133
1134         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1135         pending.slot_size.
1136         (PENDING_SCHED): Clean up trace statement.
1137         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1138         (PENDING_FILL): Delay write by only one cycle.
1139         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1140
1141         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1142         of pending writes.
1143         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1144         32 & 64.
1145         (pending_tick): Move incrementing of index to FOR statement.
1146         (pending_tick): Only update PENDING_OUT after a write has occured.
1147
1148         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1149         build simulator.
1150         * configure: Re-generate.
1151
1152         * interp.c (sim_engine_run OLD): Delete explicit call to
1153         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1154
1155 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1156
1157         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1158         interrupt level number to match changed SignalExceptionInterrupt
1159         macro.
1160
1161 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1162
1163         * interp.c: #include "itable.h" if WITH_IGEN.
1164         (get_insn_name): New function.
1165         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1166         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1167
1168 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1169
1170         * configure: Rebuilt to inhale new common/aclocal.m4.
1171
1172 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1173
1174         * dv-tx3904sio.c: Include sim-assert.h.
1175
1176 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1177
1178         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1179         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1180         Reorganize target-specific sim-hardware checks.
1181         * configure: rebuilt.
1182         * interp.c (sim_open): For tx39 target boards, set
1183         OPERATING_ENVIRONMENT, add tx3904sio devices.
1184         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1185         ROM executables.  Install dv-sockser into sim-modules list.
1186
1187         * dv-tx3904irc.c: Compiler warning clean-up.
1188         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1189         frequent hw-trace messages.
1190
1191 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1192
1193         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1194
1195 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1196
1197         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1198
1199         * vr.igen: New file.
1200         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1201         * mips.igen: Define vr4100 model. Include vr.igen.
1202 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1203
1204         * mips.igen (check_mf_hilo): Correct check.
1205
1206 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1207
1208         * sim-main.h (interrupt_event): Add prototype.
1209
1210         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1211         register_ptr, register_value.
1212         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1213
1214         * sim-main.h (tracefh): Make extern.
1215
1216 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1217
1218         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1219         Reduce unnecessarily high timer event frequency.
1220         * dv-tx3904cpu.c: Ditto for interrupt event.
1221
1222 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1223
1224         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1225         to allay warnings.
1226         (interrupt_event): Made non-static.
1227
1228         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1229         interchange of configuration values for external vs. internal
1230         clock dividers.
1231
1232 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1233
1234         * mips.igen (BREAK): Moved code to here for
1235         simulator-reserved break instructions.
1236         * gencode.c (build_instruction): Ditto.
1237         * interp.c (signal_exception): Code moved from here.  Non-
1238         reserved instructions now use exception vector, rather
1239         than halting sim.
1240         * sim-main.h: Moved magic constants to here.
1241
1242 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1243
1244         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1245         register upon non-zero interrupt event level, clear upon zero
1246         event value.
1247         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1248         by passing zero event value.
1249         (*_io_{read,write}_buffer): Endianness fixes.
1250         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1251         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1252
1253         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1254         serial I/O and timer module at base address 0xFFFF0000.
1255
1256 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1257
1258         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1259         and BigEndianCPU.
1260
1261 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1262
1263         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1264         parts.
1265         * configure: Update.
1266
1267 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1268
1269         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1270         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1271         * configure.in: Include tx3904tmr in hw_device list.
1272         * configure: Rebuilt.
1273         * interp.c (sim_open): Instantiate three timer instances.
1274         Fix address typo of tx3904irc instance.
1275
1276 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1277
1278         * interp.c (signal_exception): SystemCall exception now uses
1279         the exception vector.
1280
1281 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1282
1283         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1284         to allay warnings.
1285
1286 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1287
1288         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1289
1290 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1291
1292         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1293
1294         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1295         sim-main.h. Declare a struct hw_descriptor instead of struct
1296         hw_device_descriptor.
1297
1298 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1299
1300         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1301         right bits and then re-align left hand bytes to correct byte
1302         lanes.  Fix incorrect computation in do_store_left when loading
1303         bytes from second word.
1304
1305 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1306
1307         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1308         * interp.c (sim_open): Only create a device tree when HW is
1309         enabled.
1310
1311         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1312         * interp.c (signal_exception): Ditto.
1313
1314 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1315
1316         * gencode.c: Mark BEGEZALL as LIKELY.
1317
1318 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1319
1320         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1321         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1322
1323 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1324
1325         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1326         modules.  Recognize TX39 target with "mips*tx39" pattern.
1327         * configure: Rebuilt.
1328         * sim-main.h (*): Added many macros defining bits in
1329         TX39 control registers.
1330         (SignalInterrupt): Send actual PC instead of NULL.
1331         (SignalNMIReset): New exception type.
1332         * interp.c (board): New variable for future use to identify
1333         a particular board being simulated.
1334         (mips_option_handler,mips_options): Added "--board" option.
1335         (interrupt_event): Send actual PC.
1336         (sim_open): Make memory layout conditional on board setting.
1337         (signal_exception): Initial implementation of hardware interrupt
1338         handling.  Accept another break instruction variant for simulator
1339         exit.
1340         (decode_coproc): Implement RFE instruction for TX39.
1341         (mips.igen): Decode RFE instruction as such.
1342         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1343         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1344         bbegin to implement memory map.
1345         * dv-tx3904cpu.c: New file.
1346         * dv-tx3904irc.c: New file.
1347
1348 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1349
1350         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1351
1352 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1353
1354         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1355         with calls to check_div_hilo.
1356
1357 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1358
1359         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1360         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1361         Add special r3900 version of do_mult_hilo.
1362         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1363         with calls to check_mult_hilo.
1364         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1365         with calls to check_div_hilo.
1366
1367 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1368
1369         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1370         Document a replacement.
1371
1372 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1373
1374         * interp.c (sim_monitor): Make mon_printf work.
1375
1376 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1377
1378         * sim-main.h (INSN_NAME): New arg `cpu'.
1379
1380 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1381
1382         * configure: Regenerated to track ../common/aclocal.m4 changes.
1383
1384 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1385
1386         * configure: Regenerated to track ../common/aclocal.m4 changes.
1387         * config.in: Ditto.
1388
1389 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1390
1391         * acconfig.h: New file.
1392         * configure.in: Reverted change of Apr 24; use sinclude again.
1393
1394 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1395
1396         * configure: Regenerated to track ../common/aclocal.m4 changes.
1397         * config.in: Ditto.
1398
1399 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1400
1401         * configure.in: Don't call sinclude.
1402
1403 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1404
1405         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1406
1407 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1408
1409         * mips.igen (ERET): Implement.
1410
1411         * interp.c (decode_coproc): Return sign-extended EPC.
1412
1413         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1414
1415         * interp.c (signal_exception): Do not ignore Trap.
1416         (signal_exception): On TRAP, restart at exception address.
1417         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1418         (signal_exception): Update.
1419         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1420         so that TRAP instructions are caught.
1421
1422 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1423
1424         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1425         contains HI/LO access history.
1426         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1427         (HIACCESS, LOACCESS): Delete, replace with
1428         (HIHISTORY, LOHISTORY): New macros.
1429         (CHECKHILO): Delete all, moved to mips.igen
1430
1431         * gencode.c (build_instruction): Do not generate checks for
1432         correct HI/LO register usage.
1433
1434         * interp.c (old_engine_run): Delete checks for correct HI/LO
1435         register usage.
1436
1437         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1438         check_mf_cycles): New functions.
1439         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1440         do_divu, domultx, do_mult, do_multu): Use.
1441
1442         * tx.igen ("madd", "maddu"): Use.
1443
1444 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * mips.igen (DSRAV): Use function do_dsrav.
1447         (SRAV): Use new function do_srav.
1448
1449         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1450         (B): Sign extend 11 bit immediate.
1451         (EXT-B*): Shift 16 bit immediate left by 1.
1452         (ADDIU*): Don't sign extend immediate value.
1453
1454 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1455
1456         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1457
1458         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1459         functions.
1460
1461         * mips.igen (delayslot32, nullify_next_insn): New functions.
1462         (m16.igen): Always include.
1463         (do_*): Add more tracing.
1464
1465         * m16.igen (delayslot16): Add NIA argument, could be called by a
1466         32 bit MIPS16 instruction.
1467
1468         * interp.c (ifetch16): Move function from here.
1469         * sim-main.c (ifetch16): To here.
1470
1471         * sim-main.c (ifetch16, ifetch32): Update to match current
1472         implementations of LH, LW.
1473         (signal_exception): Don't print out incorrect hex value of illegal
1474         instruction.
1475
1476 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1477
1478         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1479         instruction.
1480
1481         * m16.igen: Implement MIPS16 instructions.
1482
1483         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1484         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1485         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1486         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1487         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1488         bodies of corresponding code from 32 bit insn to these.  Also used
1489         by MIPS16 versions of functions.
1490
1491         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1492         (IMEM16): Drop NR argument from macro.
1493
1494 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1495
1496         * Makefile.in (SIM_OBJS): Add sim-main.o.
1497
1498         * sim-main.h (address_translation, load_memory, store_memory,
1499         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1500         as INLINE_SIM_MAIN.
1501         (pr_addr, pr_uword64): Declare.
1502         (sim-main.c): Include when H_REVEALS_MODULE_P.
1503
1504         * interp.c (address_translation, load_memory, store_memory,
1505         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1506         from here.
1507         * sim-main.c: To here. Fix compilation problems.
1508
1509         * configure.in: Enable inlining.
1510         * configure: Re-config.
1511
1512 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1513
1514         * configure: Regenerated to track ../common/aclocal.m4 changes.
1515
1516 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1517
1518         * mips.igen: Include tx.igen.
1519         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1520         * tx.igen: New file, contains MADD and MADDU.
1521
1522         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1523         the hardwired constant `7'.
1524         (store_memory): Ditto.
1525         (LOADDRMASK): Move definition to sim-main.h.
1526
1527         mips.igen (MTC0): Enable for r3900.
1528         (ADDU): Add trace.
1529
1530         mips.igen (do_load_byte): Delete.
1531         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1532         do_store_right): New functions.
1533         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1534
1535         configure.in: Let the tx39 use igen again.
1536         configure: Update.
1537
1538 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1539
1540         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1541         not an address sized quantity.  Return zero for cache sizes.
1542
1543 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1544
1545         * mips.igen (r3900): r3900 does not support 64 bit integer
1546         operations.
1547
1548 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1549
1550         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1551         than igen one.
1552         * configure : Rebuild.
1553
1554 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1555
1556         * configure: Regenerated to track ../common/aclocal.m4 changes.
1557
1558 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1559
1560         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1561
1562 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1563
1564         * configure: Regenerated to track ../common/aclocal.m4 changes.
1565         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1566
1567 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1568
1569         * configure: Regenerated to track ../common/aclocal.m4 changes.
1570
1571 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1572
1573         * interp.c (Max, Min): Comment out functions. Not yet used.
1574
1575 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1576
1577         * configure: Regenerated to track ../common/aclocal.m4 changes.
1578
1579 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1580
1581         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1582         configurable settings for stand-alone simulator.
1583
1584         * configure.in: Added X11 search, just in case.
1585
1586         * configure: Regenerated.
1587
1588 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1589
1590         * interp.c (sim_write, sim_read, load_memory, store_memory):
1591         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1592
1593 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1594
1595         * sim-main.h (GETFCC): Return an unsigned value.
1596
1597 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1598
1599         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1600         (DADD): Result destination is RD not RT.
1601
1602 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1603
1604         * sim-main.h (HIACCESS, LOACCESS): Always define.
1605
1606         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1607
1608         * interp.c (sim_info): Delete.
1609
1610 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1611
1612         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1613         (mips_option_handler): New argument `cpu'.
1614         (sim_open): Update call to sim_add_option_table.
1615
1616 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1617
1618         * mips.igen (CxC1): Add tracing.
1619
1620 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1621
1622         * sim-main.h (Max, Min): Declare.
1623
1624         * interp.c (Max, Min): New functions.
1625
1626         * mips.igen (BC1): Add tracing.
1627
1628 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1629
1630         * interp.c Added memory map for stack in vr4100
1631
1632 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1633
1634         * interp.c (load_memory): Add missing "break"'s.
1635
1636 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1637
1638         * interp.c (sim_store_register, sim_fetch_register): Pass in
1639         length parameter.  Return -1.
1640
1641 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1642
1643         * interp.c: Added hardware init hook, fixed warnings.
1644
1645 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1646
1647         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1648
1649 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1650
1651         * interp.c (ifetch16): New function.
1652
1653         * sim-main.h (IMEM32): Rename IMEM.
1654         (IMEM16_IMMED): Define.
1655         (IMEM16): Define.
1656         (DELAY_SLOT): Update.
1657
1658         * m16run.c (sim_engine_run): New file.
1659
1660         * m16.igen: All instructions except LB.
1661         (LB): Call do_load_byte.
1662         * mips.igen (do_load_byte): New function.
1663         (LB): Call do_load_byte.
1664
1665         * mips.igen: Move spec for insn bit size and high bit from here.
1666         * Makefile.in (tmp-igen, tmp-m16): To here.
1667
1668         * m16.dc: New file, decode mips16 instructions.
1669
1670         * Makefile.in (SIM_NO_ALL): Define.
1671         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1672
1673 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1674
1675         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1676         point unit to 32 bit registers.
1677         * configure: Re-generate.
1678
1679 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1680
1681         * configure.in (sim_use_gen): Make IGEN the default simulator
1682         generator for generic 32 and 64 bit mips targets.
1683         * configure: Re-generate.
1684
1685 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1686
1687         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1688         bitsize.
1689
1690         * interp.c (sim_fetch_register, sim_store_register): Read/write
1691         FGR from correct location.
1692         (sim_open): Set size of FGR's according to
1693         WITH_TARGET_FLOATING_POINT_BITSIZE.
1694
1695         * sim-main.h (FGR): Store floating point registers in a separate
1696         array.
1697
1698 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1699
1700         * configure: Regenerated to track ../common/aclocal.m4 changes.
1701
1702 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1703
1704         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1705
1706         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1707
1708         * interp.c (pending_tick): New function.  Deliver pending writes.
1709
1710         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1711         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1712         it can handle mixed sized quantites and single bits.
1713
1714 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1715
1716         * interp.c (oengine.h): Do not include when building with IGEN.
1717         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1718         (sim_info): Ditto for PROCESSOR_64BIT.
1719         (sim_monitor): Replace ut_reg with unsigned_word.
1720         (*): Ditto for t_reg.
1721         (LOADDRMASK): Define.
1722         (sim_open): Remove defunct check that host FP is IEEE compliant,
1723         using software to emulate floating point.
1724         (value_fpr, ...): Always compile, was conditional on HASFPU.
1725
1726 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1727
1728         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1729         size.
1730
1731         * interp.c (SD, CPU): Define.
1732         (mips_option_handler): Set flags in each CPU.
1733         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1734         (sim_close): Do not clear STATE, deleted anyway.
1735         (sim_write, sim_read): Assume CPU zero's vm should be used for
1736         data transfers.
1737         (sim_create_inferior): Set the PC for all processors.
1738         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1739         argument.
1740         (mips16_entry): Pass correct nr of args to store_word, load_word.
1741         (ColdReset): Cold reset all cpu's.
1742         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1743         (sim_monitor, load_memory, store_memory, signal_exception): Use
1744         `CPU' instead of STATE_CPU.
1745
1746
1747         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1748         SD or CPU_.
1749
1750         * sim-main.h (signal_exception): Add sim_cpu arg.
1751         (SignalException*): Pass both SD and CPU to signal_exception.
1752         * interp.c (signal_exception): Update.
1753
1754         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1755         Ditto
1756         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1757         address_translation): Ditto
1758         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1759
1760 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1761
1762         * configure: Regenerated to track ../common/aclocal.m4 changes.
1763
1764 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1765
1766         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1767
1768         * mips.igen (model): Map processor names onto BFD name.
1769
1770         * sim-main.h (CPU_CIA): Delete.
1771         (SET_CIA, GET_CIA): Define
1772
1773 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1774
1775         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1776         regiser.
1777
1778         * configure.in (default_endian): Configure a big-endian simulator
1779         by default.
1780         * configure: Re-generate.
1781
1782 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1783
1784         * configure: Regenerated to track ../common/aclocal.m4 changes.
1785
1786 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1787
1788         * interp.c (sim_monitor): Handle Densan monitor outbyte
1789         and inbyte functions.
1790
1791 1997-12-29  Felix Lee  <flee@cygnus.com>
1792
1793         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1794
1795 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1796
1797         * Makefile.in (tmp-igen): Arrange for $zero to always be
1798         reset to zero after every instruction.
1799
1800 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1801
1802         * configure: Regenerated to track ../common/aclocal.m4 changes.
1803         * config.in: Ditto.
1804
1805 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1806
1807         * mips.igen (MSUB): Fix to work like MADD.
1808         * gencode.c (MSUB): Similarly.
1809
1810 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1811
1812         * configure: Regenerated to track ../common/aclocal.m4 changes.
1813
1814 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1815
1816         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1817
1818 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1819
1820         * sim-main.h (sim-fpu.h): Include.
1821
1822         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1823         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1824         using host independant sim_fpu module.
1825
1826 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1827
1828         * interp.c (signal_exception): Report internal errors with SIGABRT
1829         not SIGQUIT.
1830
1831         * sim-main.h (C0_CONFIG): New register.
1832         (signal.h): No longer include.
1833
1834         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1835
1836 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1837
1838         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1839
1840 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1841
1842         * mips.igen: Tag vr5000 instructions.
1843         (ANDI): Was missing mipsIV model, fix assembler syntax.
1844         (do_c_cond_fmt): New function.
1845         (C.cond.fmt): Handle mips I-III which do not support CC field
1846         separatly.
1847         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1848         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1849         in IV3.2 spec.
1850         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1851         vr5000 which saves LO in a GPR separatly.
1852
1853         * configure.in (enable-sim-igen): For vr5000, select vr5000
1854         specific instructions.
1855         * configure: Re-generate.
1856
1857 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1858
1859         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1860
1861         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1862         fmt_uninterpreted_64 bit cases to switch.  Convert to
1863         fmt_formatted,
1864
1865         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1866
1867         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1868         as specified in IV3.2 spec.
1869         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1870
1871 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1872
1873         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1874         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1875         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1876         PENDING_FILL versions of instructions.  Simplify.
1877         (X): New function.
1878         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1879         instructions.
1880         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1881         a signed value.
1882         (MTHI, MFHI): Disable code checking HI-LO.
1883
1884         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1885         global.
1886         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1887
1888 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1889
1890         * gencode.c (build_mips16_operands): Replace IPC with cia.
1891
1892         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1893         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1894         IPC to `cia'.
1895         (UndefinedResult): Replace function with macro/function
1896         combination.
1897         (sim_engine_run): Don't save PC in IPC.
1898
1899         * sim-main.h (IPC): Delete.
1900
1901
1902         * interp.c (signal_exception, store_word, load_word,
1903         address_translation, load_memory, store_memory, cache_op,
1904         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1905         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1906         current instruction address - cia - argument.
1907         (sim_read, sim_write): Call address_translation directly.
1908         (sim_engine_run): Rename variable vaddr to cia.
1909         (signal_exception): Pass cia to sim_monitor
1910
1911         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1912         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1913         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1914
1915         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1916         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1917         SIM_ASSERT.
1918
1919         * interp.c (signal_exception): Pass restart address to
1920         sim_engine_restart.
1921
1922         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1923         idecode.o): Add dependency.
1924
1925         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1926         Delete definitions
1927         (DELAY_SLOT): Update NIA not PC with branch address.
1928         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1929
1930         * mips.igen: Use CIA not PC in branch calculations.
1931         (illegal): Call SignalException.
1932         (BEQ, ADDIU): Fix assembler.
1933
1934 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1935
1936         * m16.igen (JALX): Was missing.
1937
1938         * configure.in (enable-sim-igen): New configuration option.
1939         * configure: Re-generate.
1940
1941         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1942
1943         * interp.c (load_memory, store_memory): Delete parameter RAW.
1944         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1945         bypassing {load,store}_memory.
1946
1947         * sim-main.h (ByteSwapMem): Delete definition.
1948
1949         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1950
1951         * interp.c (sim_do_command, sim_commands): Delete mips specific
1952         commands.  Handled by module sim-options.
1953
1954         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1955         (WITH_MODULO_MEMORY): Define.
1956
1957         * interp.c (sim_info): Delete code printing memory size.
1958
1959         * interp.c (mips_size): Nee sim_size, delete function.
1960         (power2): Delete.
1961         (monitor, monitor_base, monitor_size): Delete global variables.
1962         (sim_open, sim_close): Delete code creating monitor and other
1963         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1964         manage memory regions.
1965         (load_memory, store_memory): Use sim-core for memory model.
1966
1967         * interp.c (address_translation): Delete all memory map code
1968         except line forcing 32 bit addresses.
1969
1970 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1971
1972         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1973         trace options.
1974
1975         * interp.c (logfh, logfile): Delete globals.
1976         (sim_open, sim_close): Delete code opening & closing log file.
1977         (mips_option_handler): Delete -l and -n options.
1978         (OPTION mips_options): Ditto.
1979
1980         * interp.c (OPTION mips_options): Rename option trace to dinero.
1981         (mips_option_handler): Update.
1982
1983 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1984
1985         * interp.c (fetch_str): New function.
1986         (sim_monitor): Rewrite using sim_read & sim_write.
1987         (sim_open): Check magic number.
1988         (sim_open): Write monitor vectors into memory using sim_write.
1989         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1990         (sim_read, sim_write): Simplify - transfer data one byte at a
1991         time.
1992         (load_memory, store_memory): Clarify meaning of parameter RAW.
1993
1994         * sim-main.h (isHOST): Defete definition.
1995         (isTARGET): Mark as depreciated.
1996         (address_translation): Delete parameter HOST.
1997
1998         * interp.c (address_translation): Delete parameter HOST.
1999
2000 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2001
2002         * mips.igen:
2003
2004         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2005         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2006
2007 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2008
2009         * mips.igen: Add model filter field to records.
2010
2011 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2012
2013         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2014
2015         interp.c (sim_engine_run): Do not compile function sim_engine_run
2016         when WITH_IGEN == 1.
2017
2018         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2019         target architecture.
2020
2021         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2022         igen. Replace with configuration variables sim_igen_flags /
2023         sim_m16_flags.
2024
2025         * m16.igen: New file.  Copy mips16 insns here.
2026         * mips.igen: From here.
2027
2028 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2029
2030         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2031         to top.
2032         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2033
2034 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2035
2036         * gencode.c (build_instruction): Follow sim_write's lead in using
2037         BigEndianMem instead of !ByteSwapMem.
2038
2039 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2040
2041         * configure.in (sim_gen): Dependent on target, select type of
2042         generator.  Always select old style generator.
2043
2044         configure: Re-generate.
2045
2046         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2047         targets.
2048         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2049         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2050         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2051         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2052         SIM_@sim_gen@_*, set by autoconf.
2053
2054 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2055
2056         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2057
2058         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2059         CURRENT_FLOATING_POINT instead.
2060
2061         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2062         (address_translation): Raise exception InstructionFetch when
2063         translation fails and isINSTRUCTION.
2064
2065         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2066         sim_engine_run): Change type of of vaddr and paddr to
2067         address_word.
2068         (address_translation, prefetch, load_memory, store_memory,
2069         cache_op): Change type of vAddr and pAddr to address_word.
2070
2071         * gencode.c (build_instruction): Change type of vaddr and paddr to
2072         address_word.
2073
2074 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2075
2076         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2077         macro to obtain result of ALU op.
2078
2079 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2080
2081         * interp.c (sim_info): Call profile_print.
2082
2083 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2084
2085         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2086
2087         * sim-main.h (WITH_PROFILE): Do not define, defined in
2088         common/sim-config.h.  Use sim-profile module.
2089         (simPROFILE): Delete defintion.
2090
2091         * interp.c (PROFILE): Delete definition.
2092         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2093         (sim_close): Delete code writing profile histogram.
2094         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2095         Delete.
2096         (sim_engine_run): Delete code profiling the PC.
2097
2098 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2099
2100         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2101
2102         * interp.c (sim_monitor): Make register pointers of type
2103         unsigned_word*.
2104
2105         * sim-main.h: Make registers of type unsigned_word not
2106         signed_word.
2107
2108 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2109
2110         * interp.c (sync_operation): Rename from SyncOperation, make
2111         global, add SD argument.
2112         (prefetch): Rename from Prefetch, make global, add SD argument.
2113         (decode_coproc): Make global.
2114
2115         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2116
2117         * gencode.c (build_instruction): Generate DecodeCoproc not
2118         decode_coproc calls.
2119
2120         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2121         (SizeFGR): Move to sim-main.h
2122         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2123         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2124         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2125         sim-main.h.
2126         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2127         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2128         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2129         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2130         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2131         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2132
2133         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2134         exception.
2135         (sim-alu.h): Include.
2136         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2137         (sim_cia): Typedef to instruction_address.
2138
2139 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2140
2141         * Makefile.in (interp.o): Rename generated file engine.c to
2142         oengine.c.
2143
2144         * interp.c: Update.
2145
2146 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2147
2148         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2149
2150 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2151
2152         * gencode.c (build_instruction): For "FPSQRT", output correct
2153         number of arguments to Recip.
2154
2155 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2156
2157         * Makefile.in (interp.o): Depends on sim-main.h
2158
2159         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2160
2161         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2162         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2163         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2164         STATE, DSSTATE): Define
2165         (GPR, FGRIDX, ..): Define.
2166
2167         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2168         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2169         (GPR, FGRIDX, ...): Delete macros.
2170
2171         * interp.c: Update names to match defines from sim-main.h
2172
2173 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2174
2175         * interp.c (sim_monitor): Add SD argument.
2176         (sim_warning): Delete.  Replace calls with calls to
2177         sim_io_eprintf.
2178         (sim_error): Delete. Replace calls with sim_io_error.
2179         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2180         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2181         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2182         argument.
2183         (mips_size): Rename from sim_size. Add SD argument.
2184
2185         * interp.c (simulator): Delete global variable.
2186         (callback): Delete global variable.
2187         (mips_option_handler, sim_open, sim_write, sim_read,
2188         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2189         sim_size,sim_monitor): Use sim_io_* not callback->*.
2190         (sim_open): ZALLOC simulator struct.
2191         (PROFILE): Do not define.
2192
2193 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2194
2195         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2196         support.h with corresponding code.
2197
2198         * sim-main.h (word64, uword64), support.h: Move definition to
2199         sim-main.h.
2200         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2201
2202         * support.h: Delete
2203         * Makefile.in: Update dependencies
2204         * interp.c: Do not include.
2205
2206 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2207
2208         * interp.c (address_translation, load_memory, store_memory,
2209         cache_op): Rename to from AddressTranslation et.al., make global,
2210         add SD argument
2211
2212         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2213         CacheOp): Define.
2214
2215         * interp.c (SignalException): Rename to signal_exception, make
2216         global.
2217
2218         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2219
2220         * sim-main.h (SignalException, SignalExceptionInterrupt,
2221         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2222         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2223         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2224         Define.
2225
2226         * interp.c, support.h: Use.
2227
2228 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2229
2230         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2231         to value_fpr / store_fpr. Add SD argument.
2232         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2233         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2234
2235         * sim-main.h (ValueFPR, StoreFPR): Define.
2236
2237 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2238
2239         * interp.c (sim_engine_run): Check consistency between configure
2240         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2241         and HASFPU.
2242
2243         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2244         (mips_fpu): Configure WITH_FLOATING_POINT.
2245         (mips_endian): Configure WITH_TARGET_ENDIAN.
2246         * configure: Update.
2247
2248 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2249
2250         * configure: Regenerated to track ../common/aclocal.m4 changes.
2251
2252 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2253
2254         * configure: Regenerated.
2255
2256 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2257
2258         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2259
2260 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2261
2262         * gencode.c (print_igen_insn_models): Assume certain architectures
2263         include all mips* instructions.
2264         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2265         instruction.
2266
2267         * Makefile.in (tmp.igen): Add target. Generate igen input from
2268         gencode file.
2269
2270         * gencode.c (FEATURE_IGEN): Define.
2271         (main): Add --igen option.  Generate output in igen format.
2272         (process_instructions): Format output according to igen option.
2273         (print_igen_insn_format): New function.
2274         (print_igen_insn_models): New function.
2275         (process_instructions): Only issue warnings and ignore
2276         instructions when no FEATURE_IGEN.
2277
2278 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2279
2280         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2281         MIPS targets.
2282
2283 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2284
2285         * configure: Regenerated to track ../common/aclocal.m4 changes.
2286
2287 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2288
2289         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2290         SIM_RESERVED_BITS): Delete, moved to common.
2291         (SIM_EXTRA_CFLAGS): Update.
2292
2293 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2294
2295         * configure.in: Configure non-strict memory alignment.
2296         * configure: Regenerated to track ../common/aclocal.m4 changes.
2297
2298 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2299
2300         * configure: Regenerated to track ../common/aclocal.m4 changes.
2301
2302 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2303
2304         * gencode.c (SDBBP,DERET): Added (3900) insns.
2305         (RFE): Turn on for 3900.
2306         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2307         (dsstate): Made global.
2308         (SUBTARGET_R3900): Added.
2309         (CANCELDELAYSLOT): New.
2310         (SignalException): Ignore SystemCall rather than ignore and
2311         terminate.  Add DebugBreakPoint handling.
2312         (decode_coproc): New insns RFE, DERET; and new registers Debug
2313         and DEPC protected by SUBTARGET_R3900.
2314         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2315         bits explicitly.
2316         * Makefile.in,configure.in: Add mips subtarget option.
2317         * configure: Update.
2318
2319 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2320
2321         * gencode.c: Add r3900 (tx39).
2322
2323
2324 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2325
2326         * gencode.c (build_instruction): Don't need to subtract 4 for
2327         JALR, just 2.
2328
2329 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2330
2331         * interp.c: Correct some HASFPU problems.
2332
2333 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2334
2335         * configure: Regenerated to track ../common/aclocal.m4 changes.
2336
2337 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2338
2339         * interp.c (mips_options): Fix samples option short form, should
2340         be `x'.
2341
2342 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2343
2344         * interp.c (sim_info): Enable info code.  Was just returning.
2345
2346 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2347
2348         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2349         MFC0.
2350
2351 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2352
2353         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2354         constants.
2355         (build_instruction): Ditto for LL.
2356
2357 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2358
2359         * configure: Regenerated to track ../common/aclocal.m4 changes.
2360
2361 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2362
2363         * configure: Regenerated to track ../common/aclocal.m4 changes.
2364         * config.in: Ditto.
2365
2366 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2367
2368         * interp.c (sim_open): Add call to sim_analyze_program, update
2369         call to sim_config.
2370
2371 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2372
2373         * interp.c (sim_kill): Delete.
2374         (sim_create_inferior): Add ABFD argument. Set PC from same.
2375         (sim_load): Move code initializing trap handlers from here.
2376         (sim_open): To here.
2377         (sim_load): Delete, use sim-hload.c.
2378
2379         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2380
2381 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2382
2383         * configure: Regenerated to track ../common/aclocal.m4 changes.
2384         * config.in: Ditto.
2385
2386 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2387
2388         * interp.c (sim_open): Add ABFD argument.
2389         (sim_load): Move call to sim_config from here.
2390         (sim_open): To here.  Check return status.
2391
2392 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2393
2394         * gencode.c (build_instruction): Two arg MADD should
2395         not assign result to $0.
2396
2397 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2398
2399         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2400         * sim/mips/configure.in: Regenerate.
2401
2402 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2403
2404         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2405         signed8, unsigned8 et.al. types.
2406
2407         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2408         hosts when selecting subreg.
2409
2410 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2411
2412         * interp.c (sim_engine_run): Reset the ZERO register to zero
2413         regardless of FEATURE_WARN_ZERO.
2414         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2415
2416 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2417
2418         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2419         (SignalException): For BreakPoints ignore any mode bits and just
2420         save the PC.
2421         (SignalException): Always set the CAUSE register.
2422
2423 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2424
2425         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2426         exception has been taken.
2427
2428         * interp.c: Implement the ERET and mt/f sr instructions.
2429
2430 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2431
2432         * interp.c (SignalException): Don't bother restarting an
2433         interrupt.
2434
2435 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2436
2437         * interp.c (SignalException): Really take an interrupt.
2438         (interrupt_event): Only deliver interrupts when enabled.
2439
2440 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2441
2442         * interp.c (sim_info): Only print info when verbose.
2443         (sim_info) Use sim_io_printf for output.
2444
2445 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2446
2447         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2448         mips architectures.
2449
2450 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2451
2452         * interp.c (sim_do_command): Check for common commands if a
2453         simulator specific command fails.
2454
2455 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2456
2457         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2458         and simBE when DEBUG is defined.
2459
2460 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2461
2462         * interp.c (interrupt_event): New function.  Pass exception event
2463         onto exception handler.
2464
2465         * configure.in: Check for stdlib.h.
2466         * configure: Regenerate.
2467
2468         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2469         variable declaration.
2470         (build_instruction): Initialize memval1.
2471         (build_instruction): Add UNUSED attribute to byte, bigend,
2472         reverse.
2473         (build_operands): Ditto.
2474
2475         * interp.c: Fix GCC warnings.
2476         (sim_get_quit_code): Delete.
2477
2478         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2479         * Makefile.in: Ditto.
2480         * configure: Re-generate.
2481
2482         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2483
2484 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2485
2486         * interp.c (mips_option_handler): New function parse argumes using
2487         sim-options.
2488         (myname): Replace with STATE_MY_NAME.
2489         (sim_open): Delete check for host endianness - performed by
2490         sim_config.
2491         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2492         (sim_open): Move much of the initialization from here.
2493         (sim_load): To here.  After the image has been loaded and
2494         endianness set.
2495         (sim_open): Move ColdReset from here.
2496         (sim_create_inferior): To here.
2497         (sim_open): Make FP check less dependant on host endianness.
2498
2499         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2500         run.
2501         * interp.c (sim_set_callbacks): Delete.
2502
2503         * interp.c (membank, membank_base, membank_size): Replace with
2504         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2505         (sim_open): Remove call to callback->init. gdb/run do this.
2506
2507         * interp.c: Update
2508
2509         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2510
2511         * interp.c (big_endian_p): Delete, replaced by
2512         current_target_byte_order.
2513
2514 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2515
2516         * interp.c (host_read_long, host_read_word, host_swap_word,
2517         host_swap_long): Delete. Using common sim-endian.
2518         (sim_fetch_register, sim_store_register): Use H2T.
2519         (pipeline_ticks): Delete.  Handled by sim-events.
2520         (sim_info): Update.
2521         (sim_engine_run): Update.
2522
2523 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2524
2525         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2526         reason from here.
2527         (SignalException): To here. Signal using sim_engine_halt.
2528         (sim_stop_reason): Delete, moved to common.
2529
2530 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2531
2532         * interp.c (sim_open): Add callback argument.
2533         (sim_set_callbacks): Delete SIM_DESC argument.
2534         (sim_size): Ditto.
2535
2536 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2537
2538         * Makefile.in (SIM_OBJS): Add common modules.
2539
2540         * interp.c (sim_set_callbacks): Also set SD callback.
2541         (set_endianness, xfer_*, swap_*): Delete.
2542         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2543         Change to functions using sim-endian macros.
2544         (control_c, sim_stop): Delete, use common version.
2545         (simulate): Convert into.
2546         (sim_engine_run): This function.
2547         (sim_resume): Delete.
2548
2549         * interp.c (simulation): New variable - the simulator object.
2550         (sim_kind): Delete global - merged into simulation.
2551         (sim_load): Cleanup.  Move PC assignment from here.
2552         (sim_create_inferior): To here.
2553
2554         * sim-main.h: New file.
2555         * interp.c (sim-main.h): Include.
2556
2557 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2558
2559         * configure: Regenerated to track ../common/aclocal.m4 changes.
2560
2561 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2562
2563         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2564
2565 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2566
2567         * gencode.c (build_instruction): DIV instructions: check
2568         for division by zero and integer overflow before using
2569         host's division operation.
2570
2571 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2572
2573         * Makefile.in (SIM_OBJS): Add sim-load.o.
2574         * interp.c: #include bfd.h.
2575         (target_byte_order): Delete.
2576         (sim_kind, myname, big_endian_p): New static locals.
2577         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2578         after argument parsing.  Recognize -E arg, set endianness accordingly.
2579         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2580         load file into simulator.  Set PC from bfd.
2581         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2582         (set_endianness): Use big_endian_p instead of target_byte_order.
2583
2584 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2585
2586         * interp.c (sim_size): Delete prototype - conflicts with
2587         definition in remote-sim.h.  Correct definition.
2588
2589 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2590
2591         * configure: Regenerated to track ../common/aclocal.m4 changes.
2592         * config.in: Ditto.
2593
2594 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2595
2596         * interp.c (sim_open): New arg `kind'.
2597
2598         * configure: Regenerated to track ../common/aclocal.m4 changes.
2599
2600 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2601
2602         * configure: Regenerated to track ../common/aclocal.m4 changes.
2603
2604 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2605
2606         * interp.c (sim_open): Set optind to 0 before calling getopt.
2607
2608 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2609
2610         * configure: Regenerated to track ../common/aclocal.m4 changes.
2611
2612 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2613
2614         * interp.c : Replace uses of pr_addr with pr_uword64
2615         where the bit length is always 64 independent of SIM_ADDR.
2616         (pr_uword64) : added.
2617
2618 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2619
2620         * configure: Re-generate.
2621
2622 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2623
2624         * configure: Regenerate to track ../common/aclocal.m4 changes.
2625
2626 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2627
2628         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2629         in argv form.
2630         (other sim_*): New SIM_DESC argument.
2631
2632 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2633
2634         * interp.c: Fix printing of addresses for non-64-bit targets.
2635         (pr_addr): Add function to print address based on size.
2636
2637 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2638
2639         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2640
2641 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2642
2643         * gencode.c (build_mips16_operands): Correct computation of base
2644         address for extended PC relative instruction.
2645
2646 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2647
2648         * interp.c (mips16_entry): Add support for floating point cases.
2649         (SignalException): Pass floating point cases to mips16_entry.
2650         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2651         registers.
2652         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2653         or fmt_word.
2654         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2655         and then set the state to fmt_uninterpreted.
2656         (COP_SW): Temporarily set the state to fmt_word while calling
2657         ValueFPR.
2658
2659 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2660
2661         * gencode.c (build_instruction): The high order may be set in the
2662         comparison flags at any ISA level, not just ISA 4.
2663
2664 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2665
2666         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2667         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2668         * configure.in: sinclude ../common/aclocal.m4.
2669         * configure: Regenerated.
2670
2671 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2672
2673         * configure: Rebuild after change to aclocal.m4.
2674
2675 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2676
2677         * configure configure.in Makefile.in:  Update to new configure
2678         scheme which is more compatible with WinGDB builds.
2679         * configure.in:  Improve comment on how to run autoconf.
2680         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2681         * Makefile.in:  Use autoconf substitution to install common
2682         makefile fragment.
2683
2684 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2685
2686         * gencode.c (build_instruction): Use BigEndianCPU instead of
2687         ByteSwapMem.
2688
2689 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2690
2691         * interp.c (sim_monitor): Make output to stdout visible in
2692         wingdb's I/O log window.
2693
2694 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2695
2696         * support.h: Undo previous change to SIGTRAP
2697         and SIGQUIT values.
2698
2699 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2700
2701         * interp.c (store_word, load_word): New static functions.
2702         (mips16_entry): New static function.
2703         (SignalException): Look for mips16 entry and exit instructions.
2704         (simulate): Use the correct index when setting fpr_state after
2705         doing a pending move.
2706
2707 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2708
2709         * interp.c: Fix byte-swapping code throughout to work on
2710         both little- and big-endian hosts.
2711
2712 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2713
2714         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2715         with gdb/config/i386/xm-windows.h.
2716
2717 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2718
2719         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2720         that messes up arithmetic shifts.
2721
2722 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2723
2724         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2725         SIGTRAP and SIGQUIT for _WIN32.
2726
2727 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2728
2729         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2730         force a 64 bit multiplication.
2731         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2732         destination register is 0, since that is the default mips16 nop
2733         instruction.
2734
2735 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2736
2737         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2738         (build_endian_shift): Don't check proc64.
2739         (build_instruction): Always set memval to uword64.  Cast op2 to
2740         uword64 when shifting it left in memory instructions.  Always use
2741         the same code for stores--don't special case proc64.
2742
2743         * gencode.c (build_mips16_operands): Fix base PC value for PC
2744         relative operands.
2745         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2746         jal instruction.
2747         * interp.c (simJALDELAYSLOT): Define.
2748         (JALDELAYSLOT): Define.
2749         (INDELAYSLOT, INJALDELAYSLOT): Define.
2750         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2751
2752 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2753
2754         * interp.c (sim_open): add flush_cache as a PMON routine
2755         (sim_monitor): handle flush_cache by ignoring it
2756
2757 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2758
2759         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2760         BigEndianMem.
2761         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2762         (BigEndianMem): Rename to ByteSwapMem and change sense.
2763         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2764         BigEndianMem references to !ByteSwapMem.
2765         (set_endianness): New function, with prototype.
2766         (sim_open): Call set_endianness.
2767         (sim_info): Use simBE instead of BigEndianMem.
2768         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2769         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2770         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2771         ifdefs, keeping the prototype declaration.
2772         (swap_word): Rewrite correctly.
2773         (ColdReset): Delete references to CONFIG.  Delete endianness related
2774         code; moved to set_endianness.
2775
2776 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2777
2778         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2779         * interp.c (CHECKHILO): Define away.
2780         (simSIGINT): New macro.
2781         (membank_size): Increase from 1MB to 2MB.
2782         (control_c): New function.
2783         (sim_resume): Rename parameter signal to signal_number.  Add local
2784         variable prev.  Call signal before and after simulate.
2785         (sim_stop_reason): Add simSIGINT support.
2786         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2787         functions always.
2788         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2789         if logfh is NULL.
2790         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2791         a call to sim_warning.
2792
2793 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2794
2795         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2796         16 bit instructions.
2797
2798 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2799
2800         Add support for mips16 (16 bit MIPS implementation):
2801         * gencode.c (inst_type): Add mips16 instruction encoding types.
2802         (GETDATASIZEINSN): Define.
2803         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2804         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2805         mtlo.
2806         (MIPS16_DECODE): New table, for mips16 instructions.
2807         (bitmap_val): New static function.
2808         (struct mips16_op): Define.
2809         (mips16_op_table): New table, for mips16 operands.
2810         (build_mips16_operands): New static function.
2811         (process_instructions): If PC is odd, decode a mips16
2812         instruction.  Break out instruction handling into new
2813         build_instruction function.
2814         (build_instruction): New static function, broken out of
2815         process_instructions.  Check modifiers rather than flags for SHIFT
2816         bit count and m[ft]{hi,lo} direction.
2817         (usage): Pass program name to fprintf.
2818         (main): Remove unused variable this_option_optind.  Change
2819         ``*loptarg++'' to ``loptarg++''.
2820         (my_strtoul): Parenthesize && within ||.
2821         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2822         (simulate): If PC is odd, fetch a 16 bit instruction, and
2823         increment PC by 2 rather than 4.
2824         * configure.in: Add case for mips16*-*-*.
2825         * configure: Rebuild.
2826
2827 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2828
2829         * interp.c: Allow -t to enable tracing in standalone simulator.
2830         Fix garbage output in trace file and error messages.
2831
2832 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2833
2834         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2835         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2836         * configure.in: Simplify using macros in ../common/aclocal.m4.
2837         * configure: Regenerated.
2838         * tconfig.in: New file.
2839
2840 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2841
2842         * interp.c: Fix bugs in 64-bit port.
2843         Use ansi function declarations for msvc compiler.
2844         Initialize and test file pointer in trace code.
2845         Prevent duplicate definition of LAST_EMED_REGNUM.
2846
2847 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2848
2849         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2850
2851 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2852
2853         * interp.c (SignalException): Check for explicit terminating
2854         breakpoint value.
2855         * gencode.c: Pass instruction value through SignalException()
2856         calls for Trap, Breakpoint and Syscall.
2857
2858 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2859
2860         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2861         only used on those hosts that provide it.
2862         * configure.in: Add sqrt() to list of functions to be checked for.
2863         * config.in: Re-generated.
2864         * configure: Re-generated.
2865
2866 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2867
2868         * gencode.c (process_instructions): Call build_endian_shift when
2869         expanding STORE RIGHT, to fix swr.
2870         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2871         clear the high bits.
2872         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2873         Fix float to int conversions to produce signed values.
2874
2875 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2876
2877         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2878         (process_instructions): Correct handling of nor instruction.
2879         Correct shift count for 32 bit shift instructions. Correct sign
2880         extension for arithmetic shifts to not shift the number of bits in
2881         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2882         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2883         Fix madd.
2884         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2885         It's OK to have a mult follow a mult.  What's not OK is to have a
2886         mult follow an mfhi.
2887         (Convert): Comment out incorrect rounding code.
2888
2889 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2890
2891         * interp.c (sim_monitor): Improved monitor printf
2892         simulation. Tidied up simulator warnings, and added "--log" option
2893         for directing warning message output.
2894         * gencode.c: Use sim_warning() rather than WARNING macro.
2895
2896 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2897
2898         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2899         getopt1.o, rather than on gencode.c.  Link objects together.
2900         Don't link against -liberty.
2901         (gencode.o, getopt.o, getopt1.o): New targets.
2902         * gencode.c: Include <ctype.h> and "ansidecl.h".
2903         (AND): Undefine after including "ansidecl.h".
2904         (ULONG_MAX): Define if not defined.
2905         (OP_*): Don't define macros; now defined in opcode/mips.h.
2906         (main): Call my_strtoul rather than strtoul.
2907         (my_strtoul): New static function.
2908
2909 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2910
2911         * gencode.c (process_instructions):  Generate word64 and uword64
2912         instead of `long long' and `unsigned long long' data types.
2913         * interp.c:  #include sysdep.h to get signals, and define default
2914         for SIGBUS.
2915         * (Convert):  Work around for Visual-C++ compiler bug with type
2916         conversion.
2917         * support.h:  Make things compile under Visual-C++ by using
2918         __int64 instead of `long long'.  Change many refs to long long
2919         into word64/uword64 typedefs.
2920
2921 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2922
2923         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2924         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2925         (docdir): Removed.
2926         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2927         (AC_PROG_INSTALL): Added.
2928         (AC_PROG_CC): Moved to before configure.host call.
2929         * configure: Rebuilt.
2930
2931 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2932
2933         * configure.in: Define @SIMCONF@ depending on mips target.
2934         * configure: Rebuild.
2935         * Makefile.in (run): Add @SIMCONF@ to control simulator
2936         construction.
2937         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2938         * interp.c: Remove some debugging, provide more detailed error
2939         messages, update memory accesses to use LOADDRMASK.
2940
2941 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2942
2943         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2944         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2945         stamp-h.
2946         * configure: Rebuild.
2947         * config.in: New file, generated by autoheader.
2948         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2949         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2950         HAVE_ANINT and HAVE_AINT, as appropriate.
2951         * Makefile.in (run): Use @LIBS@ rather than -lm.
2952         (interp.o): Depend upon config.h.
2953         (Makefile): Just rebuild Makefile.
2954         (clean): Remove stamp-h.
2955         (mostlyclean): Make the same as clean, not as distclean.
2956         (config.h, stamp-h): New targets.
2957
2958 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2959
2960         * interp.c (ColdReset): Fix boolean test. Make all simulator
2961         globals static.
2962
2963 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2964
2965         * interp.c (xfer_direct_word, xfer_direct_long,
2966         swap_direct_word, swap_direct_long, xfer_big_word,
2967         xfer_big_long, xfer_little_word, xfer_little_long,
2968         swap_word,swap_long): Added.
2969         * interp.c (ColdReset): Provide function indirection to
2970         host<->simulated_target transfer routines.
2971         * interp.c (sim_store_register, sim_fetch_register): Updated to
2972         make use of indirected transfer routines.
2973
2974 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2975
2976         * gencode.c (process_instructions): Ensure FP ABS instruction
2977         recognised.
2978         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2979         system call support.
2980
2981 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2982
2983         * interp.c (sim_do_command): Complain if callback structure not
2984         initialised.
2985
2986 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2987
2988         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2989         support for Sun hosts.
2990         * Makefile.in (gencode): Ensure the host compiler and libraries
2991         used for cross-hosted build.
2992
2993 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2994
2995         * interp.c, gencode.c: Some more (TODO) tidying.
2996
2997 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2998
2999         * gencode.c, interp.c: Replaced explicit long long references with
3000         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3001         * support.h (SET64LO, SET64HI): Macros added.
3002
3003 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3004
3005         * configure: Regenerate with autoconf 2.7.
3006
3007 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3008
3009         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3010         * support.h: Remove superfluous "1" from #if.
3011         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3012
3013 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3014
3015         * interp.c (StoreFPR): Control UndefinedResult() call on
3016         WARN_RESULT manifest.
3017
3018 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3019
3020         * gencode.c: Tidied instruction decoding, and added FP instruction
3021         support.
3022
3023         * interp.c: Added dineroIII, and BSD profiling support. Also
3024         run-time FP handling.
3025
3026 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3027
3028         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3029         gencode.c, interp.c, support.h: created.