1 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
3 * gencode.c: Mark BEGEZALL as LIKELY.
5 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
7 * sim-main.h (ALU32_END): Sign extend 32 bit results.
8 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
11 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
13 * interp.c (sim_fetch_register): Convert internal r5900 regs to
17 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
19 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
20 modules. Recognize TX39 target with "mips*tx39" pattern.
22 * sim-main.h (*): Added many macros defining bits in
23 TX39 control registers.
24 (SignalInterrupt): Send actual PC instead of NULL.
25 (SignalNMIReset): New exception type.
26 * interp.c (board): New variable for future use to identify
27 a particular board being simulated.
28 (mips_option_handler,mips_options): Added "--board" option.
29 (interrupt_event): Send actual PC.
30 (sim_open): Make memory layout conditional on board setting.
31 (signal_exception): Initial implementation of hardware interrupt
32 handling. Accept another break instruction variant for simulator
34 (decode_coproc): Implement RFE instruction for TX39.
35 (mips.igen): Decode RFE instruction as such.
37 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
38 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
39 bbegin to implement memory map.
40 * dv-tx3904cpu.c: New file.
41 * dv-tx3904irc.c: New file.
44 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
46 * mips.igen (check_mt_hilo): Create a separate r3900 version.
49 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
51 * r5900.igen: Replace the calls and the definition of the
52 function check_op_hilo_hi1lo1 with the pair
53 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
56 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
58 * tx.igen (madd,maddu): Replace calls to check_op_hilo
59 with calls to check_div_hilo.
61 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
63 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
64 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
65 Add special r3900 version of do_mult_hilo.
66 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
67 with calls to check_mult_hilo.
68 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
69 with calls to check_div_hilo.
71 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
73 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
74 Document a replacement.
76 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
78 * interp.c (sim_monitor): Make mon_printf work.
80 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
82 * sim-main.h (INSN_NAME): New arg `cpu'.
85 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
87 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
92 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
94 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
95 * r5900.igen (r59fp_overflow): Use.
97 * r5900.igen (r59fp_op3): Rename to
98 (r59fp_mula): This, delete opm argument.
99 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
100 (r59fp_mula): Overflowing product propogates through to result.
101 (r59fp_mula): ACC to the MAX propogates to result.
102 (r59fp_mula): Underflow during multiply only sets SU.
105 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
107 * configure: Regenerated to track ../common/aclocal.m4 changes.
109 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
111 * configure: Regenerated to track ../common/aclocal.m4 changes.
114 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
116 * acconfig.h: New file.
117 * configure.in: Reverted change of Apr 24; use sinclude again.
119 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
121 * configure: Regenerated to track ../common/aclocal.m4 changes.
124 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
126 * configure.in: Don't call sinclude.
128 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
130 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
132 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
134 * mips.igen (ERET): Implement.
136 * interp.c (decode_coproc): Return sign-extended EPC.
138 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
140 * interp.c (signal_exception): Do not ignore Trap.
141 (signal_exception): On TRAP, restart at exception address.
142 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
143 (signal_exception): Update.
144 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
145 so that TRAP instructions are caught.
147 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
149 * sim-main.h (struct hilo_access, struct hilo_history): Define,
150 contains HI/LO access history.
151 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
152 (HIACCESS, LOACCESS): Delete, replace with
153 (HIHISTORY, LOHISTORY): New macros.
154 (start-sanitize-r5900):
155 (struct sim_5900_cpu): Make hi1access, lo1access of type
157 (HI1ACCESS, LO1ACCESS): Delete, replace with
158 (HI1HISTORY, LO1HISTORY): New macros.
159 (end-sanitize-r5900):
160 (CHECKHILO): Delete all, moved to mips.igen
162 * gencode.c (build_instruction): Do not generate checks for
163 correct HI/LO register usage.
165 * interp.c (old_engine_run): Delete checks for correct HI/LO
168 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
169 check_mf_cycles): New functions.
170 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
171 do_divu, domultx, do_mult, do_multu): Use.
173 * tx.igen ("madd", "maddu"): Use.
174 (start-sanitize-r5900):
176 r5900.igen: Update all HI/LO checks.
177 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
178 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
179 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
180 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
181 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
183 (end-sanitize-r5900):
186 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
188 * interp.c (decode_coproc): Correct CMFC2/QMTC2
191 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
192 instead of a single 128-bit access.
196 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
198 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
199 * interp.c (cop_[ls]q): Fixes corresponding to above.
203 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
205 * interp.c (decode_coproc): Adapt COP2 micro interlock to
206 clarified specs. Reset "M" bit; exit also on "E" bit.
210 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
212 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
213 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
215 * r5900.igen (r59fp_unpack): New function.
216 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
217 RSQRT.S, SQRT.S): Use.
218 (r59fp_zero): New function.
219 (r59fp_overflow): Generate r5900 specific overflow value.
220 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
222 (CVT.S.W, CVT.W.S): Exchange implementations.
224 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
228 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
230 * configure.in (tx19, sim_use_gen): Switch to igen.
231 * configure: Re-build.
235 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
237 * interp.c (decode_coproc): Make COP2 branch code compile after
238 igen signature changes.
241 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
243 * mips.igen (DSRAV): Use function do_dsrav.
244 (SRAV): Use new function do_srav.
246 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
247 (B): Sign extend 11 bit immediate.
248 (EXT-B*): Shift 16 bit immediate left by 1.
249 (ADDIU*): Don't sign extend immediate value.
251 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
253 * m16run.c (sim_engine_run): Restore CIA after handling an event.
256 * mips.igen (mtc0): Valid tx19 instruction.
259 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
262 * mips.igen (delayslot32, nullify_next_insn): New functions.
263 (m16.igen): Always include.
264 (do_*): Add more tracing.
266 * m16.igen (delayslot16): Add NIA argument, could be called by a
267 32 bit MIPS16 instruction.
269 * interp.c (ifetch16): Move function from here.
270 * sim-main.c (ifetch16): To here.
272 * sim-main.c (ifetch16, ifetch32): Update to match current
273 implementations of LH, LW.
274 (signal_exception): Don't print out incorrect hex value of illegal
277 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
279 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
282 * m16.igen: Implement MIPS16 instructions.
284 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
285 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
286 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
287 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
288 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
289 bodies of corresponding code from 32 bit insn to these. Also used
290 by MIPS16 versions of functions.
292 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
293 (IMEM16): Drop NR argument from macro.
296 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
298 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
299 of VU lower instruction.
303 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
305 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
308 * sim-main.h: Removed attempt at allowing 128-bit access.
312 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
314 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
316 * interp.c (decode_coproc): Refer to VU CIA as a "special"
317 register, not as a "misc" register. Aha. Add activity
318 assertions after VCALLMS* instructions.
322 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
324 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
325 to upper code of generated VU instruction.
329 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
331 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
333 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
336 * r5900.igen (SQC2): Thinko.
340 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
342 * interp.c (*): Adapt code to merged VU device & state structs.
343 (decode_coproc): Execute COP2 each macroinstruction without
344 pipelining, by stepping VU to completion state. Adapted to
345 read_vu_*_reg style of register access.
347 * mips.igen ([SL]QC2): Removed these COP2 instructions.
349 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
351 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
354 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
356 * Makefile.in (SIM_OBJS): Add sim-main.o.
358 * sim-main.h (address_translation, load_memory, store_memory,
359 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
361 (pr_addr, pr_uword64): Declare.
362 (sim-main.c): Include when H_REVEALS_MODULE_P.
364 * interp.c (address_translation, load_memory, store_memory,
365 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
367 * sim-main.c: To here. Fix compilation problems.
369 * configure.in: Enable inlining.
370 * configure: Re-config.
372 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
374 * configure: Regenerated to track ../common/aclocal.m4 changes.
376 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
378 * mips.igen: Include tx.igen.
379 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
380 * tx.igen: New file, contains MADD and MADDU.
382 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
383 the hardwired constant `7'.
384 (store_memory): Ditto.
385 (LOADDRMASK): Move definition to sim-main.h.
387 mips.igen (MTC0): Enable for r3900.
390 mips.igen (do_load_byte): Delete.
391 (do_load, do_store, do_load_left, do_load_write, do_store_left,
392 do_store_right): New functions.
393 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
395 configure.in: Let the tx39 use igen again.
398 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
400 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
401 not an address sized quantity. Return zero for cache sizes.
403 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
405 * mips.igen (r3900): r3900 does not support 64 bit integer
409 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
411 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
415 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
417 * interp.c (decode_coproc): Continuing COP2 work.
418 (cop_[ls]q): Make sky-target-only.
420 * sim-main.h (COP_[LS]Q): Make sky-target-only.
422 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
424 * configure.in (mipstx39*-*-*): Use gencode simulator rather
426 * configure : Rebuild.
429 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
431 * interp.c (decode_coproc): Added a missing TARGET_SKY check
432 around COP2 implementation skeleton.
436 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
438 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
440 * interp.c (sim_{load,store}_register): Use new vu[01]_device
441 static to access VU registers.
442 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
443 decoding. Work in progress.
445 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
446 overlapping/redundant bit pattern.
447 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
450 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
453 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
454 access to coprocessor registers.
456 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
458 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
460 * configure: Regenerated to track ../common/aclocal.m4 changes.
462 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
464 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
466 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
468 * configure: Regenerated to track ../common/aclocal.m4 changes.
469 * config.in: Regenerated to track ../common/aclocal.m4 changes.
471 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
473 * configure: Regenerated to track ../common/aclocal.m4 changes.
475 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
477 * interp.c (Max, Min): Comment out functions. Not yet used.
479 start-sanitize-vr4320
480 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
482 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
485 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
487 * configure: Regenerated to track ../common/aclocal.m4 changes.
489 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
491 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
492 configurable settings for stand-alone simulator.
495 * configure.in: Added --with-sim-gpu2 option to specify path of
496 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
497 links/compiles stand-alone simulator with this library.
499 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
501 * configure.in: Added X11 search, just in case.
503 * configure: Regenerated.
505 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
507 * interp.c (sim_write, sim_read, load_memory, store_memory):
508 Replace sim_core_*_map with read_map, write_map, exec_map resp.
510 start-sanitize-vr4320
511 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
513 * vr4320.igen (clz,dclz) : Added.
514 (dmac): Replaced 99, with LO.
517 start-sanitize-vr5400
518 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
520 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
523 start-sanitize-vr4320
524 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
526 * vr4320.igen: New file.
527 * Makefile.in (vr4320.igen) : Added.
528 * configure.in (mips64vr4320-*-*): Added.
529 * configure : Rebuilt.
530 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
531 Add the vr4320 model entry and mark the vr4320 insn as necessary.
534 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
536 * sim-main.h (GETFCC): Return an unsigned value.
539 * r5900.igen: Use an unsigned array index variable `i'.
540 (QFSRV): Ditto for variable bytes.
543 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
545 * mips.igen (DIV): Fix check for -1 / MIN_INT.
546 (DADD): Result destination is RD not RT.
549 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
550 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
554 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
556 * sim-main.h (HIACCESS, LOACCESS): Always define.
558 * mdmx.igen (Maxi, Mini): Rename Max, Min.
560 * interp.c (sim_info): Delete.
562 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
564 * interp.c (DECLARE_OPTION_HANDLER): Use it.
565 (mips_option_handler): New argument `cpu'.
566 (sim_open): Update call to sim_add_option_table.
568 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
570 * mips.igen (CxC1): Add tracing.
573 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
575 * r5900.igen (StoreFP): Delete.
576 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
578 (rsqrt.s, sqrt.s): Implement.
579 (r59cond): New function.
580 (C.COND.S): Call r59cond in assembler line.
581 (cvt.w.s, cvt.s.w): Implement.
583 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
586 * sim-main.h: Define an enum of r5900 FCSR bit fields.
590 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
592 * r5900.igen: Add tracing to all p* instructions.
594 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
596 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
597 to get gdb talking to re-aranged sim_cpu register structure.
600 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
602 * sim-main.h (Max, Min): Declare.
604 * interp.c (Max, Min): New functions.
606 * mips.igen (BC1): Add tracing.
608 start-sanitize-vr5400
609 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
611 * mdmx.igen: Tag all functions as requiring either with mdmx or
616 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
618 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
620 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
622 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
624 * r5900.igen: Rewrite.
626 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
628 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
629 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
632 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
634 * interp.c Added memory map for stack in vr4100
636 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
638 * interp.c (load_memory): Add missing "break"'s.
640 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
642 * interp.c (sim_store_register, sim_fetch_register): Pass in
643 length parameter. Return -1.
645 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
647 * interp.c: Added hardware init hook, fixed warnings.
649 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
651 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
653 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
655 * interp.c (ifetch16): New function.
657 * sim-main.h (IMEM32): Rename IMEM.
658 (IMEM16_IMMED): Define.
660 (DELAY_SLOT): Update.
662 * m16run.c (sim_engine_run): New file.
664 * m16.igen: All instructions except LB.
665 (LB): Call do_load_byte.
666 * mips.igen (do_load_byte): New function.
667 (LB): Call do_load_byte.
669 * mips.igen: Move spec for insn bit size and high bit from here.
670 * Makefile.in (tmp-igen, tmp-m16): To here.
672 * m16.dc: New file, decode mips16 instructions.
674 * Makefile.in (SIM_NO_ALL): Define.
675 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
678 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
682 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
684 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
685 point unit to 32 bit registers.
686 * configure: Re-generate.
688 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
690 * configure.in (sim_use_gen): Make IGEN the default simulator
691 generator for generic 32 and 64 bit mips targets.
692 * configure: Re-generate.
694 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
696 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
699 * interp.c (sim_fetch_register, sim_store_register): Read/write
700 FGR from correct location.
701 (sim_open): Set size of FGR's according to
702 WITH_TARGET_FLOATING_POINT_BITSIZE.
704 * sim-main.h (FGR): Store floating point registers in a separate
707 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
709 * configure: Regenerated to track ../common/aclocal.m4 changes.
711 start-sanitize-vr5400
712 * mdmx.igen: Mark all instructions as 64bit/fp specific.
715 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
717 * interp.c (ColdReset): Call PENDING_INVALIDATE.
719 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
721 * interp.c (pending_tick): New function. Deliver pending writes.
723 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
724 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
725 it can handle mixed sized quantites and single bits.
727 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
729 * interp.c (oengine.h): Do not include when building with IGEN.
730 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
731 (sim_info): Ditto for PROCESSOR_64BIT.
732 (sim_monitor): Replace ut_reg with unsigned_word.
733 (*): Ditto for t_reg.
734 (LOADDRMASK): Define.
735 (sim_open): Remove defunct check that host FP is IEEE compliant,
736 using software to emulate floating point.
737 (value_fpr, ...): Always compile, was conditional on HASFPU.
739 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
741 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
744 * interp.c (SD, CPU): Define.
745 (mips_option_handler): Set flags in each CPU.
746 (interrupt_event): Assume CPU 0 is the one being iterrupted.
747 (sim_close): Do not clear STATE, deleted anyway.
748 (sim_write, sim_read): Assume CPU zero's vm should be used for
750 (sim_create_inferior): Set the PC for all processors.
751 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
753 (mips16_entry): Pass correct nr of args to store_word, load_word.
754 (ColdReset): Cold reset all cpu's.
755 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
756 (sim_monitor, load_memory, store_memory, signal_exception): Use
757 `CPU' instead of STATE_CPU.
760 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
763 * sim-main.h (signal_exception): Add sim_cpu arg.
764 (SignalException*): Pass both SD and CPU to signal_exception.
765 * interp.c (signal_exception): Update.
767 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
769 (sync_operation, prefetch, cache_op, store_memory, load_memory,
770 address_translation): Ditto
771 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
773 start-sanitize-vr5400
774 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
776 (ByteAlign): Use StoreFPR, pass args in correct order.
780 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
782 * configure.in (sim_igen_filter): For r5900, configure as SMP.
785 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
787 * configure: Regenerated to track ../common/aclocal.m4 changes.
789 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
792 * configure.in (sim_igen_filter): For r5900, use igen.
793 * configure: Re-generate.
796 * interp.c (sim_engine_run): Add `nr_cpus' argument.
798 * mips.igen (model): Map processor names onto BFD name.
800 * sim-main.h (CPU_CIA): Delete.
801 (SET_CIA, GET_CIA): Define
803 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
805 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
808 * configure.in (default_endian): Configure a big-endian simulator
810 * configure: Re-generate.
812 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
814 * configure: Regenerated to track ../common/aclocal.m4 changes.
816 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
818 * interp.c (sim_monitor): Handle Densan monitor outbyte
819 and inbyte functions.
821 1997-12-29 Felix Lee <flee@cygnus.com>
823 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
825 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
827 * Makefile.in (tmp-igen): Arrange for $zero to always be
828 reset to zero after every instruction.
830 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
832 * configure: Regenerated to track ../common/aclocal.m4 changes.
835 start-sanitize-vr5400
836 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
838 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
842 start-sanitize-vr5400
843 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
845 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
846 vr5400 with the vr5000 as the default.
849 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
851 * mips.igen (MSUB): Fix to work like MADD.
852 * gencode.c (MSUB): Similarly.
854 start-sanitize-vr5400
855 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
857 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
861 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
863 * configure: Regenerated to track ../common/aclocal.m4 changes.
865 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
867 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
869 start-sanitize-vr5400
870 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
871 (value_cc, store_cc): Implement.
873 * sim-main.h: Add 8*3*8 bit accumulator.
875 * vr5400.igen: Move mdmx instructins from here
876 * mdmx.igen: To here - new file. Add/fix missing instructions.
877 * mips.igen: Include mdmx.igen.
878 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
881 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
883 * sim-main.h (sim-fpu.h): Include.
885 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
886 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
887 using host independant sim_fpu module.
889 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
891 * interp.c (signal_exception): Report internal errors with SIGABRT
894 * sim-main.h (C0_CONFIG): New register.
895 (signal.h): No longer include.
897 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
899 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
901 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
903 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
905 * mips.igen: Tag vr5000 instructions.
906 (ANDI): Was missing mipsIV model, fix assembler syntax.
907 (do_c_cond_fmt): New function.
908 (C.cond.fmt): Handle mips I-III which do not support CC field
910 (bc1): Handle mips IV which do not have a delaed FCC separatly.
911 (SDR): Mask paddr when BigEndianMem, not the converse as specified
913 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
914 vr5000 which saves LO in a GPR separatly.
916 * configure.in (enable-sim-igen): For vr5000, select vr5000
917 specific instructions.
918 * configure: Re-generate.
920 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
922 * Makefile.in (SIM_OBJS): Add sim-fpu module.
924 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
925 fmt_uninterpreted_64 bit cases to switch. Convert to
928 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
930 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
931 as specified in IV3.2 spec.
932 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
934 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
936 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
937 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
938 (start-sanitize-r5900):
939 (LWXC1, SWXC1): Delete from r5900 instruction set.
940 (end-sanitize-r5900):
941 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
942 PENDING_FILL versions of instructions. Simplify.
944 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
946 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
948 (MTHI, MFHI): Disable code checking HI-LO.
950 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
952 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
954 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
956 * gencode.c (build_mips16_operands): Replace IPC with cia.
958 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
959 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
961 (UndefinedResult): Replace function with macro/function
963 (sim_engine_run): Don't save PC in IPC.
965 * sim-main.h (IPC): Delete.
967 start-sanitize-vr5400
968 * vr5400.igen (vr): Add missing cia argument to value_fpr.
969 (do_select): Rename function select.
972 * interp.c (signal_exception, store_word, load_word,
973 address_translation, load_memory, store_memory, cache_op,
974 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
975 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
976 current instruction address - cia - argument.
977 (sim_read, sim_write): Call address_translation directly.
978 (sim_engine_run): Rename variable vaddr to cia.
979 (signal_exception): Pass cia to sim_monitor
981 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
982 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
983 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
985 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
986 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
989 * interp.c (signal_exception): Pass restart address to
992 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
993 idecode.o): Add dependency.
995 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
997 (DELAY_SLOT): Update NIA not PC with branch address.
998 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1000 * mips.igen: Use CIA not PC in branch calculations.
1001 (illegal): Call SignalException.
1002 (BEQ, ADDIU): Fix assembler.
1004 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1006 * m16.igen (JALX): Was missing.
1008 * configure.in (enable-sim-igen): New configuration option.
1009 * configure: Re-generate.
1011 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1013 * interp.c (load_memory, store_memory): Delete parameter RAW.
1014 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1015 bypassing {load,store}_memory.
1017 * sim-main.h (ByteSwapMem): Delete definition.
1019 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1021 * interp.c (sim_do_command, sim_commands): Delete mips specific
1022 commands. Handled by module sim-options.
1024 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1025 (WITH_MODULO_MEMORY): Define.
1027 * interp.c (sim_info): Delete code printing memory size.
1029 * interp.c (mips_size): Nee sim_size, delete function.
1031 (monitor, monitor_base, monitor_size): Delete global variables.
1032 (sim_open, sim_close): Delete code creating monitor and other
1033 memory regions. Use sim-memopts module, via sim_do_commandf, to
1034 manage memory regions.
1035 (load_memory, store_memory): Use sim-core for memory model.
1037 * interp.c (address_translation): Delete all memory map code
1038 except line forcing 32 bit addresses.
1040 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1042 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1045 * interp.c (logfh, logfile): Delete globals.
1046 (sim_open, sim_close): Delete code opening & closing log file.
1047 (mips_option_handler): Delete -l and -n options.
1048 (OPTION mips_options): Ditto.
1050 * interp.c (OPTION mips_options): Rename option trace to dinero.
1051 (mips_option_handler): Update.
1053 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1055 * interp.c (fetch_str): New function.
1056 (sim_monitor): Rewrite using sim_read & sim_write.
1057 (sim_open): Check magic number.
1058 (sim_open): Write monitor vectors into memory using sim_write.
1059 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1060 (sim_read, sim_write): Simplify - transfer data one byte at a
1062 (load_memory, store_memory): Clarify meaning of parameter RAW.
1064 * sim-main.h (isHOST): Defete definition.
1065 (isTARGET): Mark as depreciated.
1066 (address_translation): Delete parameter HOST.
1068 * interp.c (address_translation): Delete parameter HOST.
1071 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1073 * gencode.c: Add tx49 configury and insns.
1074 * configure.in: Add tx49 configury.
1075 * configure: Update.
1078 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1082 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1083 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1085 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087 * mips.igen: Add model filter field to records.
1089 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1091 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1093 interp.c (sim_engine_run): Do not compile function sim_engine_run
1094 when WITH_IGEN == 1.
1096 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1097 target architecture.
1099 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1100 igen. Replace with configuration variables sim_igen_flags /
1103 start-sanitize-r5900
1104 * r5900.igen: New file. Copy r5900 insns here.
1106 start-sanitize-vr5400
1107 * vr5400.igen: New file.
1109 * m16.igen: New file. Copy mips16 insns here.
1110 * mips.igen: From here.
1112 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1114 start-sanitize-vr5400
1115 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1117 * configure.in: Add mips64vr5400 target.
1118 * configure: Re-generate.
1121 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1123 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1125 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1127 * gencode.c (build_instruction): Follow sim_write's lead in using
1128 BigEndianMem instead of !ByteSwapMem.
1130 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1132 * configure.in (sim_gen): Dependent on target, select type of
1133 generator. Always select old style generator.
1135 configure: Re-generate.
1137 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1139 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1140 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1141 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1142 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1143 SIM_@sim_gen@_*, set by autoconf.
1145 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1149 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1150 CURRENT_FLOATING_POINT instead.
1152 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1153 (address_translation): Raise exception InstructionFetch when
1154 translation fails and isINSTRUCTION.
1156 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1157 sim_engine_run): Change type of of vaddr and paddr to
1159 (address_translation, prefetch, load_memory, store_memory,
1160 cache_op): Change type of vAddr and pAddr to address_word.
1162 * gencode.c (build_instruction): Change type of vaddr and paddr to
1165 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1168 macro to obtain result of ALU op.
1170 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1172 * interp.c (sim_info): Call profile_print.
1174 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1176 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1178 * sim-main.h (WITH_PROFILE): Do not define, defined in
1179 common/sim-config.h. Use sim-profile module.
1180 (simPROFILE): Delete defintion.
1182 * interp.c (PROFILE): Delete definition.
1183 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1184 (sim_close): Delete code writing profile histogram.
1185 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1187 (sim_engine_run): Delete code profiling the PC.
1189 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1191 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1193 * interp.c (sim_monitor): Make register pointers of type
1196 * sim-main.h: Make registers of type unsigned_word not
1199 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1201 start-sanitize-r5900
1202 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1203 ...): Move to sim-main.h
1206 * interp.c (sync_operation): Rename from SyncOperation, make
1207 global, add SD argument.
1208 (prefetch): Rename from Prefetch, make global, add SD argument.
1209 (decode_coproc): Make global.
1211 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1213 * gencode.c (build_instruction): Generate DecodeCoproc not
1214 decode_coproc calls.
1216 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1217 (SizeFGR): Move to sim-main.h
1218 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1219 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1220 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1222 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1223 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1224 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1225 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1226 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1227 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1229 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1231 (sim-alu.h): Include.
1232 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1233 (sim_cia): Typedef to instruction_address.
1235 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1237 * Makefile.in (interp.o): Rename generated file engine.c to
1242 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1244 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1246 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1248 * gencode.c (build_instruction): For "FPSQRT", output correct
1249 number of arguments to Recip.
1251 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253 * Makefile.in (interp.o): Depends on sim-main.h
1255 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1257 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1258 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1259 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1260 STATE, DSSTATE): Define
1261 (GPR, FGRIDX, ..): Define.
1263 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1264 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1265 (GPR, FGRIDX, ...): Delete macros.
1267 * interp.c: Update names to match defines from sim-main.h
1269 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1271 * interp.c (sim_monitor): Add SD argument.
1272 (sim_warning): Delete. Replace calls with calls to
1274 (sim_error): Delete. Replace calls with sim_io_error.
1275 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1276 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1277 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1279 (mips_size): Rename from sim_size. Add SD argument.
1281 * interp.c (simulator): Delete global variable.
1282 (callback): Delete global variable.
1283 (mips_option_handler, sim_open, sim_write, sim_read,
1284 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1285 sim_size,sim_monitor): Use sim_io_* not callback->*.
1286 (sim_open): ZALLOC simulator struct.
1287 (PROFILE): Do not define.
1289 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1292 support.h with corresponding code.
1294 * sim-main.h (word64, uword64), support.h: Move definition to
1296 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1299 * Makefile.in: Update dependencies
1300 * interp.c: Do not include.
1302 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1304 * interp.c (address_translation, load_memory, store_memory,
1305 cache_op): Rename to from AddressTranslation et.al., make global,
1308 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1311 * interp.c (SignalException): Rename to signal_exception, make
1314 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1316 * sim-main.h (SignalException, SignalExceptionInterrupt,
1317 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1318 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1319 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1322 * interp.c, support.h: Use.
1324 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1326 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1327 to value_fpr / store_fpr. Add SD argument.
1328 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1329 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1331 * sim-main.h (ValueFPR, StoreFPR): Define.
1333 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1335 * interp.c (sim_engine_run): Check consistency between configure
1336 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1339 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1340 (mips_fpu): Configure WITH_FLOATING_POINT.
1341 (mips_endian): Configure WITH_TARGET_ENDIAN.
1342 * configure: Update.
1344 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346 * configure: Regenerated to track ../common/aclocal.m4 changes.
1348 start-sanitize-r5900
1349 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1351 * interp.c (MAX_REG): Allow up-to 128 registers.
1352 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1353 (REGISTER_SA): Ditto.
1354 (sim_open): Initialize register_widths for r5900 specific
1356 (sim_fetch_register, sim_store_register): Check for request of
1357 r5900 specific SA register. Check for request for hi 64 bits of
1358 r5900 specific registers.
1361 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1363 * configure: Regenerated.
1365 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1367 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1369 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1371 * gencode.c (print_igen_insn_models): Assume certain architectures
1372 include all mips* instructions.
1373 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1376 * Makefile.in (tmp.igen): Add target. Generate igen input from
1379 * gencode.c (FEATURE_IGEN): Define.
1380 (main): Add --igen option. Generate output in igen format.
1381 (process_instructions): Format output according to igen option.
1382 (print_igen_insn_format): New function.
1383 (print_igen_insn_models): New function.
1384 (process_instructions): Only issue warnings and ignore
1385 instructions when no FEATURE_IGEN.
1387 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1389 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1392 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1394 * configure: Regenerated to track ../common/aclocal.m4 changes.
1396 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1399 SIM_RESERVED_BITS): Delete, moved to common.
1400 (SIM_EXTRA_CFLAGS): Update.
1402 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1404 * configure.in: Configure non-strict memory alignment.
1405 * configure: Regenerated to track ../common/aclocal.m4 changes.
1407 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1411 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1413 * gencode.c (SDBBP,DERET): Added (3900) insns.
1414 (RFE): Turn on for 3900.
1415 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1416 (dsstate): Made global.
1417 (SUBTARGET_R3900): Added.
1418 (CANCELDELAYSLOT): New.
1419 (SignalException): Ignore SystemCall rather than ignore and
1420 terminate. Add DebugBreakPoint handling.
1421 (decode_coproc): New insns RFE, DERET; and new registers Debug
1422 and DEPC protected by SUBTARGET_R3900.
1423 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1425 * Makefile.in,configure.in: Add mips subtarget option.
1426 * configure: Update.
1428 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1430 * gencode.c: Add r3900 (tx39).
1433 * gencode.c: Fix some configuration problems by improving
1434 the relationship between tx19 and tx39.
1437 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1439 * gencode.c (build_instruction): Don't need to subtract 4 for
1442 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1444 * interp.c: Correct some HASFPU problems.
1446 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1448 * configure: Regenerated to track ../common/aclocal.m4 changes.
1450 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1452 * interp.c (mips_options): Fix samples option short form, should
1455 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1457 * interp.c (sim_info): Enable info code. Was just returning.
1459 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1461 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1464 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1468 (build_instruction): Ditto for LL.
1471 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1473 * mips/configure.in, mips/gencode: Add tx19/r1900.
1476 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1478 * configure: Regenerated to track ../common/aclocal.m4 changes.
1480 start-sanitize-r5900
1481 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1484 for overflow due to ABS of MININT, set result to MAXINT.
1485 (build_instruction): For "psrlvw", signextend bit 31.
1488 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1490 * configure: Regenerated to track ../common/aclocal.m4 changes.
1493 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495 * interp.c (sim_open): Add call to sim_analyze_program, update
1498 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * interp.c (sim_kill): Delete.
1501 (sim_create_inferior): Add ABFD argument. Set PC from same.
1502 (sim_load): Move code initializing trap handlers from here.
1503 (sim_open): To here.
1504 (sim_load): Delete, use sim-hload.c.
1506 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1508 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * configure: Regenerated to track ../common/aclocal.m4 changes.
1513 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1515 * interp.c (sim_open): Add ABFD argument.
1516 (sim_load): Move call to sim_config from here.
1517 (sim_open): To here. Check return status.
1519 start-sanitize-r5900
1520 * gencode.c (build_instruction): Do not define x8000000000000000,
1521 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1524 start-sanitize-r5900
1525 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1528 "pdivuw" check for overflow due to signed divide by -1.
1531 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1533 * gencode.c (build_instruction): Two arg MADD should
1534 not assign result to $0.
1536 start-sanitize-r5900
1537 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1539 * gencode.c (build_instruction): For "ppac5" use unsigned
1540 arrithmetic so that the sign bit doesn't smear when right shifted.
1541 (build_instruction): For "pdiv" perform sign extension when
1542 storing results in HI and LO.
1543 (build_instructions): For "pdiv" and "pdivbw" check for
1545 (build_instruction): For "pmfhl.slw" update hi part of dest
1546 register as well as low part.
1547 (build_instruction): For "pmfhl" portably handle long long values.
1548 (build_instruction): For "pmfhl.sh" correctly negative values.
1549 Store half words 2 and three in the correct place.
1550 (build_instruction): For "psllvw", sign extend value after shift.
1553 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1555 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1556 * sim/mips/configure.in: Regenerate.
1558 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1560 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1561 signed8, unsigned8 et.al. types.
1563 start-sanitize-r5900
1564 * gencode.c (build_instruction): For PMULTU* do not sign extend
1565 registers. Make generated code easier to debug.
1568 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1569 hosts when selecting subreg.
1571 start-sanitize-r5900
1572 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1574 * gencode.c (type_for_data_len): For 32bit operations concerned
1575 with overflow, perform op using 64bits.
1576 (build_instruction): For PADD, always compute operation using type
1577 returned by type_for_data_len.
1578 (build_instruction): For PSUBU, when overflow, saturate to zero as
1582 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1584 start-sanitize-r5900
1585 * gencode.c (build_instruction): Handle "pext5" according to
1586 version 1.95 of the r5900 ISA.
1588 * gencode.c (build_instruction): Handle "ppac5" according to
1589 version 1.95 of the r5900 ISA.
1592 * interp.c (sim_engine_run): Reset the ZERO register to zero
1593 regardless of FEATURE_WARN_ZERO.
1594 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1596 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1598 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1599 (SignalException): For BreakPoints ignore any mode bits and just
1601 (SignalException): Always set the CAUSE register.
1603 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1606 exception has been taken.
1608 * interp.c: Implement the ERET and mt/f sr instructions.
1610 start-sanitize-r5900
1611 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1613 * gencode.c (build_instruction): For paddu, extract unsigned
1616 * gencode.c (build_instruction): Saturate padds instead of padd
1620 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1622 * interp.c (SignalException): Don't bother restarting an
1625 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627 * interp.c (SignalException): Really take an interrupt.
1628 (interrupt_event): Only deliver interrupts when enabled.
1630 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632 * interp.c (sim_info): Only print info when verbose.
1633 (sim_info) Use sim_io_printf for output.
1635 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1640 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642 * interp.c (sim_do_command): Check for common commands if a
1643 simulator specific command fails.
1645 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1647 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1648 and simBE when DEBUG is defined.
1650 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1652 * interp.c (interrupt_event): New function. Pass exception event
1653 onto exception handler.
1655 * configure.in: Check for stdlib.h.
1656 * configure: Regenerate.
1658 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1659 variable declaration.
1660 (build_instruction): Initialize memval1.
1661 (build_instruction): Add UNUSED attribute to byte, bigend,
1663 (build_operands): Ditto.
1665 * interp.c: Fix GCC warnings.
1666 (sim_get_quit_code): Delete.
1668 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1669 * Makefile.in: Ditto.
1670 * configure: Re-generate.
1672 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1674 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676 * interp.c (mips_option_handler): New function parse argumes using
1678 (myname): Replace with STATE_MY_NAME.
1679 (sim_open): Delete check for host endianness - performed by
1681 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1682 (sim_open): Move much of the initialization from here.
1683 (sim_load): To here. After the image has been loaded and
1685 (sim_open): Move ColdReset from here.
1686 (sim_create_inferior): To here.
1687 (sim_open): Make FP check less dependant on host endianness.
1689 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1691 * interp.c (sim_set_callbacks): Delete.
1693 * interp.c (membank, membank_base, membank_size): Replace with
1694 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1695 (sim_open): Remove call to callback->init. gdb/run do this.
1699 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1701 * interp.c (big_endian_p): Delete, replaced by
1702 current_target_byte_order.
1704 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706 * interp.c (host_read_long, host_read_word, host_swap_word,
1707 host_swap_long): Delete. Using common sim-endian.
1708 (sim_fetch_register, sim_store_register): Use H2T.
1709 (pipeline_ticks): Delete. Handled by sim-events.
1711 (sim_engine_run): Update.
1713 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1717 (SignalException): To here. Signal using sim_engine_halt.
1718 (sim_stop_reason): Delete, moved to common.
1720 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1722 * interp.c (sim_open): Add callback argument.
1723 (sim_set_callbacks): Delete SIM_DESC argument.
1726 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1728 * Makefile.in (SIM_OBJS): Add common modules.
1730 * interp.c (sim_set_callbacks): Also set SD callback.
1731 (set_endianness, xfer_*, swap_*): Delete.
1732 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1733 Change to functions using sim-endian macros.
1734 (control_c, sim_stop): Delete, use common version.
1735 (simulate): Convert into.
1736 (sim_engine_run): This function.
1737 (sim_resume): Delete.
1739 * interp.c (simulation): New variable - the simulator object.
1740 (sim_kind): Delete global - merged into simulation.
1741 (sim_load): Cleanup. Move PC assignment from here.
1742 (sim_create_inferior): To here.
1744 * sim-main.h: New file.
1745 * interp.c (sim-main.h): Include.
1747 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1749 * configure: Regenerated to track ../common/aclocal.m4 changes.
1751 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1753 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1755 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1757 * gencode.c (build_instruction): DIV instructions: check
1758 for division by zero and integer overflow before using
1759 host's division operation.
1761 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1763 * Makefile.in (SIM_OBJS): Add sim-load.o.
1764 * interp.c: #include bfd.h.
1765 (target_byte_order): Delete.
1766 (sim_kind, myname, big_endian_p): New static locals.
1767 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1768 after argument parsing. Recognize -E arg, set endianness accordingly.
1769 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1770 load file into simulator. Set PC from bfd.
1771 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1772 (set_endianness): Use big_endian_p instead of target_byte_order.
1774 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1776 * interp.c (sim_size): Delete prototype - conflicts with
1777 definition in remote-sim.h. Correct definition.
1779 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1781 * configure: Regenerated to track ../common/aclocal.m4 changes.
1784 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1786 * interp.c (sim_open): New arg `kind'.
1788 * configure: Regenerated to track ../common/aclocal.m4 changes.
1790 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1792 * configure: Regenerated to track ../common/aclocal.m4 changes.
1794 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1796 * interp.c (sim_open): Set optind to 0 before calling getopt.
1798 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1800 * configure: Regenerated to track ../common/aclocal.m4 changes.
1802 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1804 * interp.c : Replace uses of pr_addr with pr_uword64
1805 where the bit length is always 64 independent of SIM_ADDR.
1806 (pr_uword64) : added.
1808 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1810 * configure: Re-generate.
1812 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1814 * configure: Regenerate to track ../common/aclocal.m4 changes.
1816 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1818 * interp.c (sim_open): New SIM_DESC result. Argument is now
1820 (other sim_*): New SIM_DESC argument.
1822 start-sanitize-r5900
1823 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1825 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1826 Change values to avoid overloading DOUBLEWORD which is tested
1828 * gencode.c: reinstate "offending code".
1831 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1833 * interp.c: Fix printing of addresses for non-64-bit targets.
1834 (pr_addr): Add function to print address based on size.
1835 start-sanitize-r5900
1836 * gencode.c: #ifdef out offending code until a permanent fix
1837 can be added. Code is causing build errors for non-5900 mips targets.
1840 start-sanitize-r5900
1841 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1843 * gencode.c (process_instructions): Correct test for ISA dependent
1844 architecture bits in isa field of MIPS_DECODE.
1847 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1849 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1851 start-sanitize-r5900
1852 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1854 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1858 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1860 * gencode.c (build_mips16_operands): Correct computation of base
1861 address for extended PC relative instruction.
1863 start-sanitize-r5900
1864 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1866 * Makefile.in, configure, configure.in, gencode.c,
1867 interp.c, support.h: add r5900.
1870 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1872 * interp.c (mips16_entry): Add support for floating point cases.
1873 (SignalException): Pass floating point cases to mips16_entry.
1874 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1876 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1878 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1879 and then set the state to fmt_uninterpreted.
1880 (COP_SW): Temporarily set the state to fmt_word while calling
1883 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1885 * gencode.c (build_instruction): The high order may be set in the
1886 comparison flags at any ISA level, not just ISA 4.
1888 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1890 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1891 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1892 * configure.in: sinclude ../common/aclocal.m4.
1893 * configure: Regenerated.
1895 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1897 * configure: Rebuild after change to aclocal.m4.
1899 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1901 * configure configure.in Makefile.in: Update to new configure
1902 scheme which is more compatible with WinGDB builds.
1903 * configure.in: Improve comment on how to run autoconf.
1904 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1905 * Makefile.in: Use autoconf substitution to install common
1908 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1910 * gencode.c (build_instruction): Use BigEndianCPU instead of
1913 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1915 * interp.c (sim_monitor): Make output to stdout visible in
1916 wingdb's I/O log window.
1918 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1920 * support.h: Undo previous change to SIGTRAP
1923 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1925 * interp.c (store_word, load_word): New static functions.
1926 (mips16_entry): New static function.
1927 (SignalException): Look for mips16 entry and exit instructions.
1928 (simulate): Use the correct index when setting fpr_state after
1929 doing a pending move.
1931 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1933 * interp.c: Fix byte-swapping code throughout to work on
1934 both little- and big-endian hosts.
1936 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1938 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1939 with gdb/config/i386/xm-windows.h.
1941 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1943 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1944 that messes up arithmetic shifts.
1946 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1948 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1949 SIGTRAP and SIGQUIT for _WIN32.
1951 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1953 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1954 force a 64 bit multiplication.
1955 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1956 destination register is 0, since that is the default mips16 nop
1959 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1961 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1962 (build_endian_shift): Don't check proc64.
1963 (build_instruction): Always set memval to uword64. Cast op2 to
1964 uword64 when shifting it left in memory instructions. Always use
1965 the same code for stores--don't special case proc64.
1967 * gencode.c (build_mips16_operands): Fix base PC value for PC
1969 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1971 * interp.c (simJALDELAYSLOT): Define.
1972 (JALDELAYSLOT): Define.
1973 (INDELAYSLOT, INJALDELAYSLOT): Define.
1974 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1976 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1978 * interp.c (sim_open): add flush_cache as a PMON routine
1979 (sim_monitor): handle flush_cache by ignoring it
1981 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1983 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1985 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1986 (BigEndianMem): Rename to ByteSwapMem and change sense.
1987 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1988 BigEndianMem references to !ByteSwapMem.
1989 (set_endianness): New function, with prototype.
1990 (sim_open): Call set_endianness.
1991 (sim_info): Use simBE instead of BigEndianMem.
1992 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1993 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1994 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1995 ifdefs, keeping the prototype declaration.
1996 (swap_word): Rewrite correctly.
1997 (ColdReset): Delete references to CONFIG. Delete endianness related
1998 code; moved to set_endianness.
2000 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2002 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2003 * interp.c (CHECKHILO): Define away.
2004 (simSIGINT): New macro.
2005 (membank_size): Increase from 1MB to 2MB.
2006 (control_c): New function.
2007 (sim_resume): Rename parameter signal to signal_number. Add local
2008 variable prev. Call signal before and after simulate.
2009 (sim_stop_reason): Add simSIGINT support.
2010 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2012 (sim_warning): Delete call to SignalException. Do call printf_filtered
2014 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2015 a call to sim_warning.
2017 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2019 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2020 16 bit instructions.
2022 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2024 Add support for mips16 (16 bit MIPS implementation):
2025 * gencode.c (inst_type): Add mips16 instruction encoding types.
2026 (GETDATASIZEINSN): Define.
2027 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2028 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2030 (MIPS16_DECODE): New table, for mips16 instructions.
2031 (bitmap_val): New static function.
2032 (struct mips16_op): Define.
2033 (mips16_op_table): New table, for mips16 operands.
2034 (build_mips16_operands): New static function.
2035 (process_instructions): If PC is odd, decode a mips16
2036 instruction. Break out instruction handling into new
2037 build_instruction function.
2038 (build_instruction): New static function, broken out of
2039 process_instructions. Check modifiers rather than flags for SHIFT
2040 bit count and m[ft]{hi,lo} direction.
2041 (usage): Pass program name to fprintf.
2042 (main): Remove unused variable this_option_optind. Change
2043 ``*loptarg++'' to ``loptarg++''.
2044 (my_strtoul): Parenthesize && within ||.
2045 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2046 (simulate): If PC is odd, fetch a 16 bit instruction, and
2047 increment PC by 2 rather than 4.
2048 * configure.in: Add case for mips16*-*-*.
2049 * configure: Rebuild.
2051 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2053 * interp.c: Allow -t to enable tracing in standalone simulator.
2054 Fix garbage output in trace file and error messages.
2056 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2058 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2059 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2060 * configure.in: Simplify using macros in ../common/aclocal.m4.
2061 * configure: Regenerated.
2062 * tconfig.in: New file.
2064 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2066 * interp.c: Fix bugs in 64-bit port.
2067 Use ansi function declarations for msvc compiler.
2068 Initialize and test file pointer in trace code.
2069 Prevent duplicate definition of LAST_EMED_REGNUM.
2071 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2073 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2075 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2077 * interp.c (SignalException): Check for explicit terminating
2079 * gencode.c: Pass instruction value through SignalException()
2080 calls for Trap, Breakpoint and Syscall.
2082 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2084 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2085 only used on those hosts that provide it.
2086 * configure.in: Add sqrt() to list of functions to be checked for.
2087 * config.in: Re-generated.
2088 * configure: Re-generated.
2090 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2092 * gencode.c (process_instructions): Call build_endian_shift when
2093 expanding STORE RIGHT, to fix swr.
2094 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2095 clear the high bits.
2096 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2097 Fix float to int conversions to produce signed values.
2099 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2101 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2102 (process_instructions): Correct handling of nor instruction.
2103 Correct shift count for 32 bit shift instructions. Correct sign
2104 extension for arithmetic shifts to not shift the number of bits in
2105 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2106 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2108 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2109 It's OK to have a mult follow a mult. What's not OK is to have a
2110 mult follow an mfhi.
2111 (Convert): Comment out incorrect rounding code.
2113 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2115 * interp.c (sim_monitor): Improved monitor printf
2116 simulation. Tidied up simulator warnings, and added "--log" option
2117 for directing warning message output.
2118 * gencode.c: Use sim_warning() rather than WARNING macro.
2120 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2122 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2123 getopt1.o, rather than on gencode.c. Link objects together.
2124 Don't link against -liberty.
2125 (gencode.o, getopt.o, getopt1.o): New targets.
2126 * gencode.c: Include <ctype.h> and "ansidecl.h".
2127 (AND): Undefine after including "ansidecl.h".
2128 (ULONG_MAX): Define if not defined.
2129 (OP_*): Don't define macros; now defined in opcode/mips.h.
2130 (main): Call my_strtoul rather than strtoul.
2131 (my_strtoul): New static function.
2133 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2135 * gencode.c (process_instructions): Generate word64 and uword64
2136 instead of `long long' and `unsigned long long' data types.
2137 * interp.c: #include sysdep.h to get signals, and define default
2139 * (Convert): Work around for Visual-C++ compiler bug with type
2141 * support.h: Make things compile under Visual-C++ by using
2142 __int64 instead of `long long'. Change many refs to long long
2143 into word64/uword64 typedefs.
2145 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2147 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2148 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2150 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2151 (AC_PROG_INSTALL): Added.
2152 (AC_PROG_CC): Moved to before configure.host call.
2153 * configure: Rebuilt.
2155 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2157 * configure.in: Define @SIMCONF@ depending on mips target.
2158 * configure: Rebuild.
2159 * Makefile.in (run): Add @SIMCONF@ to control simulator
2161 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2162 * interp.c: Remove some debugging, provide more detailed error
2163 messages, update memory accesses to use LOADDRMASK.
2165 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2167 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2168 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2170 * configure: Rebuild.
2171 * config.in: New file, generated by autoheader.
2172 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2173 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2174 HAVE_ANINT and HAVE_AINT, as appropriate.
2175 * Makefile.in (run): Use @LIBS@ rather than -lm.
2176 (interp.o): Depend upon config.h.
2177 (Makefile): Just rebuild Makefile.
2178 (clean): Remove stamp-h.
2179 (mostlyclean): Make the same as clean, not as distclean.
2180 (config.h, stamp-h): New targets.
2182 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2184 * interp.c (ColdReset): Fix boolean test. Make all simulator
2187 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2189 * interp.c (xfer_direct_word, xfer_direct_long,
2190 swap_direct_word, swap_direct_long, xfer_big_word,
2191 xfer_big_long, xfer_little_word, xfer_little_long,
2192 swap_word,swap_long): Added.
2193 * interp.c (ColdReset): Provide function indirection to
2194 host<->simulated_target transfer routines.
2195 * interp.c (sim_store_register, sim_fetch_register): Updated to
2196 make use of indirected transfer routines.
2198 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2200 * gencode.c (process_instructions): Ensure FP ABS instruction
2202 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2203 system call support.
2205 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2207 * interp.c (sim_do_command): Complain if callback structure not
2210 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2212 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2213 support for Sun hosts.
2214 * Makefile.in (gencode): Ensure the host compiler and libraries
2215 used for cross-hosted build.
2217 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2219 * interp.c, gencode.c: Some more (TODO) tidying.
2221 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2223 * gencode.c, interp.c: Replaced explicit long long references with
2224 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2225 * support.h (SET64LO, SET64HI): Macros added.
2227 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2229 * configure: Regenerate with autoconf 2.7.
2231 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2233 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2234 * support.h: Remove superfluous "1" from #if.
2235 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2237 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2239 * interp.c (StoreFPR): Control UndefinedResult() call on
2240 WARN_RESULT manifest.
2242 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2244 * gencode.c: Tidied instruction decoding, and added FP instruction
2247 * interp.c: Added dineroIII, and BSD profiling support. Also
2248 run-time FP handling.
2250 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2252 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2253 gencode.c, interp.c, support.h: created.