sim/mips/ChangeLog

   1 2002-06-08  Andrew Cagney  <cagney@redhat.com>
   2
   3         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
   4
   5 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
   6             Ed Satterthwaite  <ehs@broadcom.com>
   7
   8         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
   9         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
  10         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
  11         (fp_nmsub): New prototypes.
  12         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
  13         (NegMultiplySub): New defines.
  14         * mips.igen (RSQRT.fmt): Use RSquareRoot().
  15         (MADD.D, MADD.S): Replace with...
  16         (MADD.fmt): New instruction.
  17         (MSUB.D, MSUB.S): Replace with...
  18         (MSUB.fmt): New instruction.
  19         (NMADD.D, NMADD.S): Replace with...
  20         (NMADD.fmt): New instruction.
  21         (NMSUB.D, MSUB.S): Replace with...
  22         (NMSUB.fmt): New instruction.
  23
  24 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  25             Ed Satterthwaite  <ehs@broadcom.com>
  26
  27         * cp1.c: Fix more comment spelling and formatting.
  28         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
  29         (denorm_mode): New function.
  30         (fpu_unary, fpu_binary): Round results after operation, collect
  31         status from rounding operations, and update the FCSR.
  32         (convert): Collect status from integer conversions and rounding
  33         operations, and update the FCSR.  Adjust NaN values that result
  34         from conversions.  Convert to use sim_io_eprintf rather than
  35         fprintf, and remove some debugging code.
  36         * cp1.h (fenr_FS): New define.
  37
  38 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  39
  40         * cp1.c (convert): Remove unusable debugging code, and move MIPS
  41         rounding mode to sim FP rounding mode flag conversion code into...
  42         (rounding_mode): New function.
  43
  44 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  45
  46         * cp1.c: Clean up formatting of a few comments.
  47         (value_fpr): Reformat switch statement.
  48
  49 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
  50             Ed Satterthwaite  <ehs@broadcom.com>
  51
  52         * cp1.h: New file.
  53         * sim-main.h: Include cp1.h.
  54         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
  55         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
  56         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
  57         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
  58         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
  59         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
  60         * cp1.c: Don't include sim-fpu.h; already included by
  61         sim-main.h.  Clean up formatting of some comments.
  62         (NaN, Equal, Less): Remove.
  63         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
  64         (fp_cmp): New functions.
  65         * mips.igen (do_c_cond_fmt): Remove.
  66         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
  67         Compare.  Add result tracing.
  68         (CxC1): Remove, replace with...
  69         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
  70         (DMxC1): Remove, replace with...
  71         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
  72         (MxC1): Remove, replace with...
  73         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
  74
  75 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  76
  77         * sim-main.h (FGRIDX): Remove, replace all uses with...
  78         (FGR_BASE): New macro.
  79         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
  80         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
  81         (NR_FGR, FGR): Likewise.
  82         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
  83         * mips.igen: Likewise.
  84
  85 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  86
  87         * cp1.c: Add an FSF Copyright notice to this file.
  88
  89 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  90             Ed Satterthwaite  <ehs@broadcom.com>
  91
  92         * cp1.c (Infinity): Remove.
  93         * sim-main.h (Infinity): Likewise.
  94
  95         * cp1.c (fp_unary, fp_binary): New functions.
  96         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
  97         (fp_sqrt): New functions, implemented in terms of the above.
  98         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
  99         (Recip, SquareRoot): Remove (replaced by functions above).
 100         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 101         (fp_recip, fp_sqrt): New prototypes.
 102         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 103         (Recip, SquareRoot): Replace prototypes with #defines which
 104         invoke the functions above.
 105
 106 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 107
 108         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 109         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 110         file, remove PARAMS from prototypes.
 111         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 112         simulator state arguments.
 113         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 114         pass simulator state arguments.
 115         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 116         (store_fpr, convert): Remove 'sd' argument.
 117         (value_fpr): Likewise.  Convert to use 'SD' instead.
 118
 119 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 120
 121         * cp1.c (Min, Max): Remove #if 0'd functions.
 122         * sim-main.h (Min, Max): Remove.
 123
 124 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 125
 126         * cp1.c: fix formatting of switch case and default labels.
 127         * interp.c: Likewise.
 128         * sim-main.c: Likewise.
 129
 130 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 131
 132         * cp1.c: Clean up comments which describe FP formats.
 133          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 134
 135 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 136             Ed Satterthwaite  <ehs@broadcom.com>
 137
 138         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 139         Broadcom SiByte SB-1 processor configurations.
 140         * configure: Regenerate.
 141         * sb1.igen: New file.
 142         * mips.igen: Include sb1.igen.
 143         (sb1): New model.
 144         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 145         * mdmx.igen: Add "sb1" model to all appropriate functions and
 146         instructions.
 147         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 148         (ob_func, ob_acc): Reference the above.
 149         (qh_acc): Adjust to keep the same size as ob_acc.
 150         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 151         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 152
 153 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 154
 155         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 156
 157 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 158             Ed Satterthwaite  <ehs@broadcom.com>
 159
 160         * mips.igen (mdmx): New (pseudo-)model.
 161         * mdmx.c, mdmx.igen: New files.
 162         * Makefile.in (SIM_OBJS): Add mdmx.o.
 163         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 164         New typedefs.
 165         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 166         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 167         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 168         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 169         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 170         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 171         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 172         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 173         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 174         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 175         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 176         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 177         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 178         (qh_fmtsel): New macros.
 179         (_sim_cpu): New member "acc".
 180         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 181         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 182
 183 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 184
 185         * interp.c: Use 'deprecated' rather than 'depreciated.'
 186         * sim-main.h: Likewise.
 187
 188 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 189
 190         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 191         which wouldn't compile anyway.
 192         * sim-main.h (unpredictable_action): New function prototype.
 193         (Unpredictable): Define to call igen function unpredictable().
 194         (NotWordValue): New macro to call igen function not_word_value().
 195         (UndefinedResult): Remove.
 196         * interp.c (undefined_result): Remove.
 197         (unpredictable_action): New function.
 198         * mips.igen (not_word_value, unpredictable): New functions.
 199         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 200         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 201         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 202         NotWordValue() to check for unpredictable inputs, then
 203         Unpredictable() to handle them.
 204
 205 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 206
 207         * mips.igen: Fix formatting of calls to Unpredictable().
 208
 209 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 210
 211         * interp.c (sim_open): Revert previous change.
 212
 213 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 214
 215         * interp.c (sim_open): Disable chunk of code that wrote code in
 216         vector table entries.
 217
 218 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 219
 220         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 221         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 222         unused definitions.
 223
 224 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 225
 226         * cp1.c: Fix many formatting issues.
 227
 228 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 229
 230         * cp1.c (fpu_format_name): New function to replace...
 231         (DOFMT): This.  Delete, and update all callers.
 232         (fpu_rounding_mode_name): New function to replace...
 233         (RMMODE): This.  Delete, and update all callers.
 234
 235 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 236
 237         * interp.c: Move FPU support routines from here to...
 238         * cp1.c: Here.  New file.
 239         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 240         (cp1.o): New target.
 241
 242 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 243
 244         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 245         * mips.igen (mips32, mips64): New models, add to all instructions
 246         and functions as appropriate.
 247         (loadstore_ea, check_u64): New variant for model mips64.
 248         (check_fmt_p): New variant for models mipsV and mips64, remove
 249         mipsV model marking fro other variant.
 250         (SLL) Rename to...
 251         (SLLa) this.
 252         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 253         for mips32 and mips64.
 254         (DCLO, DCLZ): New instructions for mips64.
 255
 256 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 257
 258         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 259         immediate or code as a hex value with the "%#lx" format.
 260         (ANDI): Likewise, and fix printed instruction name.
 261
 262 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 263
 264         * sim-main.h (UndefinedResult, Unpredictable): New macros
 265         which currently do nothing.
 266
 267 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 268
 269         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 270         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 271         (status_CU3): New definitions.
 272
 273         * sim-main.h (ExceptionCause): Add new values for MIPS32
 274         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 275         for DebugBreakPoint and NMIReset to note their status in
 276         MIPS32 and MIPS64.
 277         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 278         (SignalExceptionCacheErr): New exception macros.
 279
 280 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 281
 282         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 283         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 284         is always enabled.
 285         (SignalExceptionCoProcessorUnusable): Take as argument the
 286         unusable coprocessor number.
 287
 288 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 289
 290         * mips.igen: Fix formatting of all SignalException calls.
 291
 292 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 293
 294         * sim-main.h (SIGNEXTEND): Remove.
 295
 296 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 297
 298         * mips.igen: Remove gencode comment from top of file, fix
 299         spelling in another comment.
 300
 301 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 302
 303         * mips.igen (check_fmt, check_fmt_p): New functions to check
 304         whether specific floating point formats are usable.
 305         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 306         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 307         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 308         Use the new functions.
 309         (do_c_cond_fmt): Remove format checks...
 310         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 311
 312 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 313
 314         * mips.igen: Fix formatting of check_fpu calls.
 315
 316 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 319
 320 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 321
 322         * mips.igen: Remove whitespace at end of lines.
 323
 324 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 325
 326         * mips.igen (loadstore_ea): New function to do effective
 327         address calculations.
 328         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 329         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 330         CACHE): Use loadstore_ea to do effective address computations.
 331
 332 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 333
 334         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 335         * mips.igen (LL, CxC1, MxC1): Likewise.
 336
 337 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 338
 339         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 340         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 341         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 342         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 343         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 344         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 345         Don't split opcode fields by hand, use the opcode field values
 346         provided by igen.
 347
 348 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 349
 350         * mips.igen (do_divu): Fix spacing.
 351
 352         * mips.igen (do_dsllv): Move to be right before DSLLV,
 353         to match the rest of the do_<shift> functions.
 354
 355 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 356
 357         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 358         DSRL32, do_dsrlv): Trace inputs and results.
 359
 360 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 361
 362         * mips.igen (CACHE): Provide instruction-printing string.
 363
 364         * interp.c (signal_exception): Comment tokens after #endif.
 365
 366 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 367
 368         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 369         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 370         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 371         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 372         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 373         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 374         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 375         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 376
 377 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 378
 379         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 380         instruction-printing string.
 381         (LWU): Use '64' as the filter flag.
 382
 383 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * mips.igen (SDXC1): Fix instruction-printing string.
 386
 387 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 388
 389         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 390         filter flags "32,f".
 391
 392 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 393
 394         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 395         as the filter flag.
 396
 397 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 398
 399         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 400         add a comma) so that it more closely match the MIPS ISA
 401         documentation opcode partitioning.
 402         (PREF): Put useful names on opcode fields, and include
 403         instruction-printing string.
 404
 405 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 406
 407         * mips.igen (check_u64): New function which in the future will
 408         check whether 64-bit instructions are usable and signal an
 409         exception if not.  Currently a no-op.
 410         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 411         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 412         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 413         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 414
 415         * mips.igen (check_fpu): New function which in the future will
 416         check whether FPU instructions are usable and signal an exception
 417         if not.  Currently a no-op.
 418         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 419         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 420         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 421         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 422         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 423         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 424         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 425         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 426
 427 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 428
 429         * mips.igen (do_load_left, do_load_right): Move to be immediately
 430         following do_load.
 431         (do_store_left, do_store_right): Move to be immediately following
 432         do_store.
 433
 434 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 435
 436         * mips.igen (mipsV): New model name.  Also, add it to
 437         all instructions and functions where it is appropriate.
 438
 439 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 440
 441         * mips.igen: For all functions and instructions, list model
 442         names that support that instruction one per line.
 443
 444 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 445
 446         * mips.igen: Add some additional comments about supported
 447         models, and about which instructions go where.
 448         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 449         order as is used in the rest of the file.
 450
 451 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 452
 453         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 454         indicating that ALU32_END or ALU64_END are there to check
 455         for overflow.
 456         (DADD): Likewise, but also remove previous comment about
 457         overflow checking.
 458
 459 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 460
 461         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 462         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 463         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 464         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 465         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 466         fields (i.e., add and move commas) so that they more closely
 467         match the MIPS ISA documentation opcode partitioning.
 468
 469 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 470
 471         * mips.igen (ADDI): Print immediate value.
 472         (BREAK): Print code.
 473         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 474         (SLL): Print "nop" specially, and don't run the code
 475         that does the shift for the "nop" case.
 476
 477 2001-11-17  Fred Fish  <fnf@redhat.com>
 478
 479         * sim-main.h (float_operation): Move enum declaration outside
 480         of _sim_cpu struct declaration.
 481
 482 2001-04-12  Jim Blandy  <jimb@redhat.com>
 483
 484         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 485         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 486         set of the FCSR.
 487         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 488         PENDING_FILL, and you can get the intended effect gracefully by
 489         calling PENDING_SCHED directly.
 490
 491 2001-02-23  Ben Elliston  <bje@redhat.com>
 492
 493         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 494         already defined elsewhere.
 495
 496 2001-02-19  Ben Elliston  <bje@redhat.com>
 497
 498         * sim-main.h (sim_monitor): Return an int.
 499         * interp.c (sim_monitor): Add return values.
 500         (signal_exception): Handle error conditions from sim_monitor.
 501
 502 2001-02-08  Ben Elliston  <bje@redhat.com>
 503
 504         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 505         (store_memory): Likewise, pass cia to sim_core_write*.
 506
 507 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 508
 509         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 510         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 511
 512 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 513
 514         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 515         * Makefile.in: Don't delete *.igen when cleaning directory.
 516
 517 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 518
 519         * m16.igen (break): Call SignalException not sim_engine_halt.
 520
 521 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 522
 523         From Jason Eckhardt:
 524         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 525
 526 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 527
 528         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 529
 530 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 531
 532         * mips.igen (do_dmultx): Fix typo.
 533
 534 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 535
 536         * configure: Regenerated to track ../common/aclocal.m4 changes.
 537
 538 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 539
 540         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 541
 542 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 543
 544         * sim-main.h (GPR_CLEAR): Define macro.
 545
 546 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 547
 548         * interp.c (decode_coproc): Output long using %lx and not %s.
 549
 550 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 551
 552         * interp.c (sim_open): Sort & extend dummy memory regions for
 553         --board=jmr3904 for eCos.
 554
 555 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 556
 557         * configure: Regenerated.
 558
 559 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 560
 561         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 562         calls, conditional on the simulator being in verbose mode.
 563
 564 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 565
 566         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 567         cache don't get ReservedInstruction traps.
 568
 569 1999-11-29  Mark Salter  <msalter@cygnus.com>
 570
 571         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 572         to clear status bits in sdisr register. This is how the hardware works.
 573
 574         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 575         being used by cygmon.
 576
 577 1999-11-11  Andrew Haley  <aph@cygnus.com>
 578
 579         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 580         instructions.
 581
 582 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 583
 584         * mips.igen (MULT): Correct previous mis-applied patch.
 585
 586 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 587
 588         * mips.igen (delayslot32): Handle sequence like
 589         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 590         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 591         (MULT): Actually pass the third register...
 592
 593 1999-09-03  Mark Salter  <msalter@cygnus.com>
 594
 595         * interp.c (sim_open): Added more memory aliases for additional
 596         hardware being touched by cygmon on jmr3904 board.
 597
 598 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 599
 600         * configure: Regenerated to track ../common/aclocal.m4 changes.
 601
 602 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 603
 604         * interp.c (sim_store_register): Handle case where client - GDB -
 605         specifies that a 4 byte register is 8 bytes in size.
 606         (sim_fetch_register): Ditto.
 607
 608 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 609
 610         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 611         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 612         (idt_monitor_base): Base address for IDT monitor traps.
 613         (pmon_monitor_base): Ditto for PMON.
 614         (lsipmon_monitor_base): Ditto for LSI PMON.
 615         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 616         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 617         (sim_firmware_command): New function.
 618         (mips_option_handler): Call it for OPTION_FIRMWARE.
 619         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 620         option was given, add no monitor by default.  Add BREAK hooks only if
 621         monitors are also there.
 622
 623 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 624
 625         * interp.c (sim_monitor): Flush output before reading input.
 626
 627 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 628
 629         * tconfig.in (SIM_HANDLES_LMA): Always define.
 630
 631 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 632
 633         From Mark Salter <msalter@cygnus.com>:
 634         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 635         (sim_open): Add setup for BSP board.
 636
 637 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 638
 639         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 640         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 641         them as unimplemented.
 642
 643 1999-05-08  Felix Lee  <flee@cygnus.com>
 644
 645         * configure: Regenerated to track ../common/aclocal.m4 changes.
 646
 647 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 648
 649         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 650
 651 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 652
 653         * configure.in: Any mips64vr5*-*-* target should have
 654         -DTARGET_ENABLE_FR=1.
 655         (default_endian): Any mips64vr*el-*-* target should default to
 656         LITTLE_ENDIAN.
 657         * configure: Re-generate.
 658
 659 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 660
 661         * mips.igen (ldl): Extend from _16_, not 32.
 662
 663 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 664
 665         * interp.c (sim_store_register): Force registers written to by GDB
 666         into an un-interpreted state.
 667
 668 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 669
 670         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 671         CPU, start periodic background I/O polls.
 672         (tx3904sio_poll): New function: periodic I/O poller.
 673
 674 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 675
 676         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 677
 678 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 679
 680         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 681         case statement.
 682
 683 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 684
 685         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 686         (load_word): Call SIM_CORE_SIGNAL hook on error.
 687         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 688         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 689         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 690         * sim-main.h (COP0_BADVADDR): Define.
 691         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 692         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 693         (_sim_cpu): Add exc_* fields to store register value snapshots.
 694         * mips.igen (*): Replace memory-related SignalException* calls
 695         with references to SIM_CORE_SIGNAL hook.
 696
 697         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 698         fix.
 699         * sim-main.c (*): Minor warning cleanups.
 700
 701 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 702
 703         * m16.igen (DADDIU5): Correct type-o.
 704
 705 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 706
 707         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 708         variables.
 709
 710 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 711
 712         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 713         to include path.
 714         (interp.o): Add dependency on itable.h
 715         (oengine.c, gencode): Delete remaining references.
 716         (BUILT_SRC_FROM_GEN): Clean up.
 717
 718 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 719
 720         * vr4run.c: New.
 721         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 722         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 723         tmp-run-hack) : New.
 724         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 725         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 726         Drop the "64" qualifier to get the HACK generator working.
 727         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 728         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 729         qualifier to get the hack generator working.
 730         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 731         (DSLL): Use do_dsll.
 732         (DSLLV): Use do_dsllv.
 733         (DSRA): Use do_dsra.
 734         (DSRL): Use do_dsrl.
 735         (DSRLV): Use do_dsrlv.
 736         (BC1): Move *vr4100 to get the HACK generator working.
 737         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 738         get the HACK generator working.
 739         (MACC) Rename to get the HACK generator working.
 740         (DMACC,MACCS,DMACCS): Add the 64.
 741
 742 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 743
 744         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 745         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 746
 747 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 748
 749     * mips/interp.c (DEBUG): Cleanups.
 750
 751 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 752
 753         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 754         (tx3904sio_tickle): fflush after a stdout character output.
 755
 756 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 757
 758         * interp.c (sim_close): Uninstall modules.
 759
 760 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 761
 762         * sim-main.h, interp.c (sim_monitor): Change to global
 763         function.
 764
 765 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 766
 767         * configure.in (vr4100): Only include vr4100 instructions in
 768         simulator.
 769         * configure: Re-generate.
 770         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 771
 772 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 773
 774         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 775         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 776         true alternative.
 777
 778         * configure.in (sim_default_gen, sim_use_gen): Replace with
 779         sim_gen.
 780         (--enable-sim-igen): Delete config option. Always using IGEN.
 781         * configure: Re-generate.
 782
 783         * Makefile.in (gencode): Kill, kill, kill.
 784         * gencode.c: Ditto.
 785
 786 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 787
 788         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 789         bit mips16 igen simulator.
 790         * configure: Re-generate.
 791
 792         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 793         as part of vr4100 ISA.
 794         * vr.igen: Mark all instructions as 64 bit only.
 795
 796 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 797
 798         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 799         Pacify GCC.
 800
 801 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 802
 803         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 804         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 805         * configure: Re-generate.
 806
 807         * m16.igen (BREAK): Define breakpoint instruction.
 808         (JALX32): Mark instruction as mips16 and not r3900.
 809         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 810
 811         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 812
 813 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 814
 815         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 816         insn as a debug breakpoint.
 817
 818         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 819         pending.slot_size.
 820         (PENDING_SCHED): Clean up trace statement.
 821         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 822         (PENDING_FILL): Delay write by only one cycle.
 823         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 824
 825         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 826         of pending writes.
 827         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 828         32 & 64.
 829         (pending_tick): Move incrementing of index to FOR statement.
 830         (pending_tick): Only update PENDING_OUT after a write has occured.
 831
 832         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 833         build simulator.
 834         * configure: Re-generate.
 835
 836         * interp.c (sim_engine_run OLD): Delete explicit call to
 837         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 838
 839 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 840
 841         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 842         interrupt level number to match changed SignalExceptionInterrupt
 843         macro.
 844
 845 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 846
 847         * interp.c: #include "itable.h" if WITH_IGEN.
 848         (get_insn_name): New function.
 849         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 850         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 851
 852 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 853
 854         * configure: Rebuilt to inhale new common/aclocal.m4.
 855
 856 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 857
 858         * dv-tx3904sio.c: Include sim-assert.h.
 859
 860 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 861
 862         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 863         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 864         Reorganize target-specific sim-hardware checks.
 865         * configure: rebuilt.
 866         * interp.c (sim_open): For tx39 target boards, set
 867         OPERATING_ENVIRONMENT, add tx3904sio devices.
 868         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 869         ROM executables.  Install dv-sockser into sim-modules list.
 870
 871         * dv-tx3904irc.c: Compiler warning clean-up.
 872         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 873         frequent hw-trace messages.
 874
 875 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 876
 877         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 878
 879 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 880
 881         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 882
 883         * vr.igen: New file.
 884         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 885         * mips.igen: Define vr4100 model. Include vr.igen.
 886 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 887
 888         * mips.igen (check_mf_hilo): Correct check.
 889
 890 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 891
 892         * sim-main.h (interrupt_event): Add prototype.
 893
 894         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 895         register_ptr, register_value.
 896         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 897
 898         * sim-main.h (tracefh): Make extern.
 899
 900 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 901
 902         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 903         Reduce unnecessarily high timer event frequency.
 904         * dv-tx3904cpu.c: Ditto for interrupt event.
 905
 906 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 907
 908         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 909         to allay warnings.
 910         (interrupt_event): Made non-static.
 911
 912         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 913         interchange of configuration values for external vs. internal
 914         clock dividers.
 915
 916 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 917
 918         * mips.igen (BREAK): Moved code to here for
 919         simulator-reserved break instructions.
 920         * gencode.c (build_instruction): Ditto.
 921         * interp.c (signal_exception): Code moved from here.  Non-
 922         reserved instructions now use exception vector, rather
 923         than halting sim.
 924         * sim-main.h: Moved magic constants to here.
 925
 926 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 927
 928         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 929         register upon non-zero interrupt event level, clear upon zero
 930         event value.
 931         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 932         by passing zero event value.
 933         (*_io_{read,write}_buffer): Endianness fixes.
 934         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 935         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 936
 937         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 938         serial I/O and timer module at base address 0xFFFF0000.
 939
 940 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 941
 942         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 943         and BigEndianCPU.
 944
 945 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 946
 947         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 948         parts.
 949         * configure: Update.
 950
 951 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 952
 953         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 954         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 955         * configure.in: Include tx3904tmr in hw_device list.
 956         * configure: Rebuilt.
 957         * interp.c (sim_open): Instantiate three timer instances.
 958         Fix address typo of tx3904irc instance.
 959
 960 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 961
 962         * interp.c (signal_exception): SystemCall exception now uses
 963         the exception vector.
 964
 965 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 966
 967         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 968         to allay warnings.
 969
 970 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 971
 972         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 973
 974 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 975
 976         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 977
 978         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 979         sim-main.h. Declare a struct hw_descriptor instead of struct
 980         hw_device_descriptor.
 981
 982 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 983
 984         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 985         right bits and then re-align left hand bytes to correct byte
 986         lanes.  Fix incorrect computation in do_store_left when loading
 987         bytes from second word.
 988
 989 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 990
 991         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 992         * interp.c (sim_open): Only create a device tree when HW is
 993         enabled.
 994
 995         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 996         * interp.c (signal_exception): Ditto.
 997
 998 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 999
1000         * gencode.c: Mark BEGEZALL as LIKELY.
1001
1002 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1003
1004         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1005         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1006
1007 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1008
1009         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1010         modules.  Recognize TX39 target with "mips*tx39" pattern.
1011         * configure: Rebuilt.
1012         * sim-main.h (*): Added many macros defining bits in
1013         TX39 control registers.
1014         (SignalInterrupt): Send actual PC instead of NULL.
1015         (SignalNMIReset): New exception type.
1016         * interp.c (board): New variable for future use to identify
1017         a particular board being simulated.
1018         (mips_option_handler,mips_options): Added "--board" option.
1019         (interrupt_event): Send actual PC.
1020         (sim_open): Make memory layout conditional on board setting.
1021         (signal_exception): Initial implementation of hardware interrupt
1022         handling.  Accept another break instruction variant for simulator
1023         exit.
1024         (decode_coproc): Implement RFE instruction for TX39.
1025         (mips.igen): Decode RFE instruction as such.
1026         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1027         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1028         bbegin to implement memory map.
1029         * dv-tx3904cpu.c: New file.
1030         * dv-tx3904irc.c: New file.
1031
1032 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1033
1034         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1035
1036 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1037
1038         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1039         with calls to check_div_hilo.
1040
1041 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1042
1043         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1044         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1045         Add special r3900 version of do_mult_hilo.
1046         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1047         with calls to check_mult_hilo.
1048         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1049         with calls to check_div_hilo.
1050
1051 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1052
1053         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1054         Document a replacement.
1055
1056 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1057
1058         * interp.c (sim_monitor): Make mon_printf work.
1059
1060 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1061
1062         * sim-main.h (INSN_NAME): New arg `cpu'.
1063
1064 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1065
1066         * configure: Regenerated to track ../common/aclocal.m4 changes.
1067
1068 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1069
1070         * configure: Regenerated to track ../common/aclocal.m4 changes.
1071         * config.in: Ditto.
1072
1073 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1074
1075         * acconfig.h: New file.
1076         * configure.in: Reverted change of Apr 24; use sinclude again.
1077
1078 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1079
1080         * configure: Regenerated to track ../common/aclocal.m4 changes.
1081         * config.in: Ditto.
1082
1083 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1084
1085         * configure.in: Don't call sinclude.
1086
1087 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1088
1089         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1090
1091 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1092
1093         * mips.igen (ERET): Implement.
1094
1095         * interp.c (decode_coproc): Return sign-extended EPC.
1096
1097         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1098
1099         * interp.c (signal_exception): Do not ignore Trap.
1100         (signal_exception): On TRAP, restart at exception address.
1101         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1102         (signal_exception): Update.
1103         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1104         so that TRAP instructions are caught.
1105
1106 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1107
1108         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1109         contains HI/LO access history.
1110         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1111         (HIACCESS, LOACCESS): Delete, replace with
1112         (HIHISTORY, LOHISTORY): New macros.
1113         (CHECKHILO): Delete all, moved to mips.igen
1114
1115         * gencode.c (build_instruction): Do not generate checks for
1116         correct HI/LO register usage.
1117
1118         * interp.c (old_engine_run): Delete checks for correct HI/LO
1119         register usage.
1120
1121         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1122         check_mf_cycles): New functions.
1123         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1124         do_divu, domultx, do_mult, do_multu): Use.
1125
1126         * tx.igen ("madd", "maddu"): Use.
1127
1128 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1129
1130         * mips.igen (DSRAV): Use function do_dsrav.
1131         (SRAV): Use new function do_srav.
1132
1133         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1134         (B): Sign extend 11 bit immediate.
1135         (EXT-B*): Shift 16 bit immediate left by 1.
1136         (ADDIU*): Don't sign extend immediate value.
1137
1138 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1139
1140         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1141
1142         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1143         functions.
1144
1145         * mips.igen (delayslot32, nullify_next_insn): New functions.
1146         (m16.igen): Always include.
1147         (do_*): Add more tracing.
1148
1149         * m16.igen (delayslot16): Add NIA argument, could be called by a
1150         32 bit MIPS16 instruction.
1151
1152         * interp.c (ifetch16): Move function from here.
1153         * sim-main.c (ifetch16): To here.
1154
1155         * sim-main.c (ifetch16, ifetch32): Update to match current
1156         implementations of LH, LW.
1157         (signal_exception): Don't print out incorrect hex value of illegal
1158         instruction.
1159
1160 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1161
1162         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1163         instruction.
1164
1165         * m16.igen: Implement MIPS16 instructions.
1166
1167         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1168         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1169         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1170         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1171         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1172         bodies of corresponding code from 32 bit insn to these.  Also used
1173         by MIPS16 versions of functions.
1174
1175         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1176         (IMEM16): Drop NR argument from macro.
1177
1178 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1179
1180         * Makefile.in (SIM_OBJS): Add sim-main.o.
1181
1182         * sim-main.h (address_translation, load_memory, store_memory,
1183         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1184         as INLINE_SIM_MAIN.
1185         (pr_addr, pr_uword64): Declare.
1186         (sim-main.c): Include when H_REVEALS_MODULE_P.
1187
1188         * interp.c (address_translation, load_memory, store_memory,
1189         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1190         from here.
1191         * sim-main.c: To here. Fix compilation problems.
1192
1193         * configure.in: Enable inlining.
1194         * configure: Re-config.
1195
1196 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1197
1198         * configure: Regenerated to track ../common/aclocal.m4 changes.
1199
1200 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1201
1202         * mips.igen: Include tx.igen.
1203         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1204         * tx.igen: New file, contains MADD and MADDU.
1205
1206         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1207         the hardwired constant `7'.
1208         (store_memory): Ditto.
1209         (LOADDRMASK): Move definition to sim-main.h.
1210
1211         mips.igen (MTC0): Enable for r3900.
1212         (ADDU): Add trace.
1213
1214         mips.igen (do_load_byte): Delete.
1215         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1216         do_store_right): New functions.
1217         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1218
1219         configure.in: Let the tx39 use igen again.
1220         configure: Update.
1221
1222 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1223
1224         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1225         not an address sized quantity.  Return zero for cache sizes.
1226
1227 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1228
1229         * mips.igen (r3900): r3900 does not support 64 bit integer
1230         operations.
1231
1232 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1233
1234         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1235         than igen one.
1236         * configure : Rebuild.
1237
1238 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1239
1240         * configure: Regenerated to track ../common/aclocal.m4 changes.
1241
1242 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1243
1244         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1245
1246 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1247
1248         * configure: Regenerated to track ../common/aclocal.m4 changes.
1249         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1250
1251 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1252
1253         * configure: Regenerated to track ../common/aclocal.m4 changes.
1254
1255 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1256
1257         * interp.c (Max, Min): Comment out functions. Not yet used.
1258
1259 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1260
1261         * configure: Regenerated to track ../common/aclocal.m4 changes.
1262
1263 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1264
1265         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1266         configurable settings for stand-alone simulator.
1267
1268         * configure.in: Added X11 search, just in case.
1269
1270         * configure: Regenerated.
1271
1272 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1273
1274         * interp.c (sim_write, sim_read, load_memory, store_memory):
1275         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1276
1277 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1278
1279         * sim-main.h (GETFCC): Return an unsigned value.
1280
1281 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1282
1283         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1284         (DADD): Result destination is RD not RT.
1285
1286 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1287
1288         * sim-main.h (HIACCESS, LOACCESS): Always define.
1289
1290         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1291
1292         * interp.c (sim_info): Delete.
1293
1294 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1295
1296         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1297         (mips_option_handler): New argument `cpu'.
1298         (sim_open): Update call to sim_add_option_table.
1299
1300 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1301
1302         * mips.igen (CxC1): Add tracing.
1303
1304 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1305
1306         * sim-main.h (Max, Min): Declare.
1307
1308         * interp.c (Max, Min): New functions.
1309
1310         * mips.igen (BC1): Add tracing.
1311
1312 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1313
1314         * interp.c Added memory map for stack in vr4100
1315
1316 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1317
1318         * interp.c (load_memory): Add missing "break"'s.
1319
1320 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1321
1322         * interp.c (sim_store_register, sim_fetch_register): Pass in
1323         length parameter.  Return -1.
1324
1325 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1326
1327         * interp.c: Added hardware init hook, fixed warnings.
1328
1329 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1332
1333 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1334
1335         * interp.c (ifetch16): New function.
1336
1337         * sim-main.h (IMEM32): Rename IMEM.
1338         (IMEM16_IMMED): Define.
1339         (IMEM16): Define.
1340         (DELAY_SLOT): Update.
1341
1342         * m16run.c (sim_engine_run): New file.
1343
1344         * m16.igen: All instructions except LB.
1345         (LB): Call do_load_byte.
1346         * mips.igen (do_load_byte): New function.
1347         (LB): Call do_load_byte.
1348
1349         * mips.igen: Move spec for insn bit size and high bit from here.
1350         * Makefile.in (tmp-igen, tmp-m16): To here.
1351
1352         * m16.dc: New file, decode mips16 instructions.
1353
1354         * Makefile.in (SIM_NO_ALL): Define.
1355         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1356
1357 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1358
1359         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1360         point unit to 32 bit registers.
1361         * configure: Re-generate.
1362
1363 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1364
1365         * configure.in (sim_use_gen): Make IGEN the default simulator
1366         generator for generic 32 and 64 bit mips targets.
1367         * configure: Re-generate.
1368
1369 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1370
1371         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1372         bitsize.
1373
1374         * interp.c (sim_fetch_register, sim_store_register): Read/write
1375         FGR from correct location.
1376         (sim_open): Set size of FGR's according to
1377         WITH_TARGET_FLOATING_POINT_BITSIZE.
1378
1379         * sim-main.h (FGR): Store floating point registers in a separate
1380         array.
1381
1382 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1383
1384         * configure: Regenerated to track ../common/aclocal.m4 changes.
1385
1386 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1387
1388         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1389
1390         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1391
1392         * interp.c (pending_tick): New function.  Deliver pending writes.
1393
1394         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1395         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1396         it can handle mixed sized quantites and single bits.
1397
1398 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1399
1400         * interp.c (oengine.h): Do not include when building with IGEN.
1401         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1402         (sim_info): Ditto for PROCESSOR_64BIT.
1403         (sim_monitor): Replace ut_reg with unsigned_word.
1404         (*): Ditto for t_reg.
1405         (LOADDRMASK): Define.
1406         (sim_open): Remove defunct check that host FP is IEEE compliant,
1407         using software to emulate floating point.
1408         (value_fpr, ...): Always compile, was conditional on HASFPU.
1409
1410 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1411
1412         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1413         size.
1414
1415         * interp.c (SD, CPU): Define.
1416         (mips_option_handler): Set flags in each CPU.
1417         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1418         (sim_close): Do not clear STATE, deleted anyway.
1419         (sim_write, sim_read): Assume CPU zero's vm should be used for
1420         data transfers.
1421         (sim_create_inferior): Set the PC for all processors.
1422         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1423         argument.
1424         (mips16_entry): Pass correct nr of args to store_word, load_word.
1425         (ColdReset): Cold reset all cpu's.
1426         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1427         (sim_monitor, load_memory, store_memory, signal_exception): Use
1428         `CPU' instead of STATE_CPU.
1429
1430
1431         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1432         SD or CPU_.
1433
1434         * sim-main.h (signal_exception): Add sim_cpu arg.
1435         (SignalException*): Pass both SD and CPU to signal_exception.
1436         * interp.c (signal_exception): Update.
1437
1438         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1439         Ditto
1440         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1441         address_translation): Ditto
1442         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1443
1444 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * configure: Regenerated to track ../common/aclocal.m4 changes.
1447
1448 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1449
1450         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1451
1452         * mips.igen (model): Map processor names onto BFD name.
1453
1454         * sim-main.h (CPU_CIA): Delete.
1455         (SET_CIA, GET_CIA): Define
1456
1457 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1458
1459         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1460         regiser.
1461
1462         * configure.in (default_endian): Configure a big-endian simulator
1463         by default.
1464         * configure: Re-generate.
1465
1466 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1467
1468         * configure: Regenerated to track ../common/aclocal.m4 changes.
1469
1470 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1471
1472         * interp.c (sim_monitor): Handle Densan monitor outbyte
1473         and inbyte functions.
1474
1475 1997-12-29  Felix Lee  <flee@cygnus.com>
1476
1477         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1478
1479 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1480
1481         * Makefile.in (tmp-igen): Arrange for $zero to always be
1482         reset to zero after every instruction.
1483
1484 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1485
1486         * configure: Regenerated to track ../common/aclocal.m4 changes.
1487         * config.in: Ditto.
1488
1489 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1490
1491         * mips.igen (MSUB): Fix to work like MADD.
1492         * gencode.c (MSUB): Similarly.
1493
1494 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1495
1496         * configure: Regenerated to track ../common/aclocal.m4 changes.
1497
1498 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1499
1500         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1501
1502 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1503
1504         * sim-main.h (sim-fpu.h): Include.
1505
1506         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1507         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1508         using host independant sim_fpu module.
1509
1510 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1511
1512         * interp.c (signal_exception): Report internal errors with SIGABRT
1513         not SIGQUIT.
1514
1515         * sim-main.h (C0_CONFIG): New register.
1516         (signal.h): No longer include.
1517
1518         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1519
1520 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1521
1522         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1523
1524 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1525
1526         * mips.igen: Tag vr5000 instructions.
1527         (ANDI): Was missing mipsIV model, fix assembler syntax.
1528         (do_c_cond_fmt): New function.
1529         (C.cond.fmt): Handle mips I-III which do not support CC field
1530         separatly.
1531         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1532         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1533         in IV3.2 spec.
1534         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1535         vr5000 which saves LO in a GPR separatly.
1536
1537         * configure.in (enable-sim-igen): For vr5000, select vr5000
1538         specific instructions.
1539         * configure: Re-generate.
1540
1541 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1542
1543         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1544
1545         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1546         fmt_uninterpreted_64 bit cases to switch.  Convert to
1547         fmt_formatted,
1548
1549         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1550
1551         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1552         as specified in IV3.2 spec.
1553         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1554
1555 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1556
1557         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1558         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1559         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1560         PENDING_FILL versions of instructions.  Simplify.
1561         (X): New function.
1562         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1563         instructions.
1564         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1565         a signed value.
1566         (MTHI, MFHI): Disable code checking HI-LO.
1567
1568         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1569         global.
1570         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1571
1572 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1573
1574         * gencode.c (build_mips16_operands): Replace IPC with cia.
1575
1576         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1577         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1578         IPC to `cia'.
1579         (UndefinedResult): Replace function with macro/function
1580         combination.
1581         (sim_engine_run): Don't save PC in IPC.
1582
1583         * sim-main.h (IPC): Delete.
1584
1585
1586         * interp.c (signal_exception, store_word, load_word,
1587         address_translation, load_memory, store_memory, cache_op,
1588         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1589         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1590         current instruction address - cia - argument.
1591         (sim_read, sim_write): Call address_translation directly.
1592         (sim_engine_run): Rename variable vaddr to cia.
1593         (signal_exception): Pass cia to sim_monitor
1594
1595         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1596         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1597         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1598
1599         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1600         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1601         SIM_ASSERT.
1602
1603         * interp.c (signal_exception): Pass restart address to
1604         sim_engine_restart.
1605
1606         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1607         idecode.o): Add dependency.
1608
1609         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1610         Delete definitions
1611         (DELAY_SLOT): Update NIA not PC with branch address.
1612         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1613
1614         * mips.igen: Use CIA not PC in branch calculations.
1615         (illegal): Call SignalException.
1616         (BEQ, ADDIU): Fix assembler.
1617
1618 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1619
1620         * m16.igen (JALX): Was missing.
1621
1622         * configure.in (enable-sim-igen): New configuration option.
1623         * configure: Re-generate.
1624
1625         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1626
1627         * interp.c (load_memory, store_memory): Delete parameter RAW.
1628         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1629         bypassing {load,store}_memory.
1630
1631         * sim-main.h (ByteSwapMem): Delete definition.
1632
1633         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1634
1635         * interp.c (sim_do_command, sim_commands): Delete mips specific
1636         commands.  Handled by module sim-options.
1637
1638         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1639         (WITH_MODULO_MEMORY): Define.
1640
1641         * interp.c (sim_info): Delete code printing memory size.
1642
1643         * interp.c (mips_size): Nee sim_size, delete function.
1644         (power2): Delete.
1645         (monitor, monitor_base, monitor_size): Delete global variables.
1646         (sim_open, sim_close): Delete code creating monitor and other
1647         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1648         manage memory regions.
1649         (load_memory, store_memory): Use sim-core for memory model.
1650
1651         * interp.c (address_translation): Delete all memory map code
1652         except line forcing 32 bit addresses.
1653
1654 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1655
1656         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1657         trace options.
1658
1659         * interp.c (logfh, logfile): Delete globals.
1660         (sim_open, sim_close): Delete code opening & closing log file.
1661         (mips_option_handler): Delete -l and -n options.
1662         (OPTION mips_options): Ditto.
1663
1664         * interp.c (OPTION mips_options): Rename option trace to dinero.
1665         (mips_option_handler): Update.
1666
1667 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1668
1669         * interp.c (fetch_str): New function.
1670         (sim_monitor): Rewrite using sim_read & sim_write.
1671         (sim_open): Check magic number.
1672         (sim_open): Write monitor vectors into memory using sim_write.
1673         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1674         (sim_read, sim_write): Simplify - transfer data one byte at a
1675         time.
1676         (load_memory, store_memory): Clarify meaning of parameter RAW.
1677
1678         * sim-main.h (isHOST): Defete definition.
1679         (isTARGET): Mark as depreciated.
1680         (address_translation): Delete parameter HOST.
1681
1682         * interp.c (address_translation): Delete parameter HOST.
1683
1684 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1685
1686         * mips.igen:
1687
1688         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1689         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1690
1691 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1692
1693         * mips.igen: Add model filter field to records.
1694
1695 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1696
1697         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1698
1699         interp.c (sim_engine_run): Do not compile function sim_engine_run
1700         when WITH_IGEN == 1.
1701
1702         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1703         target architecture.
1704
1705         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1706         igen. Replace with configuration variables sim_igen_flags /
1707         sim_m16_flags.
1708
1709         * m16.igen: New file.  Copy mips16 insns here.
1710         * mips.igen: From here.
1711
1712 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1713
1714         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1715         to top.
1716         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1717
1718 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1719
1720         * gencode.c (build_instruction): Follow sim_write's lead in using
1721         BigEndianMem instead of !ByteSwapMem.
1722
1723 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1724
1725         * configure.in (sim_gen): Dependent on target, select type of
1726         generator.  Always select old style generator.
1727
1728         configure: Re-generate.
1729
1730         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1731         targets.
1732         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1733         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1734         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1735         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1736         SIM_@sim_gen@_*, set by autoconf.
1737
1738 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1739
1740         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1741
1742         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1743         CURRENT_FLOATING_POINT instead.
1744
1745         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1746         (address_translation): Raise exception InstructionFetch when
1747         translation fails and isINSTRUCTION.
1748
1749         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1750         sim_engine_run): Change type of of vaddr and paddr to
1751         address_word.
1752         (address_translation, prefetch, load_memory, store_memory,
1753         cache_op): Change type of vAddr and pAddr to address_word.
1754
1755         * gencode.c (build_instruction): Change type of vaddr and paddr to
1756         address_word.
1757
1758 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1759
1760         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1761         macro to obtain result of ALU op.
1762
1763 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1764
1765         * interp.c (sim_info): Call profile_print.
1766
1767 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1768
1769         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1770
1771         * sim-main.h (WITH_PROFILE): Do not define, defined in
1772         common/sim-config.h.  Use sim-profile module.
1773         (simPROFILE): Delete defintion.
1774
1775         * interp.c (PROFILE): Delete definition.
1776         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1777         (sim_close): Delete code writing profile histogram.
1778         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1779         Delete.
1780         (sim_engine_run): Delete code profiling the PC.
1781
1782 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1783
1784         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1785
1786         * interp.c (sim_monitor): Make register pointers of type
1787         unsigned_word*.
1788
1789         * sim-main.h: Make registers of type unsigned_word not
1790         signed_word.
1791
1792 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1793
1794         * interp.c (sync_operation): Rename from SyncOperation, make
1795         global, add SD argument.
1796         (prefetch): Rename from Prefetch, make global, add SD argument.
1797         (decode_coproc): Make global.
1798
1799         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1800
1801         * gencode.c (build_instruction): Generate DecodeCoproc not
1802         decode_coproc calls.
1803
1804         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1805         (SizeFGR): Move to sim-main.h
1806         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1807         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1808         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1809         sim-main.h.
1810         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1811         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1812         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1813         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1814         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1815         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1816
1817         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1818         exception.
1819         (sim-alu.h): Include.
1820         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1821         (sim_cia): Typedef to instruction_address.
1822
1823 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1824
1825         * Makefile.in (interp.o): Rename generated file engine.c to
1826         oengine.c.
1827
1828         * interp.c: Update.
1829
1830 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1831
1832         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1833
1834 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1835
1836         * gencode.c (build_instruction): For "FPSQRT", output correct
1837         number of arguments to Recip.
1838
1839 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1840
1841         * Makefile.in (interp.o): Depends on sim-main.h
1842
1843         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1844
1845         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1846         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1847         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1848         STATE, DSSTATE): Define
1849         (GPR, FGRIDX, ..): Define.
1850
1851         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1852         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1853         (GPR, FGRIDX, ...): Delete macros.
1854
1855         * interp.c: Update names to match defines from sim-main.h
1856
1857 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1858
1859         * interp.c (sim_monitor): Add SD argument.
1860         (sim_warning): Delete.  Replace calls with calls to
1861         sim_io_eprintf.
1862         (sim_error): Delete. Replace calls with sim_io_error.
1863         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1864         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1865         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1866         argument.
1867         (mips_size): Rename from sim_size. Add SD argument.
1868
1869         * interp.c (simulator): Delete global variable.
1870         (callback): Delete global variable.
1871         (mips_option_handler, sim_open, sim_write, sim_read,
1872         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1873         sim_size,sim_monitor): Use sim_io_* not callback->*.
1874         (sim_open): ZALLOC simulator struct.
1875         (PROFILE): Do not define.
1876
1877 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1878
1879         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1880         support.h with corresponding code.
1881
1882         * sim-main.h (word64, uword64), support.h: Move definition to
1883         sim-main.h.
1884         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1885
1886         * support.h: Delete
1887         * Makefile.in: Update dependencies
1888         * interp.c: Do not include.
1889
1890 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1891
1892         * interp.c (address_translation, load_memory, store_memory,
1893         cache_op): Rename to from AddressTranslation et.al., make global,
1894         add SD argument
1895
1896         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1897         CacheOp): Define.
1898
1899         * interp.c (SignalException): Rename to signal_exception, make
1900         global.
1901
1902         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1903
1904         * sim-main.h (SignalException, SignalExceptionInterrupt,
1905         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1906         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1907         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1908         Define.
1909
1910         * interp.c, support.h: Use.
1911
1912 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1913
1914         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1915         to value_fpr / store_fpr. Add SD argument.
1916         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1917         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1918
1919         * sim-main.h (ValueFPR, StoreFPR): Define.
1920
1921 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * interp.c (sim_engine_run): Check consistency between configure
1924         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1925         and HASFPU.
1926
1927         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1928         (mips_fpu): Configure WITH_FLOATING_POINT.
1929         (mips_endian): Configure WITH_TARGET_ENDIAN.
1930         * configure: Update.
1931
1932 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * configure: Regenerated to track ../common/aclocal.m4 changes.
1935
1936 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1937
1938         * configure: Regenerated.
1939
1940 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1941
1942         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1943
1944 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1945
1946         * gencode.c (print_igen_insn_models): Assume certain architectures
1947         include all mips* instructions.
1948         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1949         instruction.
1950
1951         * Makefile.in (tmp.igen): Add target. Generate igen input from
1952         gencode file.
1953
1954         * gencode.c (FEATURE_IGEN): Define.
1955         (main): Add --igen option.  Generate output in igen format.
1956         (process_instructions): Format output according to igen option.
1957         (print_igen_insn_format): New function.
1958         (print_igen_insn_models): New function.
1959         (process_instructions): Only issue warnings and ignore
1960         instructions when no FEATURE_IGEN.
1961
1962 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1963
1964         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1965         MIPS targets.
1966
1967 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1968
1969         * configure: Regenerated to track ../common/aclocal.m4 changes.
1970
1971 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1972
1973         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1974         SIM_RESERVED_BITS): Delete, moved to common.
1975         (SIM_EXTRA_CFLAGS): Update.
1976
1977 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * configure.in: Configure non-strict memory alignment.
1980         * configure: Regenerated to track ../common/aclocal.m4 changes.
1981
1982 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1983
1984         * configure: Regenerated to track ../common/aclocal.m4 changes.
1985
1986 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1987
1988         * gencode.c (SDBBP,DERET): Added (3900) insns.
1989         (RFE): Turn on for 3900.
1990         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1991         (dsstate): Made global.
1992         (SUBTARGET_R3900): Added.
1993         (CANCELDELAYSLOT): New.
1994         (SignalException): Ignore SystemCall rather than ignore and
1995         terminate.  Add DebugBreakPoint handling.
1996         (decode_coproc): New insns RFE, DERET; and new registers Debug
1997         and DEPC protected by SUBTARGET_R3900.
1998         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1999         bits explicitly.
2000         * Makefile.in,configure.in: Add mips subtarget option.
2001         * configure: Update.
2002
2003 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2004
2005         * gencode.c: Add r3900 (tx39).
2006
2007
2008 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2009
2010         * gencode.c (build_instruction): Don't need to subtract 4 for
2011         JALR, just 2.
2012
2013 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2014
2015         * interp.c: Correct some HASFPU problems.
2016
2017 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2018
2019         * configure: Regenerated to track ../common/aclocal.m4 changes.
2020
2021 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2022
2023         * interp.c (mips_options): Fix samples option short form, should
2024         be `x'.
2025
2026 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2027
2028         * interp.c (sim_info): Enable info code.  Was just returning.
2029
2030 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2031
2032         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2033         MFC0.
2034
2035 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2036
2037         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2038         constants.
2039         (build_instruction): Ditto for LL.
2040
2041 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2042
2043         * configure: Regenerated to track ../common/aclocal.m4 changes.
2044
2045 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2046
2047         * configure: Regenerated to track ../common/aclocal.m4 changes.
2048         * config.in: Ditto.
2049
2050 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2051
2052         * interp.c (sim_open): Add call to sim_analyze_program, update
2053         call to sim_config.
2054
2055 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2056
2057         * interp.c (sim_kill): Delete.
2058         (sim_create_inferior): Add ABFD argument. Set PC from same.
2059         (sim_load): Move code initializing trap handlers from here.
2060         (sim_open): To here.
2061         (sim_load): Delete, use sim-hload.c.
2062
2063         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2064
2065 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2066
2067         * configure: Regenerated to track ../common/aclocal.m4 changes.
2068         * config.in: Ditto.
2069
2070 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2071
2072         * interp.c (sim_open): Add ABFD argument.
2073         (sim_load): Move call to sim_config from here.
2074         (sim_open): To here.  Check return status.
2075
2076 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2077
2078         * gencode.c (build_instruction): Two arg MADD should
2079         not assign result to $0.
2080
2081 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2082
2083         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2084         * sim/mips/configure.in: Regenerate.
2085
2086 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2087
2088         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2089         signed8, unsigned8 et.al. types.
2090
2091         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2092         hosts when selecting subreg.
2093
2094 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2095
2096         * interp.c (sim_engine_run): Reset the ZERO register to zero
2097         regardless of FEATURE_WARN_ZERO.
2098         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2099
2100 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2101
2102         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2103         (SignalException): For BreakPoints ignore any mode bits and just
2104         save the PC.
2105         (SignalException): Always set the CAUSE register.
2106
2107 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2108
2109         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2110         exception has been taken.
2111
2112         * interp.c: Implement the ERET and mt/f sr instructions.
2113
2114 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2115
2116         * interp.c (SignalException): Don't bother restarting an
2117         interrupt.
2118
2119 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2120
2121         * interp.c (SignalException): Really take an interrupt.
2122         (interrupt_event): Only deliver interrupts when enabled.
2123
2124 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2125
2126         * interp.c (sim_info): Only print info when verbose.
2127         (sim_info) Use sim_io_printf for output.
2128
2129 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2130
2131         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2132         mips architectures.
2133
2134 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2135
2136         * interp.c (sim_do_command): Check for common commands if a
2137         simulator specific command fails.
2138
2139 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2140
2141         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2142         and simBE when DEBUG is defined.
2143
2144 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2145
2146         * interp.c (interrupt_event): New function.  Pass exception event
2147         onto exception handler.
2148
2149         * configure.in: Check for stdlib.h.
2150         * configure: Regenerate.
2151
2152         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2153         variable declaration.
2154         (build_instruction): Initialize memval1.
2155         (build_instruction): Add UNUSED attribute to byte, bigend,
2156         reverse.
2157         (build_operands): Ditto.
2158
2159         * interp.c: Fix GCC warnings.
2160         (sim_get_quit_code): Delete.
2161
2162         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2163         * Makefile.in: Ditto.
2164         * configure: Re-generate.
2165
2166         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2167
2168 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2169
2170         * interp.c (mips_option_handler): New function parse argumes using
2171         sim-options.
2172         (myname): Replace with STATE_MY_NAME.
2173         (sim_open): Delete check for host endianness - performed by
2174         sim_config.
2175         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2176         (sim_open): Move much of the initialization from here.
2177         (sim_load): To here.  After the image has been loaded and
2178         endianness set.
2179         (sim_open): Move ColdReset from here.
2180         (sim_create_inferior): To here.
2181         (sim_open): Make FP check less dependant on host endianness.
2182
2183         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2184         run.
2185         * interp.c (sim_set_callbacks): Delete.
2186
2187         * interp.c (membank, membank_base, membank_size): Replace with
2188         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2189         (sim_open): Remove call to callback->init. gdb/run do this.
2190
2191         * interp.c: Update
2192
2193         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2194
2195         * interp.c (big_endian_p): Delete, replaced by
2196         current_target_byte_order.
2197
2198 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2199
2200         * interp.c (host_read_long, host_read_word, host_swap_word,
2201         host_swap_long): Delete. Using common sim-endian.
2202         (sim_fetch_register, sim_store_register): Use H2T.
2203         (pipeline_ticks): Delete.  Handled by sim-events.
2204         (sim_info): Update.
2205         (sim_engine_run): Update.
2206
2207 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2208
2209         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2210         reason from here.
2211         (SignalException): To here. Signal using sim_engine_halt.
2212         (sim_stop_reason): Delete, moved to common.
2213
2214 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2215
2216         * interp.c (sim_open): Add callback argument.
2217         (sim_set_callbacks): Delete SIM_DESC argument.
2218         (sim_size): Ditto.
2219
2220 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2221
2222         * Makefile.in (SIM_OBJS): Add common modules.
2223
2224         * interp.c (sim_set_callbacks): Also set SD callback.
2225         (set_endianness, xfer_*, swap_*): Delete.
2226         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2227         Change to functions using sim-endian macros.
2228         (control_c, sim_stop): Delete, use common version.
2229         (simulate): Convert into.
2230         (sim_engine_run): This function.
2231         (sim_resume): Delete.
2232
2233         * interp.c (simulation): New variable - the simulator object.
2234         (sim_kind): Delete global - merged into simulation.
2235         (sim_load): Cleanup.  Move PC assignment from here.
2236         (sim_create_inferior): To here.
2237
2238         * sim-main.h: New file.
2239         * interp.c (sim-main.h): Include.
2240
2241 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2242
2243         * configure: Regenerated to track ../common/aclocal.m4 changes.
2244
2245 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2246
2247         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2248
2249 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2250
2251         * gencode.c (build_instruction): DIV instructions: check
2252         for division by zero and integer overflow before using
2253         host's division operation.
2254
2255 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2256
2257         * Makefile.in (SIM_OBJS): Add sim-load.o.
2258         * interp.c: #include bfd.h.
2259         (target_byte_order): Delete.
2260         (sim_kind, myname, big_endian_p): New static locals.
2261         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2262         after argument parsing.  Recognize -E arg, set endianness accordingly.
2263         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2264         load file into simulator.  Set PC from bfd.
2265         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2266         (set_endianness): Use big_endian_p instead of target_byte_order.
2267
2268 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2269
2270         * interp.c (sim_size): Delete prototype - conflicts with
2271         definition in remote-sim.h.  Correct definition.
2272
2273 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2274
2275         * configure: Regenerated to track ../common/aclocal.m4 changes.
2276         * config.in: Ditto.
2277
2278 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2279
2280         * interp.c (sim_open): New arg `kind'.
2281
2282         * configure: Regenerated to track ../common/aclocal.m4 changes.
2283
2284 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2285
2286         * configure: Regenerated to track ../common/aclocal.m4 changes.
2287
2288 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2289
2290         * interp.c (sim_open): Set optind to 0 before calling getopt.
2291
2292 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2293
2294         * configure: Regenerated to track ../common/aclocal.m4 changes.
2295
2296 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2297
2298         * interp.c : Replace uses of pr_addr with pr_uword64
2299         where the bit length is always 64 independent of SIM_ADDR.
2300         (pr_uword64) : added.
2301
2302 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2303
2304         * configure: Re-generate.
2305
2306 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2307
2308         * configure: Regenerate to track ../common/aclocal.m4 changes.
2309
2310 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2311
2312         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2313         in argv form.
2314         (other sim_*): New SIM_DESC argument.
2315
2316 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2317
2318         * interp.c: Fix printing of addresses for non-64-bit targets.
2319         (pr_addr): Add function to print address based on size.
2320
2321 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2322
2323         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2324
2325 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2326
2327         * gencode.c (build_mips16_operands): Correct computation of base
2328         address for extended PC relative instruction.
2329
2330 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2331
2332         * interp.c (mips16_entry): Add support for floating point cases.
2333         (SignalException): Pass floating point cases to mips16_entry.
2334         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2335         registers.
2336         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2337         or fmt_word.
2338         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2339         and then set the state to fmt_uninterpreted.
2340         (COP_SW): Temporarily set the state to fmt_word while calling
2341         ValueFPR.
2342
2343 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2344
2345         * gencode.c (build_instruction): The high order may be set in the
2346         comparison flags at any ISA level, not just ISA 4.
2347
2348 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2349
2350         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2351         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2352         * configure.in: sinclude ../common/aclocal.m4.
2353         * configure: Regenerated.
2354
2355 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2356
2357         * configure: Rebuild after change to aclocal.m4.
2358
2359 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2360
2361         * configure configure.in Makefile.in:  Update to new configure
2362         scheme which is more compatible with WinGDB builds.
2363         * configure.in:  Improve comment on how to run autoconf.
2364         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2365         * Makefile.in:  Use autoconf substitution to install common
2366         makefile fragment.
2367
2368 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2369
2370         * gencode.c (build_instruction): Use BigEndianCPU instead of
2371         ByteSwapMem.
2372
2373 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2374
2375         * interp.c (sim_monitor): Make output to stdout visible in
2376         wingdb's I/O log window.
2377
2378 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2379
2380         * support.h: Undo previous change to SIGTRAP
2381         and SIGQUIT values.
2382
2383 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2384
2385         * interp.c (store_word, load_word): New static functions.
2386         (mips16_entry): New static function.
2387         (SignalException): Look for mips16 entry and exit instructions.
2388         (simulate): Use the correct index when setting fpr_state after
2389         doing a pending move.
2390
2391 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2392
2393         * interp.c: Fix byte-swapping code throughout to work on
2394         both little- and big-endian hosts.
2395
2396 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2397
2398         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2399         with gdb/config/i386/xm-windows.h.
2400
2401 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2402
2403         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2404         that messes up arithmetic shifts.
2405
2406 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2407
2408         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2409         SIGTRAP and SIGQUIT for _WIN32.
2410
2411 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2412
2413         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2414         force a 64 bit multiplication.
2415         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2416         destination register is 0, since that is the default mips16 nop
2417         instruction.
2418
2419 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2420
2421         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2422         (build_endian_shift): Don't check proc64.
2423         (build_instruction): Always set memval to uword64.  Cast op2 to
2424         uword64 when shifting it left in memory instructions.  Always use
2425         the same code for stores--don't special case proc64.
2426
2427         * gencode.c (build_mips16_operands): Fix base PC value for PC
2428         relative operands.
2429         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2430         jal instruction.
2431         * interp.c (simJALDELAYSLOT): Define.
2432         (JALDELAYSLOT): Define.
2433         (INDELAYSLOT, INJALDELAYSLOT): Define.
2434         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2435
2436 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2437
2438         * interp.c (sim_open): add flush_cache as a PMON routine
2439         (sim_monitor): handle flush_cache by ignoring it
2440
2441 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2442
2443         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2444         BigEndianMem.
2445         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2446         (BigEndianMem): Rename to ByteSwapMem and change sense.
2447         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2448         BigEndianMem references to !ByteSwapMem.
2449         (set_endianness): New function, with prototype.
2450         (sim_open): Call set_endianness.
2451         (sim_info): Use simBE instead of BigEndianMem.
2452         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2453         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2454         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2455         ifdefs, keeping the prototype declaration.
2456         (swap_word): Rewrite correctly.
2457         (ColdReset): Delete references to CONFIG.  Delete endianness related
2458         code; moved to set_endianness.
2459
2460 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2461
2462         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2463         * interp.c (CHECKHILO): Define away.
2464         (simSIGINT): New macro.
2465         (membank_size): Increase from 1MB to 2MB.
2466         (control_c): New function.
2467         (sim_resume): Rename parameter signal to signal_number.  Add local
2468         variable prev.  Call signal before and after simulate.
2469         (sim_stop_reason): Add simSIGINT support.
2470         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2471         functions always.
2472         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2473         if logfh is NULL.
2474         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2475         a call to sim_warning.
2476
2477 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2478
2479         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2480         16 bit instructions.
2481
2482 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2483
2484         Add support for mips16 (16 bit MIPS implementation):
2485         * gencode.c (inst_type): Add mips16 instruction encoding types.
2486         (GETDATASIZEINSN): Define.
2487         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2488         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2489         mtlo.
2490         (MIPS16_DECODE): New table, for mips16 instructions.
2491         (bitmap_val): New static function.
2492         (struct mips16_op): Define.
2493         (mips16_op_table): New table, for mips16 operands.
2494         (build_mips16_operands): New static function.
2495         (process_instructions): If PC is odd, decode a mips16
2496         instruction.  Break out instruction handling into new
2497         build_instruction function.
2498         (build_instruction): New static function, broken out of
2499         process_instructions.  Check modifiers rather than flags for SHIFT
2500         bit count and m[ft]{hi,lo} direction.
2501         (usage): Pass program name to fprintf.
2502         (main): Remove unused variable this_option_optind.  Change
2503         ``*loptarg++'' to ``loptarg++''.
2504         (my_strtoul): Parenthesize && within ||.
2505         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2506         (simulate): If PC is odd, fetch a 16 bit instruction, and
2507         increment PC by 2 rather than 4.
2508         * configure.in: Add case for mips16*-*-*.
2509         * configure: Rebuild.
2510
2511 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2512
2513         * interp.c: Allow -t to enable tracing in standalone simulator.
2514         Fix garbage output in trace file and error messages.
2515
2516 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2517
2518         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2519         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2520         * configure.in: Simplify using macros in ../common/aclocal.m4.
2521         * configure: Regenerated.
2522         * tconfig.in: New file.
2523
2524 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2525
2526         * interp.c: Fix bugs in 64-bit port.
2527         Use ansi function declarations for msvc compiler.
2528         Initialize and test file pointer in trace code.
2529         Prevent duplicate definition of LAST_EMED_REGNUM.
2530
2531 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2532
2533         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2534
2535 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2536
2537         * interp.c (SignalException): Check for explicit terminating
2538         breakpoint value.
2539         * gencode.c: Pass instruction value through SignalException()
2540         calls for Trap, Breakpoint and Syscall.
2541
2542 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2543
2544         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2545         only used on those hosts that provide it.
2546         * configure.in: Add sqrt() to list of functions to be checked for.
2547         * config.in: Re-generated.
2548         * configure: Re-generated.
2549
2550 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2551
2552         * gencode.c (process_instructions): Call build_endian_shift when
2553         expanding STORE RIGHT, to fix swr.
2554         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2555         clear the high bits.
2556         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2557         Fix float to int conversions to produce signed values.
2558
2559 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2560
2561         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2562         (process_instructions): Correct handling of nor instruction.
2563         Correct shift count for 32 bit shift instructions. Correct sign
2564         extension for arithmetic shifts to not shift the number of bits in
2565         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2566         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2567         Fix madd.
2568         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2569         It's OK to have a mult follow a mult.  What's not OK is to have a
2570         mult follow an mfhi.
2571         (Convert): Comment out incorrect rounding code.
2572
2573 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2574
2575         * interp.c (sim_monitor): Improved monitor printf
2576         simulation. Tidied up simulator warnings, and added "--log" option
2577         for directing warning message output.
2578         * gencode.c: Use sim_warning() rather than WARNING macro.
2579
2580 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2581
2582         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2583         getopt1.o, rather than on gencode.c.  Link objects together.
2584         Don't link against -liberty.
2585         (gencode.o, getopt.o, getopt1.o): New targets.
2586         * gencode.c: Include <ctype.h> and "ansidecl.h".
2587         (AND): Undefine after including "ansidecl.h".
2588         (ULONG_MAX): Define if not defined.
2589         (OP_*): Don't define macros; now defined in opcode/mips.h.
2590         (main): Call my_strtoul rather than strtoul.
2591         (my_strtoul): New static function.
2592
2593 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2594
2595         * gencode.c (process_instructions):  Generate word64 and uword64
2596         instead of `long long' and `unsigned long long' data types.
2597         * interp.c:  #include sysdep.h to get signals, and define default
2598         for SIGBUS.
2599         * (Convert):  Work around for Visual-C++ compiler bug with type
2600         conversion.
2601         * support.h:  Make things compile under Visual-C++ by using
2602         __int64 instead of `long long'.  Change many refs to long long
2603         into word64/uword64 typedefs.
2604
2605 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2606
2607         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2608         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2609         (docdir): Removed.
2610         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2611         (AC_PROG_INSTALL): Added.
2612         (AC_PROG_CC): Moved to before configure.host call.
2613         * configure: Rebuilt.
2614
2615 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2616
2617         * configure.in: Define @SIMCONF@ depending on mips target.
2618         * configure: Rebuild.
2619         * Makefile.in (run): Add @SIMCONF@ to control simulator
2620         construction.
2621         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2622         * interp.c: Remove some debugging, provide more detailed error
2623         messages, update memory accesses to use LOADDRMASK.
2624
2625 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2626
2627         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2628         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2629         stamp-h.
2630         * configure: Rebuild.
2631         * config.in: New file, generated by autoheader.
2632         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2633         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2634         HAVE_ANINT and HAVE_AINT, as appropriate.
2635         * Makefile.in (run): Use @LIBS@ rather than -lm.
2636         (interp.o): Depend upon config.h.
2637         (Makefile): Just rebuild Makefile.
2638         (clean): Remove stamp-h.
2639         (mostlyclean): Make the same as clean, not as distclean.
2640         (config.h, stamp-h): New targets.
2641
2642 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2643
2644         * interp.c (ColdReset): Fix boolean test. Make all simulator
2645         globals static.
2646
2647 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2648
2649         * interp.c (xfer_direct_word, xfer_direct_long,
2650         swap_direct_word, swap_direct_long, xfer_big_word,
2651         xfer_big_long, xfer_little_word, xfer_little_long,
2652         swap_word,swap_long): Added.
2653         * interp.c (ColdReset): Provide function indirection to
2654         host<->simulated_target transfer routines.
2655         * interp.c (sim_store_register, sim_fetch_register): Updated to
2656         make use of indirected transfer routines.
2657
2658 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2659
2660         * gencode.c (process_instructions): Ensure FP ABS instruction
2661         recognised.
2662         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2663         system call support.
2664
2665 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2666
2667         * interp.c (sim_do_command): Complain if callback structure not
2668         initialised.
2669
2670 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2671
2672         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2673         support for Sun hosts.
2674         * Makefile.in (gencode): Ensure the host compiler and libraries
2675         used for cross-hosted build.
2676
2677 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2678
2679         * interp.c, gencode.c: Some more (TODO) tidying.
2680
2681 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2682
2683         * gencode.c, interp.c: Replaced explicit long long references with
2684         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2685         * support.h (SET64LO, SET64HI): Macros added.
2686
2687 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2688
2689         * configure: Regenerate with autoconf 2.7.
2690
2691 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2692
2693         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2694         * support.h: Remove superfluous "1" from #if.
2695         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2696
2697 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2698
2699         * interp.c (StoreFPR): Control UndefinedResult() call on
2700         WARN_RESULT manifest.
2701
2702 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2703
2704         * gencode.c: Tidied instruction decoding, and added FP instruction
2705         support.
2706
2707         * interp.c: Added dineroIII, and BSD profiling support. Also
2708         run-time FP handling.
2709
2710 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2711
2712         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2713         gencode.c, interp.c, support.h: created.