1 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
3 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
8 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
10 * dv-tx3904tmr.c: New file - implements tx3904 timer.
11 * dv-tx3904{irc,cpu}.c: Mild reformatting.
12 * configure.in: Include tx3904tmr in hw_device list.
14 * interp.c (sim_open): Instantiate three timer instances.
15 Fix address typo of tx3904irc instance.
19 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
21 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
22 Select corresponding check_mt_hilo function.
23 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
26 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
30 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
32 * interp.c (signal_exception): SystemCall exception now uses
35 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
37 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
41 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
43 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
47 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
49 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
52 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
54 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
56 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
57 sim-main.h. Declare a struct hw_descriptor instead of struct
61 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
63 * mips.igen (do_store_left, do_load_left): Compute nr of left and
64 right bits and then re-align left hand bytes to correct byte
65 lanes. Fix incorrect computation in do_store_left when loading
66 bytes from second word.
69 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
71 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
72 * interp.c (sim_open): Only create a device tree when HW is
75 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
76 * interp.c (signal_exception): Ditto.
79 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
81 * gencode.c: Mark BEGEZALL as LIKELY.
83 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
85 * sim-main.h (ALU32_END): Sign extend 32 bit results.
86 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
89 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
91 * interp.c (sim_fetch_register): Convert internal r5900 regs to
95 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
97 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
98 modules. Recognize TX39 target with "mips*tx39" pattern.
100 * sim-main.h (*): Added many macros defining bits in
101 TX39 control registers.
102 (SignalInterrupt): Send actual PC instead of NULL.
103 (SignalNMIReset): New exception type.
104 * interp.c (board): New variable for future use to identify
105 a particular board being simulated.
106 (mips_option_handler,mips_options): Added "--board" option.
107 (interrupt_event): Send actual PC.
108 (sim_open): Make memory layout conditional on board setting.
109 (signal_exception): Initial implementation of hardware interrupt
110 handling. Accept another break instruction variant for simulator
112 (decode_coproc): Implement RFE instruction for TX39.
113 (mips.igen): Decode RFE instruction as such.
114 start-sanitize-tx3904
115 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
116 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
117 bbegin to implement memory map.
118 * dv-tx3904cpu.c: New file.
119 * dv-tx3904irc.c: New file.
122 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
124 * mips.igen (check_mt_hilo): Create a separate r3900 version.
127 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
129 * r5900.igen: Replace the calls and the definition of the
130 function check_op_hilo_hi1lo1 with the pair
131 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
134 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
136 * tx.igen (madd,maddu): Replace calls to check_op_hilo
137 with calls to check_div_hilo.
139 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
141 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
142 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
143 Add special r3900 version of do_mult_hilo.
144 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
145 with calls to check_mult_hilo.
146 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
147 with calls to check_div_hilo.
149 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
151 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
152 Document a replacement.
154 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
156 * interp.c (sim_monitor): Make mon_printf work.
158 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
160 * sim-main.h (INSN_NAME): New arg `cpu'.
163 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
165 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
170 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
172 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
173 * r5900.igen (r59fp_overflow): Use.
175 * r5900.igen (r59fp_op3): Rename to
176 (r59fp_mula): This, delete opm argument.
177 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
178 (r59fp_mula): Overflowing product propogates through to result.
179 (r59fp_mula): ACC to the MAX propogates to result.
180 (r59fp_mula): Underflow during multiply only sets SU.
183 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
185 * configure: Regenerated to track ../common/aclocal.m4 changes.
187 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
189 * configure: Regenerated to track ../common/aclocal.m4 changes.
192 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
194 * acconfig.h: New file.
195 * configure.in: Reverted change of Apr 24; use sinclude again.
197 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
199 * configure: Regenerated to track ../common/aclocal.m4 changes.
202 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
204 * configure.in: Don't call sinclude.
206 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
208 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
210 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
212 * mips.igen (ERET): Implement.
214 * interp.c (decode_coproc): Return sign-extended EPC.
216 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
218 * interp.c (signal_exception): Do not ignore Trap.
219 (signal_exception): On TRAP, restart at exception address.
220 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
221 (signal_exception): Update.
222 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
223 so that TRAP instructions are caught.
225 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
227 * sim-main.h (struct hilo_access, struct hilo_history): Define,
228 contains HI/LO access history.
229 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
230 (HIACCESS, LOACCESS): Delete, replace with
231 (HIHISTORY, LOHISTORY): New macros.
232 (start-sanitize-r5900):
233 (struct sim_5900_cpu): Make hi1access, lo1access of type
235 (HI1ACCESS, LO1ACCESS): Delete, replace with
236 (HI1HISTORY, LO1HISTORY): New macros.
237 (end-sanitize-r5900):
238 (CHECKHILO): Delete all, moved to mips.igen
240 * gencode.c (build_instruction): Do not generate checks for
241 correct HI/LO register usage.
243 * interp.c (old_engine_run): Delete checks for correct HI/LO
246 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
247 check_mf_cycles): New functions.
248 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
249 do_divu, domultx, do_mult, do_multu): Use.
251 * tx.igen ("madd", "maddu"): Use.
252 (start-sanitize-r5900):
254 r5900.igen: Update all HI/LO checks.
255 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
256 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
257 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
258 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
259 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
261 (end-sanitize-r5900):
264 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
266 * interp.c (decode_coproc): Correct CMFC2/QMTC2
269 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
270 instead of a single 128-bit access.
274 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
276 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
277 * interp.c (cop_[ls]q): Fixes corresponding to above.
281 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
283 * interp.c (decode_coproc): Adapt COP2 micro interlock to
284 clarified specs. Reset "M" bit; exit also on "E" bit.
288 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
290 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
291 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
293 * r5900.igen (r59fp_unpack): New function.
294 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
295 RSQRT.S, SQRT.S): Use.
296 (r59fp_zero): New function.
297 (r59fp_overflow): Generate r5900 specific overflow value.
298 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
300 (CVT.S.W, CVT.W.S): Exchange implementations.
302 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
306 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
308 * configure.in (tx19, sim_use_gen): Switch to igen.
309 * configure: Re-build.
313 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
315 * interp.c (decode_coproc): Make COP2 branch code compile after
316 igen signature changes.
319 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
321 * mips.igen (DSRAV): Use function do_dsrav.
322 (SRAV): Use new function do_srav.
324 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
325 (B): Sign extend 11 bit immediate.
326 (EXT-B*): Shift 16 bit immediate left by 1.
327 (ADDIU*): Don't sign extend immediate value.
329 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
331 * m16run.c (sim_engine_run): Restore CIA after handling an event.
334 * mips.igen (mtc0): Valid tx19 instruction.
337 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
340 * mips.igen (delayslot32, nullify_next_insn): New functions.
341 (m16.igen): Always include.
342 (do_*): Add more tracing.
344 * m16.igen (delayslot16): Add NIA argument, could be called by a
345 32 bit MIPS16 instruction.
347 * interp.c (ifetch16): Move function from here.
348 * sim-main.c (ifetch16): To here.
350 * sim-main.c (ifetch16, ifetch32): Update to match current
351 implementations of LH, LW.
352 (signal_exception): Don't print out incorrect hex value of illegal
355 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
357 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
360 * m16.igen: Implement MIPS16 instructions.
362 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
363 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
364 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
365 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
366 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
367 bodies of corresponding code from 32 bit insn to these. Also used
368 by MIPS16 versions of functions.
370 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
371 (IMEM16): Drop NR argument from macro.
374 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
376 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
377 of VU lower instruction.
381 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
383 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
386 * sim-main.h: Removed attempt at allowing 128-bit access.
390 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
392 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
394 * interp.c (decode_coproc): Refer to VU CIA as a "special"
395 register, not as a "misc" register. Aha. Add activity
396 assertions after VCALLMS* instructions.
400 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
402 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
403 to upper code of generated VU instruction.
407 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
409 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
411 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
414 * r5900.igen (SQC2): Thinko.
418 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
420 * interp.c (*): Adapt code to merged VU device & state structs.
421 (decode_coproc): Execute COP2 each macroinstruction without
422 pipelining, by stepping VU to completion state. Adapted to
423 read_vu_*_reg style of register access.
425 * mips.igen ([SL]QC2): Removed these COP2 instructions.
427 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
429 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
432 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
434 * Makefile.in (SIM_OBJS): Add sim-main.o.
436 * sim-main.h (address_translation, load_memory, store_memory,
437 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
439 (pr_addr, pr_uword64): Declare.
440 (sim-main.c): Include when H_REVEALS_MODULE_P.
442 * interp.c (address_translation, load_memory, store_memory,
443 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
445 * sim-main.c: To here. Fix compilation problems.
447 * configure.in: Enable inlining.
448 * configure: Re-config.
450 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
452 * configure: Regenerated to track ../common/aclocal.m4 changes.
454 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
456 * mips.igen: Include tx.igen.
457 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
458 * tx.igen: New file, contains MADD and MADDU.
460 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
461 the hardwired constant `7'.
462 (store_memory): Ditto.
463 (LOADDRMASK): Move definition to sim-main.h.
465 mips.igen (MTC0): Enable for r3900.
468 mips.igen (do_load_byte): Delete.
469 (do_load, do_store, do_load_left, do_load_write, do_store_left,
470 do_store_right): New functions.
471 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
473 configure.in: Let the tx39 use igen again.
476 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
478 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
479 not an address sized quantity. Return zero for cache sizes.
481 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
483 * mips.igen (r3900): r3900 does not support 64 bit integer
487 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
489 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
493 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
495 * interp.c (decode_coproc): Continuing COP2 work.
496 (cop_[ls]q): Make sky-target-only.
498 * sim-main.h (COP_[LS]Q): Make sky-target-only.
500 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
502 * configure.in (mipstx39*-*-*): Use gencode simulator rather
504 * configure : Rebuild.
507 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
509 * interp.c (decode_coproc): Added a missing TARGET_SKY check
510 around COP2 implementation skeleton.
514 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
516 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
518 * interp.c (sim_{load,store}_register): Use new vu[01]_device
519 static to access VU registers.
520 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
521 decoding. Work in progress.
523 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
524 overlapping/redundant bit pattern.
525 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
528 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
531 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
532 access to coprocessor registers.
534 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
536 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
538 * configure: Regenerated to track ../common/aclocal.m4 changes.
540 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
542 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
544 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
546 * configure: Regenerated to track ../common/aclocal.m4 changes.
547 * config.in: Regenerated to track ../common/aclocal.m4 changes.
549 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
551 * configure: Regenerated to track ../common/aclocal.m4 changes.
553 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
555 * interp.c (Max, Min): Comment out functions. Not yet used.
557 start-sanitize-vr4320
558 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
560 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
563 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
565 * configure: Regenerated to track ../common/aclocal.m4 changes.
567 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
569 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
570 configurable settings for stand-alone simulator.
573 * configure.in: Added --with-sim-gpu2 option to specify path of
574 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
575 links/compiles stand-alone simulator with this library.
577 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
579 * configure.in: Added X11 search, just in case.
581 * configure: Regenerated.
583 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
585 * interp.c (sim_write, sim_read, load_memory, store_memory):
586 Replace sim_core_*_map with read_map, write_map, exec_map resp.
588 start-sanitize-vr4320
589 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
591 * vr4320.igen (clz,dclz) : Added.
592 (dmac): Replaced 99, with LO.
595 start-sanitize-vr5400
596 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
598 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
601 start-sanitize-vr4320
602 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
604 * vr4320.igen: New file.
605 * Makefile.in (vr4320.igen) : Added.
606 * configure.in (mips64vr4320-*-*): Added.
607 * configure : Rebuilt.
608 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
609 Add the vr4320 model entry and mark the vr4320 insn as necessary.
612 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
614 * sim-main.h (GETFCC): Return an unsigned value.
617 * r5900.igen: Use an unsigned array index variable `i'.
618 (QFSRV): Ditto for variable bytes.
621 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
623 * mips.igen (DIV): Fix check for -1 / MIN_INT.
624 (DADD): Result destination is RD not RT.
627 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
628 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
632 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
634 * sim-main.h (HIACCESS, LOACCESS): Always define.
636 * mdmx.igen (Maxi, Mini): Rename Max, Min.
638 * interp.c (sim_info): Delete.
640 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
642 * interp.c (DECLARE_OPTION_HANDLER): Use it.
643 (mips_option_handler): New argument `cpu'.
644 (sim_open): Update call to sim_add_option_table.
646 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
648 * mips.igen (CxC1): Add tracing.
651 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
653 * r5900.igen (StoreFP): Delete.
654 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
656 (rsqrt.s, sqrt.s): Implement.
657 (r59cond): New function.
658 (C.COND.S): Call r59cond in assembler line.
659 (cvt.w.s, cvt.s.w): Implement.
661 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
664 * sim-main.h: Define an enum of r5900 FCSR bit fields.
668 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
670 * r5900.igen: Add tracing to all p* instructions.
672 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
674 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
675 to get gdb talking to re-aranged sim_cpu register structure.
678 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
680 * sim-main.h (Max, Min): Declare.
682 * interp.c (Max, Min): New functions.
684 * mips.igen (BC1): Add tracing.
686 start-sanitize-vr5400
687 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
689 * mdmx.igen: Tag all functions as requiring either with mdmx or
694 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
696 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
698 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
700 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
702 * r5900.igen: Rewrite.
704 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
706 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
707 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
710 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
712 * interp.c Added memory map for stack in vr4100
714 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
716 * interp.c (load_memory): Add missing "break"'s.
718 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
720 * interp.c (sim_store_register, sim_fetch_register): Pass in
721 length parameter. Return -1.
723 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
725 * interp.c: Added hardware init hook, fixed warnings.
727 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
729 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
731 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
733 * interp.c (ifetch16): New function.
735 * sim-main.h (IMEM32): Rename IMEM.
736 (IMEM16_IMMED): Define.
738 (DELAY_SLOT): Update.
740 * m16run.c (sim_engine_run): New file.
742 * m16.igen: All instructions except LB.
743 (LB): Call do_load_byte.
744 * mips.igen (do_load_byte): New function.
745 (LB): Call do_load_byte.
747 * mips.igen: Move spec for insn bit size and high bit from here.
748 * Makefile.in (tmp-igen, tmp-m16): To here.
750 * m16.dc: New file, decode mips16 instructions.
752 * Makefile.in (SIM_NO_ALL): Define.
753 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
756 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
760 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
762 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
763 point unit to 32 bit registers.
764 * configure: Re-generate.
766 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
768 * configure.in (sim_use_gen): Make IGEN the default simulator
769 generator for generic 32 and 64 bit mips targets.
770 * configure: Re-generate.
772 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
774 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
777 * interp.c (sim_fetch_register, sim_store_register): Read/write
778 FGR from correct location.
779 (sim_open): Set size of FGR's according to
780 WITH_TARGET_FLOATING_POINT_BITSIZE.
782 * sim-main.h (FGR): Store floating point registers in a separate
785 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
787 * configure: Regenerated to track ../common/aclocal.m4 changes.
789 start-sanitize-vr5400
790 * mdmx.igen: Mark all instructions as 64bit/fp specific.
793 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
795 * interp.c (ColdReset): Call PENDING_INVALIDATE.
797 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
799 * interp.c (pending_tick): New function. Deliver pending writes.
801 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
802 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
803 it can handle mixed sized quantites and single bits.
805 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
807 * interp.c (oengine.h): Do not include when building with IGEN.
808 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
809 (sim_info): Ditto for PROCESSOR_64BIT.
810 (sim_monitor): Replace ut_reg with unsigned_word.
811 (*): Ditto for t_reg.
812 (LOADDRMASK): Define.
813 (sim_open): Remove defunct check that host FP is IEEE compliant,
814 using software to emulate floating point.
815 (value_fpr, ...): Always compile, was conditional on HASFPU.
817 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
819 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
822 * interp.c (SD, CPU): Define.
823 (mips_option_handler): Set flags in each CPU.
824 (interrupt_event): Assume CPU 0 is the one being iterrupted.
825 (sim_close): Do not clear STATE, deleted anyway.
826 (sim_write, sim_read): Assume CPU zero's vm should be used for
828 (sim_create_inferior): Set the PC for all processors.
829 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
831 (mips16_entry): Pass correct nr of args to store_word, load_word.
832 (ColdReset): Cold reset all cpu's.
833 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
834 (sim_monitor, load_memory, store_memory, signal_exception): Use
835 `CPU' instead of STATE_CPU.
838 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
841 * sim-main.h (signal_exception): Add sim_cpu arg.
842 (SignalException*): Pass both SD and CPU to signal_exception.
843 * interp.c (signal_exception): Update.
845 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
847 (sync_operation, prefetch, cache_op, store_memory, load_memory,
848 address_translation): Ditto
849 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
851 start-sanitize-vr5400
852 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
854 (ByteAlign): Use StoreFPR, pass args in correct order.
858 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
860 * configure.in (sim_igen_filter): For r5900, configure as SMP.
863 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
865 * configure: Regenerated to track ../common/aclocal.m4 changes.
867 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * configure.in (sim_igen_filter): For r5900, use igen.
871 * configure: Re-generate.
874 * interp.c (sim_engine_run): Add `nr_cpus' argument.
876 * mips.igen (model): Map processor names onto BFD name.
878 * sim-main.h (CPU_CIA): Delete.
879 (SET_CIA, GET_CIA): Define
881 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
883 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
886 * configure.in (default_endian): Configure a big-endian simulator
888 * configure: Re-generate.
890 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
892 * configure: Regenerated to track ../common/aclocal.m4 changes.
894 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
896 * interp.c (sim_monitor): Handle Densan monitor outbyte
897 and inbyte functions.
899 1997-12-29 Felix Lee <flee@cygnus.com>
901 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
903 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
905 * Makefile.in (tmp-igen): Arrange for $zero to always be
906 reset to zero after every instruction.
908 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
910 * configure: Regenerated to track ../common/aclocal.m4 changes.
913 start-sanitize-vr5400
914 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
916 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
920 start-sanitize-vr5400
921 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
923 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
924 vr5400 with the vr5000 as the default.
927 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
929 * mips.igen (MSUB): Fix to work like MADD.
930 * gencode.c (MSUB): Similarly.
932 start-sanitize-vr5400
933 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
935 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
939 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
941 * configure: Regenerated to track ../common/aclocal.m4 changes.
943 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
945 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
947 start-sanitize-vr5400
948 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
949 (value_cc, store_cc): Implement.
951 * sim-main.h: Add 8*3*8 bit accumulator.
953 * vr5400.igen: Move mdmx instructins from here
954 * mdmx.igen: To here - new file. Add/fix missing instructions.
955 * mips.igen: Include mdmx.igen.
956 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
959 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
961 * sim-main.h (sim-fpu.h): Include.
963 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
964 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
965 using host independant sim_fpu module.
967 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
969 * interp.c (signal_exception): Report internal errors with SIGABRT
972 * sim-main.h (C0_CONFIG): New register.
973 (signal.h): No longer include.
975 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
977 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
979 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
981 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
983 * mips.igen: Tag vr5000 instructions.
984 (ANDI): Was missing mipsIV model, fix assembler syntax.
985 (do_c_cond_fmt): New function.
986 (C.cond.fmt): Handle mips I-III which do not support CC field
988 (bc1): Handle mips IV which do not have a delaed FCC separatly.
989 (SDR): Mask paddr when BigEndianMem, not the converse as specified
991 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
992 vr5000 which saves LO in a GPR separatly.
994 * configure.in (enable-sim-igen): For vr5000, select vr5000
995 specific instructions.
996 * configure: Re-generate.
998 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1000 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1002 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1003 fmt_uninterpreted_64 bit cases to switch. Convert to
1006 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1008 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1009 as specified in IV3.2 spec.
1010 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1012 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1014 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1015 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1016 (start-sanitize-r5900):
1017 (LWXC1, SWXC1): Delete from r5900 instruction set.
1018 (end-sanitize-r5900):
1019 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1020 PENDING_FILL versions of instructions. Simplify.
1022 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1024 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1026 (MTHI, MFHI): Disable code checking HI-LO.
1028 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1030 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1032 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1034 * gencode.c (build_mips16_operands): Replace IPC with cia.
1036 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1037 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1039 (UndefinedResult): Replace function with macro/function
1041 (sim_engine_run): Don't save PC in IPC.
1043 * sim-main.h (IPC): Delete.
1045 start-sanitize-vr5400
1046 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1047 (do_select): Rename function select.
1050 * interp.c (signal_exception, store_word, load_word,
1051 address_translation, load_memory, store_memory, cache_op,
1052 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1053 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1054 current instruction address - cia - argument.
1055 (sim_read, sim_write): Call address_translation directly.
1056 (sim_engine_run): Rename variable vaddr to cia.
1057 (signal_exception): Pass cia to sim_monitor
1059 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1060 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1061 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1063 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1064 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1067 * interp.c (signal_exception): Pass restart address to
1070 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1071 idecode.o): Add dependency.
1073 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1075 (DELAY_SLOT): Update NIA not PC with branch address.
1076 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1078 * mips.igen: Use CIA not PC in branch calculations.
1079 (illegal): Call SignalException.
1080 (BEQ, ADDIU): Fix assembler.
1082 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1084 * m16.igen (JALX): Was missing.
1086 * configure.in (enable-sim-igen): New configuration option.
1087 * configure: Re-generate.
1089 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1091 * interp.c (load_memory, store_memory): Delete parameter RAW.
1092 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1093 bypassing {load,store}_memory.
1095 * sim-main.h (ByteSwapMem): Delete definition.
1097 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1099 * interp.c (sim_do_command, sim_commands): Delete mips specific
1100 commands. Handled by module sim-options.
1102 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1103 (WITH_MODULO_MEMORY): Define.
1105 * interp.c (sim_info): Delete code printing memory size.
1107 * interp.c (mips_size): Nee sim_size, delete function.
1109 (monitor, monitor_base, monitor_size): Delete global variables.
1110 (sim_open, sim_close): Delete code creating monitor and other
1111 memory regions. Use sim-memopts module, via sim_do_commandf, to
1112 manage memory regions.
1113 (load_memory, store_memory): Use sim-core for memory model.
1115 * interp.c (address_translation): Delete all memory map code
1116 except line forcing 32 bit addresses.
1118 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1120 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1123 * interp.c (logfh, logfile): Delete globals.
1124 (sim_open, sim_close): Delete code opening & closing log file.
1125 (mips_option_handler): Delete -l and -n options.
1126 (OPTION mips_options): Ditto.
1128 * interp.c (OPTION mips_options): Rename option trace to dinero.
1129 (mips_option_handler): Update.
1131 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1133 * interp.c (fetch_str): New function.
1134 (sim_monitor): Rewrite using sim_read & sim_write.
1135 (sim_open): Check magic number.
1136 (sim_open): Write monitor vectors into memory using sim_write.
1137 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1138 (sim_read, sim_write): Simplify - transfer data one byte at a
1140 (load_memory, store_memory): Clarify meaning of parameter RAW.
1142 * sim-main.h (isHOST): Defete definition.
1143 (isTARGET): Mark as depreciated.
1144 (address_translation): Delete parameter HOST.
1146 * interp.c (address_translation): Delete parameter HOST.
1149 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1151 * gencode.c: Add tx49 configury and insns.
1152 * configure.in: Add tx49 configury.
1153 * configure: Update.
1156 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1160 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1161 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1163 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1165 * mips.igen: Add model filter field to records.
1167 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1169 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1171 interp.c (sim_engine_run): Do not compile function sim_engine_run
1172 when WITH_IGEN == 1.
1174 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1175 target architecture.
1177 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1178 igen. Replace with configuration variables sim_igen_flags /
1181 start-sanitize-r5900
1182 * r5900.igen: New file. Copy r5900 insns here.
1184 start-sanitize-vr5400
1185 * vr5400.igen: New file.
1187 * m16.igen: New file. Copy mips16 insns here.
1188 * mips.igen: From here.
1190 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1192 start-sanitize-vr5400
1193 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1195 * configure.in: Add mips64vr5400 target.
1196 * configure: Re-generate.
1199 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1201 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1203 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1205 * gencode.c (build_instruction): Follow sim_write's lead in using
1206 BigEndianMem instead of !ByteSwapMem.
1208 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1210 * configure.in (sim_gen): Dependent on target, select type of
1211 generator. Always select old style generator.
1213 configure: Re-generate.
1215 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1217 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1218 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1219 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1220 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1221 SIM_@sim_gen@_*, set by autoconf.
1223 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1225 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1227 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1228 CURRENT_FLOATING_POINT instead.
1230 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1231 (address_translation): Raise exception InstructionFetch when
1232 translation fails and isINSTRUCTION.
1234 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1235 sim_engine_run): Change type of of vaddr and paddr to
1237 (address_translation, prefetch, load_memory, store_memory,
1238 cache_op): Change type of vAddr and pAddr to address_word.
1240 * gencode.c (build_instruction): Change type of vaddr and paddr to
1243 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1246 macro to obtain result of ALU op.
1248 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1250 * interp.c (sim_info): Call profile_print.
1252 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1254 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1256 * sim-main.h (WITH_PROFILE): Do not define, defined in
1257 common/sim-config.h. Use sim-profile module.
1258 (simPROFILE): Delete defintion.
1260 * interp.c (PROFILE): Delete definition.
1261 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1262 (sim_close): Delete code writing profile histogram.
1263 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1265 (sim_engine_run): Delete code profiling the PC.
1267 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1269 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1271 * interp.c (sim_monitor): Make register pointers of type
1274 * sim-main.h: Make registers of type unsigned_word not
1277 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1279 start-sanitize-r5900
1280 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1281 ...): Move to sim-main.h
1284 * interp.c (sync_operation): Rename from SyncOperation, make
1285 global, add SD argument.
1286 (prefetch): Rename from Prefetch, make global, add SD argument.
1287 (decode_coproc): Make global.
1289 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1291 * gencode.c (build_instruction): Generate DecodeCoproc not
1292 decode_coproc calls.
1294 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1295 (SizeFGR): Move to sim-main.h
1296 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1297 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1298 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1300 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1301 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1302 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1303 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1304 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1305 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1307 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1309 (sim-alu.h): Include.
1310 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1311 (sim_cia): Typedef to instruction_address.
1313 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315 * Makefile.in (interp.o): Rename generated file engine.c to
1320 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1324 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1326 * gencode.c (build_instruction): For "FPSQRT", output correct
1327 number of arguments to Recip.
1329 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1331 * Makefile.in (interp.o): Depends on sim-main.h
1333 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1335 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1336 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1337 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1338 STATE, DSSTATE): Define
1339 (GPR, FGRIDX, ..): Define.
1341 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1342 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1343 (GPR, FGRIDX, ...): Delete macros.
1345 * interp.c: Update names to match defines from sim-main.h
1347 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1349 * interp.c (sim_monitor): Add SD argument.
1350 (sim_warning): Delete. Replace calls with calls to
1352 (sim_error): Delete. Replace calls with sim_io_error.
1353 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1354 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1355 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1357 (mips_size): Rename from sim_size. Add SD argument.
1359 * interp.c (simulator): Delete global variable.
1360 (callback): Delete global variable.
1361 (mips_option_handler, sim_open, sim_write, sim_read,
1362 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1363 sim_size,sim_monitor): Use sim_io_* not callback->*.
1364 (sim_open): ZALLOC simulator struct.
1365 (PROFILE): Do not define.
1367 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1369 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1370 support.h with corresponding code.
1372 * sim-main.h (word64, uword64), support.h: Move definition to
1374 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1377 * Makefile.in: Update dependencies
1378 * interp.c: Do not include.
1380 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1382 * interp.c (address_translation, load_memory, store_memory,
1383 cache_op): Rename to from AddressTranslation et.al., make global,
1386 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1389 * interp.c (SignalException): Rename to signal_exception, make
1392 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1394 * sim-main.h (SignalException, SignalExceptionInterrupt,
1395 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1396 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1397 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1400 * interp.c, support.h: Use.
1402 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1404 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1405 to value_fpr / store_fpr. Add SD argument.
1406 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1407 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1409 * sim-main.h (ValueFPR, StoreFPR): Define.
1411 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1413 * interp.c (sim_engine_run): Check consistency between configure
1414 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1417 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1418 (mips_fpu): Configure WITH_FLOATING_POINT.
1419 (mips_endian): Configure WITH_TARGET_ENDIAN.
1420 * configure: Update.
1422 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424 * configure: Regenerated to track ../common/aclocal.m4 changes.
1426 start-sanitize-r5900
1427 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429 * interp.c (MAX_REG): Allow up-to 128 registers.
1430 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1431 (REGISTER_SA): Ditto.
1432 (sim_open): Initialize register_widths for r5900 specific
1434 (sim_fetch_register, sim_store_register): Check for request of
1435 r5900 specific SA register. Check for request for hi 64 bits of
1436 r5900 specific registers.
1439 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1441 * configure: Regenerated.
1443 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1445 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1447 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1449 * gencode.c (print_igen_insn_models): Assume certain architectures
1450 include all mips* instructions.
1451 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1454 * Makefile.in (tmp.igen): Add target. Generate igen input from
1457 * gencode.c (FEATURE_IGEN): Define.
1458 (main): Add --igen option. Generate output in igen format.
1459 (process_instructions): Format output according to igen option.
1460 (print_igen_insn_format): New function.
1461 (print_igen_insn_models): New function.
1462 (process_instructions): Only issue warnings and ignore
1463 instructions when no FEATURE_IGEN.
1465 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1467 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1470 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472 * configure: Regenerated to track ../common/aclocal.m4 changes.
1474 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1476 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1477 SIM_RESERVED_BITS): Delete, moved to common.
1478 (SIM_EXTRA_CFLAGS): Update.
1480 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482 * configure.in: Configure non-strict memory alignment.
1483 * configure: Regenerated to track ../common/aclocal.m4 changes.
1485 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1487 * configure: Regenerated to track ../common/aclocal.m4 changes.
1489 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1491 * gencode.c (SDBBP,DERET): Added (3900) insns.
1492 (RFE): Turn on for 3900.
1493 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1494 (dsstate): Made global.
1495 (SUBTARGET_R3900): Added.
1496 (CANCELDELAYSLOT): New.
1497 (SignalException): Ignore SystemCall rather than ignore and
1498 terminate. Add DebugBreakPoint handling.
1499 (decode_coproc): New insns RFE, DERET; and new registers Debug
1500 and DEPC protected by SUBTARGET_R3900.
1501 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1503 * Makefile.in,configure.in: Add mips subtarget option.
1504 * configure: Update.
1506 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1508 * gencode.c: Add r3900 (tx39).
1511 * gencode.c: Fix some configuration problems by improving
1512 the relationship between tx19 and tx39.
1515 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1517 * gencode.c (build_instruction): Don't need to subtract 4 for
1520 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1522 * interp.c: Correct some HASFPU problems.
1524 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1526 * configure: Regenerated to track ../common/aclocal.m4 changes.
1528 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * interp.c (mips_options): Fix samples option short form, should
1533 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1535 * interp.c (sim_info): Enable info code. Was just returning.
1537 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1542 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1544 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1546 (build_instruction): Ditto for LL.
1549 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1551 * mips/configure.in, mips/gencode: Add tx19/r1900.
1554 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1556 * configure: Regenerated to track ../common/aclocal.m4 changes.
1558 start-sanitize-r5900
1559 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1561 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1562 for overflow due to ABS of MININT, set result to MAXINT.
1563 (build_instruction): For "psrlvw", signextend bit 31.
1566 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568 * configure: Regenerated to track ../common/aclocal.m4 changes.
1571 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * interp.c (sim_open): Add call to sim_analyze_program, update
1576 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578 * interp.c (sim_kill): Delete.
1579 (sim_create_inferior): Add ABFD argument. Set PC from same.
1580 (sim_load): Move code initializing trap handlers from here.
1581 (sim_open): To here.
1582 (sim_load): Delete, use sim-hload.c.
1584 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1586 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588 * configure: Regenerated to track ../common/aclocal.m4 changes.
1591 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1593 * interp.c (sim_open): Add ABFD argument.
1594 (sim_load): Move call to sim_config from here.
1595 (sim_open): To here. Check return status.
1597 start-sanitize-r5900
1598 * gencode.c (build_instruction): Do not define x8000000000000000,
1599 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1602 start-sanitize-r5900
1603 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1606 "pdivuw" check for overflow due to signed divide by -1.
1609 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1611 * gencode.c (build_instruction): Two arg MADD should
1612 not assign result to $0.
1614 start-sanitize-r5900
1615 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1617 * gencode.c (build_instruction): For "ppac5" use unsigned
1618 arrithmetic so that the sign bit doesn't smear when right shifted.
1619 (build_instruction): For "pdiv" perform sign extension when
1620 storing results in HI and LO.
1621 (build_instructions): For "pdiv" and "pdivbw" check for
1623 (build_instruction): For "pmfhl.slw" update hi part of dest
1624 register as well as low part.
1625 (build_instruction): For "pmfhl" portably handle long long values.
1626 (build_instruction): For "pmfhl.sh" correctly negative values.
1627 Store half words 2 and three in the correct place.
1628 (build_instruction): For "psllvw", sign extend value after shift.
1631 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1633 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1634 * sim/mips/configure.in: Regenerate.
1636 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1638 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1639 signed8, unsigned8 et.al. types.
1641 start-sanitize-r5900
1642 * gencode.c (build_instruction): For PMULTU* do not sign extend
1643 registers. Make generated code easier to debug.
1646 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1647 hosts when selecting subreg.
1649 start-sanitize-r5900
1650 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1652 * gencode.c (type_for_data_len): For 32bit operations concerned
1653 with overflow, perform op using 64bits.
1654 (build_instruction): For PADD, always compute operation using type
1655 returned by type_for_data_len.
1656 (build_instruction): For PSUBU, when overflow, saturate to zero as
1660 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1662 start-sanitize-r5900
1663 * gencode.c (build_instruction): Handle "pext5" according to
1664 version 1.95 of the r5900 ISA.
1666 * gencode.c (build_instruction): Handle "ppac5" according to
1667 version 1.95 of the r5900 ISA.
1670 * interp.c (sim_engine_run): Reset the ZERO register to zero
1671 regardless of FEATURE_WARN_ZERO.
1672 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1674 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1677 (SignalException): For BreakPoints ignore any mode bits and just
1679 (SignalException): Always set the CAUSE register.
1681 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1683 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1684 exception has been taken.
1686 * interp.c: Implement the ERET and mt/f sr instructions.
1688 start-sanitize-r5900
1689 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1691 * gencode.c (build_instruction): For paddu, extract unsigned
1694 * gencode.c (build_instruction): Saturate padds instead of padd
1698 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1700 * interp.c (SignalException): Don't bother restarting an
1703 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705 * interp.c (SignalException): Really take an interrupt.
1706 (interrupt_event): Only deliver interrupts when enabled.
1708 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1710 * interp.c (sim_info): Only print info when verbose.
1711 (sim_info) Use sim_io_printf for output.
1713 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1718 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720 * interp.c (sim_do_command): Check for common commands if a
1721 simulator specific command fails.
1723 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1725 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1726 and simBE when DEBUG is defined.
1728 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * interp.c (interrupt_event): New function. Pass exception event
1731 onto exception handler.
1733 * configure.in: Check for stdlib.h.
1734 * configure: Regenerate.
1736 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1737 variable declaration.
1738 (build_instruction): Initialize memval1.
1739 (build_instruction): Add UNUSED attribute to byte, bigend,
1741 (build_operands): Ditto.
1743 * interp.c: Fix GCC warnings.
1744 (sim_get_quit_code): Delete.
1746 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1747 * Makefile.in: Ditto.
1748 * configure: Re-generate.
1750 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1752 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1754 * interp.c (mips_option_handler): New function parse argumes using
1756 (myname): Replace with STATE_MY_NAME.
1757 (sim_open): Delete check for host endianness - performed by
1759 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1760 (sim_open): Move much of the initialization from here.
1761 (sim_load): To here. After the image has been loaded and
1763 (sim_open): Move ColdReset from here.
1764 (sim_create_inferior): To here.
1765 (sim_open): Make FP check less dependant on host endianness.
1767 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1769 * interp.c (sim_set_callbacks): Delete.
1771 * interp.c (membank, membank_base, membank_size): Replace with
1772 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1773 (sim_open): Remove call to callback->init. gdb/run do this.
1777 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1779 * interp.c (big_endian_p): Delete, replaced by
1780 current_target_byte_order.
1782 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784 * interp.c (host_read_long, host_read_word, host_swap_word,
1785 host_swap_long): Delete. Using common sim-endian.
1786 (sim_fetch_register, sim_store_register): Use H2T.
1787 (pipeline_ticks): Delete. Handled by sim-events.
1789 (sim_engine_run): Update.
1791 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1795 (SignalException): To here. Signal using sim_engine_halt.
1796 (sim_stop_reason): Delete, moved to common.
1798 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1800 * interp.c (sim_open): Add callback argument.
1801 (sim_set_callbacks): Delete SIM_DESC argument.
1804 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1806 * Makefile.in (SIM_OBJS): Add common modules.
1808 * interp.c (sim_set_callbacks): Also set SD callback.
1809 (set_endianness, xfer_*, swap_*): Delete.
1810 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1811 Change to functions using sim-endian macros.
1812 (control_c, sim_stop): Delete, use common version.
1813 (simulate): Convert into.
1814 (sim_engine_run): This function.
1815 (sim_resume): Delete.
1817 * interp.c (simulation): New variable - the simulator object.
1818 (sim_kind): Delete global - merged into simulation.
1819 (sim_load): Cleanup. Move PC assignment from here.
1820 (sim_create_inferior): To here.
1822 * sim-main.h: New file.
1823 * interp.c (sim-main.h): Include.
1825 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1827 * configure: Regenerated to track ../common/aclocal.m4 changes.
1829 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1831 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1833 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1835 * gencode.c (build_instruction): DIV instructions: check
1836 for division by zero and integer overflow before using
1837 host's division operation.
1839 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1841 * Makefile.in (SIM_OBJS): Add sim-load.o.
1842 * interp.c: #include bfd.h.
1843 (target_byte_order): Delete.
1844 (sim_kind, myname, big_endian_p): New static locals.
1845 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1846 after argument parsing. Recognize -E arg, set endianness accordingly.
1847 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1848 load file into simulator. Set PC from bfd.
1849 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1850 (set_endianness): Use big_endian_p instead of target_byte_order.
1852 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854 * interp.c (sim_size): Delete prototype - conflicts with
1855 definition in remote-sim.h. Correct definition.
1857 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1859 * configure: Regenerated to track ../common/aclocal.m4 changes.
1862 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1864 * interp.c (sim_open): New arg `kind'.
1866 * configure: Regenerated to track ../common/aclocal.m4 changes.
1868 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1870 * configure: Regenerated to track ../common/aclocal.m4 changes.
1872 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1874 * interp.c (sim_open): Set optind to 0 before calling getopt.
1876 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1878 * configure: Regenerated to track ../common/aclocal.m4 changes.
1880 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1882 * interp.c : Replace uses of pr_addr with pr_uword64
1883 where the bit length is always 64 independent of SIM_ADDR.
1884 (pr_uword64) : added.
1886 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1888 * configure: Re-generate.
1890 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1892 * configure: Regenerate to track ../common/aclocal.m4 changes.
1894 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1896 * interp.c (sim_open): New SIM_DESC result. Argument is now
1898 (other sim_*): New SIM_DESC argument.
1900 start-sanitize-r5900
1901 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1903 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1904 Change values to avoid overloading DOUBLEWORD which is tested
1906 * gencode.c: reinstate "offending code".
1909 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1911 * interp.c: Fix printing of addresses for non-64-bit targets.
1912 (pr_addr): Add function to print address based on size.
1913 start-sanitize-r5900
1914 * gencode.c: #ifdef out offending code until a permanent fix
1915 can be added. Code is causing build errors for non-5900 mips targets.
1918 start-sanitize-r5900
1919 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1921 * gencode.c (process_instructions): Correct test for ISA dependent
1922 architecture bits in isa field of MIPS_DECODE.
1925 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1927 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1929 start-sanitize-r5900
1930 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1932 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1936 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1938 * gencode.c (build_mips16_operands): Correct computation of base
1939 address for extended PC relative instruction.
1941 start-sanitize-r5900
1942 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1944 * Makefile.in, configure, configure.in, gencode.c,
1945 interp.c, support.h: add r5900.
1948 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1950 * interp.c (mips16_entry): Add support for floating point cases.
1951 (SignalException): Pass floating point cases to mips16_entry.
1952 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1954 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1956 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1957 and then set the state to fmt_uninterpreted.
1958 (COP_SW): Temporarily set the state to fmt_word while calling
1961 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1963 * gencode.c (build_instruction): The high order may be set in the
1964 comparison flags at any ISA level, not just ISA 4.
1966 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1968 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1969 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1970 * configure.in: sinclude ../common/aclocal.m4.
1971 * configure: Regenerated.
1973 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1975 * configure: Rebuild after change to aclocal.m4.
1977 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1979 * configure configure.in Makefile.in: Update to new configure
1980 scheme which is more compatible with WinGDB builds.
1981 * configure.in: Improve comment on how to run autoconf.
1982 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1983 * Makefile.in: Use autoconf substitution to install common
1986 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1988 * gencode.c (build_instruction): Use BigEndianCPU instead of
1991 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1993 * interp.c (sim_monitor): Make output to stdout visible in
1994 wingdb's I/O log window.
1996 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1998 * support.h: Undo previous change to SIGTRAP
2001 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2003 * interp.c (store_word, load_word): New static functions.
2004 (mips16_entry): New static function.
2005 (SignalException): Look for mips16 entry and exit instructions.
2006 (simulate): Use the correct index when setting fpr_state after
2007 doing a pending move.
2009 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2011 * interp.c: Fix byte-swapping code throughout to work on
2012 both little- and big-endian hosts.
2014 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2016 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2017 with gdb/config/i386/xm-windows.h.
2019 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2021 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2022 that messes up arithmetic shifts.
2024 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2026 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2027 SIGTRAP and SIGQUIT for _WIN32.
2029 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2031 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2032 force a 64 bit multiplication.
2033 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2034 destination register is 0, since that is the default mips16 nop
2037 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2039 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2040 (build_endian_shift): Don't check proc64.
2041 (build_instruction): Always set memval to uword64. Cast op2 to
2042 uword64 when shifting it left in memory instructions. Always use
2043 the same code for stores--don't special case proc64.
2045 * gencode.c (build_mips16_operands): Fix base PC value for PC
2047 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2049 * interp.c (simJALDELAYSLOT): Define.
2050 (JALDELAYSLOT): Define.
2051 (INDELAYSLOT, INJALDELAYSLOT): Define.
2052 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2054 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2056 * interp.c (sim_open): add flush_cache as a PMON routine
2057 (sim_monitor): handle flush_cache by ignoring it
2059 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2061 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2063 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2064 (BigEndianMem): Rename to ByteSwapMem and change sense.
2065 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2066 BigEndianMem references to !ByteSwapMem.
2067 (set_endianness): New function, with prototype.
2068 (sim_open): Call set_endianness.
2069 (sim_info): Use simBE instead of BigEndianMem.
2070 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2071 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2072 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2073 ifdefs, keeping the prototype declaration.
2074 (swap_word): Rewrite correctly.
2075 (ColdReset): Delete references to CONFIG. Delete endianness related
2076 code; moved to set_endianness.
2078 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2080 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2081 * interp.c (CHECKHILO): Define away.
2082 (simSIGINT): New macro.
2083 (membank_size): Increase from 1MB to 2MB.
2084 (control_c): New function.
2085 (sim_resume): Rename parameter signal to signal_number. Add local
2086 variable prev. Call signal before and after simulate.
2087 (sim_stop_reason): Add simSIGINT support.
2088 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2090 (sim_warning): Delete call to SignalException. Do call printf_filtered
2092 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2093 a call to sim_warning.
2095 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2097 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2098 16 bit instructions.
2100 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2102 Add support for mips16 (16 bit MIPS implementation):
2103 * gencode.c (inst_type): Add mips16 instruction encoding types.
2104 (GETDATASIZEINSN): Define.
2105 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2106 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2108 (MIPS16_DECODE): New table, for mips16 instructions.
2109 (bitmap_val): New static function.
2110 (struct mips16_op): Define.
2111 (mips16_op_table): New table, for mips16 operands.
2112 (build_mips16_operands): New static function.
2113 (process_instructions): If PC is odd, decode a mips16
2114 instruction. Break out instruction handling into new
2115 build_instruction function.
2116 (build_instruction): New static function, broken out of
2117 process_instructions. Check modifiers rather than flags for SHIFT
2118 bit count and m[ft]{hi,lo} direction.
2119 (usage): Pass program name to fprintf.
2120 (main): Remove unused variable this_option_optind. Change
2121 ``*loptarg++'' to ``loptarg++''.
2122 (my_strtoul): Parenthesize && within ||.
2123 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2124 (simulate): If PC is odd, fetch a 16 bit instruction, and
2125 increment PC by 2 rather than 4.
2126 * configure.in: Add case for mips16*-*-*.
2127 * configure: Rebuild.
2129 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2131 * interp.c: Allow -t to enable tracing in standalone simulator.
2132 Fix garbage output in trace file and error messages.
2134 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2136 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2137 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2138 * configure.in: Simplify using macros in ../common/aclocal.m4.
2139 * configure: Regenerated.
2140 * tconfig.in: New file.
2142 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2144 * interp.c: Fix bugs in 64-bit port.
2145 Use ansi function declarations for msvc compiler.
2146 Initialize and test file pointer in trace code.
2147 Prevent duplicate definition of LAST_EMED_REGNUM.
2149 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2151 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2153 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2155 * interp.c (SignalException): Check for explicit terminating
2157 * gencode.c: Pass instruction value through SignalException()
2158 calls for Trap, Breakpoint and Syscall.
2160 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2162 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2163 only used on those hosts that provide it.
2164 * configure.in: Add sqrt() to list of functions to be checked for.
2165 * config.in: Re-generated.
2166 * configure: Re-generated.
2168 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2170 * gencode.c (process_instructions): Call build_endian_shift when
2171 expanding STORE RIGHT, to fix swr.
2172 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2173 clear the high bits.
2174 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2175 Fix float to int conversions to produce signed values.
2177 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2179 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2180 (process_instructions): Correct handling of nor instruction.
2181 Correct shift count for 32 bit shift instructions. Correct sign
2182 extension for arithmetic shifts to not shift the number of bits in
2183 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2184 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2186 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2187 It's OK to have a mult follow a mult. What's not OK is to have a
2188 mult follow an mfhi.
2189 (Convert): Comment out incorrect rounding code.
2191 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2193 * interp.c (sim_monitor): Improved monitor printf
2194 simulation. Tidied up simulator warnings, and added "--log" option
2195 for directing warning message output.
2196 * gencode.c: Use sim_warning() rather than WARNING macro.
2198 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2200 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2201 getopt1.o, rather than on gencode.c. Link objects together.
2202 Don't link against -liberty.
2203 (gencode.o, getopt.o, getopt1.o): New targets.
2204 * gencode.c: Include <ctype.h> and "ansidecl.h".
2205 (AND): Undefine after including "ansidecl.h".
2206 (ULONG_MAX): Define if not defined.
2207 (OP_*): Don't define macros; now defined in opcode/mips.h.
2208 (main): Call my_strtoul rather than strtoul.
2209 (my_strtoul): New static function.
2211 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2213 * gencode.c (process_instructions): Generate word64 and uword64
2214 instead of `long long' and `unsigned long long' data types.
2215 * interp.c: #include sysdep.h to get signals, and define default
2217 * (Convert): Work around for Visual-C++ compiler bug with type
2219 * support.h: Make things compile under Visual-C++ by using
2220 __int64 instead of `long long'. Change many refs to long long
2221 into word64/uword64 typedefs.
2223 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2225 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2226 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2228 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2229 (AC_PROG_INSTALL): Added.
2230 (AC_PROG_CC): Moved to before configure.host call.
2231 * configure: Rebuilt.
2233 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2235 * configure.in: Define @SIMCONF@ depending on mips target.
2236 * configure: Rebuild.
2237 * Makefile.in (run): Add @SIMCONF@ to control simulator
2239 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2240 * interp.c: Remove some debugging, provide more detailed error
2241 messages, update memory accesses to use LOADDRMASK.
2243 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2245 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2246 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2248 * configure: Rebuild.
2249 * config.in: New file, generated by autoheader.
2250 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2251 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2252 HAVE_ANINT and HAVE_AINT, as appropriate.
2253 * Makefile.in (run): Use @LIBS@ rather than -lm.
2254 (interp.o): Depend upon config.h.
2255 (Makefile): Just rebuild Makefile.
2256 (clean): Remove stamp-h.
2257 (mostlyclean): Make the same as clean, not as distclean.
2258 (config.h, stamp-h): New targets.
2260 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2262 * interp.c (ColdReset): Fix boolean test. Make all simulator
2265 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2267 * interp.c (xfer_direct_word, xfer_direct_long,
2268 swap_direct_word, swap_direct_long, xfer_big_word,
2269 xfer_big_long, xfer_little_word, xfer_little_long,
2270 swap_word,swap_long): Added.
2271 * interp.c (ColdReset): Provide function indirection to
2272 host<->simulated_target transfer routines.
2273 * interp.c (sim_store_register, sim_fetch_register): Updated to
2274 make use of indirected transfer routines.
2276 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2278 * gencode.c (process_instructions): Ensure FP ABS instruction
2280 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2281 system call support.
2283 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2285 * interp.c (sim_do_command): Complain if callback structure not
2288 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2290 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2291 support for Sun hosts.
2292 * Makefile.in (gencode): Ensure the host compiler and libraries
2293 used for cross-hosted build.
2295 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2297 * interp.c, gencode.c: Some more (TODO) tidying.
2299 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2301 * gencode.c, interp.c: Replaced explicit long long references with
2302 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2303 * support.h (SET64LO, SET64HI): Macros added.
2305 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2307 * configure: Regenerate with autoconf 2.7.
2309 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2311 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2312 * support.h: Remove superfluous "1" from #if.
2313 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2315 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2317 * interp.c (StoreFPR): Control UndefinedResult() call on
2318 WARN_RESULT manifest.
2320 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2322 * gencode.c: Tidied instruction decoding, and added FP instruction
2325 * interp.c: Added dineroIII, and BSD profiling support. Also
2326 run-time FP handling.
2328 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2330 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2331 gencode.c, interp.c, support.h: created.