sim/mips/ChangeLog

   1 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
   2
   3         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
   4         unsigned operands.
   5
   6 2003-02-27  Andrew Cagney  <cagney@redhat.com>
   7
   8         * interp.c (sim_open): Rename _bfd to bfd.
   9         (sim_create_inferior): Ditto.
  10
  11 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
  12
  13         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
  14
  15 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
  16
  17         * mips.igen (EI, DI): Remove.
  18
  19 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
  20
  21         * Makefile.in (tmp-run-multi): Fix mips16 filter.
  22
  23 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
  24             Andrew Cagney  <ac131313@redhat.com>
  25             Gavin Romig-Koch  <gavin@redhat.com>
  26             Graydon Hoare  <graydon@redhat.com>
  27             Aldy Hernandez  <aldyh@redhat.com>
  28             Dave Brolley  <brolley@redhat.com>
  29             Chris Demetriou  <cgd@broadcom.com>
  30
  31         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
  32         (sim_mach_default): New variable.
  33         (mips64vr-*-*, mips64vrel-*-*): New configurations.
  34         Add a new simulator generator, MULTI.
  35         * configure: Regenerate.
  36         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
  37         (multi-run.o): New dependency.
  38         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
  39         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
  40         (tmp-multi): Combine them.
  41         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
  42         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
  43         (distclean-extra): New rule.
  44         * sim-main.h: Include bfd.h.
  45         (MIPS_MACH): New macro.
  46         * mips.igen (vr4120, vr5400, vr5500): New models.
  47         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
  48         * vr.igen: Replace with new version.
  49
  50 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
  51
  52         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
  53         * configure: Regenerate.
  54
  55 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
  56
  57         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
  58         * mips.igen: Remove all invocations of check_branch_bug and
  59         mark_branch_bug.
  60
  61 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
  62
  63         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
  64
  65 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
  66
  67         * mips.igen (do_load_double, do_store_double): New functions.
  68         (LDC1, SDC1): Rename to...
  69         (LDC1b, SDC1b): respectively.
  70         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
  71
  72 2002-07-29  Michael Snyder  <msnyder@redhat.com>
  73
  74         * cp1.c (fp_recip2): Modify initialization expression so that
  75         GCC will recognize it as constant.
  76
  77 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
  78
  79         * mdmx.c (SD_): Delete.
  80         (Unpredictable): Re-define, for now, to directly invoke
  81         unpredictable_action().
  82         (mdmx_acc_op): Fix error in .ob immediate handling.
  83
  84 2002-06-18  Andrew Cagney  <cagney@redhat.com>
  85
  86         * interp.c (sim_firmware_command): Initialize `address'.
  87
  88 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
  89
  90         * configure: Regenerated to track ../common/aclocal.m4 changes.
  91
  92 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
  93             Ed Satterthwaite  <ehs@broadcom.com>
  94
  95         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
  96         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
  97         * mips.igen: Include mips3d.igen.
  98         (mips3d): New model name for MIPS-3D ASE instructions.
  99         (CVT.W.fmt): Don't use this instruction for word (source) format
 100         instructions.
 101         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 102         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 103         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 104         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 105         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 106         (RSquareRoot1, RSquareRoot2): New macros.
 107         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 108         (fp_rsqrt2): New functions.
 109         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 110         * configure: Regenerate.
 111
 112 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 113             Ed Satterthwaite  <ehs@broadcom.com>
 114
 115         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 116         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 117         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 118         (convert): Note that this function is not used for paired-single
 119         format conversions.
 120         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 121         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 122         (check_fmt_p): Enable paired-single support.
 123         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 124         (PUU.PS): New instructions.
 125         (CVT.S.fmt): Don't use this instruction for paired-single format
 126         destinations.
 127         * sim-main.h (FP_formats): New value 'fmt_ps.'
 128         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 129         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 130
 131 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 132
 133         * mips.igen: Fix formatting of function calls in
 134         many FP operations.
 135
 136 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 137
 138         * mips.igen (MOVN, MOVZ): Trace result.
 139         (TNEI): Print "tnei" as the opcode name in traces.
 140         (CEIL.W): Add disassembly string for traces.
 141         (RSQRT.fmt): Make location of disassembly string consistent
 142         with other instructions.
 143
 144 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 145
 146         * mips.igen (X): Delete unused function.
 147
 148 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 149
 150         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 151
 152 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 153             Ed Satterthwaite  <ehs@broadcom.com>
 154
 155         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 156         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 157         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 158         (fp_nmsub): New prototypes.
 159         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 160         (NegMultiplySub): New defines.
 161         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 162         (MADD.D, MADD.S): Replace with...
 163         (MADD.fmt): New instruction.
 164         (MSUB.D, MSUB.S): Replace with...
 165         (MSUB.fmt): New instruction.
 166         (NMADD.D, NMADD.S): Replace with...
 167         (NMADD.fmt): New instruction.
 168         (NMSUB.D, MSUB.S): Replace with...
 169         (NMSUB.fmt): New instruction.
 170
 171 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 172             Ed Satterthwaite  <ehs@broadcom.com>
 173
 174         * cp1.c: Fix more comment spelling and formatting.
 175         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 176         (denorm_mode): New function.
 177         (fpu_unary, fpu_binary): Round results after operation, collect
 178         status from rounding operations, and update the FCSR.
 179         (convert): Collect status from integer conversions and rounding
 180         operations, and update the FCSR.  Adjust NaN values that result
 181         from conversions.  Convert to use sim_io_eprintf rather than
 182         fprintf, and remove some debugging code.
 183         * cp1.h (fenr_FS): New define.
 184
 185 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 186
 187         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 188         rounding mode to sim FP rounding mode flag conversion code into...
 189         (rounding_mode): New function.
 190
 191 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 192
 193         * cp1.c: Clean up formatting of a few comments.
 194         (value_fpr): Reformat switch statement.
 195
 196 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 197             Ed Satterthwaite  <ehs@broadcom.com>
 198
 199         * cp1.h: New file.
 200         * sim-main.h: Include cp1.h.
 201         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 202         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 203         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 204         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 205         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 206         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 207         * cp1.c: Don't include sim-fpu.h; already included by
 208         sim-main.h.  Clean up formatting of some comments.
 209         (NaN, Equal, Less): Remove.
 210         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 211         (fp_cmp): New functions.
 212         * mips.igen (do_c_cond_fmt): Remove.
 213         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 214         Compare.  Add result tracing.
 215         (CxC1): Remove, replace with...
 216         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 217         (DMxC1): Remove, replace with...
 218         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 219         (MxC1): Remove, replace with...
 220         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 221
 222 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 223
 224         * sim-main.h (FGRIDX): Remove, replace all uses with...
 225         (FGR_BASE): New macro.
 226         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 227         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 228         (NR_FGR, FGR): Likewise.
 229         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 230         * mips.igen: Likewise.
 231
 232 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 233
 234         * cp1.c: Add an FSF Copyright notice to this file.
 235
 236 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 237             Ed Satterthwaite  <ehs@broadcom.com>
 238
 239         * cp1.c (Infinity): Remove.
 240         * sim-main.h (Infinity): Likewise.
 241
 242         * cp1.c (fp_unary, fp_binary): New functions.
 243         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 244         (fp_sqrt): New functions, implemented in terms of the above.
 245         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 246         (Recip, SquareRoot): Remove (replaced by functions above).
 247         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 248         (fp_recip, fp_sqrt): New prototypes.
 249         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 250         (Recip, SquareRoot): Replace prototypes with #defines which
 251         invoke the functions above.
 252
 253 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 254
 255         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 256         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 257         file, remove PARAMS from prototypes.
 258         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 259         simulator state arguments.
 260         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 261         pass simulator state arguments.
 262         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 263         (store_fpr, convert): Remove 'sd' argument.
 264         (value_fpr): Likewise.  Convert to use 'SD' instead.
 265
 266 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 267
 268         * cp1.c (Min, Max): Remove #if 0'd functions.
 269         * sim-main.h (Min, Max): Remove.
 270
 271 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 272
 273         * cp1.c: fix formatting of switch case and default labels.
 274         * interp.c: Likewise.
 275         * sim-main.c: Likewise.
 276
 277 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 278
 279         * cp1.c: Clean up comments which describe FP formats.
 280          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 281
 282 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 283             Ed Satterthwaite  <ehs@broadcom.com>
 284
 285         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 286         Broadcom SiByte SB-1 processor configurations.
 287         * configure: Regenerate.
 288         * sb1.igen: New file.
 289         * mips.igen: Include sb1.igen.
 290         (sb1): New model.
 291         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 292         * mdmx.igen: Add "sb1" model to all appropriate functions and
 293         instructions.
 294         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 295         (ob_func, ob_acc): Reference the above.
 296         (qh_acc): Adjust to keep the same size as ob_acc.
 297         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 298         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 299
 300 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 301
 302         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 303
 304 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 305             Ed Satterthwaite  <ehs@broadcom.com>
 306
 307         * mips.igen (mdmx): New (pseudo-)model.
 308         * mdmx.c, mdmx.igen: New files.
 309         * Makefile.in (SIM_OBJS): Add mdmx.o.
 310         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 311         New typedefs.
 312         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 313         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 314         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 315         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 316         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 317         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 318         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 319         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 320         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 321         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 322         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 323         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 324         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 325         (qh_fmtsel): New macros.
 326         (_sim_cpu): New member "acc".
 327         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 328         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 329
 330 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 331
 332         * interp.c: Use 'deprecated' rather than 'depreciated.'
 333         * sim-main.h: Likewise.
 334
 335 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 336
 337         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 338         which wouldn't compile anyway.
 339         * sim-main.h (unpredictable_action): New function prototype.
 340         (Unpredictable): Define to call igen function unpredictable().
 341         (NotWordValue): New macro to call igen function not_word_value().
 342         (UndefinedResult): Remove.
 343         * interp.c (undefined_result): Remove.
 344         (unpredictable_action): New function.
 345         * mips.igen (not_word_value, unpredictable): New functions.
 346         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 347         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 348         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 349         NotWordValue() to check for unpredictable inputs, then
 350         Unpredictable() to handle them.
 351
 352 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 353
 354         * mips.igen: Fix formatting of calls to Unpredictable().
 355
 356 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 357
 358         * interp.c (sim_open): Revert previous change.
 359
 360 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 361
 362         * interp.c (sim_open): Disable chunk of code that wrote code in
 363         vector table entries.
 364
 365 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 366
 367         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 368         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 369         unused definitions.
 370
 371 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 372
 373         * cp1.c: Fix many formatting issues.
 374
 375 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 376
 377         * cp1.c (fpu_format_name): New function to replace...
 378         (DOFMT): This.  Delete, and update all callers.
 379         (fpu_rounding_mode_name): New function to replace...
 380         (RMMODE): This.  Delete, and update all callers.
 381
 382 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 383
 384         * interp.c: Move FPU support routines from here to...
 385         * cp1.c: Here.  New file.
 386         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 387         (cp1.o): New target.
 388
 389 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 390
 391         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 392         * mips.igen (mips32, mips64): New models, add to all instructions
 393         and functions as appropriate.
 394         (loadstore_ea, check_u64): New variant for model mips64.
 395         (check_fmt_p): New variant for models mipsV and mips64, remove
 396         mipsV model marking fro other variant.
 397         (SLL) Rename to...
 398         (SLLa) this.
 399         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 400         for mips32 and mips64.
 401         (DCLO, DCLZ): New instructions for mips64.
 402
 403 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 404
 405         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 406         immediate or code as a hex value with the "%#lx" format.
 407         (ANDI): Likewise, and fix printed instruction name.
 408
 409 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 410
 411         * sim-main.h (UndefinedResult, Unpredictable): New macros
 412         which currently do nothing.
 413
 414 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 415
 416         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 417         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 418         (status_CU3): New definitions.
 419
 420         * sim-main.h (ExceptionCause): Add new values for MIPS32
 421         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 422         for DebugBreakPoint and NMIReset to note their status in
 423         MIPS32 and MIPS64.
 424         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 425         (SignalExceptionCacheErr): New exception macros.
 426
 427 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 428
 429         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 430         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 431         is always enabled.
 432         (SignalExceptionCoProcessorUnusable): Take as argument the
 433         unusable coprocessor number.
 434
 435 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 436
 437         * mips.igen: Fix formatting of all SignalException calls.
 438
 439 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 440
 441         * sim-main.h (SIGNEXTEND): Remove.
 442
 443 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 444
 445         * mips.igen: Remove gencode comment from top of file, fix
 446         spelling in another comment.
 447
 448 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 449
 450         * mips.igen (check_fmt, check_fmt_p): New functions to check
 451         whether specific floating point formats are usable.
 452         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 453         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 454         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 455         Use the new functions.
 456         (do_c_cond_fmt): Remove format checks...
 457         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 458
 459 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 460
 461         * mips.igen: Fix formatting of check_fpu calls.
 462
 463 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 464
 465         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 466
 467 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 468
 469         * mips.igen: Remove whitespace at end of lines.
 470
 471 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 472
 473         * mips.igen (loadstore_ea): New function to do effective
 474         address calculations.
 475         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 476         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 477         CACHE): Use loadstore_ea to do effective address computations.
 478
 479 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 480
 481         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 482         * mips.igen (LL, CxC1, MxC1): Likewise.
 483
 484 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 485
 486         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 487         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 488         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 489         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 490         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 491         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 492         Don't split opcode fields by hand, use the opcode field values
 493         provided by igen.
 494
 495 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 496
 497         * mips.igen (do_divu): Fix spacing.
 498
 499         * mips.igen (do_dsllv): Move to be right before DSLLV,
 500         to match the rest of the do_<shift> functions.
 501
 502 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 503
 504         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 505         DSRL32, do_dsrlv): Trace inputs and results.
 506
 507 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 508
 509         * mips.igen (CACHE): Provide instruction-printing string.
 510
 511         * interp.c (signal_exception): Comment tokens after #endif.
 512
 513 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 514
 515         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 516         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 517         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 518         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 519         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 520         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 521         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 522         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 523
 524 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 525
 526         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 527         instruction-printing string.
 528         (LWU): Use '64' as the filter flag.
 529
 530 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 531
 532         * mips.igen (SDXC1): Fix instruction-printing string.
 533
 534 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 535
 536         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 537         filter flags "32,f".
 538
 539 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 540
 541         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 542         as the filter flag.
 543
 544 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 545
 546         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 547         add a comma) so that it more closely match the MIPS ISA
 548         documentation opcode partitioning.
 549         (PREF): Put useful names on opcode fields, and include
 550         instruction-printing string.
 551
 552 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 553
 554         * mips.igen (check_u64): New function which in the future will
 555         check whether 64-bit instructions are usable and signal an
 556         exception if not.  Currently a no-op.
 557         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 558         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 559         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 560         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 561
 562         * mips.igen (check_fpu): New function which in the future will
 563         check whether FPU instructions are usable and signal an exception
 564         if not.  Currently a no-op.
 565         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 566         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 567         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 568         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 569         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 570         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 571         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 572         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 573
 574 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 575
 576         * mips.igen (do_load_left, do_load_right): Move to be immediately
 577         following do_load.
 578         (do_store_left, do_store_right): Move to be immediately following
 579         do_store.
 580
 581 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 582
 583         * mips.igen (mipsV): New model name.  Also, add it to
 584         all instructions and functions where it is appropriate.
 585
 586 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 587
 588         * mips.igen: For all functions and instructions, list model
 589         names that support that instruction one per line.
 590
 591 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 592
 593         * mips.igen: Add some additional comments about supported
 594         models, and about which instructions go where.
 595         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 596         order as is used in the rest of the file.
 597
 598 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 599
 600         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 601         indicating that ALU32_END or ALU64_END are there to check
 602         for overflow.
 603         (DADD): Likewise, but also remove previous comment about
 604         overflow checking.
 605
 606 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 607
 608         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 609         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 610         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 611         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 612         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 613         fields (i.e., add and move commas) so that they more closely
 614         match the MIPS ISA documentation opcode partitioning.
 615
 616 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 617
 618         * mips.igen (ADDI): Print immediate value.
 619         (BREAK): Print code.
 620         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 621         (SLL): Print "nop" specially, and don't run the code
 622         that does the shift for the "nop" case.
 623
 624 2001-11-17  Fred Fish  <fnf@redhat.com>
 625
 626         * sim-main.h (float_operation): Move enum declaration outside
 627         of _sim_cpu struct declaration.
 628
 629 2001-04-12  Jim Blandy  <jimb@redhat.com>
 630
 631         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 632         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 633         set of the FCSR.
 634         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 635         PENDING_FILL, and you can get the intended effect gracefully by
 636         calling PENDING_SCHED directly.
 637
 638 2001-02-23  Ben Elliston  <bje@redhat.com>
 639
 640         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 641         already defined elsewhere.
 642
 643 2001-02-19  Ben Elliston  <bje@redhat.com>
 644
 645         * sim-main.h (sim_monitor): Return an int.
 646         * interp.c (sim_monitor): Add return values.
 647         (signal_exception): Handle error conditions from sim_monitor.
 648
 649 2001-02-08  Ben Elliston  <bje@redhat.com>
 650
 651         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 652         (store_memory): Likewise, pass cia to sim_core_write*.
 653
 654 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 655
 656         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 657         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 658
 659 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 660
 661         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 662         * Makefile.in: Don't delete *.igen when cleaning directory.
 663
 664 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 665
 666         * m16.igen (break): Call SignalException not sim_engine_halt.
 667
 668 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 669
 670         From Jason Eckhardt:
 671         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 672
 673 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 674
 675         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 676
 677 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 678
 679         * mips.igen (do_dmultx): Fix typo.
 680
 681 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 682
 683         * configure: Regenerated to track ../common/aclocal.m4 changes.
 684
 685 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 686
 687         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 688
 689 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 690
 691         * sim-main.h (GPR_CLEAR): Define macro.
 692
 693 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 694
 695         * interp.c (decode_coproc): Output long using %lx and not %s.
 696
 697 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 698
 699         * interp.c (sim_open): Sort & extend dummy memory regions for
 700         --board=jmr3904 for eCos.
 701
 702 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 703
 704         * configure: Regenerated.
 705
 706 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 707
 708         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 709         calls, conditional on the simulator being in verbose mode.
 710
 711 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 712
 713         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 714         cache don't get ReservedInstruction traps.
 715
 716 1999-11-29  Mark Salter  <msalter@cygnus.com>
 717
 718         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 719         to clear status bits in sdisr register. This is how the hardware works.
 720
 721         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 722         being used by cygmon.
 723
 724 1999-11-11  Andrew Haley  <aph@cygnus.com>
 725
 726         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 727         instructions.
 728
 729 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 730
 731         * mips.igen (MULT): Correct previous mis-applied patch.
 732
 733 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 734
 735         * mips.igen (delayslot32): Handle sequence like
 736         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 737         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 738         (MULT): Actually pass the third register...
 739
 740 1999-09-03  Mark Salter  <msalter@cygnus.com>
 741
 742         * interp.c (sim_open): Added more memory aliases for additional
 743         hardware being touched by cygmon on jmr3904 board.
 744
 745 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 746
 747         * configure: Regenerated to track ../common/aclocal.m4 changes.
 748
 749 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 750
 751         * interp.c (sim_store_register): Handle case where client - GDB -
 752         specifies that a 4 byte register is 8 bytes in size.
 753         (sim_fetch_register): Ditto.
 754
 755 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 756
 757         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 758         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 759         (idt_monitor_base): Base address for IDT monitor traps.
 760         (pmon_monitor_base): Ditto for PMON.
 761         (lsipmon_monitor_base): Ditto for LSI PMON.
 762         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 763         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 764         (sim_firmware_command): New function.
 765         (mips_option_handler): Call it for OPTION_FIRMWARE.
 766         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 767         option was given, add no monitor by default.  Add BREAK hooks only if
 768         monitors are also there.
 769
 770 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 771
 772         * interp.c (sim_monitor): Flush output before reading input.
 773
 774 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 775
 776         * tconfig.in (SIM_HANDLES_LMA): Always define.
 777
 778 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 779
 780         From Mark Salter <msalter@cygnus.com>:
 781         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 782         (sim_open): Add setup for BSP board.
 783
 784 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 785
 786         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 787         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 788         them as unimplemented.
 789
 790 1999-05-08  Felix Lee  <flee@cygnus.com>
 791
 792         * configure: Regenerated to track ../common/aclocal.m4 changes.
 793
 794 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 795
 796         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 797
 798 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 799
 800         * configure.in: Any mips64vr5*-*-* target should have
 801         -DTARGET_ENABLE_FR=1.
 802         (default_endian): Any mips64vr*el-*-* target should default to
 803         LITTLE_ENDIAN.
 804         * configure: Re-generate.
 805
 806 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 807
 808         * mips.igen (ldl): Extend from _16_, not 32.
 809
 810 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 811
 812         * interp.c (sim_store_register): Force registers written to by GDB
 813         into an un-interpreted state.
 814
 815 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 816
 817         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 818         CPU, start periodic background I/O polls.
 819         (tx3904sio_poll): New function: periodic I/O poller.
 820
 821 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 822
 823         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 824
 825 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 826
 827         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 828         case statement.
 829
 830 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 831
 832         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 833         (load_word): Call SIM_CORE_SIGNAL hook on error.
 834         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 835         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 836         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 837         * sim-main.h (COP0_BADVADDR): Define.
 838         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 839         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 840         (_sim_cpu): Add exc_* fields to store register value snapshots.
 841         * mips.igen (*): Replace memory-related SignalException* calls
 842         with references to SIM_CORE_SIGNAL hook.
 843
 844         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 845         fix.
 846         * sim-main.c (*): Minor warning cleanups.
 847
 848 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 849
 850         * m16.igen (DADDIU5): Correct type-o.
 851
 852 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 853
 854         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 855         variables.
 856
 857 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 858
 859         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 860         to include path.
 861         (interp.o): Add dependency on itable.h
 862         (oengine.c, gencode): Delete remaining references.
 863         (BUILT_SRC_FROM_GEN): Clean up.
 864
 865 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 866
 867         * vr4run.c: New.
 868         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 869         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 870         tmp-run-hack) : New.
 871         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 872         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 873         Drop the "64" qualifier to get the HACK generator working.
 874         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 875         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 876         qualifier to get the hack generator working.
 877         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 878         (DSLL): Use do_dsll.
 879         (DSLLV): Use do_dsllv.
 880         (DSRA): Use do_dsra.
 881         (DSRL): Use do_dsrl.
 882         (DSRLV): Use do_dsrlv.
 883         (BC1): Move *vr4100 to get the HACK generator working.
 884         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 885         get the HACK generator working.
 886         (MACC) Rename to get the HACK generator working.
 887         (DMACC,MACCS,DMACCS): Add the 64.
 888
 889 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 890
 891         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 892         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 893
 894 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 895
 896     * mips/interp.c (DEBUG): Cleanups.
 897
 898 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 899
 900         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 901         (tx3904sio_tickle): fflush after a stdout character output.
 902
 903 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 904
 905         * interp.c (sim_close): Uninstall modules.
 906
 907 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 908
 909         * sim-main.h, interp.c (sim_monitor): Change to global
 910         function.
 911
 912 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 913
 914         * configure.in (vr4100): Only include vr4100 instructions in
 915         simulator.
 916         * configure: Re-generate.
 917         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 918
 919 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 920
 921         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 922         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 923         true alternative.
 924
 925         * configure.in (sim_default_gen, sim_use_gen): Replace with
 926         sim_gen.
 927         (--enable-sim-igen): Delete config option. Always using IGEN.
 928         * configure: Re-generate.
 929
 930         * Makefile.in (gencode): Kill, kill, kill.
 931         * gencode.c: Ditto.
 932
 933 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 934
 935         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 936         bit mips16 igen simulator.
 937         * configure: Re-generate.
 938
 939         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 940         as part of vr4100 ISA.
 941         * vr.igen: Mark all instructions as 64 bit only.
 942
 943 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 944
 945         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 946         Pacify GCC.
 947
 948 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 949
 950         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 951         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 952         * configure: Re-generate.
 953
 954         * m16.igen (BREAK): Define breakpoint instruction.
 955         (JALX32): Mark instruction as mips16 and not r3900.
 956         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 957
 958         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 959
 960 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 961
 962         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 963         insn as a debug breakpoint.
 964
 965         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 966         pending.slot_size.
 967         (PENDING_SCHED): Clean up trace statement.
 968         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 969         (PENDING_FILL): Delay write by only one cycle.
 970         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 971
 972         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 973         of pending writes.
 974         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 975         32 & 64.
 976         (pending_tick): Move incrementing of index to FOR statement.
 977         (pending_tick): Only update PENDING_OUT after a write has occured.
 978
 979         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 980         build simulator.
 981         * configure: Re-generate.
 982
 983         * interp.c (sim_engine_run OLD): Delete explicit call to
 984         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 985
 986 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 987
 988         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 989         interrupt level number to match changed SignalExceptionInterrupt
 990         macro.
 991
 992 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 993
 994         * interp.c: #include "itable.h" if WITH_IGEN.
 995         (get_insn_name): New function.
 996         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 997         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 998
 999 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1000
1001         * configure: Rebuilt to inhale new common/aclocal.m4.
1002
1003 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1004
1005         * dv-tx3904sio.c: Include sim-assert.h.
1006
1007 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1008
1009         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1010         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1011         Reorganize target-specific sim-hardware checks.
1012         * configure: rebuilt.
1013         * interp.c (sim_open): For tx39 target boards, set
1014         OPERATING_ENVIRONMENT, add tx3904sio devices.
1015         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1016         ROM executables.  Install dv-sockser into sim-modules list.
1017
1018         * dv-tx3904irc.c: Compiler warning clean-up.
1019         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1020         frequent hw-trace messages.
1021
1022 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1023
1024         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1025
1026 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1027
1028         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1029
1030         * vr.igen: New file.
1031         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1032         * mips.igen: Define vr4100 model. Include vr.igen.
1033 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1034
1035         * mips.igen (check_mf_hilo): Correct check.
1036
1037 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1038
1039         * sim-main.h (interrupt_event): Add prototype.
1040
1041         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1042         register_ptr, register_value.
1043         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1044
1045         * sim-main.h (tracefh): Make extern.
1046
1047 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1048
1049         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1050         Reduce unnecessarily high timer event frequency.
1051         * dv-tx3904cpu.c: Ditto for interrupt event.
1052
1053 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1054
1055         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1056         to allay warnings.
1057         (interrupt_event): Made non-static.
1058
1059         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1060         interchange of configuration values for external vs. internal
1061         clock dividers.
1062
1063 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1064
1065         * mips.igen (BREAK): Moved code to here for
1066         simulator-reserved break instructions.
1067         * gencode.c (build_instruction): Ditto.
1068         * interp.c (signal_exception): Code moved from here.  Non-
1069         reserved instructions now use exception vector, rather
1070         than halting sim.
1071         * sim-main.h: Moved magic constants to here.
1072
1073 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1074
1075         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1076         register upon non-zero interrupt event level, clear upon zero
1077         event value.
1078         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1079         by passing zero event value.
1080         (*_io_{read,write}_buffer): Endianness fixes.
1081         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1082         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1083
1084         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1085         serial I/O and timer module at base address 0xFFFF0000.
1086
1087 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1088
1089         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1090         and BigEndianCPU.
1091
1092 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1093
1094         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1095         parts.
1096         * configure: Update.
1097
1098 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1099
1100         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1101         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1102         * configure.in: Include tx3904tmr in hw_device list.
1103         * configure: Rebuilt.
1104         * interp.c (sim_open): Instantiate three timer instances.
1105         Fix address typo of tx3904irc instance.
1106
1107 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1108
1109         * interp.c (signal_exception): SystemCall exception now uses
1110         the exception vector.
1111
1112 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1113
1114         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1115         to allay warnings.
1116
1117 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1118
1119         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1120
1121 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1122
1123         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1124
1125         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1126         sim-main.h. Declare a struct hw_descriptor instead of struct
1127         hw_device_descriptor.
1128
1129 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1130
1131         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1132         right bits and then re-align left hand bytes to correct byte
1133         lanes.  Fix incorrect computation in do_store_left when loading
1134         bytes from second word.
1135
1136 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1137
1138         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1139         * interp.c (sim_open): Only create a device tree when HW is
1140         enabled.
1141
1142         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1143         * interp.c (signal_exception): Ditto.
1144
1145 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1146
1147         * gencode.c: Mark BEGEZALL as LIKELY.
1148
1149 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1150
1151         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1152         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1153
1154 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1155
1156         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1157         modules.  Recognize TX39 target with "mips*tx39" pattern.
1158         * configure: Rebuilt.
1159         * sim-main.h (*): Added many macros defining bits in
1160         TX39 control registers.
1161         (SignalInterrupt): Send actual PC instead of NULL.
1162         (SignalNMIReset): New exception type.
1163         * interp.c (board): New variable for future use to identify
1164         a particular board being simulated.
1165         (mips_option_handler,mips_options): Added "--board" option.
1166         (interrupt_event): Send actual PC.
1167         (sim_open): Make memory layout conditional on board setting.
1168         (signal_exception): Initial implementation of hardware interrupt
1169         handling.  Accept another break instruction variant for simulator
1170         exit.
1171         (decode_coproc): Implement RFE instruction for TX39.
1172         (mips.igen): Decode RFE instruction as such.
1173         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1174         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1175         bbegin to implement memory map.
1176         * dv-tx3904cpu.c: New file.
1177         * dv-tx3904irc.c: New file.
1178
1179 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1180
1181         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1182
1183 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1184
1185         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1186         with calls to check_div_hilo.
1187
1188 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1189
1190         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1191         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1192         Add special r3900 version of do_mult_hilo.
1193         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1194         with calls to check_mult_hilo.
1195         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1196         with calls to check_div_hilo.
1197
1198 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1199
1200         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1201         Document a replacement.
1202
1203 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1204
1205         * interp.c (sim_monitor): Make mon_printf work.
1206
1207 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1208
1209         * sim-main.h (INSN_NAME): New arg `cpu'.
1210
1211 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1212
1213         * configure: Regenerated to track ../common/aclocal.m4 changes.
1214
1215 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1216
1217         * configure: Regenerated to track ../common/aclocal.m4 changes.
1218         * config.in: Ditto.
1219
1220 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1221
1222         * acconfig.h: New file.
1223         * configure.in: Reverted change of Apr 24; use sinclude again.
1224
1225 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1226
1227         * configure: Regenerated to track ../common/aclocal.m4 changes.
1228         * config.in: Ditto.
1229
1230 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1231
1232         * configure.in: Don't call sinclude.
1233
1234 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1235
1236         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1237
1238 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1239
1240         * mips.igen (ERET): Implement.
1241
1242         * interp.c (decode_coproc): Return sign-extended EPC.
1243
1244         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1245
1246         * interp.c (signal_exception): Do not ignore Trap.
1247         (signal_exception): On TRAP, restart at exception address.
1248         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1249         (signal_exception): Update.
1250         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1251         so that TRAP instructions are caught.
1252
1253 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1254
1255         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1256         contains HI/LO access history.
1257         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1258         (HIACCESS, LOACCESS): Delete, replace with
1259         (HIHISTORY, LOHISTORY): New macros.
1260         (CHECKHILO): Delete all, moved to mips.igen
1261
1262         * gencode.c (build_instruction): Do not generate checks for
1263         correct HI/LO register usage.
1264
1265         * interp.c (old_engine_run): Delete checks for correct HI/LO
1266         register usage.
1267
1268         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1269         check_mf_cycles): New functions.
1270         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1271         do_divu, domultx, do_mult, do_multu): Use.
1272
1273         * tx.igen ("madd", "maddu"): Use.
1274
1275 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1276
1277         * mips.igen (DSRAV): Use function do_dsrav.
1278         (SRAV): Use new function do_srav.
1279
1280         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1281         (B): Sign extend 11 bit immediate.
1282         (EXT-B*): Shift 16 bit immediate left by 1.
1283         (ADDIU*): Don't sign extend immediate value.
1284
1285 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1286
1287         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1288
1289         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1290         functions.
1291
1292         * mips.igen (delayslot32, nullify_next_insn): New functions.
1293         (m16.igen): Always include.
1294         (do_*): Add more tracing.
1295
1296         * m16.igen (delayslot16): Add NIA argument, could be called by a
1297         32 bit MIPS16 instruction.
1298
1299         * interp.c (ifetch16): Move function from here.
1300         * sim-main.c (ifetch16): To here.
1301
1302         * sim-main.c (ifetch16, ifetch32): Update to match current
1303         implementations of LH, LW.
1304         (signal_exception): Don't print out incorrect hex value of illegal
1305         instruction.
1306
1307 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1308
1309         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1310         instruction.
1311
1312         * m16.igen: Implement MIPS16 instructions.
1313
1314         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1315         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1316         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1317         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1318         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1319         bodies of corresponding code from 32 bit insn to these.  Also used
1320         by MIPS16 versions of functions.
1321
1322         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1323         (IMEM16): Drop NR argument from macro.
1324
1325 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * Makefile.in (SIM_OBJS): Add sim-main.o.
1328
1329         * sim-main.h (address_translation, load_memory, store_memory,
1330         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1331         as INLINE_SIM_MAIN.
1332         (pr_addr, pr_uword64): Declare.
1333         (sim-main.c): Include when H_REVEALS_MODULE_P.
1334
1335         * interp.c (address_translation, load_memory, store_memory,
1336         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1337         from here.
1338         * sim-main.c: To here. Fix compilation problems.
1339
1340         * configure.in: Enable inlining.
1341         * configure: Re-config.
1342
1343 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1344
1345         * configure: Regenerated to track ../common/aclocal.m4 changes.
1346
1347 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1348
1349         * mips.igen: Include tx.igen.
1350         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1351         * tx.igen: New file, contains MADD and MADDU.
1352
1353         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1354         the hardwired constant `7'.
1355         (store_memory): Ditto.
1356         (LOADDRMASK): Move definition to sim-main.h.
1357
1358         mips.igen (MTC0): Enable for r3900.
1359         (ADDU): Add trace.
1360
1361         mips.igen (do_load_byte): Delete.
1362         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1363         do_store_right): New functions.
1364         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1365
1366         configure.in: Let the tx39 use igen again.
1367         configure: Update.
1368
1369 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1370
1371         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1372         not an address sized quantity.  Return zero for cache sizes.
1373
1374 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1375
1376         * mips.igen (r3900): r3900 does not support 64 bit integer
1377         operations.
1378
1379 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1380
1381         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1382         than igen one.
1383         * configure : Rebuild.
1384
1385 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1386
1387         * configure: Regenerated to track ../common/aclocal.m4 changes.
1388
1389 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1390
1391         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1392
1393 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1394
1395         * configure: Regenerated to track ../common/aclocal.m4 changes.
1396         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1397
1398 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1399
1400         * configure: Regenerated to track ../common/aclocal.m4 changes.
1401
1402 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1403
1404         * interp.c (Max, Min): Comment out functions. Not yet used.
1405
1406 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * configure: Regenerated to track ../common/aclocal.m4 changes.
1409
1410 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1411
1412         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1413         configurable settings for stand-alone simulator.
1414
1415         * configure.in: Added X11 search, just in case.
1416
1417         * configure: Regenerated.
1418
1419 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1420
1421         * interp.c (sim_write, sim_read, load_memory, store_memory):
1422         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1423
1424 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1425
1426         * sim-main.h (GETFCC): Return an unsigned value.
1427
1428 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1429
1430         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1431         (DADD): Result destination is RD not RT.
1432
1433 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1434
1435         * sim-main.h (HIACCESS, LOACCESS): Always define.
1436
1437         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1438
1439         * interp.c (sim_info): Delete.
1440
1441 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1442
1443         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1444         (mips_option_handler): New argument `cpu'.
1445         (sim_open): Update call to sim_add_option_table.
1446
1447 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1448
1449         * mips.igen (CxC1): Add tracing.
1450
1451 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1452
1453         * sim-main.h (Max, Min): Declare.
1454
1455         * interp.c (Max, Min): New functions.
1456
1457         * mips.igen (BC1): Add tracing.
1458
1459 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1460
1461         * interp.c Added memory map for stack in vr4100
1462
1463 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1464
1465         * interp.c (load_memory): Add missing "break"'s.
1466
1467 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * interp.c (sim_store_register, sim_fetch_register): Pass in
1470         length parameter.  Return -1.
1471
1472 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1473
1474         * interp.c: Added hardware init hook, fixed warnings.
1475
1476 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1477
1478         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1479
1480 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1481
1482         * interp.c (ifetch16): New function.
1483
1484         * sim-main.h (IMEM32): Rename IMEM.
1485         (IMEM16_IMMED): Define.
1486         (IMEM16): Define.
1487         (DELAY_SLOT): Update.
1488
1489         * m16run.c (sim_engine_run): New file.
1490
1491         * m16.igen: All instructions except LB.
1492         (LB): Call do_load_byte.
1493         * mips.igen (do_load_byte): New function.
1494         (LB): Call do_load_byte.
1495
1496         * mips.igen: Move spec for insn bit size and high bit from here.
1497         * Makefile.in (tmp-igen, tmp-m16): To here.
1498
1499         * m16.dc: New file, decode mips16 instructions.
1500
1501         * Makefile.in (SIM_NO_ALL): Define.
1502         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1503
1504 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1505
1506         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1507         point unit to 32 bit registers.
1508         * configure: Re-generate.
1509
1510 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1511
1512         * configure.in (sim_use_gen): Make IGEN the default simulator
1513         generator for generic 32 and 64 bit mips targets.
1514         * configure: Re-generate.
1515
1516 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1517
1518         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1519         bitsize.
1520
1521         * interp.c (sim_fetch_register, sim_store_register): Read/write
1522         FGR from correct location.
1523         (sim_open): Set size of FGR's according to
1524         WITH_TARGET_FLOATING_POINT_BITSIZE.
1525
1526         * sim-main.h (FGR): Store floating point registers in a separate
1527         array.
1528
1529 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1530
1531         * configure: Regenerated to track ../common/aclocal.m4 changes.
1532
1533 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1534
1535         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1536
1537         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1538
1539         * interp.c (pending_tick): New function.  Deliver pending writes.
1540
1541         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1542         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1543         it can handle mixed sized quantites and single bits.
1544
1545 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1546
1547         * interp.c (oengine.h): Do not include when building with IGEN.
1548         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1549         (sim_info): Ditto for PROCESSOR_64BIT.
1550         (sim_monitor): Replace ut_reg with unsigned_word.
1551         (*): Ditto for t_reg.
1552         (LOADDRMASK): Define.
1553         (sim_open): Remove defunct check that host FP is IEEE compliant,
1554         using software to emulate floating point.
1555         (value_fpr, ...): Always compile, was conditional on HASFPU.
1556
1557 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1558
1559         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1560         size.
1561
1562         * interp.c (SD, CPU): Define.
1563         (mips_option_handler): Set flags in each CPU.
1564         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1565         (sim_close): Do not clear STATE, deleted anyway.
1566         (sim_write, sim_read): Assume CPU zero's vm should be used for
1567         data transfers.
1568         (sim_create_inferior): Set the PC for all processors.
1569         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1570         argument.
1571         (mips16_entry): Pass correct nr of args to store_word, load_word.
1572         (ColdReset): Cold reset all cpu's.
1573         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1574         (sim_monitor, load_memory, store_memory, signal_exception): Use
1575         `CPU' instead of STATE_CPU.
1576
1577
1578         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1579         SD or CPU_.
1580
1581         * sim-main.h (signal_exception): Add sim_cpu arg.
1582         (SignalException*): Pass both SD and CPU to signal_exception.
1583         * interp.c (signal_exception): Update.
1584
1585         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1586         Ditto
1587         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1588         address_translation): Ditto
1589         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1590
1591 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * configure: Regenerated to track ../common/aclocal.m4 changes.
1594
1595 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1596
1597         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1598
1599         * mips.igen (model): Map processor names onto BFD name.
1600
1601         * sim-main.h (CPU_CIA): Delete.
1602         (SET_CIA, GET_CIA): Define
1603
1604 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1605
1606         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1607         regiser.
1608
1609         * configure.in (default_endian): Configure a big-endian simulator
1610         by default.
1611         * configure: Re-generate.
1612
1613 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1614
1615         * configure: Regenerated to track ../common/aclocal.m4 changes.
1616
1617 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1618
1619         * interp.c (sim_monitor): Handle Densan monitor outbyte
1620         and inbyte functions.
1621
1622 1997-12-29  Felix Lee  <flee@cygnus.com>
1623
1624         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1625
1626 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1627
1628         * Makefile.in (tmp-igen): Arrange for $zero to always be
1629         reset to zero after every instruction.
1630
1631 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1632
1633         * configure: Regenerated to track ../common/aclocal.m4 changes.
1634         * config.in: Ditto.
1635
1636 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1637
1638         * mips.igen (MSUB): Fix to work like MADD.
1639         * gencode.c (MSUB): Similarly.
1640
1641 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1642
1643         * configure: Regenerated to track ../common/aclocal.m4 changes.
1644
1645 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1646
1647         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1648
1649 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1650
1651         * sim-main.h (sim-fpu.h): Include.
1652
1653         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1654         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1655         using host independant sim_fpu module.
1656
1657 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1658
1659         * interp.c (signal_exception): Report internal errors with SIGABRT
1660         not SIGQUIT.
1661
1662         * sim-main.h (C0_CONFIG): New register.
1663         (signal.h): No longer include.
1664
1665         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1666
1667 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1668
1669         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1670
1671 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1672
1673         * mips.igen: Tag vr5000 instructions.
1674         (ANDI): Was missing mipsIV model, fix assembler syntax.
1675         (do_c_cond_fmt): New function.
1676         (C.cond.fmt): Handle mips I-III which do not support CC field
1677         separatly.
1678         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1679         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1680         in IV3.2 spec.
1681         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1682         vr5000 which saves LO in a GPR separatly.
1683
1684         * configure.in (enable-sim-igen): For vr5000, select vr5000
1685         specific instructions.
1686         * configure: Re-generate.
1687
1688 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1689
1690         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1691
1692         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1693         fmt_uninterpreted_64 bit cases to switch.  Convert to
1694         fmt_formatted,
1695
1696         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1697
1698         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1699         as specified in IV3.2 spec.
1700         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1701
1702 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1703
1704         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1705         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1706         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1707         PENDING_FILL versions of instructions.  Simplify.
1708         (X): New function.
1709         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1710         instructions.
1711         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1712         a signed value.
1713         (MTHI, MFHI): Disable code checking HI-LO.
1714
1715         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1716         global.
1717         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1718
1719 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1720
1721         * gencode.c (build_mips16_operands): Replace IPC with cia.
1722
1723         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1724         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1725         IPC to `cia'.
1726         (UndefinedResult): Replace function with macro/function
1727         combination.
1728         (sim_engine_run): Don't save PC in IPC.
1729
1730         * sim-main.h (IPC): Delete.
1731
1732
1733         * interp.c (signal_exception, store_word, load_word,
1734         address_translation, load_memory, store_memory, cache_op,
1735         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1736         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1737         current instruction address - cia - argument.
1738         (sim_read, sim_write): Call address_translation directly.
1739         (sim_engine_run): Rename variable vaddr to cia.
1740         (signal_exception): Pass cia to sim_monitor
1741
1742         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1743         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1744         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1745
1746         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1747         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1748         SIM_ASSERT.
1749
1750         * interp.c (signal_exception): Pass restart address to
1751         sim_engine_restart.
1752
1753         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1754         idecode.o): Add dependency.
1755
1756         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1757         Delete definitions
1758         (DELAY_SLOT): Update NIA not PC with branch address.
1759         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1760
1761         * mips.igen: Use CIA not PC in branch calculations.
1762         (illegal): Call SignalException.
1763         (BEQ, ADDIU): Fix assembler.
1764
1765 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * m16.igen (JALX): Was missing.
1768
1769         * configure.in (enable-sim-igen): New configuration option.
1770         * configure: Re-generate.
1771
1772         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1773
1774         * interp.c (load_memory, store_memory): Delete parameter RAW.
1775         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1776         bypassing {load,store}_memory.
1777
1778         * sim-main.h (ByteSwapMem): Delete definition.
1779
1780         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1781
1782         * interp.c (sim_do_command, sim_commands): Delete mips specific
1783         commands.  Handled by module sim-options.
1784
1785         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1786         (WITH_MODULO_MEMORY): Define.
1787
1788         * interp.c (sim_info): Delete code printing memory size.
1789
1790         * interp.c (mips_size): Nee sim_size, delete function.
1791         (power2): Delete.
1792         (monitor, monitor_base, monitor_size): Delete global variables.
1793         (sim_open, sim_close): Delete code creating monitor and other
1794         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1795         manage memory regions.
1796         (load_memory, store_memory): Use sim-core for memory model.
1797
1798         * interp.c (address_translation): Delete all memory map code
1799         except line forcing 32 bit addresses.
1800
1801 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1802
1803         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1804         trace options.
1805
1806         * interp.c (logfh, logfile): Delete globals.
1807         (sim_open, sim_close): Delete code opening & closing log file.
1808         (mips_option_handler): Delete -l and -n options.
1809         (OPTION mips_options): Ditto.
1810
1811         * interp.c (OPTION mips_options): Rename option trace to dinero.
1812         (mips_option_handler): Update.
1813
1814 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1815
1816         * interp.c (fetch_str): New function.
1817         (sim_monitor): Rewrite using sim_read & sim_write.
1818         (sim_open): Check magic number.
1819         (sim_open): Write monitor vectors into memory using sim_write.
1820         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1821         (sim_read, sim_write): Simplify - transfer data one byte at a
1822         time.
1823         (load_memory, store_memory): Clarify meaning of parameter RAW.
1824
1825         * sim-main.h (isHOST): Defete definition.
1826         (isTARGET): Mark as depreciated.
1827         (address_translation): Delete parameter HOST.
1828
1829         * interp.c (address_translation): Delete parameter HOST.
1830
1831 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1832
1833         * mips.igen:
1834
1835         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1836         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1837
1838 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1839
1840         * mips.igen: Add model filter field to records.
1841
1842 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1843
1844         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1845
1846         interp.c (sim_engine_run): Do not compile function sim_engine_run
1847         when WITH_IGEN == 1.
1848
1849         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1850         target architecture.
1851
1852         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1853         igen. Replace with configuration variables sim_igen_flags /
1854         sim_m16_flags.
1855
1856         * m16.igen: New file.  Copy mips16 insns here.
1857         * mips.igen: From here.
1858
1859 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1860
1861         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1862         to top.
1863         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1864
1865 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1866
1867         * gencode.c (build_instruction): Follow sim_write's lead in using
1868         BigEndianMem instead of !ByteSwapMem.
1869
1870 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1871
1872         * configure.in (sim_gen): Dependent on target, select type of
1873         generator.  Always select old style generator.
1874
1875         configure: Re-generate.
1876
1877         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1878         targets.
1879         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1880         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1881         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1882         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1883         SIM_@sim_gen@_*, set by autoconf.
1884
1885 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1886
1887         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1888
1889         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1890         CURRENT_FLOATING_POINT instead.
1891
1892         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1893         (address_translation): Raise exception InstructionFetch when
1894         translation fails and isINSTRUCTION.
1895
1896         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1897         sim_engine_run): Change type of of vaddr and paddr to
1898         address_word.
1899         (address_translation, prefetch, load_memory, store_memory,
1900         cache_op): Change type of vAddr and pAddr to address_word.
1901
1902         * gencode.c (build_instruction): Change type of vaddr and paddr to
1903         address_word.
1904
1905 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1906
1907         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1908         macro to obtain result of ALU op.
1909
1910 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1911
1912         * interp.c (sim_info): Call profile_print.
1913
1914 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1915
1916         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1917
1918         * sim-main.h (WITH_PROFILE): Do not define, defined in
1919         common/sim-config.h.  Use sim-profile module.
1920         (simPROFILE): Delete defintion.
1921
1922         * interp.c (PROFILE): Delete definition.
1923         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1924         (sim_close): Delete code writing profile histogram.
1925         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1926         Delete.
1927         (sim_engine_run): Delete code profiling the PC.
1928
1929 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1930
1931         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1932
1933         * interp.c (sim_monitor): Make register pointers of type
1934         unsigned_word*.
1935
1936         * sim-main.h: Make registers of type unsigned_word not
1937         signed_word.
1938
1939 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1940
1941         * interp.c (sync_operation): Rename from SyncOperation, make
1942         global, add SD argument.
1943         (prefetch): Rename from Prefetch, make global, add SD argument.
1944         (decode_coproc): Make global.
1945
1946         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1947
1948         * gencode.c (build_instruction): Generate DecodeCoproc not
1949         decode_coproc calls.
1950
1951         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1952         (SizeFGR): Move to sim-main.h
1953         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1954         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1955         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1956         sim-main.h.
1957         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1958         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1959         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1960         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1961         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1962         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1963
1964         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1965         exception.
1966         (sim-alu.h): Include.
1967         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1968         (sim_cia): Typedef to instruction_address.
1969
1970 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1971
1972         * Makefile.in (interp.o): Rename generated file engine.c to
1973         oengine.c.
1974
1975         * interp.c: Update.
1976
1977 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1980
1981 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1982
1983         * gencode.c (build_instruction): For "FPSQRT", output correct
1984         number of arguments to Recip.
1985
1986 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1987
1988         * Makefile.in (interp.o): Depends on sim-main.h
1989
1990         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1991
1992         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1993         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1994         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1995         STATE, DSSTATE): Define
1996         (GPR, FGRIDX, ..): Define.
1997
1998         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1999         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2000         (GPR, FGRIDX, ...): Delete macros.
2001
2002         * interp.c: Update names to match defines from sim-main.h
2003
2004 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2005
2006         * interp.c (sim_monitor): Add SD argument.
2007         (sim_warning): Delete.  Replace calls with calls to
2008         sim_io_eprintf.
2009         (sim_error): Delete. Replace calls with sim_io_error.
2010         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2011         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2012         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2013         argument.
2014         (mips_size): Rename from sim_size. Add SD argument.
2015
2016         * interp.c (simulator): Delete global variable.
2017         (callback): Delete global variable.
2018         (mips_option_handler, sim_open, sim_write, sim_read,
2019         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2020         sim_size,sim_monitor): Use sim_io_* not callback->*.
2021         (sim_open): ZALLOC simulator struct.
2022         (PROFILE): Do not define.
2023
2024 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2025
2026         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2027         support.h with corresponding code.
2028
2029         * sim-main.h (word64, uword64), support.h: Move definition to
2030         sim-main.h.
2031         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2032
2033         * support.h: Delete
2034         * Makefile.in: Update dependencies
2035         * interp.c: Do not include.
2036
2037 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2038
2039         * interp.c (address_translation, load_memory, store_memory,
2040         cache_op): Rename to from AddressTranslation et.al., make global,
2041         add SD argument
2042
2043         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2044         CacheOp): Define.
2045
2046         * interp.c (SignalException): Rename to signal_exception, make
2047         global.
2048
2049         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2050
2051         * sim-main.h (SignalException, SignalExceptionInterrupt,
2052         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2053         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2054         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2055         Define.
2056
2057         * interp.c, support.h: Use.
2058
2059 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2060
2061         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2062         to value_fpr / store_fpr. Add SD argument.
2063         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2064         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2065
2066         * sim-main.h (ValueFPR, StoreFPR): Define.
2067
2068 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2069
2070         * interp.c (sim_engine_run): Check consistency between configure
2071         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2072         and HASFPU.
2073
2074         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2075         (mips_fpu): Configure WITH_FLOATING_POINT.
2076         (mips_endian): Configure WITH_TARGET_ENDIAN.
2077         * configure: Update.
2078
2079 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2080
2081         * configure: Regenerated to track ../common/aclocal.m4 changes.
2082
2083 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2084
2085         * configure: Regenerated.
2086
2087 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2088
2089         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2090
2091 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2092
2093         * gencode.c (print_igen_insn_models): Assume certain architectures
2094         include all mips* instructions.
2095         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2096         instruction.
2097
2098         * Makefile.in (tmp.igen): Add target. Generate igen input from
2099         gencode file.
2100
2101         * gencode.c (FEATURE_IGEN): Define.
2102         (main): Add --igen option.  Generate output in igen format.
2103         (process_instructions): Format output according to igen option.
2104         (print_igen_insn_format): New function.
2105         (print_igen_insn_models): New function.
2106         (process_instructions): Only issue warnings and ignore
2107         instructions when no FEATURE_IGEN.
2108
2109 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2110
2111         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2112         MIPS targets.
2113
2114 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2115
2116         * configure: Regenerated to track ../common/aclocal.m4 changes.
2117
2118 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2119
2120         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2121         SIM_RESERVED_BITS): Delete, moved to common.
2122         (SIM_EXTRA_CFLAGS): Update.
2123
2124 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2125
2126         * configure.in: Configure non-strict memory alignment.
2127         * configure: Regenerated to track ../common/aclocal.m4 changes.
2128
2129 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2130
2131         * configure: Regenerated to track ../common/aclocal.m4 changes.
2132
2133 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2134
2135         * gencode.c (SDBBP,DERET): Added (3900) insns.
2136         (RFE): Turn on for 3900.
2137         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2138         (dsstate): Made global.
2139         (SUBTARGET_R3900): Added.
2140         (CANCELDELAYSLOT): New.
2141         (SignalException): Ignore SystemCall rather than ignore and
2142         terminate.  Add DebugBreakPoint handling.
2143         (decode_coproc): New insns RFE, DERET; and new registers Debug
2144         and DEPC protected by SUBTARGET_R3900.
2145         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2146         bits explicitly.
2147         * Makefile.in,configure.in: Add mips subtarget option.
2148         * configure: Update.
2149
2150 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2151
2152         * gencode.c: Add r3900 (tx39).
2153
2154
2155 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2156
2157         * gencode.c (build_instruction): Don't need to subtract 4 for
2158         JALR, just 2.
2159
2160 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2161
2162         * interp.c: Correct some HASFPU problems.
2163
2164 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2165
2166         * configure: Regenerated to track ../common/aclocal.m4 changes.
2167
2168 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2169
2170         * interp.c (mips_options): Fix samples option short form, should
2171         be `x'.
2172
2173 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2174
2175         * interp.c (sim_info): Enable info code.  Was just returning.
2176
2177 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2178
2179         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2180         MFC0.
2181
2182 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2183
2184         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2185         constants.
2186         (build_instruction): Ditto for LL.
2187
2188 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2189
2190         * configure: Regenerated to track ../common/aclocal.m4 changes.
2191
2192 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2193
2194         * configure: Regenerated to track ../common/aclocal.m4 changes.
2195         * config.in: Ditto.
2196
2197 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2198
2199         * interp.c (sim_open): Add call to sim_analyze_program, update
2200         call to sim_config.
2201
2202 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2203
2204         * interp.c (sim_kill): Delete.
2205         (sim_create_inferior): Add ABFD argument. Set PC from same.
2206         (sim_load): Move code initializing trap handlers from here.
2207         (sim_open): To here.
2208         (sim_load): Delete, use sim-hload.c.
2209
2210         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2211
2212 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2213
2214         * configure: Regenerated to track ../common/aclocal.m4 changes.
2215         * config.in: Ditto.
2216
2217 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2218
2219         * interp.c (sim_open): Add ABFD argument.
2220         (sim_load): Move call to sim_config from here.
2221         (sim_open): To here.  Check return status.
2222
2223 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2224
2225         * gencode.c (build_instruction): Two arg MADD should
2226         not assign result to $0.
2227
2228 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2229
2230         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2231         * sim/mips/configure.in: Regenerate.
2232
2233 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2234
2235         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2236         signed8, unsigned8 et.al. types.
2237
2238         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2239         hosts when selecting subreg.
2240
2241 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2242
2243         * interp.c (sim_engine_run): Reset the ZERO register to zero
2244         regardless of FEATURE_WARN_ZERO.
2245         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2246
2247 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2248
2249         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2250         (SignalException): For BreakPoints ignore any mode bits and just
2251         save the PC.
2252         (SignalException): Always set the CAUSE register.
2253
2254 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2255
2256         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2257         exception has been taken.
2258
2259         * interp.c: Implement the ERET and mt/f sr instructions.
2260
2261 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2262
2263         * interp.c (SignalException): Don't bother restarting an
2264         interrupt.
2265
2266 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2267
2268         * interp.c (SignalException): Really take an interrupt.
2269         (interrupt_event): Only deliver interrupts when enabled.
2270
2271 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2272
2273         * interp.c (sim_info): Only print info when verbose.
2274         (sim_info) Use sim_io_printf for output.
2275
2276 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2277
2278         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2279         mips architectures.
2280
2281 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2282
2283         * interp.c (sim_do_command): Check for common commands if a
2284         simulator specific command fails.
2285
2286 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2287
2288         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2289         and simBE when DEBUG is defined.
2290
2291 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2292
2293         * interp.c (interrupt_event): New function.  Pass exception event
2294         onto exception handler.
2295
2296         * configure.in: Check for stdlib.h.
2297         * configure: Regenerate.
2298
2299         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2300         variable declaration.
2301         (build_instruction): Initialize memval1.
2302         (build_instruction): Add UNUSED attribute to byte, bigend,
2303         reverse.
2304         (build_operands): Ditto.
2305
2306         * interp.c: Fix GCC warnings.
2307         (sim_get_quit_code): Delete.
2308
2309         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2310         * Makefile.in: Ditto.
2311         * configure: Re-generate.
2312
2313         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2314
2315 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2316
2317         * interp.c (mips_option_handler): New function parse argumes using
2318         sim-options.
2319         (myname): Replace with STATE_MY_NAME.
2320         (sim_open): Delete check for host endianness - performed by
2321         sim_config.
2322         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2323         (sim_open): Move much of the initialization from here.
2324         (sim_load): To here.  After the image has been loaded and
2325         endianness set.
2326         (sim_open): Move ColdReset from here.
2327         (sim_create_inferior): To here.
2328         (sim_open): Make FP check less dependant on host endianness.
2329
2330         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2331         run.
2332         * interp.c (sim_set_callbacks): Delete.
2333
2334         * interp.c (membank, membank_base, membank_size): Replace with
2335         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2336         (sim_open): Remove call to callback->init. gdb/run do this.
2337
2338         * interp.c: Update
2339
2340         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2341
2342         * interp.c (big_endian_p): Delete, replaced by
2343         current_target_byte_order.
2344
2345 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2346
2347         * interp.c (host_read_long, host_read_word, host_swap_word,
2348         host_swap_long): Delete. Using common sim-endian.
2349         (sim_fetch_register, sim_store_register): Use H2T.
2350         (pipeline_ticks): Delete.  Handled by sim-events.
2351         (sim_info): Update.
2352         (sim_engine_run): Update.
2353
2354 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2355
2356         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2357         reason from here.
2358         (SignalException): To here. Signal using sim_engine_halt.
2359         (sim_stop_reason): Delete, moved to common.
2360
2361 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2362
2363         * interp.c (sim_open): Add callback argument.
2364         (sim_set_callbacks): Delete SIM_DESC argument.
2365         (sim_size): Ditto.
2366
2367 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2368
2369         * Makefile.in (SIM_OBJS): Add common modules.
2370
2371         * interp.c (sim_set_callbacks): Also set SD callback.
2372         (set_endianness, xfer_*, swap_*): Delete.
2373         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2374         Change to functions using sim-endian macros.
2375         (control_c, sim_stop): Delete, use common version.
2376         (simulate): Convert into.
2377         (sim_engine_run): This function.
2378         (sim_resume): Delete.
2379
2380         * interp.c (simulation): New variable - the simulator object.
2381         (sim_kind): Delete global - merged into simulation.
2382         (sim_load): Cleanup.  Move PC assignment from here.
2383         (sim_create_inferior): To here.
2384
2385         * sim-main.h: New file.
2386         * interp.c (sim-main.h): Include.
2387
2388 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2389
2390         * configure: Regenerated to track ../common/aclocal.m4 changes.
2391
2392 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2393
2394         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2395
2396 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2397
2398         * gencode.c (build_instruction): DIV instructions: check
2399         for division by zero and integer overflow before using
2400         host's division operation.
2401
2402 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2403
2404         * Makefile.in (SIM_OBJS): Add sim-load.o.
2405         * interp.c: #include bfd.h.
2406         (target_byte_order): Delete.
2407         (sim_kind, myname, big_endian_p): New static locals.
2408         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2409         after argument parsing.  Recognize -E arg, set endianness accordingly.
2410         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2411         load file into simulator.  Set PC from bfd.
2412         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2413         (set_endianness): Use big_endian_p instead of target_byte_order.
2414
2415 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2416
2417         * interp.c (sim_size): Delete prototype - conflicts with
2418         definition in remote-sim.h.  Correct definition.
2419
2420 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2421
2422         * configure: Regenerated to track ../common/aclocal.m4 changes.
2423         * config.in: Ditto.
2424
2425 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2426
2427         * interp.c (sim_open): New arg `kind'.
2428
2429         * configure: Regenerated to track ../common/aclocal.m4 changes.
2430
2431 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2432
2433         * configure: Regenerated to track ../common/aclocal.m4 changes.
2434
2435 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2436
2437         * interp.c (sim_open): Set optind to 0 before calling getopt.
2438
2439 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2440
2441         * configure: Regenerated to track ../common/aclocal.m4 changes.
2442
2443 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2444
2445         * interp.c : Replace uses of pr_addr with pr_uword64
2446         where the bit length is always 64 independent of SIM_ADDR.
2447         (pr_uword64) : added.
2448
2449 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2450
2451         * configure: Re-generate.
2452
2453 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2454
2455         * configure: Regenerate to track ../common/aclocal.m4 changes.
2456
2457 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2458
2459         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2460         in argv form.
2461         (other sim_*): New SIM_DESC argument.
2462
2463 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2464
2465         * interp.c: Fix printing of addresses for non-64-bit targets.
2466         (pr_addr): Add function to print address based on size.
2467
2468 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2469
2470         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2471
2472 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2473
2474         * gencode.c (build_mips16_operands): Correct computation of base
2475         address for extended PC relative instruction.
2476
2477 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2478
2479         * interp.c (mips16_entry): Add support for floating point cases.
2480         (SignalException): Pass floating point cases to mips16_entry.
2481         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2482         registers.
2483         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2484         or fmt_word.
2485         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2486         and then set the state to fmt_uninterpreted.
2487         (COP_SW): Temporarily set the state to fmt_word while calling
2488         ValueFPR.
2489
2490 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2491
2492         * gencode.c (build_instruction): The high order may be set in the
2493         comparison flags at any ISA level, not just ISA 4.
2494
2495 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2496
2497         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2498         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2499         * configure.in: sinclude ../common/aclocal.m4.
2500         * configure: Regenerated.
2501
2502 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2503
2504         * configure: Rebuild after change to aclocal.m4.
2505
2506 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2507
2508         * configure configure.in Makefile.in:  Update to new configure
2509         scheme which is more compatible with WinGDB builds.
2510         * configure.in:  Improve comment on how to run autoconf.
2511         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2512         * Makefile.in:  Use autoconf substitution to install common
2513         makefile fragment.
2514
2515 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2516
2517         * gencode.c (build_instruction): Use BigEndianCPU instead of
2518         ByteSwapMem.
2519
2520 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2521
2522         * interp.c (sim_monitor): Make output to stdout visible in
2523         wingdb's I/O log window.
2524
2525 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2526
2527         * support.h: Undo previous change to SIGTRAP
2528         and SIGQUIT values.
2529
2530 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2531
2532         * interp.c (store_word, load_word): New static functions.
2533         (mips16_entry): New static function.
2534         (SignalException): Look for mips16 entry and exit instructions.
2535         (simulate): Use the correct index when setting fpr_state after
2536         doing a pending move.
2537
2538 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2539
2540         * interp.c: Fix byte-swapping code throughout to work on
2541         both little- and big-endian hosts.
2542
2543 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2544
2545         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2546         with gdb/config/i386/xm-windows.h.
2547
2548 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2549
2550         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2551         that messes up arithmetic shifts.
2552
2553 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2554
2555         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2556         SIGTRAP and SIGQUIT for _WIN32.
2557
2558 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2559
2560         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2561         force a 64 bit multiplication.
2562         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2563         destination register is 0, since that is the default mips16 nop
2564         instruction.
2565
2566 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2567
2568         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2569         (build_endian_shift): Don't check proc64.
2570         (build_instruction): Always set memval to uword64.  Cast op2 to
2571         uword64 when shifting it left in memory instructions.  Always use
2572         the same code for stores--don't special case proc64.
2573
2574         * gencode.c (build_mips16_operands): Fix base PC value for PC
2575         relative operands.
2576         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2577         jal instruction.
2578         * interp.c (simJALDELAYSLOT): Define.
2579         (JALDELAYSLOT): Define.
2580         (INDELAYSLOT, INJALDELAYSLOT): Define.
2581         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2582
2583 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2584
2585         * interp.c (sim_open): add flush_cache as a PMON routine
2586         (sim_monitor): handle flush_cache by ignoring it
2587
2588 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2589
2590         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2591         BigEndianMem.
2592         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2593         (BigEndianMem): Rename to ByteSwapMem and change sense.
2594         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2595         BigEndianMem references to !ByteSwapMem.
2596         (set_endianness): New function, with prototype.
2597         (sim_open): Call set_endianness.
2598         (sim_info): Use simBE instead of BigEndianMem.
2599         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2600         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2601         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2602         ifdefs, keeping the prototype declaration.
2603         (swap_word): Rewrite correctly.
2604         (ColdReset): Delete references to CONFIG.  Delete endianness related
2605         code; moved to set_endianness.
2606
2607 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2608
2609         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2610         * interp.c (CHECKHILO): Define away.
2611         (simSIGINT): New macro.
2612         (membank_size): Increase from 1MB to 2MB.
2613         (control_c): New function.
2614         (sim_resume): Rename parameter signal to signal_number.  Add local
2615         variable prev.  Call signal before and after simulate.
2616         (sim_stop_reason): Add simSIGINT support.
2617         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2618         functions always.
2619         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2620         if logfh is NULL.
2621         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2622         a call to sim_warning.
2623
2624 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2625
2626         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2627         16 bit instructions.
2628
2629 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2630
2631         Add support for mips16 (16 bit MIPS implementation):
2632         * gencode.c (inst_type): Add mips16 instruction encoding types.
2633         (GETDATASIZEINSN): Define.
2634         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2635         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2636         mtlo.
2637         (MIPS16_DECODE): New table, for mips16 instructions.
2638         (bitmap_val): New static function.
2639         (struct mips16_op): Define.
2640         (mips16_op_table): New table, for mips16 operands.
2641         (build_mips16_operands): New static function.
2642         (process_instructions): If PC is odd, decode a mips16
2643         instruction.  Break out instruction handling into new
2644         build_instruction function.
2645         (build_instruction): New static function, broken out of
2646         process_instructions.  Check modifiers rather than flags for SHIFT
2647         bit count and m[ft]{hi,lo} direction.
2648         (usage): Pass program name to fprintf.
2649         (main): Remove unused variable this_option_optind.  Change
2650         ``*loptarg++'' to ``loptarg++''.
2651         (my_strtoul): Parenthesize && within ||.
2652         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2653         (simulate): If PC is odd, fetch a 16 bit instruction, and
2654         increment PC by 2 rather than 4.
2655         * configure.in: Add case for mips16*-*-*.
2656         * configure: Rebuild.
2657
2658 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2659
2660         * interp.c: Allow -t to enable tracing in standalone simulator.
2661         Fix garbage output in trace file and error messages.
2662
2663 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2664
2665         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2666         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2667         * configure.in: Simplify using macros in ../common/aclocal.m4.
2668         * configure: Regenerated.
2669         * tconfig.in: New file.
2670
2671 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2672
2673         * interp.c: Fix bugs in 64-bit port.
2674         Use ansi function declarations for msvc compiler.
2675         Initialize and test file pointer in trace code.
2676         Prevent duplicate definition of LAST_EMED_REGNUM.
2677
2678 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2679
2680         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2681
2682 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2683
2684         * interp.c (SignalException): Check for explicit terminating
2685         breakpoint value.
2686         * gencode.c: Pass instruction value through SignalException()
2687         calls for Trap, Breakpoint and Syscall.
2688
2689 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2690
2691         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2692         only used on those hosts that provide it.
2693         * configure.in: Add sqrt() to list of functions to be checked for.
2694         * config.in: Re-generated.
2695         * configure: Re-generated.
2696
2697 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2698
2699         * gencode.c (process_instructions): Call build_endian_shift when
2700         expanding STORE RIGHT, to fix swr.
2701         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2702         clear the high bits.
2703         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2704         Fix float to int conversions to produce signed values.
2705
2706 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2707
2708         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2709         (process_instructions): Correct handling of nor instruction.
2710         Correct shift count for 32 bit shift instructions. Correct sign
2711         extension for arithmetic shifts to not shift the number of bits in
2712         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2713         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2714         Fix madd.
2715         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2716         It's OK to have a mult follow a mult.  What's not OK is to have a
2717         mult follow an mfhi.
2718         (Convert): Comment out incorrect rounding code.
2719
2720 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2721
2722         * interp.c (sim_monitor): Improved monitor printf
2723         simulation. Tidied up simulator warnings, and added "--log" option
2724         for directing warning message output.
2725         * gencode.c: Use sim_warning() rather than WARNING macro.
2726
2727 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2728
2729         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2730         getopt1.o, rather than on gencode.c.  Link objects together.
2731         Don't link against -liberty.
2732         (gencode.o, getopt.o, getopt1.o): New targets.
2733         * gencode.c: Include <ctype.h> and "ansidecl.h".
2734         (AND): Undefine after including "ansidecl.h".
2735         (ULONG_MAX): Define if not defined.
2736         (OP_*): Don't define macros; now defined in opcode/mips.h.
2737         (main): Call my_strtoul rather than strtoul.
2738         (my_strtoul): New static function.
2739
2740 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2741
2742         * gencode.c (process_instructions):  Generate word64 and uword64
2743         instead of `long long' and `unsigned long long' data types.
2744         * interp.c:  #include sysdep.h to get signals, and define default
2745         for SIGBUS.
2746         * (Convert):  Work around for Visual-C++ compiler bug with type
2747         conversion.
2748         * support.h:  Make things compile under Visual-C++ by using
2749         __int64 instead of `long long'.  Change many refs to long long
2750         into word64/uword64 typedefs.
2751
2752 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2753
2754         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2755         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2756         (docdir): Removed.
2757         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2758         (AC_PROG_INSTALL): Added.
2759         (AC_PROG_CC): Moved to before configure.host call.
2760         * configure: Rebuilt.
2761
2762 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2763
2764         * configure.in: Define @SIMCONF@ depending on mips target.
2765         * configure: Rebuild.
2766         * Makefile.in (run): Add @SIMCONF@ to control simulator
2767         construction.
2768         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2769         * interp.c: Remove some debugging, provide more detailed error
2770         messages, update memory accesses to use LOADDRMASK.
2771
2772 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2773
2774         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2775         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2776         stamp-h.
2777         * configure: Rebuild.
2778         * config.in: New file, generated by autoheader.
2779         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2780         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2781         HAVE_ANINT and HAVE_AINT, as appropriate.
2782         * Makefile.in (run): Use @LIBS@ rather than -lm.
2783         (interp.o): Depend upon config.h.
2784         (Makefile): Just rebuild Makefile.
2785         (clean): Remove stamp-h.
2786         (mostlyclean): Make the same as clean, not as distclean.
2787         (config.h, stamp-h): New targets.
2788
2789 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2790
2791         * interp.c (ColdReset): Fix boolean test. Make all simulator
2792         globals static.
2793
2794 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2795
2796         * interp.c (xfer_direct_word, xfer_direct_long,
2797         swap_direct_word, swap_direct_long, xfer_big_word,
2798         xfer_big_long, xfer_little_word, xfer_little_long,
2799         swap_word,swap_long): Added.
2800         * interp.c (ColdReset): Provide function indirection to
2801         host<->simulated_target transfer routines.
2802         * interp.c (sim_store_register, sim_fetch_register): Updated to
2803         make use of indirected transfer routines.
2804
2805 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2806
2807         * gencode.c (process_instructions): Ensure FP ABS instruction
2808         recognised.
2809         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2810         system call support.
2811
2812 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2813
2814         * interp.c (sim_do_command): Complain if callback structure not
2815         initialised.
2816
2817 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2818
2819         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2820         support for Sun hosts.
2821         * Makefile.in (gencode): Ensure the host compiler and libraries
2822         used for cross-hosted build.
2823
2824 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2825
2826         * interp.c, gencode.c: Some more (TODO) tidying.
2827
2828 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2829
2830         * gencode.c, interp.c: Replaced explicit long long references with
2831         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2832         * support.h (SET64LO, SET64HI): Macros added.
2833
2834 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2835
2836         * configure: Regenerate with autoconf 2.7.
2837
2838 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2839
2840         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2841         * support.h: Remove superfluous "1" from #if.
2842         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2843
2844 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2845
2846         * interp.c (StoreFPR): Control UndefinedResult() call on
2847         WARN_RESULT manifest.
2848
2849 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2850
2851         * gencode.c: Tidied instruction decoding, and added FP instruction
2852         support.
2853
2854         * interp.c: Added dineroIII, and BSD profiling support. Also
2855         run-time FP handling.
2856
2857 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2858
2859         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2860         gencode.c, interp.c, support.h: created.