1 2002-02-27 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
4 add a comma) so that it more closely match the MIPS ISA
5 documentation opcode partitioning.
6 (PREF): Put useful names on opcode fields, and include
7 instruction-printing string.
9 2002-02-27 Chris Demetriou <cgd@broadcom.com>
11 * mips.igen (check_u64): New function which in the future will
12 check whether 64-bit instructions are usable and signal an
13 exception if not. Currently a no-op.
14 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
15 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
16 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
17 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
19 * mips.igen (check_fpu): New function which in the future will
20 check whether FPU instructions are usable and signal an exception
21 if not. Currently a no-op.
22 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
23 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
24 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
25 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
26 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
27 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
28 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
29 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
31 2002-02-27 Chris Demetriou <cgd@broadcom.com>
33 * mips.igen (do_load_left, do_load_right): Move to be immediately
35 (do_store_left, do_store_right): Move to be immediately following
38 2002-02-27 Chris Demetriou <cgd@broadcom.com>
40 * mips.igen (mipsV): New model name. Also, add it to
41 all instructions and functions where it is appropriate.
43 2002-02-18 Chris Demetriou <cgd@broadcom.com>
45 * mips.igen: For all functions and instructions, list model
46 names that support that instruction one per line.
48 2002-02-11 Chris Demetriou <cgd@broadcom.com>
50 * mips.igen: Add some additional comments about supported
51 models, and about which instructions go where.
52 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
53 order as is used in the rest of the file.
55 2002-02-11 Chris Demetriou <cgd@broadcom.com>
57 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
58 indicating that ALU32_END or ALU64_END are there to check
60 (DADD): Likewise, but also remove previous comment about
63 2002-02-10 Chris Demetriou <cgd@broadcom.com>
65 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
66 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
67 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
68 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
69 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
70 fields (i.e., add and move commas) so that they more closely
71 match the MIPS ISA documentation opcode partitioning.
73 2002-02-10 Chris Demetriou <cgd@broadcom.com>
75 * mips.igen (ADDI): Print immediate value.
77 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
78 (SLL): Print "nop" specially, and don't run the code
79 that does the shift for the "nop" case.
81 2001-11-17 Fred Fish <fnf@redhat.com>
83 * sim-main.h (float_operation): Move enum declaration outside
84 of _sim_cpu struct declaration.
86 2001-04-12 Jim Blandy <jimb@redhat.com>
88 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
89 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
91 * sim-main.h (COCIDX): Remove definition; this isn't supported by
92 PENDING_FILL, and you can get the intended effect gracefully by
93 calling PENDING_SCHED directly.
95 2001-02-23 Ben Elliston <bje@redhat.com>
97 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
98 already defined elsewhere.
100 2001-02-19 Ben Elliston <bje@redhat.com>
102 * sim-main.h (sim_monitor): Return an int.
103 * interp.c (sim_monitor): Add return values.
104 (signal_exception): Handle error conditions from sim_monitor.
106 2001-02-08 Ben Elliston <bje@redhat.com>
108 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
109 (store_memory): Likewise, pass cia to sim_core_write*.
111 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
113 On advice from Chris G. Demetriou <cgd@sibyte.com>:
114 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
116 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
118 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
119 * Makefile.in: Don't delete *.igen when cleaning directory.
121 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
123 * m16.igen (break): Call SignalException not sim_engine_halt.
125 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
128 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
130 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
132 * mips.igen (MxC1, DMxC1): Fix printf formatting.
134 2000-05-24 Michael Hayes <mhayes@cygnus.com>
136 * mips.igen (do_dmultx): Fix typo.
138 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
140 * configure: Regenerated to track ../common/aclocal.m4 changes.
142 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
144 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
146 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
148 * sim-main.h (GPR_CLEAR): Define macro.
150 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
152 * interp.c (decode_coproc): Output long using %lx and not %s.
154 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
156 * interp.c (sim_open): Sort & extend dummy memory regions for
157 --board=jmr3904 for eCos.
159 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
161 * configure: Regenerated.
163 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
165 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
166 calls, conditional on the simulator being in verbose mode.
168 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
170 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
171 cache don't get ReservedInstruction traps.
173 1999-11-29 Mark Salter <msalter@cygnus.com>
175 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
176 to clear status bits in sdisr register. This is how the hardware works.
178 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
179 being used by cygmon.
181 1999-11-11 Andrew Haley <aph@cygnus.com>
183 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
186 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
188 * mips.igen (MULT): Correct previous mis-applied patch.
190 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
192 * mips.igen (delayslot32): Handle sequence like
193 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
194 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
195 (MULT): Actually pass the third register...
197 1999-09-03 Mark Salter <msalter@cygnus.com>
199 * interp.c (sim_open): Added more memory aliases for additional
200 hardware being touched by cygmon on jmr3904 board.
202 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
204 * configure: Regenerated to track ../common/aclocal.m4 changes.
206 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
208 * interp.c (sim_store_register): Handle case where client - GDB -
209 specifies that a 4 byte register is 8 bytes in size.
210 (sim_fetch_register): Ditto.
212 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
214 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
215 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
216 (idt_monitor_base): Base address for IDT monitor traps.
217 (pmon_monitor_base): Ditto for PMON.
218 (lsipmon_monitor_base): Ditto for LSI PMON.
219 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
220 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
221 (sim_firmware_command): New function.
222 (mips_option_handler): Call it for OPTION_FIRMWARE.
223 (sim_open): Allocate memory for idt_monitor region. If "--board"
224 option was given, add no monitor by default. Add BREAK hooks only if
225 monitors are also there.
227 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
229 * interp.c (sim_monitor): Flush output before reading input.
231 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
233 * tconfig.in (SIM_HANDLES_LMA): Always define.
235 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
237 From Mark Salter <msalter@cygnus.com>:
238 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
239 (sim_open): Add setup for BSP board.
241 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
243 * mips.igen (MULT, MULTU): Add syntax for two operand version.
244 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
245 them as unimplemented.
247 1999-05-08 Felix Lee <flee@cygnus.com>
249 * configure: Regenerated to track ../common/aclocal.m4 changes.
251 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
253 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
255 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
257 * configure.in: Any mips64vr5*-*-* target should have
258 -DTARGET_ENABLE_FR=1.
259 (default_endian): Any mips64vr*el-*-* target should default to
261 * configure: Re-generate.
263 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
265 * mips.igen (ldl): Extend from _16_, not 32.
267 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
269 * interp.c (sim_store_register): Force registers written to by GDB
270 into an un-interpreted state.
272 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
274 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
275 CPU, start periodic background I/O polls.
276 (tx3904sio_poll): New function: periodic I/O poller.
278 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
280 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
282 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
284 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
287 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
289 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
290 (load_word): Call SIM_CORE_SIGNAL hook on error.
291 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
292 starting. For exception dispatching, pass PC instead of NULL_CIA.
293 (decode_coproc): Use COP0_BADVADDR to store faulting address.
294 * sim-main.h (COP0_BADVADDR): Define.
295 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
296 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
297 (_sim_cpu): Add exc_* fields to store register value snapshots.
298 * mips.igen (*): Replace memory-related SignalException* calls
299 with references to SIM_CORE_SIGNAL hook.
301 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
303 * sim-main.c (*): Minor warning cleanups.
305 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
307 * m16.igen (DADDIU5): Correct type-o.
309 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
311 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
314 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
316 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
318 (interp.o): Add dependency on itable.h
319 (oengine.c, gencode): Delete remaining references.
320 (BUILT_SRC_FROM_GEN): Clean up.
322 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
325 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
326 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
328 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
329 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
330 Drop the "64" qualifier to get the HACK generator working.
331 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
332 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
333 qualifier to get the hack generator working.
334 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
336 (DSLLV): Use do_dsllv.
339 (DSRLV): Use do_dsrlv.
340 (BC1): Move *vr4100 to get the HACK generator working.
341 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
342 get the HACK generator working.
343 (MACC) Rename to get the HACK generator working.
344 (DMACC,MACCS,DMACCS): Add the 64.
346 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
348 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
349 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
351 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
353 * mips/interp.c (DEBUG): Cleanups.
355 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
357 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
358 (tx3904sio_tickle): fflush after a stdout character output.
360 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
362 * interp.c (sim_close): Uninstall modules.
364 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
366 * sim-main.h, interp.c (sim_monitor): Change to global
369 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
371 * configure.in (vr4100): Only include vr4100 instructions in
373 * configure: Re-generate.
374 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
376 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
378 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
379 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
382 * configure.in (sim_default_gen, sim_use_gen): Replace with
384 (--enable-sim-igen): Delete config option. Always using IGEN.
385 * configure: Re-generate.
387 * Makefile.in (gencode): Kill, kill, kill.
390 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
392 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
393 bit mips16 igen simulator.
394 * configure: Re-generate.
396 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
397 as part of vr4100 ISA.
398 * vr.igen: Mark all instructions as 64 bit only.
400 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
402 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
405 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
407 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
408 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
409 * configure: Re-generate.
411 * m16.igen (BREAK): Define breakpoint instruction.
412 (JALX32): Mark instruction as mips16 and not r3900.
413 * mips.igen (C.cond.fmt): Fix typo in instruction format.
415 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
417 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
419 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
420 insn as a debug breakpoint.
422 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
424 (PENDING_SCHED): Clean up trace statement.
425 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
426 (PENDING_FILL): Delay write by only one cycle.
427 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
429 * sim-main.c (pending_tick): Clean up trace statements. Add trace
431 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
433 (pending_tick): Move incrementing of index to FOR statement.
434 (pending_tick): Only update PENDING_OUT after a write has occured.
436 * configure.in: Add explicit mips-lsi-* target. Use gencode to
438 * configure: Re-generate.
440 * interp.c (sim_engine_run OLD): Delete explicit call to
441 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
443 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
445 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
446 interrupt level number to match changed SignalExceptionInterrupt
449 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
451 * interp.c: #include "itable.h" if WITH_IGEN.
452 (get_insn_name): New function.
453 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
454 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
456 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
458 * configure: Rebuilt to inhale new common/aclocal.m4.
460 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
462 * dv-tx3904sio.c: Include sim-assert.h.
464 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
466 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
467 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
468 Reorganize target-specific sim-hardware checks.
469 * configure: rebuilt.
470 * interp.c (sim_open): For tx39 target boards, set
471 OPERATING_ENVIRONMENT, add tx3904sio devices.
472 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
473 ROM executables. Install dv-sockser into sim-modules list.
475 * dv-tx3904irc.c: Compiler warning clean-up.
476 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
477 frequent hw-trace messages.
479 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
481 * vr.igen (MulAcc): Identify as a vr4100 specific function.
483 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
485 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
488 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
489 * mips.igen: Define vr4100 model. Include vr.igen.
490 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
492 * mips.igen (check_mf_hilo): Correct check.
494 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
496 * sim-main.h (interrupt_event): Add prototype.
498 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
499 register_ptr, register_value.
500 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
502 * sim-main.h (tracefh): Make extern.
504 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
506 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
507 Reduce unnecessarily high timer event frequency.
508 * dv-tx3904cpu.c: Ditto for interrupt event.
510 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
512 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
514 (interrupt_event): Made non-static.
516 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
517 interchange of configuration values for external vs. internal
520 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
522 * mips.igen (BREAK): Moved code to here for
523 simulator-reserved break instructions.
524 * gencode.c (build_instruction): Ditto.
525 * interp.c (signal_exception): Code moved from here. Non-
526 reserved instructions now use exception vector, rather
528 * sim-main.h: Moved magic constants to here.
530 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
532 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
533 register upon non-zero interrupt event level, clear upon zero
535 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
536 by passing zero event value.
537 (*_io_{read,write}_buffer): Endianness fixes.
538 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
539 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
541 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
542 serial I/O and timer module at base address 0xFFFF0000.
544 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
546 * mips.igen (SWC1) : Correct the handling of ReverseEndian
549 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
551 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
555 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
557 * dv-tx3904tmr.c: New file - implements tx3904 timer.
558 * dv-tx3904{irc,cpu}.c: Mild reformatting.
559 * configure.in: Include tx3904tmr in hw_device list.
560 * configure: Rebuilt.
561 * interp.c (sim_open): Instantiate three timer instances.
562 Fix address typo of tx3904irc instance.
564 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
566 * interp.c (signal_exception): SystemCall exception now uses
567 the exception vector.
569 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
571 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
574 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
576 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
578 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
580 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
582 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
583 sim-main.h. Declare a struct hw_descriptor instead of struct
584 hw_device_descriptor.
586 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
588 * mips.igen (do_store_left, do_load_left): Compute nr of left and
589 right bits and then re-align left hand bytes to correct byte
590 lanes. Fix incorrect computation in do_store_left when loading
591 bytes from second word.
593 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
595 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
596 * interp.c (sim_open): Only create a device tree when HW is
599 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
600 * interp.c (signal_exception): Ditto.
602 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
604 * gencode.c: Mark BEGEZALL as LIKELY.
606 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
608 * sim-main.h (ALU32_END): Sign extend 32 bit results.
609 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
611 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
613 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
614 modules. Recognize TX39 target with "mips*tx39" pattern.
615 * configure: Rebuilt.
616 * sim-main.h (*): Added many macros defining bits in
617 TX39 control registers.
618 (SignalInterrupt): Send actual PC instead of NULL.
619 (SignalNMIReset): New exception type.
620 * interp.c (board): New variable for future use to identify
621 a particular board being simulated.
622 (mips_option_handler,mips_options): Added "--board" option.
623 (interrupt_event): Send actual PC.
624 (sim_open): Make memory layout conditional on board setting.
625 (signal_exception): Initial implementation of hardware interrupt
626 handling. Accept another break instruction variant for simulator
628 (decode_coproc): Implement RFE instruction for TX39.
629 (mips.igen): Decode RFE instruction as such.
630 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
631 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
632 bbegin to implement memory map.
633 * dv-tx3904cpu.c: New file.
634 * dv-tx3904irc.c: New file.
636 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
638 * mips.igen (check_mt_hilo): Create a separate r3900 version.
640 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
642 * tx.igen (madd,maddu): Replace calls to check_op_hilo
643 with calls to check_div_hilo.
645 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
647 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
648 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
649 Add special r3900 version of do_mult_hilo.
650 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
651 with calls to check_mult_hilo.
652 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
653 with calls to check_div_hilo.
655 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
657 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
658 Document a replacement.
660 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
662 * interp.c (sim_monitor): Make mon_printf work.
664 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
666 * sim-main.h (INSN_NAME): New arg `cpu'.
668 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
670 * configure: Regenerated to track ../common/aclocal.m4 changes.
672 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
674 * configure: Regenerated to track ../common/aclocal.m4 changes.
677 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
679 * acconfig.h: New file.
680 * configure.in: Reverted change of Apr 24; use sinclude again.
682 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
684 * configure: Regenerated to track ../common/aclocal.m4 changes.
687 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
689 * configure.in: Don't call sinclude.
691 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
693 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
695 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
697 * mips.igen (ERET): Implement.
699 * interp.c (decode_coproc): Return sign-extended EPC.
701 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
703 * interp.c (signal_exception): Do not ignore Trap.
704 (signal_exception): On TRAP, restart at exception address.
705 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
706 (signal_exception): Update.
707 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
708 so that TRAP instructions are caught.
710 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
712 * sim-main.h (struct hilo_access, struct hilo_history): Define,
713 contains HI/LO access history.
714 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
715 (HIACCESS, LOACCESS): Delete, replace with
716 (HIHISTORY, LOHISTORY): New macros.
717 (CHECKHILO): Delete all, moved to mips.igen
719 * gencode.c (build_instruction): Do not generate checks for
720 correct HI/LO register usage.
722 * interp.c (old_engine_run): Delete checks for correct HI/LO
725 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
726 check_mf_cycles): New functions.
727 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
728 do_divu, domultx, do_mult, do_multu): Use.
730 * tx.igen ("madd", "maddu"): Use.
732 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
734 * mips.igen (DSRAV): Use function do_dsrav.
735 (SRAV): Use new function do_srav.
737 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
738 (B): Sign extend 11 bit immediate.
739 (EXT-B*): Shift 16 bit immediate left by 1.
740 (ADDIU*): Don't sign extend immediate value.
742 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
744 * m16run.c (sim_engine_run): Restore CIA after handling an event.
746 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
749 * mips.igen (delayslot32, nullify_next_insn): New functions.
750 (m16.igen): Always include.
751 (do_*): Add more tracing.
753 * m16.igen (delayslot16): Add NIA argument, could be called by a
754 32 bit MIPS16 instruction.
756 * interp.c (ifetch16): Move function from here.
757 * sim-main.c (ifetch16): To here.
759 * sim-main.c (ifetch16, ifetch32): Update to match current
760 implementations of LH, LW.
761 (signal_exception): Don't print out incorrect hex value of illegal
764 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
766 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
769 * m16.igen: Implement MIPS16 instructions.
771 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
772 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
773 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
774 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
775 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
776 bodies of corresponding code from 32 bit insn to these. Also used
777 by MIPS16 versions of functions.
779 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
780 (IMEM16): Drop NR argument from macro.
782 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
784 * Makefile.in (SIM_OBJS): Add sim-main.o.
786 * sim-main.h (address_translation, load_memory, store_memory,
787 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
789 (pr_addr, pr_uword64): Declare.
790 (sim-main.c): Include when H_REVEALS_MODULE_P.
792 * interp.c (address_translation, load_memory, store_memory,
793 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
795 * sim-main.c: To here. Fix compilation problems.
797 * configure.in: Enable inlining.
798 * configure: Re-config.
800 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
802 * configure: Regenerated to track ../common/aclocal.m4 changes.
804 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
806 * mips.igen: Include tx.igen.
807 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
808 * tx.igen: New file, contains MADD and MADDU.
810 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
811 the hardwired constant `7'.
812 (store_memory): Ditto.
813 (LOADDRMASK): Move definition to sim-main.h.
815 mips.igen (MTC0): Enable for r3900.
818 mips.igen (do_load_byte): Delete.
819 (do_load, do_store, do_load_left, do_load_write, do_store_left,
820 do_store_right): New functions.
821 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
823 configure.in: Let the tx39 use igen again.
826 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
828 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
829 not an address sized quantity. Return zero for cache sizes.
831 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
833 * mips.igen (r3900): r3900 does not support 64 bit integer
836 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
838 * configure.in (mipstx39*-*-*): Use gencode simulator rather
840 * configure : Rebuild.
842 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
844 * configure: Regenerated to track ../common/aclocal.m4 changes.
846 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
848 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
850 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
852 * configure: Regenerated to track ../common/aclocal.m4 changes.
853 * config.in: Regenerated to track ../common/aclocal.m4 changes.
855 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
857 * configure: Regenerated to track ../common/aclocal.m4 changes.
859 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
861 * interp.c (Max, Min): Comment out functions. Not yet used.
863 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
865 * configure: Regenerated to track ../common/aclocal.m4 changes.
867 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
869 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
870 configurable settings for stand-alone simulator.
872 * configure.in: Added X11 search, just in case.
874 * configure: Regenerated.
876 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
878 * interp.c (sim_write, sim_read, load_memory, store_memory):
879 Replace sim_core_*_map with read_map, write_map, exec_map resp.
881 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
883 * sim-main.h (GETFCC): Return an unsigned value.
885 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
887 * mips.igen (DIV): Fix check for -1 / MIN_INT.
888 (DADD): Result destination is RD not RT.
890 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
892 * sim-main.h (HIACCESS, LOACCESS): Always define.
894 * mdmx.igen (Maxi, Mini): Rename Max, Min.
896 * interp.c (sim_info): Delete.
898 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
900 * interp.c (DECLARE_OPTION_HANDLER): Use it.
901 (mips_option_handler): New argument `cpu'.
902 (sim_open): Update call to sim_add_option_table.
904 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
906 * mips.igen (CxC1): Add tracing.
908 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
910 * sim-main.h (Max, Min): Declare.
912 * interp.c (Max, Min): New functions.
914 * mips.igen (BC1): Add tracing.
916 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
918 * interp.c Added memory map for stack in vr4100
920 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
922 * interp.c (load_memory): Add missing "break"'s.
924 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
926 * interp.c (sim_store_register, sim_fetch_register): Pass in
927 length parameter. Return -1.
929 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
931 * interp.c: Added hardware init hook, fixed warnings.
933 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
935 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
937 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
939 * interp.c (ifetch16): New function.
941 * sim-main.h (IMEM32): Rename IMEM.
942 (IMEM16_IMMED): Define.
944 (DELAY_SLOT): Update.
946 * m16run.c (sim_engine_run): New file.
948 * m16.igen: All instructions except LB.
949 (LB): Call do_load_byte.
950 * mips.igen (do_load_byte): New function.
951 (LB): Call do_load_byte.
953 * mips.igen: Move spec for insn bit size and high bit from here.
954 * Makefile.in (tmp-igen, tmp-m16): To here.
956 * m16.dc: New file, decode mips16 instructions.
958 * Makefile.in (SIM_NO_ALL): Define.
959 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
961 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
963 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
964 point unit to 32 bit registers.
965 * configure: Re-generate.
967 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
969 * configure.in (sim_use_gen): Make IGEN the default simulator
970 generator for generic 32 and 64 bit mips targets.
971 * configure: Re-generate.
973 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
975 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
978 * interp.c (sim_fetch_register, sim_store_register): Read/write
979 FGR from correct location.
980 (sim_open): Set size of FGR's according to
981 WITH_TARGET_FLOATING_POINT_BITSIZE.
983 * sim-main.h (FGR): Store floating point registers in a separate
986 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
988 * configure: Regenerated to track ../common/aclocal.m4 changes.
990 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
992 * interp.c (ColdReset): Call PENDING_INVALIDATE.
994 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
996 * interp.c (pending_tick): New function. Deliver pending writes.
998 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
999 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1000 it can handle mixed sized quantites and single bits.
1002 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1004 * interp.c (oengine.h): Do not include when building with IGEN.
1005 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1006 (sim_info): Ditto for PROCESSOR_64BIT.
1007 (sim_monitor): Replace ut_reg with unsigned_word.
1008 (*): Ditto for t_reg.
1009 (LOADDRMASK): Define.
1010 (sim_open): Remove defunct check that host FP is IEEE compliant,
1011 using software to emulate floating point.
1012 (value_fpr, ...): Always compile, was conditional on HASFPU.
1014 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1019 * interp.c (SD, CPU): Define.
1020 (mips_option_handler): Set flags in each CPU.
1021 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1022 (sim_close): Do not clear STATE, deleted anyway.
1023 (sim_write, sim_read): Assume CPU zero's vm should be used for
1025 (sim_create_inferior): Set the PC for all processors.
1026 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1028 (mips16_entry): Pass correct nr of args to store_word, load_word.
1029 (ColdReset): Cold reset all cpu's.
1030 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1031 (sim_monitor, load_memory, store_memory, signal_exception): Use
1032 `CPU' instead of STATE_CPU.
1035 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1038 * sim-main.h (signal_exception): Add sim_cpu arg.
1039 (SignalException*): Pass both SD and CPU to signal_exception.
1040 * interp.c (signal_exception): Update.
1042 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1044 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1045 address_translation): Ditto
1046 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1048 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1050 * configure: Regenerated to track ../common/aclocal.m4 changes.
1052 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1054 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1056 * mips.igen (model): Map processor names onto BFD name.
1058 * sim-main.h (CPU_CIA): Delete.
1059 (SET_CIA, GET_CIA): Define
1061 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1063 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1066 * configure.in (default_endian): Configure a big-endian simulator
1068 * configure: Re-generate.
1070 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1072 * configure: Regenerated to track ../common/aclocal.m4 changes.
1074 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1076 * interp.c (sim_monitor): Handle Densan monitor outbyte
1077 and inbyte functions.
1079 1997-12-29 Felix Lee <flee@cygnus.com>
1081 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1083 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1085 * Makefile.in (tmp-igen): Arrange for $zero to always be
1086 reset to zero after every instruction.
1088 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1090 * configure: Regenerated to track ../common/aclocal.m4 changes.
1093 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1095 * mips.igen (MSUB): Fix to work like MADD.
1096 * gencode.c (MSUB): Similarly.
1098 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1100 * configure: Regenerated to track ../common/aclocal.m4 changes.
1102 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1104 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1106 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1108 * sim-main.h (sim-fpu.h): Include.
1110 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1111 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1112 using host independant sim_fpu module.
1114 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1116 * interp.c (signal_exception): Report internal errors with SIGABRT
1119 * sim-main.h (C0_CONFIG): New register.
1120 (signal.h): No longer include.
1122 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1124 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1126 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1128 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1130 * mips.igen: Tag vr5000 instructions.
1131 (ANDI): Was missing mipsIV model, fix assembler syntax.
1132 (do_c_cond_fmt): New function.
1133 (C.cond.fmt): Handle mips I-III which do not support CC field
1135 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1136 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1138 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1139 vr5000 which saves LO in a GPR separatly.
1141 * configure.in (enable-sim-igen): For vr5000, select vr5000
1142 specific instructions.
1143 * configure: Re-generate.
1145 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1149 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1150 fmt_uninterpreted_64 bit cases to switch. Convert to
1153 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1155 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1156 as specified in IV3.2 spec.
1157 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1159 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1161 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1162 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1163 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1164 PENDING_FILL versions of instructions. Simplify.
1166 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1168 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1170 (MTHI, MFHI): Disable code checking HI-LO.
1172 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1174 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1176 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1178 * gencode.c (build_mips16_operands): Replace IPC with cia.
1180 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1181 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1183 (UndefinedResult): Replace function with macro/function
1185 (sim_engine_run): Don't save PC in IPC.
1187 * sim-main.h (IPC): Delete.
1190 * interp.c (signal_exception, store_word, load_word,
1191 address_translation, load_memory, store_memory, cache_op,
1192 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1193 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1194 current instruction address - cia - argument.
1195 (sim_read, sim_write): Call address_translation directly.
1196 (sim_engine_run): Rename variable vaddr to cia.
1197 (signal_exception): Pass cia to sim_monitor
1199 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1200 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1201 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1203 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1204 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1207 * interp.c (signal_exception): Pass restart address to
1210 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1211 idecode.o): Add dependency.
1213 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1215 (DELAY_SLOT): Update NIA not PC with branch address.
1216 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1218 * mips.igen: Use CIA not PC in branch calculations.
1219 (illegal): Call SignalException.
1220 (BEQ, ADDIU): Fix assembler.
1222 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224 * m16.igen (JALX): Was missing.
1226 * configure.in (enable-sim-igen): New configuration option.
1227 * configure: Re-generate.
1229 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1231 * interp.c (load_memory, store_memory): Delete parameter RAW.
1232 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1233 bypassing {load,store}_memory.
1235 * sim-main.h (ByteSwapMem): Delete definition.
1237 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1239 * interp.c (sim_do_command, sim_commands): Delete mips specific
1240 commands. Handled by module sim-options.
1242 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1243 (WITH_MODULO_MEMORY): Define.
1245 * interp.c (sim_info): Delete code printing memory size.
1247 * interp.c (mips_size): Nee sim_size, delete function.
1249 (monitor, monitor_base, monitor_size): Delete global variables.
1250 (sim_open, sim_close): Delete code creating monitor and other
1251 memory regions. Use sim-memopts module, via sim_do_commandf, to
1252 manage memory regions.
1253 (load_memory, store_memory): Use sim-core for memory model.
1255 * interp.c (address_translation): Delete all memory map code
1256 except line forcing 32 bit addresses.
1258 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1260 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1263 * interp.c (logfh, logfile): Delete globals.
1264 (sim_open, sim_close): Delete code opening & closing log file.
1265 (mips_option_handler): Delete -l and -n options.
1266 (OPTION mips_options): Ditto.
1268 * interp.c (OPTION mips_options): Rename option trace to dinero.
1269 (mips_option_handler): Update.
1271 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1273 * interp.c (fetch_str): New function.
1274 (sim_monitor): Rewrite using sim_read & sim_write.
1275 (sim_open): Check magic number.
1276 (sim_open): Write monitor vectors into memory using sim_write.
1277 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1278 (sim_read, sim_write): Simplify - transfer data one byte at a
1280 (load_memory, store_memory): Clarify meaning of parameter RAW.
1282 * sim-main.h (isHOST): Defete definition.
1283 (isTARGET): Mark as depreciated.
1284 (address_translation): Delete parameter HOST.
1286 * interp.c (address_translation): Delete parameter HOST.
1288 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1292 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1293 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1295 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * mips.igen: Add model filter field to records.
1299 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1301 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1303 interp.c (sim_engine_run): Do not compile function sim_engine_run
1304 when WITH_IGEN == 1.
1306 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1307 target architecture.
1309 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1310 igen. Replace with configuration variables sim_igen_flags /
1313 * m16.igen: New file. Copy mips16 insns here.
1314 * mips.igen: From here.
1316 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1318 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1320 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1322 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1324 * gencode.c (build_instruction): Follow sim_write's lead in using
1325 BigEndianMem instead of !ByteSwapMem.
1327 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329 * configure.in (sim_gen): Dependent on target, select type of
1330 generator. Always select old style generator.
1332 configure: Re-generate.
1334 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1336 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1337 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1338 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1339 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1340 SIM_@sim_gen@_*, set by autoconf.
1342 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1344 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1346 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1347 CURRENT_FLOATING_POINT instead.
1349 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1350 (address_translation): Raise exception InstructionFetch when
1351 translation fails and isINSTRUCTION.
1353 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1354 sim_engine_run): Change type of of vaddr and paddr to
1356 (address_translation, prefetch, load_memory, store_memory,
1357 cache_op): Change type of vAddr and pAddr to address_word.
1359 * gencode.c (build_instruction): Change type of vaddr and paddr to
1362 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1364 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1365 macro to obtain result of ALU op.
1367 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1369 * interp.c (sim_info): Call profile_print.
1371 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1373 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1375 * sim-main.h (WITH_PROFILE): Do not define, defined in
1376 common/sim-config.h. Use sim-profile module.
1377 (simPROFILE): Delete defintion.
1379 * interp.c (PROFILE): Delete definition.
1380 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1381 (sim_close): Delete code writing profile histogram.
1382 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1384 (sim_engine_run): Delete code profiling the PC.
1386 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1388 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1390 * interp.c (sim_monitor): Make register pointers of type
1393 * sim-main.h: Make registers of type unsigned_word not
1396 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398 * interp.c (sync_operation): Rename from SyncOperation, make
1399 global, add SD argument.
1400 (prefetch): Rename from Prefetch, make global, add SD argument.
1401 (decode_coproc): Make global.
1403 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1405 * gencode.c (build_instruction): Generate DecodeCoproc not
1406 decode_coproc calls.
1408 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1409 (SizeFGR): Move to sim-main.h
1410 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1411 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1412 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1414 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1415 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1416 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1417 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1418 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1419 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1421 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1423 (sim-alu.h): Include.
1424 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1425 (sim_cia): Typedef to instruction_address.
1427 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429 * Makefile.in (interp.o): Rename generated file engine.c to
1434 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1436 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1438 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1440 * gencode.c (build_instruction): For "FPSQRT", output correct
1441 number of arguments to Recip.
1443 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1445 * Makefile.in (interp.o): Depends on sim-main.h
1447 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1449 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1450 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1451 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1452 STATE, DSSTATE): Define
1453 (GPR, FGRIDX, ..): Define.
1455 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1456 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1457 (GPR, FGRIDX, ...): Delete macros.
1459 * interp.c: Update names to match defines from sim-main.h
1461 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463 * interp.c (sim_monitor): Add SD argument.
1464 (sim_warning): Delete. Replace calls with calls to
1466 (sim_error): Delete. Replace calls with sim_io_error.
1467 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1468 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1469 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1471 (mips_size): Rename from sim_size. Add SD argument.
1473 * interp.c (simulator): Delete global variable.
1474 (callback): Delete global variable.
1475 (mips_option_handler, sim_open, sim_write, sim_read,
1476 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1477 sim_size,sim_monitor): Use sim_io_* not callback->*.
1478 (sim_open): ZALLOC simulator struct.
1479 (PROFILE): Do not define.
1481 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1484 support.h with corresponding code.
1486 * sim-main.h (word64, uword64), support.h: Move definition to
1488 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1491 * Makefile.in: Update dependencies
1492 * interp.c: Do not include.
1494 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1496 * interp.c (address_translation, load_memory, store_memory,
1497 cache_op): Rename to from AddressTranslation et.al., make global,
1500 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1503 * interp.c (SignalException): Rename to signal_exception, make
1506 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1508 * sim-main.h (SignalException, SignalExceptionInterrupt,
1509 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1510 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1511 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1514 * interp.c, support.h: Use.
1516 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1519 to value_fpr / store_fpr. Add SD argument.
1520 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1521 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1523 * sim-main.h (ValueFPR, StoreFPR): Define.
1525 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527 * interp.c (sim_engine_run): Check consistency between configure
1528 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1531 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1532 (mips_fpu): Configure WITH_FLOATING_POINT.
1533 (mips_endian): Configure WITH_TARGET_ENDIAN.
1534 * configure: Update.
1536 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1538 * configure: Regenerated to track ../common/aclocal.m4 changes.
1540 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1542 * configure: Regenerated.
1544 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1546 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1548 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1550 * gencode.c (print_igen_insn_models): Assume certain architectures
1551 include all mips* instructions.
1552 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1555 * Makefile.in (tmp.igen): Add target. Generate igen input from
1558 * gencode.c (FEATURE_IGEN): Define.
1559 (main): Add --igen option. Generate output in igen format.
1560 (process_instructions): Format output according to igen option.
1561 (print_igen_insn_format): New function.
1562 (print_igen_insn_models): New function.
1563 (process_instructions): Only issue warnings and ignore
1564 instructions when no FEATURE_IGEN.
1566 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1571 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * configure: Regenerated to track ../common/aclocal.m4 changes.
1575 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1578 SIM_RESERVED_BITS): Delete, moved to common.
1579 (SIM_EXTRA_CFLAGS): Update.
1581 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583 * configure.in: Configure non-strict memory alignment.
1584 * configure: Regenerated to track ../common/aclocal.m4 changes.
1586 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588 * configure: Regenerated to track ../common/aclocal.m4 changes.
1590 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1592 * gencode.c (SDBBP,DERET): Added (3900) insns.
1593 (RFE): Turn on for 3900.
1594 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1595 (dsstate): Made global.
1596 (SUBTARGET_R3900): Added.
1597 (CANCELDELAYSLOT): New.
1598 (SignalException): Ignore SystemCall rather than ignore and
1599 terminate. Add DebugBreakPoint handling.
1600 (decode_coproc): New insns RFE, DERET; and new registers Debug
1601 and DEPC protected by SUBTARGET_R3900.
1602 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1604 * Makefile.in,configure.in: Add mips subtarget option.
1605 * configure: Update.
1607 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1609 * gencode.c: Add r3900 (tx39).
1612 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1614 * gencode.c (build_instruction): Don't need to subtract 4 for
1617 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1619 * interp.c: Correct some HASFPU problems.
1621 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623 * configure: Regenerated to track ../common/aclocal.m4 changes.
1625 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627 * interp.c (mips_options): Fix samples option short form, should
1630 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632 * interp.c (sim_info): Enable info code. Was just returning.
1634 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1639 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1643 (build_instruction): Ditto for LL.
1645 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1647 * configure: Regenerated to track ../common/aclocal.m4 changes.
1649 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651 * configure: Regenerated to track ../common/aclocal.m4 changes.
1654 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1656 * interp.c (sim_open): Add call to sim_analyze_program, update
1659 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661 * interp.c (sim_kill): Delete.
1662 (sim_create_inferior): Add ABFD argument. Set PC from same.
1663 (sim_load): Move code initializing trap handlers from here.
1664 (sim_open): To here.
1665 (sim_load): Delete, use sim-hload.c.
1667 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1669 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1671 * configure: Regenerated to track ../common/aclocal.m4 changes.
1674 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676 * interp.c (sim_open): Add ABFD argument.
1677 (sim_load): Move call to sim_config from here.
1678 (sim_open): To here. Check return status.
1680 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1682 * gencode.c (build_instruction): Two arg MADD should
1683 not assign result to $0.
1685 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1687 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1688 * sim/mips/configure.in: Regenerate.
1690 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1692 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1693 signed8, unsigned8 et.al. types.
1695 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1696 hosts when selecting subreg.
1698 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1700 * interp.c (sim_engine_run): Reset the ZERO register to zero
1701 regardless of FEATURE_WARN_ZERO.
1702 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1704 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1707 (SignalException): For BreakPoints ignore any mode bits and just
1709 (SignalException): Always set the CAUSE register.
1711 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1713 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1714 exception has been taken.
1716 * interp.c: Implement the ERET and mt/f sr instructions.
1718 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720 * interp.c (SignalException): Don't bother restarting an
1723 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1725 * interp.c (SignalException): Really take an interrupt.
1726 (interrupt_event): Only deliver interrupts when enabled.
1728 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * interp.c (sim_info): Only print info when verbose.
1731 (sim_info) Use sim_io_printf for output.
1733 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1738 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740 * interp.c (sim_do_command): Check for common commands if a
1741 simulator specific command fails.
1743 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1745 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1746 and simBE when DEBUG is defined.
1748 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750 * interp.c (interrupt_event): New function. Pass exception event
1751 onto exception handler.
1753 * configure.in: Check for stdlib.h.
1754 * configure: Regenerate.
1756 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1757 variable declaration.
1758 (build_instruction): Initialize memval1.
1759 (build_instruction): Add UNUSED attribute to byte, bigend,
1761 (build_operands): Ditto.
1763 * interp.c: Fix GCC warnings.
1764 (sim_get_quit_code): Delete.
1766 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1767 * Makefile.in: Ditto.
1768 * configure: Re-generate.
1770 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1772 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1774 * interp.c (mips_option_handler): New function parse argumes using
1776 (myname): Replace with STATE_MY_NAME.
1777 (sim_open): Delete check for host endianness - performed by
1779 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1780 (sim_open): Move much of the initialization from here.
1781 (sim_load): To here. After the image has been loaded and
1783 (sim_open): Move ColdReset from here.
1784 (sim_create_inferior): To here.
1785 (sim_open): Make FP check less dependant on host endianness.
1787 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1789 * interp.c (sim_set_callbacks): Delete.
1791 * interp.c (membank, membank_base, membank_size): Replace with
1792 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1793 (sim_open): Remove call to callback->init. gdb/run do this.
1797 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1799 * interp.c (big_endian_p): Delete, replaced by
1800 current_target_byte_order.
1802 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804 * interp.c (host_read_long, host_read_word, host_swap_word,
1805 host_swap_long): Delete. Using common sim-endian.
1806 (sim_fetch_register, sim_store_register): Use H2T.
1807 (pipeline_ticks): Delete. Handled by sim-events.
1809 (sim_engine_run): Update.
1811 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1813 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1815 (SignalException): To here. Signal using sim_engine_halt.
1816 (sim_stop_reason): Delete, moved to common.
1818 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1820 * interp.c (sim_open): Add callback argument.
1821 (sim_set_callbacks): Delete SIM_DESC argument.
1824 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1826 * Makefile.in (SIM_OBJS): Add common modules.
1828 * interp.c (sim_set_callbacks): Also set SD callback.
1829 (set_endianness, xfer_*, swap_*): Delete.
1830 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1831 Change to functions using sim-endian macros.
1832 (control_c, sim_stop): Delete, use common version.
1833 (simulate): Convert into.
1834 (sim_engine_run): This function.
1835 (sim_resume): Delete.
1837 * interp.c (simulation): New variable - the simulator object.
1838 (sim_kind): Delete global - merged into simulation.
1839 (sim_load): Cleanup. Move PC assignment from here.
1840 (sim_create_inferior): To here.
1842 * sim-main.h: New file.
1843 * interp.c (sim-main.h): Include.
1845 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1847 * configure: Regenerated to track ../common/aclocal.m4 changes.
1849 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1851 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1853 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1855 * gencode.c (build_instruction): DIV instructions: check
1856 for division by zero and integer overflow before using
1857 host's division operation.
1859 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1861 * Makefile.in (SIM_OBJS): Add sim-load.o.
1862 * interp.c: #include bfd.h.
1863 (target_byte_order): Delete.
1864 (sim_kind, myname, big_endian_p): New static locals.
1865 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1866 after argument parsing. Recognize -E arg, set endianness accordingly.
1867 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1868 load file into simulator. Set PC from bfd.
1869 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1870 (set_endianness): Use big_endian_p instead of target_byte_order.
1872 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874 * interp.c (sim_size): Delete prototype - conflicts with
1875 definition in remote-sim.h. Correct definition.
1877 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1879 * configure: Regenerated to track ../common/aclocal.m4 changes.
1882 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1884 * interp.c (sim_open): New arg `kind'.
1886 * configure: Regenerated to track ../common/aclocal.m4 changes.
1888 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1890 * configure: Regenerated to track ../common/aclocal.m4 changes.
1892 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1894 * interp.c (sim_open): Set optind to 0 before calling getopt.
1896 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1898 * configure: Regenerated to track ../common/aclocal.m4 changes.
1900 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1902 * interp.c : Replace uses of pr_addr with pr_uword64
1903 where the bit length is always 64 independent of SIM_ADDR.
1904 (pr_uword64) : added.
1906 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1908 * configure: Re-generate.
1910 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1912 * configure: Regenerate to track ../common/aclocal.m4 changes.
1914 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1916 * interp.c (sim_open): New SIM_DESC result. Argument is now
1918 (other sim_*): New SIM_DESC argument.
1920 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1922 * interp.c: Fix printing of addresses for non-64-bit targets.
1923 (pr_addr): Add function to print address based on size.
1925 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1927 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1929 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1931 * gencode.c (build_mips16_operands): Correct computation of base
1932 address for extended PC relative instruction.
1934 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1936 * interp.c (mips16_entry): Add support for floating point cases.
1937 (SignalException): Pass floating point cases to mips16_entry.
1938 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1940 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1942 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1943 and then set the state to fmt_uninterpreted.
1944 (COP_SW): Temporarily set the state to fmt_word while calling
1947 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1949 * gencode.c (build_instruction): The high order may be set in the
1950 comparison flags at any ISA level, not just ISA 4.
1952 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1954 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1955 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1956 * configure.in: sinclude ../common/aclocal.m4.
1957 * configure: Regenerated.
1959 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1961 * configure: Rebuild after change to aclocal.m4.
1963 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1965 * configure configure.in Makefile.in: Update to new configure
1966 scheme which is more compatible with WinGDB builds.
1967 * configure.in: Improve comment on how to run autoconf.
1968 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1969 * Makefile.in: Use autoconf substitution to install common
1972 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1974 * gencode.c (build_instruction): Use BigEndianCPU instead of
1977 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1979 * interp.c (sim_monitor): Make output to stdout visible in
1980 wingdb's I/O log window.
1982 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1984 * support.h: Undo previous change to SIGTRAP
1987 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1989 * interp.c (store_word, load_word): New static functions.
1990 (mips16_entry): New static function.
1991 (SignalException): Look for mips16 entry and exit instructions.
1992 (simulate): Use the correct index when setting fpr_state after
1993 doing a pending move.
1995 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1997 * interp.c: Fix byte-swapping code throughout to work on
1998 both little- and big-endian hosts.
2000 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2002 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2003 with gdb/config/i386/xm-windows.h.
2005 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2007 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2008 that messes up arithmetic shifts.
2010 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2012 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2013 SIGTRAP and SIGQUIT for _WIN32.
2015 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2017 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2018 force a 64 bit multiplication.
2019 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2020 destination register is 0, since that is the default mips16 nop
2023 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2025 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2026 (build_endian_shift): Don't check proc64.
2027 (build_instruction): Always set memval to uword64. Cast op2 to
2028 uword64 when shifting it left in memory instructions. Always use
2029 the same code for stores--don't special case proc64.
2031 * gencode.c (build_mips16_operands): Fix base PC value for PC
2033 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2035 * interp.c (simJALDELAYSLOT): Define.
2036 (JALDELAYSLOT): Define.
2037 (INDELAYSLOT, INJALDELAYSLOT): Define.
2038 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2040 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2042 * interp.c (sim_open): add flush_cache as a PMON routine
2043 (sim_monitor): handle flush_cache by ignoring it
2045 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2047 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2049 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2050 (BigEndianMem): Rename to ByteSwapMem and change sense.
2051 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2052 BigEndianMem references to !ByteSwapMem.
2053 (set_endianness): New function, with prototype.
2054 (sim_open): Call set_endianness.
2055 (sim_info): Use simBE instead of BigEndianMem.
2056 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2057 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2058 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2059 ifdefs, keeping the prototype declaration.
2060 (swap_word): Rewrite correctly.
2061 (ColdReset): Delete references to CONFIG. Delete endianness related
2062 code; moved to set_endianness.
2064 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2066 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2067 * interp.c (CHECKHILO): Define away.
2068 (simSIGINT): New macro.
2069 (membank_size): Increase from 1MB to 2MB.
2070 (control_c): New function.
2071 (sim_resume): Rename parameter signal to signal_number. Add local
2072 variable prev. Call signal before and after simulate.
2073 (sim_stop_reason): Add simSIGINT support.
2074 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2076 (sim_warning): Delete call to SignalException. Do call printf_filtered
2078 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2079 a call to sim_warning.
2081 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2083 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2084 16 bit instructions.
2086 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2088 Add support for mips16 (16 bit MIPS implementation):
2089 * gencode.c (inst_type): Add mips16 instruction encoding types.
2090 (GETDATASIZEINSN): Define.
2091 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2092 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2094 (MIPS16_DECODE): New table, for mips16 instructions.
2095 (bitmap_val): New static function.
2096 (struct mips16_op): Define.
2097 (mips16_op_table): New table, for mips16 operands.
2098 (build_mips16_operands): New static function.
2099 (process_instructions): If PC is odd, decode a mips16
2100 instruction. Break out instruction handling into new
2101 build_instruction function.
2102 (build_instruction): New static function, broken out of
2103 process_instructions. Check modifiers rather than flags for SHIFT
2104 bit count and m[ft]{hi,lo} direction.
2105 (usage): Pass program name to fprintf.
2106 (main): Remove unused variable this_option_optind. Change
2107 ``*loptarg++'' to ``loptarg++''.
2108 (my_strtoul): Parenthesize && within ||.
2109 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2110 (simulate): If PC is odd, fetch a 16 bit instruction, and
2111 increment PC by 2 rather than 4.
2112 * configure.in: Add case for mips16*-*-*.
2113 * configure: Rebuild.
2115 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2117 * interp.c: Allow -t to enable tracing in standalone simulator.
2118 Fix garbage output in trace file and error messages.
2120 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2122 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2123 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2124 * configure.in: Simplify using macros in ../common/aclocal.m4.
2125 * configure: Regenerated.
2126 * tconfig.in: New file.
2128 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2130 * interp.c: Fix bugs in 64-bit port.
2131 Use ansi function declarations for msvc compiler.
2132 Initialize and test file pointer in trace code.
2133 Prevent duplicate definition of LAST_EMED_REGNUM.
2135 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2137 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2139 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2141 * interp.c (SignalException): Check for explicit terminating
2143 * gencode.c: Pass instruction value through SignalException()
2144 calls for Trap, Breakpoint and Syscall.
2146 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2148 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2149 only used on those hosts that provide it.
2150 * configure.in: Add sqrt() to list of functions to be checked for.
2151 * config.in: Re-generated.
2152 * configure: Re-generated.
2154 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2156 * gencode.c (process_instructions): Call build_endian_shift when
2157 expanding STORE RIGHT, to fix swr.
2158 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2159 clear the high bits.
2160 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2161 Fix float to int conversions to produce signed values.
2163 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2165 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2166 (process_instructions): Correct handling of nor instruction.
2167 Correct shift count for 32 bit shift instructions. Correct sign
2168 extension for arithmetic shifts to not shift the number of bits in
2169 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2170 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2172 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2173 It's OK to have a mult follow a mult. What's not OK is to have a
2174 mult follow an mfhi.
2175 (Convert): Comment out incorrect rounding code.
2177 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2179 * interp.c (sim_monitor): Improved monitor printf
2180 simulation. Tidied up simulator warnings, and added "--log" option
2181 for directing warning message output.
2182 * gencode.c: Use sim_warning() rather than WARNING macro.
2184 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2186 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2187 getopt1.o, rather than on gencode.c. Link objects together.
2188 Don't link against -liberty.
2189 (gencode.o, getopt.o, getopt1.o): New targets.
2190 * gencode.c: Include <ctype.h> and "ansidecl.h".
2191 (AND): Undefine after including "ansidecl.h".
2192 (ULONG_MAX): Define if not defined.
2193 (OP_*): Don't define macros; now defined in opcode/mips.h.
2194 (main): Call my_strtoul rather than strtoul.
2195 (my_strtoul): New static function.
2197 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2199 * gencode.c (process_instructions): Generate word64 and uword64
2200 instead of `long long' and `unsigned long long' data types.
2201 * interp.c: #include sysdep.h to get signals, and define default
2203 * (Convert): Work around for Visual-C++ compiler bug with type
2205 * support.h: Make things compile under Visual-C++ by using
2206 __int64 instead of `long long'. Change many refs to long long
2207 into word64/uword64 typedefs.
2209 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2211 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2212 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2214 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2215 (AC_PROG_INSTALL): Added.
2216 (AC_PROG_CC): Moved to before configure.host call.
2217 * configure: Rebuilt.
2219 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2221 * configure.in: Define @SIMCONF@ depending on mips target.
2222 * configure: Rebuild.
2223 * Makefile.in (run): Add @SIMCONF@ to control simulator
2225 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2226 * interp.c: Remove some debugging, provide more detailed error
2227 messages, update memory accesses to use LOADDRMASK.
2229 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2231 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2232 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2234 * configure: Rebuild.
2235 * config.in: New file, generated by autoheader.
2236 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2237 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2238 HAVE_ANINT and HAVE_AINT, as appropriate.
2239 * Makefile.in (run): Use @LIBS@ rather than -lm.
2240 (interp.o): Depend upon config.h.
2241 (Makefile): Just rebuild Makefile.
2242 (clean): Remove stamp-h.
2243 (mostlyclean): Make the same as clean, not as distclean.
2244 (config.h, stamp-h): New targets.
2246 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2248 * interp.c (ColdReset): Fix boolean test. Make all simulator
2251 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2253 * interp.c (xfer_direct_word, xfer_direct_long,
2254 swap_direct_word, swap_direct_long, xfer_big_word,
2255 xfer_big_long, xfer_little_word, xfer_little_long,
2256 swap_word,swap_long): Added.
2257 * interp.c (ColdReset): Provide function indirection to
2258 host<->simulated_target transfer routines.
2259 * interp.c (sim_store_register, sim_fetch_register): Updated to
2260 make use of indirected transfer routines.
2262 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2264 * gencode.c (process_instructions): Ensure FP ABS instruction
2266 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2267 system call support.
2269 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2271 * interp.c (sim_do_command): Complain if callback structure not
2274 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2276 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2277 support for Sun hosts.
2278 * Makefile.in (gencode): Ensure the host compiler and libraries
2279 used for cross-hosted build.
2281 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2283 * interp.c, gencode.c: Some more (TODO) tidying.
2285 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2287 * gencode.c, interp.c: Replaced explicit long long references with
2288 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2289 * support.h (SET64LO, SET64HI): Macros added.
2291 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2293 * configure: Regenerate with autoconf 2.7.
2295 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2297 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2298 * support.h: Remove superfluous "1" from #if.
2299 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2301 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2303 * interp.c (StoreFPR): Control UndefinedResult() call on
2304 WARN_RESULT manifest.
2306 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2308 * gencode.c: Tidied instruction decoding, and added FP instruction
2311 * interp.c: Added dineroIII, and BSD profiling support. Also
2312 run-time FP handling.
2314 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2316 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2317 gencode.c, interp.c, support.h: created.