1 2002-02-04 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen: Remove gencode comment from top of file, fix
4 spelling in another comment.
6 2002-02-04 Chris Demetriou <cgd@broadcom.com>
8 * mips.igen (check_fmt, check_fmt_p): New functions to check
9 whether specific floating point formats are usable.
10 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
11 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
12 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
13 Use the new functions.
14 (do_c_cond_fmt): Remove format checks...
15 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
17 2002-02-03 Chris Demetriou <cgd@broadcom.com>
19 * mips.igen: Fix formatting of check_fpu calls.
21 2002-03-03 Chris Demetriou <cgd@broadcom.com>
23 * mips.igen (FLOOR.L.fmt): Store correct destination register.
25 2002-03-03 Chris Demetriou <cgd@broadcom.com>
27 * mips.igen: Remove whitespace at end of lines.
29 2002-03-02 Chris Demetriou <cgd@broadcom.com>
31 * mips.igen (loadstore_ea): New function to do effective
33 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
34 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
35 CACHE): Use loadstore_ea to do effective address computations.
37 2002-03-02 Chris Demetriou <cgd@broadcom.com>
39 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
40 * mips.igen (LL, CxC1, MxC1): Likewise.
42 2002-03-02 Chris Demetriou <cgd@broadcom.com>
44 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
45 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
46 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
47 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
48 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
49 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
50 Don't split opcode fields by hand, use the opcode field values
53 2002-03-01 Chris Demetriou <cgd@broadcom.com>
55 * mips.igen (do_divu): Fix spacing.
57 * mips.igen (do_dsllv): Move to be right before DSLLV,
58 to match the rest of the do_<shift> functions.
60 2002-03-01 Chris Demetriou <cgd@broadcom.com>
62 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
63 DSRL32, do_dsrlv): Trace inputs and results.
65 2002-03-01 Chris Demetriou <cgd@broadcom.com>
67 * mips.igen (CACHE): Provide instruction-printing string.
69 * interp.c (signal_exception): Comment tokens after #endif.
71 2002-02-28 Chris Demetriou <cgd@broadcom.com>
73 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
74 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
75 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
76 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
77 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
78 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
79 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
80 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
82 2002-02-28 Chris Demetriou <cgd@broadcom.com>
84 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
85 instruction-printing string.
86 (LWU): Use '64' as the filter flag.
88 2002-02-28 Chris Demetriou <cgd@broadcom.com>
90 * mips.igen (SDXC1): Fix instruction-printing string.
92 2002-02-28 Chris Demetriou <cgd@broadcom.com>
94 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
97 2002-02-27 Chris Demetriou <cgd@broadcom.com>
99 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
102 2002-02-27 Chris Demetriou <cgd@broadcom.com>
104 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
105 add a comma) so that it more closely match the MIPS ISA
106 documentation opcode partitioning.
107 (PREF): Put useful names on opcode fields, and include
108 instruction-printing string.
110 2002-02-27 Chris Demetriou <cgd@broadcom.com>
112 * mips.igen (check_u64): New function which in the future will
113 check whether 64-bit instructions are usable and signal an
114 exception if not. Currently a no-op.
115 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
116 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
117 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
118 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
120 * mips.igen (check_fpu): New function which in the future will
121 check whether FPU instructions are usable and signal an exception
122 if not. Currently a no-op.
123 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
124 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
125 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
126 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
127 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
128 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
129 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
130 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
132 2002-02-27 Chris Demetriou <cgd@broadcom.com>
134 * mips.igen (do_load_left, do_load_right): Move to be immediately
136 (do_store_left, do_store_right): Move to be immediately following
139 2002-02-27 Chris Demetriou <cgd@broadcom.com>
141 * mips.igen (mipsV): New model name. Also, add it to
142 all instructions and functions where it is appropriate.
144 2002-02-18 Chris Demetriou <cgd@broadcom.com>
146 * mips.igen: For all functions and instructions, list model
147 names that support that instruction one per line.
149 2002-02-11 Chris Demetriou <cgd@broadcom.com>
151 * mips.igen: Add some additional comments about supported
152 models, and about which instructions go where.
153 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
154 order as is used in the rest of the file.
156 2002-02-11 Chris Demetriou <cgd@broadcom.com>
158 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
159 indicating that ALU32_END or ALU64_END are there to check
161 (DADD): Likewise, but also remove previous comment about
164 2002-02-10 Chris Demetriou <cgd@broadcom.com>
166 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
167 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
168 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
169 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
170 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
171 fields (i.e., add and move commas) so that they more closely
172 match the MIPS ISA documentation opcode partitioning.
174 2002-02-10 Chris Demetriou <cgd@broadcom.com>
176 * mips.igen (ADDI): Print immediate value.
178 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
179 (SLL): Print "nop" specially, and don't run the code
180 that does the shift for the "nop" case.
182 2001-11-17 Fred Fish <fnf@redhat.com>
184 * sim-main.h (float_operation): Move enum declaration outside
185 of _sim_cpu struct declaration.
187 2001-04-12 Jim Blandy <jimb@redhat.com>
189 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
190 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
192 * sim-main.h (COCIDX): Remove definition; this isn't supported by
193 PENDING_FILL, and you can get the intended effect gracefully by
194 calling PENDING_SCHED directly.
196 2001-02-23 Ben Elliston <bje@redhat.com>
198 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
199 already defined elsewhere.
201 2001-02-19 Ben Elliston <bje@redhat.com>
203 * sim-main.h (sim_monitor): Return an int.
204 * interp.c (sim_monitor): Add return values.
205 (signal_exception): Handle error conditions from sim_monitor.
207 2001-02-08 Ben Elliston <bje@redhat.com>
209 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
210 (store_memory): Likewise, pass cia to sim_core_write*.
212 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
214 On advice from Chris G. Demetriou <cgd@sibyte.com>:
215 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
217 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
219 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
220 * Makefile.in: Don't delete *.igen when cleaning directory.
222 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
224 * m16.igen (break): Call SignalException not sim_engine_halt.
226 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
229 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
231 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
233 * mips.igen (MxC1, DMxC1): Fix printf formatting.
235 2000-05-24 Michael Hayes <mhayes@cygnus.com>
237 * mips.igen (do_dmultx): Fix typo.
239 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
241 * configure: Regenerated to track ../common/aclocal.m4 changes.
243 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
245 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
247 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
249 * sim-main.h (GPR_CLEAR): Define macro.
251 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
253 * interp.c (decode_coproc): Output long using %lx and not %s.
255 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
257 * interp.c (sim_open): Sort & extend dummy memory regions for
258 --board=jmr3904 for eCos.
260 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
262 * configure: Regenerated.
264 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
266 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
267 calls, conditional on the simulator being in verbose mode.
269 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
271 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
272 cache don't get ReservedInstruction traps.
274 1999-11-29 Mark Salter <msalter@cygnus.com>
276 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
277 to clear status bits in sdisr register. This is how the hardware works.
279 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
280 being used by cygmon.
282 1999-11-11 Andrew Haley <aph@cygnus.com>
284 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
287 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
289 * mips.igen (MULT): Correct previous mis-applied patch.
291 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
293 * mips.igen (delayslot32): Handle sequence like
294 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
295 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
296 (MULT): Actually pass the third register...
298 1999-09-03 Mark Salter <msalter@cygnus.com>
300 * interp.c (sim_open): Added more memory aliases for additional
301 hardware being touched by cygmon on jmr3904 board.
303 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
305 * configure: Regenerated to track ../common/aclocal.m4 changes.
307 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
309 * interp.c (sim_store_register): Handle case where client - GDB -
310 specifies that a 4 byte register is 8 bytes in size.
311 (sim_fetch_register): Ditto.
313 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
315 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
316 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
317 (idt_monitor_base): Base address for IDT monitor traps.
318 (pmon_monitor_base): Ditto for PMON.
319 (lsipmon_monitor_base): Ditto for LSI PMON.
320 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
321 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
322 (sim_firmware_command): New function.
323 (mips_option_handler): Call it for OPTION_FIRMWARE.
324 (sim_open): Allocate memory for idt_monitor region. If "--board"
325 option was given, add no monitor by default. Add BREAK hooks only if
326 monitors are also there.
328 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
330 * interp.c (sim_monitor): Flush output before reading input.
332 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
334 * tconfig.in (SIM_HANDLES_LMA): Always define.
336 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
338 From Mark Salter <msalter@cygnus.com>:
339 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
340 (sim_open): Add setup for BSP board.
342 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
344 * mips.igen (MULT, MULTU): Add syntax for two operand version.
345 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
346 them as unimplemented.
348 1999-05-08 Felix Lee <flee@cygnus.com>
350 * configure: Regenerated to track ../common/aclocal.m4 changes.
352 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
354 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
356 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
358 * configure.in: Any mips64vr5*-*-* target should have
359 -DTARGET_ENABLE_FR=1.
360 (default_endian): Any mips64vr*el-*-* target should default to
362 * configure: Re-generate.
364 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
366 * mips.igen (ldl): Extend from _16_, not 32.
368 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
370 * interp.c (sim_store_register): Force registers written to by GDB
371 into an un-interpreted state.
373 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
375 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
376 CPU, start periodic background I/O polls.
377 (tx3904sio_poll): New function: periodic I/O poller.
379 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
381 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
383 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
385 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
388 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
390 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
391 (load_word): Call SIM_CORE_SIGNAL hook on error.
392 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
393 starting. For exception dispatching, pass PC instead of NULL_CIA.
394 (decode_coproc): Use COP0_BADVADDR to store faulting address.
395 * sim-main.h (COP0_BADVADDR): Define.
396 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
397 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
398 (_sim_cpu): Add exc_* fields to store register value snapshots.
399 * mips.igen (*): Replace memory-related SignalException* calls
400 with references to SIM_CORE_SIGNAL hook.
402 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
404 * sim-main.c (*): Minor warning cleanups.
406 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
408 * m16.igen (DADDIU5): Correct type-o.
410 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
412 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
415 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
417 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
419 (interp.o): Add dependency on itable.h
420 (oengine.c, gencode): Delete remaining references.
421 (BUILT_SRC_FROM_GEN): Clean up.
423 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
426 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
427 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
429 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
430 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
431 Drop the "64" qualifier to get the HACK generator working.
432 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
433 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
434 qualifier to get the hack generator working.
435 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
437 (DSLLV): Use do_dsllv.
440 (DSRLV): Use do_dsrlv.
441 (BC1): Move *vr4100 to get the HACK generator working.
442 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
443 get the HACK generator working.
444 (MACC) Rename to get the HACK generator working.
445 (DMACC,MACCS,DMACCS): Add the 64.
447 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
449 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
450 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
452 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
454 * mips/interp.c (DEBUG): Cleanups.
456 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
458 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
459 (tx3904sio_tickle): fflush after a stdout character output.
461 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
463 * interp.c (sim_close): Uninstall modules.
465 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
467 * sim-main.h, interp.c (sim_monitor): Change to global
470 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
472 * configure.in (vr4100): Only include vr4100 instructions in
474 * configure: Re-generate.
475 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
477 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
479 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
480 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
483 * configure.in (sim_default_gen, sim_use_gen): Replace with
485 (--enable-sim-igen): Delete config option. Always using IGEN.
486 * configure: Re-generate.
488 * Makefile.in (gencode): Kill, kill, kill.
491 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
493 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
494 bit mips16 igen simulator.
495 * configure: Re-generate.
497 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
498 as part of vr4100 ISA.
499 * vr.igen: Mark all instructions as 64 bit only.
501 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
503 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
506 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
508 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
509 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
510 * configure: Re-generate.
512 * m16.igen (BREAK): Define breakpoint instruction.
513 (JALX32): Mark instruction as mips16 and not r3900.
514 * mips.igen (C.cond.fmt): Fix typo in instruction format.
516 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
518 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
520 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
521 insn as a debug breakpoint.
523 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
525 (PENDING_SCHED): Clean up trace statement.
526 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
527 (PENDING_FILL): Delay write by only one cycle.
528 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
530 * sim-main.c (pending_tick): Clean up trace statements. Add trace
532 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
534 (pending_tick): Move incrementing of index to FOR statement.
535 (pending_tick): Only update PENDING_OUT after a write has occured.
537 * configure.in: Add explicit mips-lsi-* target. Use gencode to
539 * configure: Re-generate.
541 * interp.c (sim_engine_run OLD): Delete explicit call to
542 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
544 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
546 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
547 interrupt level number to match changed SignalExceptionInterrupt
550 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
552 * interp.c: #include "itable.h" if WITH_IGEN.
553 (get_insn_name): New function.
554 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
555 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
557 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
559 * configure: Rebuilt to inhale new common/aclocal.m4.
561 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
563 * dv-tx3904sio.c: Include sim-assert.h.
565 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
567 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
568 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
569 Reorganize target-specific sim-hardware checks.
570 * configure: rebuilt.
571 * interp.c (sim_open): For tx39 target boards, set
572 OPERATING_ENVIRONMENT, add tx3904sio devices.
573 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
574 ROM executables. Install dv-sockser into sim-modules list.
576 * dv-tx3904irc.c: Compiler warning clean-up.
577 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
578 frequent hw-trace messages.
580 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
582 * vr.igen (MulAcc): Identify as a vr4100 specific function.
584 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
586 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
589 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
590 * mips.igen: Define vr4100 model. Include vr.igen.
591 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
593 * mips.igen (check_mf_hilo): Correct check.
595 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
597 * sim-main.h (interrupt_event): Add prototype.
599 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
600 register_ptr, register_value.
601 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
603 * sim-main.h (tracefh): Make extern.
605 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
607 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
608 Reduce unnecessarily high timer event frequency.
609 * dv-tx3904cpu.c: Ditto for interrupt event.
611 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
613 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
615 (interrupt_event): Made non-static.
617 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
618 interchange of configuration values for external vs. internal
621 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
623 * mips.igen (BREAK): Moved code to here for
624 simulator-reserved break instructions.
625 * gencode.c (build_instruction): Ditto.
626 * interp.c (signal_exception): Code moved from here. Non-
627 reserved instructions now use exception vector, rather
629 * sim-main.h: Moved magic constants to here.
631 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
633 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
634 register upon non-zero interrupt event level, clear upon zero
636 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
637 by passing zero event value.
638 (*_io_{read,write}_buffer): Endianness fixes.
639 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
640 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
642 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
643 serial I/O and timer module at base address 0xFFFF0000.
645 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
647 * mips.igen (SWC1) : Correct the handling of ReverseEndian
650 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
652 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
656 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
658 * dv-tx3904tmr.c: New file - implements tx3904 timer.
659 * dv-tx3904{irc,cpu}.c: Mild reformatting.
660 * configure.in: Include tx3904tmr in hw_device list.
661 * configure: Rebuilt.
662 * interp.c (sim_open): Instantiate three timer instances.
663 Fix address typo of tx3904irc instance.
665 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
667 * interp.c (signal_exception): SystemCall exception now uses
668 the exception vector.
670 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
672 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
675 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
677 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
679 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
681 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
683 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
684 sim-main.h. Declare a struct hw_descriptor instead of struct
685 hw_device_descriptor.
687 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
689 * mips.igen (do_store_left, do_load_left): Compute nr of left and
690 right bits and then re-align left hand bytes to correct byte
691 lanes. Fix incorrect computation in do_store_left when loading
692 bytes from second word.
694 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
696 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
697 * interp.c (sim_open): Only create a device tree when HW is
700 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
701 * interp.c (signal_exception): Ditto.
703 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
705 * gencode.c: Mark BEGEZALL as LIKELY.
707 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
709 * sim-main.h (ALU32_END): Sign extend 32 bit results.
710 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
712 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
714 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
715 modules. Recognize TX39 target with "mips*tx39" pattern.
716 * configure: Rebuilt.
717 * sim-main.h (*): Added many macros defining bits in
718 TX39 control registers.
719 (SignalInterrupt): Send actual PC instead of NULL.
720 (SignalNMIReset): New exception type.
721 * interp.c (board): New variable for future use to identify
722 a particular board being simulated.
723 (mips_option_handler,mips_options): Added "--board" option.
724 (interrupt_event): Send actual PC.
725 (sim_open): Make memory layout conditional on board setting.
726 (signal_exception): Initial implementation of hardware interrupt
727 handling. Accept another break instruction variant for simulator
729 (decode_coproc): Implement RFE instruction for TX39.
730 (mips.igen): Decode RFE instruction as such.
731 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
732 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
733 bbegin to implement memory map.
734 * dv-tx3904cpu.c: New file.
735 * dv-tx3904irc.c: New file.
737 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
739 * mips.igen (check_mt_hilo): Create a separate r3900 version.
741 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
743 * tx.igen (madd,maddu): Replace calls to check_op_hilo
744 with calls to check_div_hilo.
746 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
748 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
749 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
750 Add special r3900 version of do_mult_hilo.
751 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
752 with calls to check_mult_hilo.
753 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
754 with calls to check_div_hilo.
756 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
758 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
759 Document a replacement.
761 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
763 * interp.c (sim_monitor): Make mon_printf work.
765 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
767 * sim-main.h (INSN_NAME): New arg `cpu'.
769 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
771 * configure: Regenerated to track ../common/aclocal.m4 changes.
773 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
775 * configure: Regenerated to track ../common/aclocal.m4 changes.
778 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
780 * acconfig.h: New file.
781 * configure.in: Reverted change of Apr 24; use sinclude again.
783 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
785 * configure: Regenerated to track ../common/aclocal.m4 changes.
788 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
790 * configure.in: Don't call sinclude.
792 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
794 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
796 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
798 * mips.igen (ERET): Implement.
800 * interp.c (decode_coproc): Return sign-extended EPC.
802 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
804 * interp.c (signal_exception): Do not ignore Trap.
805 (signal_exception): On TRAP, restart at exception address.
806 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
807 (signal_exception): Update.
808 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
809 so that TRAP instructions are caught.
811 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
813 * sim-main.h (struct hilo_access, struct hilo_history): Define,
814 contains HI/LO access history.
815 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
816 (HIACCESS, LOACCESS): Delete, replace with
817 (HIHISTORY, LOHISTORY): New macros.
818 (CHECKHILO): Delete all, moved to mips.igen
820 * gencode.c (build_instruction): Do not generate checks for
821 correct HI/LO register usage.
823 * interp.c (old_engine_run): Delete checks for correct HI/LO
826 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
827 check_mf_cycles): New functions.
828 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
829 do_divu, domultx, do_mult, do_multu): Use.
831 * tx.igen ("madd", "maddu"): Use.
833 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
835 * mips.igen (DSRAV): Use function do_dsrav.
836 (SRAV): Use new function do_srav.
838 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
839 (B): Sign extend 11 bit immediate.
840 (EXT-B*): Shift 16 bit immediate left by 1.
841 (ADDIU*): Don't sign extend immediate value.
843 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
845 * m16run.c (sim_engine_run): Restore CIA after handling an event.
847 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
850 * mips.igen (delayslot32, nullify_next_insn): New functions.
851 (m16.igen): Always include.
852 (do_*): Add more tracing.
854 * m16.igen (delayslot16): Add NIA argument, could be called by a
855 32 bit MIPS16 instruction.
857 * interp.c (ifetch16): Move function from here.
858 * sim-main.c (ifetch16): To here.
860 * sim-main.c (ifetch16, ifetch32): Update to match current
861 implementations of LH, LW.
862 (signal_exception): Don't print out incorrect hex value of illegal
865 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
867 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
870 * m16.igen: Implement MIPS16 instructions.
872 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
873 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
874 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
875 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
876 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
877 bodies of corresponding code from 32 bit insn to these. Also used
878 by MIPS16 versions of functions.
880 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
881 (IMEM16): Drop NR argument from macro.
883 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
885 * Makefile.in (SIM_OBJS): Add sim-main.o.
887 * sim-main.h (address_translation, load_memory, store_memory,
888 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
890 (pr_addr, pr_uword64): Declare.
891 (sim-main.c): Include when H_REVEALS_MODULE_P.
893 * interp.c (address_translation, load_memory, store_memory,
894 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
896 * sim-main.c: To here. Fix compilation problems.
898 * configure.in: Enable inlining.
899 * configure: Re-config.
901 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
903 * configure: Regenerated to track ../common/aclocal.m4 changes.
905 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
907 * mips.igen: Include tx.igen.
908 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
909 * tx.igen: New file, contains MADD and MADDU.
911 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
912 the hardwired constant `7'.
913 (store_memory): Ditto.
914 (LOADDRMASK): Move definition to sim-main.h.
916 mips.igen (MTC0): Enable for r3900.
919 mips.igen (do_load_byte): Delete.
920 (do_load, do_store, do_load_left, do_load_write, do_store_left,
921 do_store_right): New functions.
922 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
924 configure.in: Let the tx39 use igen again.
927 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
929 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
930 not an address sized quantity. Return zero for cache sizes.
932 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
934 * mips.igen (r3900): r3900 does not support 64 bit integer
937 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
939 * configure.in (mipstx39*-*-*): Use gencode simulator rather
941 * configure : Rebuild.
943 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
945 * configure: Regenerated to track ../common/aclocal.m4 changes.
947 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
949 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
951 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
953 * configure: Regenerated to track ../common/aclocal.m4 changes.
954 * config.in: Regenerated to track ../common/aclocal.m4 changes.
956 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
958 * configure: Regenerated to track ../common/aclocal.m4 changes.
960 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
962 * interp.c (Max, Min): Comment out functions. Not yet used.
964 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
966 * configure: Regenerated to track ../common/aclocal.m4 changes.
968 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
970 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
971 configurable settings for stand-alone simulator.
973 * configure.in: Added X11 search, just in case.
975 * configure: Regenerated.
977 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
979 * interp.c (sim_write, sim_read, load_memory, store_memory):
980 Replace sim_core_*_map with read_map, write_map, exec_map resp.
982 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
984 * sim-main.h (GETFCC): Return an unsigned value.
986 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
988 * mips.igen (DIV): Fix check for -1 / MIN_INT.
989 (DADD): Result destination is RD not RT.
991 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
993 * sim-main.h (HIACCESS, LOACCESS): Always define.
995 * mdmx.igen (Maxi, Mini): Rename Max, Min.
997 * interp.c (sim_info): Delete.
999 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1001 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1002 (mips_option_handler): New argument `cpu'.
1003 (sim_open): Update call to sim_add_option_table.
1005 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1007 * mips.igen (CxC1): Add tracing.
1009 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011 * sim-main.h (Max, Min): Declare.
1013 * interp.c (Max, Min): New functions.
1015 * mips.igen (BC1): Add tracing.
1017 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1019 * interp.c Added memory map for stack in vr4100
1021 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1023 * interp.c (load_memory): Add missing "break"'s.
1025 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1027 * interp.c (sim_store_register, sim_fetch_register): Pass in
1028 length parameter. Return -1.
1030 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1032 * interp.c: Added hardware init hook, fixed warnings.
1034 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1036 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1038 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1040 * interp.c (ifetch16): New function.
1042 * sim-main.h (IMEM32): Rename IMEM.
1043 (IMEM16_IMMED): Define.
1045 (DELAY_SLOT): Update.
1047 * m16run.c (sim_engine_run): New file.
1049 * m16.igen: All instructions except LB.
1050 (LB): Call do_load_byte.
1051 * mips.igen (do_load_byte): New function.
1052 (LB): Call do_load_byte.
1054 * mips.igen: Move spec for insn bit size and high bit from here.
1055 * Makefile.in (tmp-igen, tmp-m16): To here.
1057 * m16.dc: New file, decode mips16 instructions.
1059 * Makefile.in (SIM_NO_ALL): Define.
1060 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1062 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1065 point unit to 32 bit registers.
1066 * configure: Re-generate.
1068 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070 * configure.in (sim_use_gen): Make IGEN the default simulator
1071 generator for generic 32 and 64 bit mips targets.
1072 * configure: Re-generate.
1074 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1076 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1079 * interp.c (sim_fetch_register, sim_store_register): Read/write
1080 FGR from correct location.
1081 (sim_open): Set size of FGR's according to
1082 WITH_TARGET_FLOATING_POINT_BITSIZE.
1084 * sim-main.h (FGR): Store floating point registers in a separate
1087 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1089 * configure: Regenerated to track ../common/aclocal.m4 changes.
1091 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1093 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1095 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1097 * interp.c (pending_tick): New function. Deliver pending writes.
1099 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1100 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1101 it can handle mixed sized quantites and single bits.
1103 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105 * interp.c (oengine.h): Do not include when building with IGEN.
1106 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1107 (sim_info): Ditto for PROCESSOR_64BIT.
1108 (sim_monitor): Replace ut_reg with unsigned_word.
1109 (*): Ditto for t_reg.
1110 (LOADDRMASK): Define.
1111 (sim_open): Remove defunct check that host FP is IEEE compliant,
1112 using software to emulate floating point.
1113 (value_fpr, ...): Always compile, was conditional on HASFPU.
1115 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1120 * interp.c (SD, CPU): Define.
1121 (mips_option_handler): Set flags in each CPU.
1122 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1123 (sim_close): Do not clear STATE, deleted anyway.
1124 (sim_write, sim_read): Assume CPU zero's vm should be used for
1126 (sim_create_inferior): Set the PC for all processors.
1127 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1129 (mips16_entry): Pass correct nr of args to store_word, load_word.
1130 (ColdReset): Cold reset all cpu's.
1131 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1132 (sim_monitor, load_memory, store_memory, signal_exception): Use
1133 `CPU' instead of STATE_CPU.
1136 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1139 * sim-main.h (signal_exception): Add sim_cpu arg.
1140 (SignalException*): Pass both SD and CPU to signal_exception.
1141 * interp.c (signal_exception): Update.
1143 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1145 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1146 address_translation): Ditto
1147 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1149 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1151 * configure: Regenerated to track ../common/aclocal.m4 changes.
1153 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1157 * mips.igen (model): Map processor names onto BFD name.
1159 * sim-main.h (CPU_CIA): Delete.
1160 (SET_CIA, GET_CIA): Define
1162 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1164 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1167 * configure.in (default_endian): Configure a big-endian simulator
1169 * configure: Re-generate.
1171 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1173 * configure: Regenerated to track ../common/aclocal.m4 changes.
1175 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1177 * interp.c (sim_monitor): Handle Densan monitor outbyte
1178 and inbyte functions.
1180 1997-12-29 Felix Lee <flee@cygnus.com>
1182 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1184 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1186 * Makefile.in (tmp-igen): Arrange for $zero to always be
1187 reset to zero after every instruction.
1189 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1191 * configure: Regenerated to track ../common/aclocal.m4 changes.
1194 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1196 * mips.igen (MSUB): Fix to work like MADD.
1197 * gencode.c (MSUB): Similarly.
1199 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1201 * configure: Regenerated to track ../common/aclocal.m4 changes.
1203 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1207 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1209 * sim-main.h (sim-fpu.h): Include.
1211 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1212 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1213 using host independant sim_fpu module.
1215 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1217 * interp.c (signal_exception): Report internal errors with SIGABRT
1220 * sim-main.h (C0_CONFIG): New register.
1221 (signal.h): No longer include.
1223 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1225 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1227 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1229 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1231 * mips.igen: Tag vr5000 instructions.
1232 (ANDI): Was missing mipsIV model, fix assembler syntax.
1233 (do_c_cond_fmt): New function.
1234 (C.cond.fmt): Handle mips I-III which do not support CC field
1236 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1237 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1239 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1240 vr5000 which saves LO in a GPR separatly.
1242 * configure.in (enable-sim-igen): For vr5000, select vr5000
1243 specific instructions.
1244 * configure: Re-generate.
1246 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1248 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1250 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1251 fmt_uninterpreted_64 bit cases to switch. Convert to
1254 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1256 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1257 as specified in IV3.2 spec.
1258 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1260 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1262 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1263 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1264 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1265 PENDING_FILL versions of instructions. Simplify.
1267 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1269 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1271 (MTHI, MFHI): Disable code checking HI-LO.
1273 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1275 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1277 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1279 * gencode.c (build_mips16_operands): Replace IPC with cia.
1281 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1282 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1284 (UndefinedResult): Replace function with macro/function
1286 (sim_engine_run): Don't save PC in IPC.
1288 * sim-main.h (IPC): Delete.
1291 * interp.c (signal_exception, store_word, load_word,
1292 address_translation, load_memory, store_memory, cache_op,
1293 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1294 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1295 current instruction address - cia - argument.
1296 (sim_read, sim_write): Call address_translation directly.
1297 (sim_engine_run): Rename variable vaddr to cia.
1298 (signal_exception): Pass cia to sim_monitor
1300 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1301 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1302 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1304 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1305 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1308 * interp.c (signal_exception): Pass restart address to
1311 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1312 idecode.o): Add dependency.
1314 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1316 (DELAY_SLOT): Update NIA not PC with branch address.
1317 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1319 * mips.igen: Use CIA not PC in branch calculations.
1320 (illegal): Call SignalException.
1321 (BEQ, ADDIU): Fix assembler.
1323 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1325 * m16.igen (JALX): Was missing.
1327 * configure.in (enable-sim-igen): New configuration option.
1328 * configure: Re-generate.
1330 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1332 * interp.c (load_memory, store_memory): Delete parameter RAW.
1333 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1334 bypassing {load,store}_memory.
1336 * sim-main.h (ByteSwapMem): Delete definition.
1338 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1340 * interp.c (sim_do_command, sim_commands): Delete mips specific
1341 commands. Handled by module sim-options.
1343 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1344 (WITH_MODULO_MEMORY): Define.
1346 * interp.c (sim_info): Delete code printing memory size.
1348 * interp.c (mips_size): Nee sim_size, delete function.
1350 (monitor, monitor_base, monitor_size): Delete global variables.
1351 (sim_open, sim_close): Delete code creating monitor and other
1352 memory regions. Use sim-memopts module, via sim_do_commandf, to
1353 manage memory regions.
1354 (load_memory, store_memory): Use sim-core for memory model.
1356 * interp.c (address_translation): Delete all memory map code
1357 except line forcing 32 bit addresses.
1359 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1361 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1364 * interp.c (logfh, logfile): Delete globals.
1365 (sim_open, sim_close): Delete code opening & closing log file.
1366 (mips_option_handler): Delete -l and -n options.
1367 (OPTION mips_options): Ditto.
1369 * interp.c (OPTION mips_options): Rename option trace to dinero.
1370 (mips_option_handler): Update.
1372 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374 * interp.c (fetch_str): New function.
1375 (sim_monitor): Rewrite using sim_read & sim_write.
1376 (sim_open): Check magic number.
1377 (sim_open): Write monitor vectors into memory using sim_write.
1378 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1379 (sim_read, sim_write): Simplify - transfer data one byte at a
1381 (load_memory, store_memory): Clarify meaning of parameter RAW.
1383 * sim-main.h (isHOST): Defete definition.
1384 (isTARGET): Mark as depreciated.
1385 (address_translation): Delete parameter HOST.
1387 * interp.c (address_translation): Delete parameter HOST.
1389 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1393 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1394 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1396 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398 * mips.igen: Add model filter field to records.
1400 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1404 interp.c (sim_engine_run): Do not compile function sim_engine_run
1405 when WITH_IGEN == 1.
1407 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1408 target architecture.
1410 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1411 igen. Replace with configuration variables sim_igen_flags /
1414 * m16.igen: New file. Copy mips16 insns here.
1415 * mips.igen: From here.
1417 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1419 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1421 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1423 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1425 * gencode.c (build_instruction): Follow sim_write's lead in using
1426 BigEndianMem instead of !ByteSwapMem.
1428 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430 * configure.in (sim_gen): Dependent on target, select type of
1431 generator. Always select old style generator.
1433 configure: Re-generate.
1435 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1437 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1438 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1439 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1440 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1441 SIM_@sim_gen@_*, set by autoconf.
1443 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1445 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1447 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1448 CURRENT_FLOATING_POINT instead.
1450 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1451 (address_translation): Raise exception InstructionFetch when
1452 translation fails and isINSTRUCTION.
1454 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1455 sim_engine_run): Change type of of vaddr and paddr to
1457 (address_translation, prefetch, load_memory, store_memory,
1458 cache_op): Change type of vAddr and pAddr to address_word.
1460 * gencode.c (build_instruction): Change type of vaddr and paddr to
1463 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1466 macro to obtain result of ALU op.
1468 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1470 * interp.c (sim_info): Call profile_print.
1472 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1474 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1476 * sim-main.h (WITH_PROFILE): Do not define, defined in
1477 common/sim-config.h. Use sim-profile module.
1478 (simPROFILE): Delete defintion.
1480 * interp.c (PROFILE): Delete definition.
1481 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1482 (sim_close): Delete code writing profile histogram.
1483 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1485 (sim_engine_run): Delete code profiling the PC.
1487 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1491 * interp.c (sim_monitor): Make register pointers of type
1494 * sim-main.h: Make registers of type unsigned_word not
1497 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499 * interp.c (sync_operation): Rename from SyncOperation, make
1500 global, add SD argument.
1501 (prefetch): Rename from Prefetch, make global, add SD argument.
1502 (decode_coproc): Make global.
1504 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1506 * gencode.c (build_instruction): Generate DecodeCoproc not
1507 decode_coproc calls.
1509 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1510 (SizeFGR): Move to sim-main.h
1511 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1512 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1513 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1515 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1516 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1517 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1518 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1519 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1520 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1522 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1524 (sim-alu.h): Include.
1525 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1526 (sim_cia): Typedef to instruction_address.
1528 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * Makefile.in (interp.o): Rename generated file engine.c to
1535 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1539 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1541 * gencode.c (build_instruction): For "FPSQRT", output correct
1542 number of arguments to Recip.
1544 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1546 * Makefile.in (interp.o): Depends on sim-main.h
1548 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1550 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1551 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1552 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1553 STATE, DSSTATE): Define
1554 (GPR, FGRIDX, ..): Define.
1556 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1557 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1558 (GPR, FGRIDX, ...): Delete macros.
1560 * interp.c: Update names to match defines from sim-main.h
1562 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564 * interp.c (sim_monitor): Add SD argument.
1565 (sim_warning): Delete. Replace calls with calls to
1567 (sim_error): Delete. Replace calls with sim_io_error.
1568 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1569 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1570 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1572 (mips_size): Rename from sim_size. Add SD argument.
1574 * interp.c (simulator): Delete global variable.
1575 (callback): Delete global variable.
1576 (mips_option_handler, sim_open, sim_write, sim_read,
1577 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1578 sim_size,sim_monitor): Use sim_io_* not callback->*.
1579 (sim_open): ZALLOC simulator struct.
1580 (PROFILE): Do not define.
1582 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1584 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1585 support.h with corresponding code.
1587 * sim-main.h (word64, uword64), support.h: Move definition to
1589 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1592 * Makefile.in: Update dependencies
1593 * interp.c: Do not include.
1595 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597 * interp.c (address_translation, load_memory, store_memory,
1598 cache_op): Rename to from AddressTranslation et.al., make global,
1601 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1604 * interp.c (SignalException): Rename to signal_exception, make
1607 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1609 * sim-main.h (SignalException, SignalExceptionInterrupt,
1610 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1611 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1612 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1615 * interp.c, support.h: Use.
1617 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1620 to value_fpr / store_fpr. Add SD argument.
1621 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1622 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1624 * sim-main.h (ValueFPR, StoreFPR): Define.
1626 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628 * interp.c (sim_engine_run): Check consistency between configure
1629 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1632 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1633 (mips_fpu): Configure WITH_FLOATING_POINT.
1634 (mips_endian): Configure WITH_TARGET_ENDIAN.
1635 * configure: Update.
1637 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1639 * configure: Regenerated to track ../common/aclocal.m4 changes.
1641 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1643 * configure: Regenerated.
1645 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1647 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1649 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651 * gencode.c (print_igen_insn_models): Assume certain architectures
1652 include all mips* instructions.
1653 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1656 * Makefile.in (tmp.igen): Add target. Generate igen input from
1659 * gencode.c (FEATURE_IGEN): Define.
1660 (main): Add --igen option. Generate output in igen format.
1661 (process_instructions): Format output according to igen option.
1662 (print_igen_insn_format): New function.
1663 (print_igen_insn_models): New function.
1664 (process_instructions): Only issue warnings and ignore
1665 instructions when no FEATURE_IGEN.
1667 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1669 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1672 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1674 * configure: Regenerated to track ../common/aclocal.m4 changes.
1676 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1678 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1679 SIM_RESERVED_BITS): Delete, moved to common.
1680 (SIM_EXTRA_CFLAGS): Update.
1682 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1684 * configure.in: Configure non-strict memory alignment.
1685 * configure: Regenerated to track ../common/aclocal.m4 changes.
1687 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1689 * configure: Regenerated to track ../common/aclocal.m4 changes.
1691 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1693 * gencode.c (SDBBP,DERET): Added (3900) insns.
1694 (RFE): Turn on for 3900.
1695 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1696 (dsstate): Made global.
1697 (SUBTARGET_R3900): Added.
1698 (CANCELDELAYSLOT): New.
1699 (SignalException): Ignore SystemCall rather than ignore and
1700 terminate. Add DebugBreakPoint handling.
1701 (decode_coproc): New insns RFE, DERET; and new registers Debug
1702 and DEPC protected by SUBTARGET_R3900.
1703 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1705 * Makefile.in,configure.in: Add mips subtarget option.
1706 * configure: Update.
1708 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1710 * gencode.c: Add r3900 (tx39).
1713 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1715 * gencode.c (build_instruction): Don't need to subtract 4 for
1718 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1720 * interp.c: Correct some HASFPU problems.
1722 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1724 * configure: Regenerated to track ../common/aclocal.m4 changes.
1726 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1728 * interp.c (mips_options): Fix samples option short form, should
1731 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1733 * interp.c (sim_info): Enable info code. Was just returning.
1735 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1740 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1744 (build_instruction): Ditto for LL.
1746 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1748 * configure: Regenerated to track ../common/aclocal.m4 changes.
1750 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752 * configure: Regenerated to track ../common/aclocal.m4 changes.
1755 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757 * interp.c (sim_open): Add call to sim_analyze_program, update
1760 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1762 * interp.c (sim_kill): Delete.
1763 (sim_create_inferior): Add ABFD argument. Set PC from same.
1764 (sim_load): Move code initializing trap handlers from here.
1765 (sim_open): To here.
1766 (sim_load): Delete, use sim-hload.c.
1768 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1770 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772 * configure: Regenerated to track ../common/aclocal.m4 changes.
1775 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1777 * interp.c (sim_open): Add ABFD argument.
1778 (sim_load): Move call to sim_config from here.
1779 (sim_open): To here. Check return status.
1781 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1783 * gencode.c (build_instruction): Two arg MADD should
1784 not assign result to $0.
1786 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1788 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1789 * sim/mips/configure.in: Regenerate.
1791 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1793 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1794 signed8, unsigned8 et.al. types.
1796 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1797 hosts when selecting subreg.
1799 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1801 * interp.c (sim_engine_run): Reset the ZERO register to zero
1802 regardless of FEATURE_WARN_ZERO.
1803 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1805 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1807 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1808 (SignalException): For BreakPoints ignore any mode bits and just
1810 (SignalException): Always set the CAUSE register.
1812 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1815 exception has been taken.
1817 * interp.c: Implement the ERET and mt/f sr instructions.
1819 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1821 * interp.c (SignalException): Don't bother restarting an
1824 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1826 * interp.c (SignalException): Really take an interrupt.
1827 (interrupt_event): Only deliver interrupts when enabled.
1829 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1831 * interp.c (sim_info): Only print info when verbose.
1832 (sim_info) Use sim_io_printf for output.
1834 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1839 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1841 * interp.c (sim_do_command): Check for common commands if a
1842 simulator specific command fails.
1844 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1846 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1847 and simBE when DEBUG is defined.
1849 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1851 * interp.c (interrupt_event): New function. Pass exception event
1852 onto exception handler.
1854 * configure.in: Check for stdlib.h.
1855 * configure: Regenerate.
1857 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1858 variable declaration.
1859 (build_instruction): Initialize memval1.
1860 (build_instruction): Add UNUSED attribute to byte, bigend,
1862 (build_operands): Ditto.
1864 * interp.c: Fix GCC warnings.
1865 (sim_get_quit_code): Delete.
1867 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1868 * Makefile.in: Ditto.
1869 * configure: Re-generate.
1871 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1873 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * interp.c (mips_option_handler): New function parse argumes using
1877 (myname): Replace with STATE_MY_NAME.
1878 (sim_open): Delete check for host endianness - performed by
1880 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1881 (sim_open): Move much of the initialization from here.
1882 (sim_load): To here. After the image has been loaded and
1884 (sim_open): Move ColdReset from here.
1885 (sim_create_inferior): To here.
1886 (sim_open): Make FP check less dependant on host endianness.
1888 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1890 * interp.c (sim_set_callbacks): Delete.
1892 * interp.c (membank, membank_base, membank_size): Replace with
1893 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1894 (sim_open): Remove call to callback->init. gdb/run do this.
1898 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1900 * interp.c (big_endian_p): Delete, replaced by
1901 current_target_byte_order.
1903 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1905 * interp.c (host_read_long, host_read_word, host_swap_word,
1906 host_swap_long): Delete. Using common sim-endian.
1907 (sim_fetch_register, sim_store_register): Use H2T.
1908 (pipeline_ticks): Delete. Handled by sim-events.
1910 (sim_engine_run): Update.
1912 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1914 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1916 (SignalException): To here. Signal using sim_engine_halt.
1917 (sim_stop_reason): Delete, moved to common.
1919 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1921 * interp.c (sim_open): Add callback argument.
1922 (sim_set_callbacks): Delete SIM_DESC argument.
1925 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * Makefile.in (SIM_OBJS): Add common modules.
1929 * interp.c (sim_set_callbacks): Also set SD callback.
1930 (set_endianness, xfer_*, swap_*): Delete.
1931 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1932 Change to functions using sim-endian macros.
1933 (control_c, sim_stop): Delete, use common version.
1934 (simulate): Convert into.
1935 (sim_engine_run): This function.
1936 (sim_resume): Delete.
1938 * interp.c (simulation): New variable - the simulator object.
1939 (sim_kind): Delete global - merged into simulation.
1940 (sim_load): Cleanup. Move PC assignment from here.
1941 (sim_create_inferior): To here.
1943 * sim-main.h: New file.
1944 * interp.c (sim-main.h): Include.
1946 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1948 * configure: Regenerated to track ../common/aclocal.m4 changes.
1950 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1952 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1954 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1956 * gencode.c (build_instruction): DIV instructions: check
1957 for division by zero and integer overflow before using
1958 host's division operation.
1960 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1962 * Makefile.in (SIM_OBJS): Add sim-load.o.
1963 * interp.c: #include bfd.h.
1964 (target_byte_order): Delete.
1965 (sim_kind, myname, big_endian_p): New static locals.
1966 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1967 after argument parsing. Recognize -E arg, set endianness accordingly.
1968 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1969 load file into simulator. Set PC from bfd.
1970 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1971 (set_endianness): Use big_endian_p instead of target_byte_order.
1973 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * interp.c (sim_size): Delete prototype - conflicts with
1976 definition in remote-sim.h. Correct definition.
1978 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1980 * configure: Regenerated to track ../common/aclocal.m4 changes.
1983 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1985 * interp.c (sim_open): New arg `kind'.
1987 * configure: Regenerated to track ../common/aclocal.m4 changes.
1989 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1991 * configure: Regenerated to track ../common/aclocal.m4 changes.
1993 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1995 * interp.c (sim_open): Set optind to 0 before calling getopt.
1997 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1999 * configure: Regenerated to track ../common/aclocal.m4 changes.
2001 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2003 * interp.c : Replace uses of pr_addr with pr_uword64
2004 where the bit length is always 64 independent of SIM_ADDR.
2005 (pr_uword64) : added.
2007 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2009 * configure: Re-generate.
2011 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2013 * configure: Regenerate to track ../common/aclocal.m4 changes.
2015 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2017 * interp.c (sim_open): New SIM_DESC result. Argument is now
2019 (other sim_*): New SIM_DESC argument.
2021 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2023 * interp.c: Fix printing of addresses for non-64-bit targets.
2024 (pr_addr): Add function to print address based on size.
2026 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2028 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2030 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2032 * gencode.c (build_mips16_operands): Correct computation of base
2033 address for extended PC relative instruction.
2035 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2037 * interp.c (mips16_entry): Add support for floating point cases.
2038 (SignalException): Pass floating point cases to mips16_entry.
2039 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2041 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2043 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2044 and then set the state to fmt_uninterpreted.
2045 (COP_SW): Temporarily set the state to fmt_word while calling
2048 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2050 * gencode.c (build_instruction): The high order may be set in the
2051 comparison flags at any ISA level, not just ISA 4.
2053 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2055 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2056 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2057 * configure.in: sinclude ../common/aclocal.m4.
2058 * configure: Regenerated.
2060 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2062 * configure: Rebuild after change to aclocal.m4.
2064 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2066 * configure configure.in Makefile.in: Update to new configure
2067 scheme which is more compatible with WinGDB builds.
2068 * configure.in: Improve comment on how to run autoconf.
2069 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2070 * Makefile.in: Use autoconf substitution to install common
2073 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2075 * gencode.c (build_instruction): Use BigEndianCPU instead of
2078 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2080 * interp.c (sim_monitor): Make output to stdout visible in
2081 wingdb's I/O log window.
2083 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2085 * support.h: Undo previous change to SIGTRAP
2088 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2090 * interp.c (store_word, load_word): New static functions.
2091 (mips16_entry): New static function.
2092 (SignalException): Look for mips16 entry and exit instructions.
2093 (simulate): Use the correct index when setting fpr_state after
2094 doing a pending move.
2096 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2098 * interp.c: Fix byte-swapping code throughout to work on
2099 both little- and big-endian hosts.
2101 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2103 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2104 with gdb/config/i386/xm-windows.h.
2106 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2108 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2109 that messes up arithmetic shifts.
2111 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2113 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2114 SIGTRAP and SIGQUIT for _WIN32.
2116 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2118 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2119 force a 64 bit multiplication.
2120 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2121 destination register is 0, since that is the default mips16 nop
2124 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2126 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2127 (build_endian_shift): Don't check proc64.
2128 (build_instruction): Always set memval to uword64. Cast op2 to
2129 uword64 when shifting it left in memory instructions. Always use
2130 the same code for stores--don't special case proc64.
2132 * gencode.c (build_mips16_operands): Fix base PC value for PC
2134 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2136 * interp.c (simJALDELAYSLOT): Define.
2137 (JALDELAYSLOT): Define.
2138 (INDELAYSLOT, INJALDELAYSLOT): Define.
2139 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2141 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2143 * interp.c (sim_open): add flush_cache as a PMON routine
2144 (sim_monitor): handle flush_cache by ignoring it
2146 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2148 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2150 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2151 (BigEndianMem): Rename to ByteSwapMem and change sense.
2152 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2153 BigEndianMem references to !ByteSwapMem.
2154 (set_endianness): New function, with prototype.
2155 (sim_open): Call set_endianness.
2156 (sim_info): Use simBE instead of BigEndianMem.
2157 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2158 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2159 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2160 ifdefs, keeping the prototype declaration.
2161 (swap_word): Rewrite correctly.
2162 (ColdReset): Delete references to CONFIG. Delete endianness related
2163 code; moved to set_endianness.
2165 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2167 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2168 * interp.c (CHECKHILO): Define away.
2169 (simSIGINT): New macro.
2170 (membank_size): Increase from 1MB to 2MB.
2171 (control_c): New function.
2172 (sim_resume): Rename parameter signal to signal_number. Add local
2173 variable prev. Call signal before and after simulate.
2174 (sim_stop_reason): Add simSIGINT support.
2175 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2177 (sim_warning): Delete call to SignalException. Do call printf_filtered
2179 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2180 a call to sim_warning.
2182 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2184 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2185 16 bit instructions.
2187 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2189 Add support for mips16 (16 bit MIPS implementation):
2190 * gencode.c (inst_type): Add mips16 instruction encoding types.
2191 (GETDATASIZEINSN): Define.
2192 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2193 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2195 (MIPS16_DECODE): New table, for mips16 instructions.
2196 (bitmap_val): New static function.
2197 (struct mips16_op): Define.
2198 (mips16_op_table): New table, for mips16 operands.
2199 (build_mips16_operands): New static function.
2200 (process_instructions): If PC is odd, decode a mips16
2201 instruction. Break out instruction handling into new
2202 build_instruction function.
2203 (build_instruction): New static function, broken out of
2204 process_instructions. Check modifiers rather than flags for SHIFT
2205 bit count and m[ft]{hi,lo} direction.
2206 (usage): Pass program name to fprintf.
2207 (main): Remove unused variable this_option_optind. Change
2208 ``*loptarg++'' to ``loptarg++''.
2209 (my_strtoul): Parenthesize && within ||.
2210 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2211 (simulate): If PC is odd, fetch a 16 bit instruction, and
2212 increment PC by 2 rather than 4.
2213 * configure.in: Add case for mips16*-*-*.
2214 * configure: Rebuild.
2216 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2218 * interp.c: Allow -t to enable tracing in standalone simulator.
2219 Fix garbage output in trace file and error messages.
2221 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2223 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2224 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2225 * configure.in: Simplify using macros in ../common/aclocal.m4.
2226 * configure: Regenerated.
2227 * tconfig.in: New file.
2229 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2231 * interp.c: Fix bugs in 64-bit port.
2232 Use ansi function declarations for msvc compiler.
2233 Initialize and test file pointer in trace code.
2234 Prevent duplicate definition of LAST_EMED_REGNUM.
2236 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2238 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2240 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2242 * interp.c (SignalException): Check for explicit terminating
2244 * gencode.c: Pass instruction value through SignalException()
2245 calls for Trap, Breakpoint and Syscall.
2247 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2249 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2250 only used on those hosts that provide it.
2251 * configure.in: Add sqrt() to list of functions to be checked for.
2252 * config.in: Re-generated.
2253 * configure: Re-generated.
2255 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2257 * gencode.c (process_instructions): Call build_endian_shift when
2258 expanding STORE RIGHT, to fix swr.
2259 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2260 clear the high bits.
2261 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2262 Fix float to int conversions to produce signed values.
2264 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2266 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2267 (process_instructions): Correct handling of nor instruction.
2268 Correct shift count for 32 bit shift instructions. Correct sign
2269 extension for arithmetic shifts to not shift the number of bits in
2270 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2271 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2273 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2274 It's OK to have a mult follow a mult. What's not OK is to have a
2275 mult follow an mfhi.
2276 (Convert): Comment out incorrect rounding code.
2278 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2280 * interp.c (sim_monitor): Improved monitor printf
2281 simulation. Tidied up simulator warnings, and added "--log" option
2282 for directing warning message output.
2283 * gencode.c: Use sim_warning() rather than WARNING macro.
2285 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2287 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2288 getopt1.o, rather than on gencode.c. Link objects together.
2289 Don't link against -liberty.
2290 (gencode.o, getopt.o, getopt1.o): New targets.
2291 * gencode.c: Include <ctype.h> and "ansidecl.h".
2292 (AND): Undefine after including "ansidecl.h".
2293 (ULONG_MAX): Define if not defined.
2294 (OP_*): Don't define macros; now defined in opcode/mips.h.
2295 (main): Call my_strtoul rather than strtoul.
2296 (my_strtoul): New static function.
2298 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2300 * gencode.c (process_instructions): Generate word64 and uword64
2301 instead of `long long' and `unsigned long long' data types.
2302 * interp.c: #include sysdep.h to get signals, and define default
2304 * (Convert): Work around for Visual-C++ compiler bug with type
2306 * support.h: Make things compile under Visual-C++ by using
2307 __int64 instead of `long long'. Change many refs to long long
2308 into word64/uword64 typedefs.
2310 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2312 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2313 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2315 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2316 (AC_PROG_INSTALL): Added.
2317 (AC_PROG_CC): Moved to before configure.host call.
2318 * configure: Rebuilt.
2320 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2322 * configure.in: Define @SIMCONF@ depending on mips target.
2323 * configure: Rebuild.
2324 * Makefile.in (run): Add @SIMCONF@ to control simulator
2326 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2327 * interp.c: Remove some debugging, provide more detailed error
2328 messages, update memory accesses to use LOADDRMASK.
2330 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2332 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2333 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2335 * configure: Rebuild.
2336 * config.in: New file, generated by autoheader.
2337 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2338 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2339 HAVE_ANINT and HAVE_AINT, as appropriate.
2340 * Makefile.in (run): Use @LIBS@ rather than -lm.
2341 (interp.o): Depend upon config.h.
2342 (Makefile): Just rebuild Makefile.
2343 (clean): Remove stamp-h.
2344 (mostlyclean): Make the same as clean, not as distclean.
2345 (config.h, stamp-h): New targets.
2347 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2349 * interp.c (ColdReset): Fix boolean test. Make all simulator
2352 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2354 * interp.c (xfer_direct_word, xfer_direct_long,
2355 swap_direct_word, swap_direct_long, xfer_big_word,
2356 xfer_big_long, xfer_little_word, xfer_little_long,
2357 swap_word,swap_long): Added.
2358 * interp.c (ColdReset): Provide function indirection to
2359 host<->simulated_target transfer routines.
2360 * interp.c (sim_store_register, sim_fetch_register): Updated to
2361 make use of indirected transfer routines.
2363 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2365 * gencode.c (process_instructions): Ensure FP ABS instruction
2367 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2368 system call support.
2370 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2372 * interp.c (sim_do_command): Complain if callback structure not
2375 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2377 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2378 support for Sun hosts.
2379 * Makefile.in (gencode): Ensure the host compiler and libraries
2380 used for cross-hosted build.
2382 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2384 * interp.c, gencode.c: Some more (TODO) tidying.
2386 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2388 * gencode.c, interp.c: Replaced explicit long long references with
2389 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2390 * support.h (SET64LO, SET64HI): Macros added.
2392 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2394 * configure: Regenerate with autoconf 2.7.
2396 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2398 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2399 * support.h: Remove superfluous "1" from #if.
2400 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2402 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2404 * interp.c (StoreFPR): Control UndefinedResult() call on
2405 WARN_RESULT manifest.
2407 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2409 * gencode.c: Tidied instruction decoding, and added FP instruction
2412 * interp.c: Added dineroIII, and BSD profiling support. Also
2413 run-time FP handling.
2415 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2417 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2418 gencode.c, interp.c, support.h: created.