sim/mips/ChangeLog

   1 start-sanitize-vr4xxx
   2 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
   3
   4         * vr4run.c: New.
   5         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
   6         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
   7         tmp-run-hack) : New.
   8         * configure.in (mips64vr4xxx): Switch to using the HACK
   9         generator.  Set TARGET_ENABLE_FR.
  10         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
  11         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
  12         Drop the "64" qualifier to get the HACK generator working.
  13         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
  14         Add vr4121 where necessary.
  15         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
  16         qualifier to get the hack generator working.
  17         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
  18         (DSLL): Use do_dsll.
  19         (DSLLV): Use do_dsllv.
  20         (DSRA): Use do_dsra.
  21         (DSRL): Use do_dsrl.
  22         (DSRLV): Use do_dsrlv.
  23         (BC1): Move *vr4100,*vr4111, and *vr4121 to get the HACK
  24         generator working.
  25         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
  26         get the HACK generator working.
  27         * vr.igen: Add *vr4320 where missing.
  28         (MACC) Rename to get the HACK generator working.
  29         (DMACC,MACCS,DMACCS): Add the 64.
  30
  31 start-sanitize-vr4320
  32 1998-12-14  Gavin Romig-Koch  <gavin@cygnus.com>
  33
  34         * vr.igen (Low32Bits): Add vr4320.
  35
  36 end-sanitize-vr4320
  37 1998-12-14  Gavin Romig-Koch  <gavin@cygnus.com>
  38
  39         * configure.in: Add support for 5xxx and "el".
  40         * configure: Rebuild.
  41
  42 start-sanitize-vr4xxx
  43 1998-12-13  Gavin Romig-Koch  <gavin@cygnus.com>
  44
  45         * configure.in,mips.igen,vr.igen: Add vr4121.
  46         * configure: Rebuilt.
  47
  48 end-sanitize-vr4xxx
  49 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
  50
  51 start-sanitize-vr4xxx
  52         * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.
  53         Set mips_fpu, and mips_fpu_bitsize.
  54         Set sim_gen, and sim_igen_machine.
  55         * configure: Rebuild.
  56
  57 end-sanitize-vr4xxx
  58         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
  59         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
  60
  61 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
  62
  63     * mips/interp.c (DEBUG): Cleanups.
  64
  65 start-sanitize-tx3904
  66 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
  67
  68         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
  69         (tx3904sio_tickle): fflush after a stdout character output.
  70
  71 end-sanitize-tx3904
  72 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
  73
  74         * interp.c (sim_close): Uninstall modules.
  75
  76 start-sanitize-sky
  77 Tue Dec  1 18:40:30 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  78
  79         * sky-libvpe.c (FCmp): Abort when no result.
  80
  81 end-sanitize-sky
  82 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  83
  84         * sim-main.h, interp.c (sim_monitor): Change to global
  85         function.
  86
  87 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  88
  89         * configure.in (vr4100): Only include vr4100 instructions in
  90         simulator.
  91         * configure: Re-generate.
  92         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
  93
  94 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  95
  96         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
  97         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
  98         true alternative.
  99
 100         * configure.in (sim_default_gen, sim_use_gen): Replace with
 101         sim_gen.
 102         (--enable-sim-igen): Delete config option. Always using IGEN.
 103         * configure: Re-generate.
 104
 105         * Makefile.in (gencode): Kill, kill, kill.
 106         * gencode.c: Ditto.
 107
 108 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 109
 110         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 111         bit mips16 igen simulator.
 112         * configure: Re-generate.
 113
 114         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 115         as part of vr4100 ISA.
 116         * vr.igen: Mark all instructions as 64 bit only.
 117
 118 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 119
 120         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 121         Pacify GCC.
 122
 123 start-sanitize-tx19
 124 Mon Nov 23 16:51:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 125
 126         * configure.in (tx19): Reconize target mips-tx19-elf.
 127         * configure: Re-generate.
 128
 129 end-sanitize-tx19
 130 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 131
 132         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 133         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 134         * configure: Re-generate.
 135
 136         * m16.igen (BREAK): Define breakpoint instruction.
 137         (JALX32): Mark instruction as mips16 and not r3900.
 138         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 139
 140         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 141
 142 start-sanitize-r5900
 143 Mon Nov 16 11:44:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 144
 145         * r5900.igen (CVT.W.S): Always round towards zero.
 146
 147 end-sanitize-r5900
 148 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 149
 150         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 151         insn as a debug breakpoint.
 152
 153         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 154         pending.slot_size.
 155         (PENDING_SCHED): Clean up trace statement.
 156         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 157         (PENDING_FILL): Delay write by only one cycle.
 158         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 159
 160         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 161         of pending writes.
 162         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 163         32 & 64.
 164         (pending_tick): Move incrementing of index to FOR statement.
 165         (pending_tick): Only update PENDING_OUT after a write has occured.
 166
 167         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 168         build simulator.
 169         * configure: Re-generate.
 170
 171         * interp.c (sim_engine_run OLD): Delete explicit call to
 172         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 173
 174 start-sanitize-r5900
 175 Wed Nov 11 16:53:57 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 176
 177         * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0.
 178
 179 Thu Nov  5 10:29:42 EST 1998  Frank Ch. Eigler  <fche@cygnus.com>
 180
 181         * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
 182
 183 Thu Nov  5 19:40:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 184
 185         * r5900.igen (DIV): Do not clear clear SO/SU when already set.
 186
 187         * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T
 188         negative, compute S/sqrt(abs(T)) instead.  Correctly set FCSR
 189         bits.
 190
 191         * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check
 192         sign of FT not FS.
 193         (r59fp_store): Clarify "bad value" abort messages.
 194
 195 end-sanitize-r5900
 196 start-sanitize-tx3904
 197 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 198
 199         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 200         interrupt level number to match changed SignalExceptionInterrupt
 201         macro.
 202
 203 end-sanitize-tx3904
 204 start-sanitize-sky
 205 Thu Oct 29 12:47:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 206
 207         * sim-main.c (tlb_try_match): Include physical address in
 208         scratchpad non-mapping warning.
 209
 210 end-sanitize-sky
 211 start-sanitize-r5900
 212 Thu Oct 29 11:06:30 EST 1998  Frank Ch. Eigler <fche@cygnus.com>
 213
 214         * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
 215         as per customer patch.
 216
 217 end-sanitize-r5900
 218 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 219
 220         * interp.c: #include "itable.h" if WITH_IGEN.
 221         (get_insn_name): New function.
 222         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 223         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 224
 225 start-sanitize-sky
 226 Tue Sep 22 10:35:37 1998  Frank Ch. Eigler  <fche@cygnus.com>
 227
 228         * sim-main.c (tlb_try_match): Specially match virtual
 229         pages mapped to scratchpad RAM, an unimplemented feature.
 230
 231 end-sanitize-sky
 232 start-sanitize-r5900
 233 Fri Sep 18 11:31:16 1998  Frank Ch. Eigler <fche@cygnus.com>
 234
 235         * r5900.igen (prot3w): Correct rotation sequence; patch
 236         from customer.
 237
 238 end-sanitize-r5900
 239 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 240
 241         * configure: Rebuilt to inhale new common/aclocal.m4.
 242
 243 start-sanitize-r5900
 244 Thu Sep 10 11:50:54 1998  Doug Evans  <devans@canuck.cygnus.com>
 245
 246         * r5900.igen (plzcw): Make `i' signed.
 247
 248 Wed Sep  9 15:02:10 1998  Doug Evans  <devans@canuck.cygnus.com>
 249
 250         * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
 251         * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
 252         interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
 253         * interp.c (signal_exception, sky version): Handle INT 2.
 254
 255 Wed Sep 9 11:28:20 1998  Ron Unrau <runrau@cygnus.com>
 256
 257         * sim-main.h: track COP0 registers
 258         * interp.c (sim_{fetch,store}_register): read/write COP0 registers
 259
 260 Fri Sep  4 10:37:57 1998  Frank Ch. Eigler  <fche@cygnus.com>
 261
 262         * r5900.igen (mtsab): Correct typo in input register.
 263
 264         * sim-main.h (TMP_*): New macros for accessing local 128-bit
 265         temporary for multimedia instructions.
 266         * r5900.igen (*): Convert most instructions to use new TMP
 267         macros to store output result during computation.
 268
 269 end-sanitize-r5900
 270 start-sanitize-tx3904
 271 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 272
 273         * dv-tx3904sio.c: Include sim-assert.h.
 274
 275 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 276
 277         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 278         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 279         Reorganize target-specific sim-hardware checks.
 280         * configure: rebuilt.
 281         * interp.c (sim_open): For tx39 target boards, set
 282         OPERATING_ENVIRONMENT, add tx3904sio devices.
 283         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 284         ROM executables.  Install dv-sockser into sim-modules list.
 285
 286         * dv-tx3904irc.c: Compiler warning clean-up.
 287         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 288         frequent hw-trace messages.
 289
 290 end-sanitize-tx3904
 291 start-sanitize-sky
 292 Tue Aug 11 13:52:16 1998  Frank Ch. Eigler  <fche@cygnus.com>
 293
 294         * interp.c (signal_exception): Set IP3 bit in CAUSE on
 295         sky interrupt.
 296
 297 end-sanitize-sky
 298 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 299
 300         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 301
 302 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 303
 304         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 305
 306         * vr.igen: New file.
 307         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 308         * mips.igen: Define vr4100 model. Include vr.igen.
 309 start-sanitize-cygnus
 310         * vr5400.igen: Move instructions to vr.igen
 311         * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
 312 end-sanitize-cygnus
 313 start-sanitize-vr4320
 314         * vr4320.igen: Move instructions to vr.igen.
 315         * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
 316
 317 end-sanitize-vr4320
 318 start-sanitize-sky
 319 Fri Jul 24 16:01:03 1998  Ian Carmichael  <iancarm@cygnus.com>
 320
 321         * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
 322         * mips.igen (BREAK): Fix 0xffff2 monitor call.  Slightly less
 323         confusing message if not enough --load-next options appear.
 324
 325         * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
 326         * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
 327         * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
 328         (resume_handler): Same.
 329         (suspend_handler): Same.
 330
 331 Wed Jul 22 13:04:13 1998  Frank Ch. Eigler  <fche@cygnus.com>
 332
 333         * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
 334         to trigger multi-phase load.
 335
 336         * sim-main.c: Include sim-assert.h for ASSERT macro.
 337         * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
 338         "break 0xffff2".
 339
 340 Tue Jul 21 18:37:36 1998  Ian Carmichael  <iancarm@cygnus.com>
 341
 342         MMU support.
 343         * interp.c (sim_open): Initialize TLB.
 344         * interp.c (signal_exceptions): New 5900 handling.
 345         * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
 346         * sim-main.c (tlb_try_match, tlb_lookup): New functions.
 347         (address_translation): Use the TLB.
 348         * sim-main.h (r4000_tlb_entry_t): New type.
 349         (TLB_*): New constants.
 350         (COP0_*): New register names.
 351
 352         Sky character I/O device.
 353         * sky-psio.c: New file.
 354         * sky-psio.h: New file.
 355         * Makefile.in: Add sky-psio.o.
 356
 357 end-sanitize-sky
 358 start-sanitize-r5900
 359 Tue Jul 14 16:10:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 360
 361         * r5900.igen (r59fp_overflow): Replace argument ANS with argument
 362         SIGN_P.
 363         (r59fp_zero): Ditto.
 364         (r59fp_store): Update calls.
 365         (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
 366
 367 end-sanitize-r5900
 368 start-sanitize-branchbug4011
 369 Mon Jun 29 09:31:27 1998  Gavin Koch  <gavin@cygnus.com>
 370
 371         * interp.c (OPTION_BRANCH_BUG_4011): Add.
 372         (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
 373         (mips_options): Define the option.
 374         * mips.igen (check_4011_branch_bug): New.
 375         (mark_4011_branch_bug): New.
 376         (all branch insn): Call mark_branch_bug, and check_branch_bug.
 377         * sim-main.h (branchbug4011_option, branchbug4011_last_target,
 378         branchbug4011_last_cia, BRANCHBUG4011_OPTION,
 379         BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
 380         check_branch_bug, mark_branch_bug): Define.
 381
 382 end-sanitize-branchbug4011
 383 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 384
 385         * mips.igen (check_mf_hilo): Correct check.
 386
 387 start-sanitize-r5900
 388 Fri Jun 19 14:44:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 389
 390         * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
 391         COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
 392         purpose registers, add 8 COP0 break-point registers, add 64 COP0
 393         performance registers.
 394
 395         * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
 396         MFP* instructions.  Just transfer value to/from corresponding
 397         register.
 398
 399         * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
 400         status is always true.
 401         (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
 402         (EI, DI): Set/clear Status-EIE bit.
 403
 404 end-sanitize-r5900
 405 start-sanitize-sky
 406 Fri Jun 19 14:44:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 407
 408         * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
 409         r5900.igen.
 410
 411 end-sanitize-sky
 412 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 413
 414 start-sanitize-sky
 415         * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
 416         ASSERT not assert.
 417         * sky-gdb.c: Include "sim-assert.h".
 418
 419 end-sanitize-sky
 420         * sim-main.h (interrupt_event): Add prototype.
 421
 422 start-sanitize-tx3904
 423         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 424         register_ptr, register_value.
 425         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 426
 427 end-sanitize-tx3904
 428         * sim-main.h (tracefh): Make extern.
 429
 430 start-sanitize-tx3904
 431 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 432
 433         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 434         Reduce unnecessarily high timer event frequency.
 435         * dv-tx3904cpu.c: Ditto for interrupt event.
 436
 437 end-sanitize-tx3904
 438 start-sanitize-sky
 439 Tue Jun 16 14:12:09 1998  Frank Ch. Eigler  <fche@cygnus.com>
 440
 441         * interp.c (decode_coproc): Removed COP2 branches.
 442         * r5900.igen: Moved COP2 branch instructions here.
 443         * mips.igen: Restricted COPz == COP2 bit pattern to
 444         exclude COP2 branches.
 445
 446 end-sanitize-sky
 447 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 448
 449         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 450         to allay warnings.
 451         (interrupt_event): Made non-static.
 452 start-sanitize-tx3904
 453
 454         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 455         interchange of configuration values for external vs. internal
 456         clock dividers.
 457 end-sanitize-tx3904
 458
 459 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 460
 461         * mips.igen (BREAK): Moved code to here for
 462         simulator-reserved break instructions.
 463         * gencode.c (build_instruction): Ditto.
 464         * interp.c (signal_exception): Code moved from here.  Non-
 465         reserved instructions now use exception vector, rather
 466         than halting sim.
 467         * sim-main.h: Moved magic constants to here.
 468
 469 start-sanitize-tx3904
 470 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 471
 472         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 473         register upon non-zero interrupt event level, clear upon zero
 474         event value.
 475         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 476         by passing zero event value.
 477         (*_io_{read,write}_buffer): Endianness fixes.
 478         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 479         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 480
 481         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 482         serial I/O and timer module at base address 0xFFFF0000.
 483
 484 end-sanitize-tx3904
 485 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 486
 487         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 488         and BigEndianCPU.
 489
 490 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 491
 492         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 493         parts.
 494         * configure: Update.
 495
 496 start-sanitize-tx3904
 497 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 498
 499         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 500         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 501         * configure.in: Include tx3904tmr in hw_device list.
 502         * configure: Rebuilt.
 503         * interp.c (sim_open): Instantiate three timer instances.
 504         Fix address typo of tx3904irc instance.
 505
 506 end-sanitize-tx3904
 507 start-sanitize-r5900
 508 Thu Jun  4 16:47:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 509
 510         * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
 511         Select corresponding check_mt_hilo function.
 512         (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
 513         Ditto.
 514
 515         * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
 516         as r5900 specific.
 517
 518 end-sanitize-r5900
 519 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 520
 521         * interp.c (signal_exception): SystemCall exception now uses
 522         the exception vector.
 523
 524 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 525
 526         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 527         to allay warnings.
 528
 529 start-sanitize-r5900
 530 Mon Jun  1 10:28:25 1998  Jeffrey A Law  (law@cygnus.com)
 531
 532         * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
 533         (sqrt.s): Likewise.
 534
 535 end-sanitize-r5900
 536 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 537
 538         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 539
 540 start-sanitize-tx3904
 541 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 542
 543         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 544
 545         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 546         sim-main.h. Declare a struct hw_descriptor instead of struct
 547         hw_device_descriptor.
 548
 549 end-sanitize-tx3904
 550 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 551
 552         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 553         right bits and then re-align left hand bytes to correct byte
 554         lanes.  Fix incorrect computation in do_store_left when loading
 555         bytes from second word.
 556
 557 start-sanitize-tx3904
 558 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 559
 560         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 561         * interp.c (sim_open): Only create a device tree when HW is
 562         enabled.
 563
 564         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 565         * interp.c (signal_exception): Ditto.
 566
 567 end-sanitize-tx3904
 568 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 569
 570         * gencode.c: Mark BEGEZALL as LIKELY.
 571
 572 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 573
 574         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 575         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 576
 577 start-sanitize-r5900
 578 Thu May 21 17:15:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 579
 580         * interp.c (sim_fetch_register): Convert internal r5900 regs to
 581         target byte order
 582
 583 end-sanitize-r5900
 584 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 585
 586         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 587         modules.  Recognize TX39 target with "mips*tx39" pattern.
 588         * configure: Rebuilt.
 589         * sim-main.h (*): Added many macros defining bits in
 590         TX39 control registers.
 591         (SignalInterrupt): Send actual PC instead of NULL.
 592         (SignalNMIReset): New exception type.
 593         * interp.c (board): New variable for future use to identify
 594         a particular board being simulated.
 595         (mips_option_handler,mips_options): Added "--board" option.
 596         (interrupt_event): Send actual PC.
 597         (sim_open): Make memory layout conditional on board setting.
 598         (signal_exception): Initial implementation of hardware interrupt
 599         handling.  Accept another break instruction variant for simulator
 600         exit.
 601         (decode_coproc): Implement RFE instruction for TX39.
 602         (mips.igen): Decode RFE instruction as such.
 603 start-sanitize-tx3904
 604         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 605         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 606         bbegin to implement memory map.
 607         * dv-tx3904cpu.c: New file.
 608         * dv-tx3904irc.c: New file.
 609 end-sanitize-tx3904
 610
 611 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 612
 613         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 614
 615 start-sanitize-r5900
 616 Wed May 13 14:27:53 1998  Gavin Koch  <gavin@cygnus.com>
 617
 618         * r5900.igen: Replace the calls and the definition of the
 619         function check_op_hilo_hi1lo1 with the pair
 620         check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
 621
 622 end-sanitize-r5900
 623 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 624
 625         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 626         with calls to check_div_hilo.
 627
 628 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 629
 630         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 631         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 632         Add special r3900 version of do_mult_hilo.
 633         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 634         with calls to check_mult_hilo.
 635         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 636         with calls to check_div_hilo.
 637
 638 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 639
 640         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 641         Document a replacement.
 642
 643 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 644
 645         * interp.c (sim_monitor): Make mon_printf work.
 646
 647 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 648
 649         * sim-main.h (INSN_NAME): New arg `cpu'.
 650
 651 start-sanitize-sky
 652 Thu Apr 30 18:51:26 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 653
 654         * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
 655         r59fp_mula.
 656
 657 end-sanitize-sky
 658 start-sanitize-r5900
 659 Wed Apr 29 22:54:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 660
 661         * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
 662         * r5900.igen (r59fp_overflow): Use.
 663
 664         * r5900.igen (r59fp_op3): Rename to
 665         (r59fp_mula): This, delete opm argument.
 666         (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
 667         (r59fp_mula): Overflowing product propogates through to result.
 668         (r59fp_mula): ACC to the MAX propogates to result.
 669         (r59fp_mula): Underflow during multiply only sets SU.
 670
 671 end-sanitize-r5900
 672 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 673
 674         * configure: Regenerated to track ../common/aclocal.m4 changes.
 675
 676 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 677
 678         * configure: Regenerated to track ../common/aclocal.m4 changes.
 679         * config.in: Ditto.
 680
 681 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 682
 683         * acconfig.h: New file.
 684         * configure.in: Reverted change of Apr 24; use sinclude again.
 685
 686 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 687
 688         * configure: Regenerated to track ../common/aclocal.m4 changes.
 689         * config.in: Ditto.
 690
 691 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 692
 693         * configure.in: Don't call sinclude.
 694
 695 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 696
 697         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 698
 699 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 700
 701         * mips.igen (ERET): Implement.
 702
 703         * interp.c (decode_coproc): Return sign-extended EPC.
 704
 705         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 706
 707         * interp.c (signal_exception): Do not ignore Trap.
 708         (signal_exception): On TRAP, restart at exception address.
 709         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 710         (signal_exception): Update.
 711         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 712         so that TRAP instructions are caught.
 713
 714 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 715
 716         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 717         contains HI/LO access history.
 718         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 719         (HIACCESS, LOACCESS): Delete, replace with
 720         (HIHISTORY, LOHISTORY): New macros.
 721         (start-sanitize-r5900):
 722         (struct sim_5900_cpu): Make hi1access, lo1access of type
 723         hilo_access.
 724         (HI1ACCESS, LO1ACCESS): Delete, replace with
 725         (HI1HISTORY, LO1HISTORY): New macros.
 726         (end-sanitize-r5900):
 727         (CHECKHILO): Delete all, moved to mips.igen
 728
 729         * gencode.c (build_instruction): Do not generate checks for
 730         correct HI/LO register usage.
 731
 732         * interp.c (old_engine_run): Delete checks for correct HI/LO
 733         register usage.
 734
 735         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 736         check_mf_cycles): New functions.
 737         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 738         do_divu, domultx, do_mult, do_multu): Use.
 739
 740         * tx.igen ("madd", "maddu"): Use.
 741         (start-sanitize-r5900):
 742
 743         r5900.igen: Update all HI/LO checks.
 744         ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
 745         "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
 746         ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
 747         "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
 748         "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
 749         Check HI/LO op.
 750         (end-sanitize-r5900):
 751
 752 start-sanitize-sky
 753 Mon Apr 20 18:39:47 1998  Frank Ch. Eigler  <fche@cygnus.com>
 754
 755         * interp.c (decode_coproc): Correct CMFC2/QMTC2
 756         GPR access.
 757
 758         * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
 759         instead of a single 128-bit access.
 760
 761 end-sanitize-sky
 762 start-sanitize-sky
 763 Fri Apr 17 14:50:39 1998  Frank Ch. Eigler  <fche@cygnus.com>
 764
 765         * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
 766         * interp.c (cop_[ls]q): Fixes corresponding to above.
 767
 768 end-sanitize-sky
 769 start-sanitize-sky
 770 Thu Apr 16 15:24:14 1998  Frank Ch. Eigler  <fche@cygnus.com>
 771
 772         * interp.c (decode_coproc): Adapt COP2 micro interlock to
 773         clarified specs.  Reset "M" bit; exit also on "E" bit.
 774
 775 end-sanitize-sky
 776 start-sanitize-r5900
 777 Thu Apr 16 10:40:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 778
 779         * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
 780         * mips.igen (CFC1, CTC1): R5900 des not use generic version.
 781
 782         * r5900.igen (r59fp_unpack): New function.
 783         (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
 784         RSQRT.S, SQRT.S): Use.
 785         (r59fp_zero): New function.
 786         (r59fp_overflow): Generate r5900 specific overflow value.
 787         (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
 788         to zero.
 789         (CVT.S.W, CVT.W.S): Exchange implementations.
 790
 791         * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
 792
 793 end-sanitize-r5900
 794 start-sanitize-tx19
 795 Thu Apr 16 09:14:44 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 796
 797         * configure.in (tx19, sim_use_gen): Switch to igen.
 798         * configure: Re-build.
 799
 800 end-sanitize-tx19
 801 start-sanitize-sky
 802 Wed Apr 15 12:41:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 803
 804         * interp.c (decode_coproc): Make COP2 branch code compile after
 805         igen signature changes.
 806
 807 end-sanitize-sky
 808 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 809
 810         * mips.igen (DSRAV): Use function do_dsrav.
 811         (SRAV): Use new function do_srav.
 812
 813         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 814         (B): Sign extend 11 bit immediate.
 815         (EXT-B*): Shift 16 bit immediate left by 1.
 816         (ADDIU*): Don't sign extend immediate value.
 817
 818 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 819
 820         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 821
 822 start-sanitize-tx19
 823         * mips.igen (mtc0): Valid tx19 instruction.
 824
 825 end-sanitize-tx19
 826         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 827         functions.
 828
 829         * mips.igen (delayslot32, nullify_next_insn): New functions.
 830         (m16.igen): Always include.
 831         (do_*): Add more tracing.
 832
 833         * m16.igen (delayslot16): Add NIA argument, could be called by a
 834         32 bit MIPS16 instruction.
 835
 836         * interp.c (ifetch16): Move function from here.
 837         * sim-main.c (ifetch16): To here.
 838
 839         * sim-main.c (ifetch16, ifetch32): Update to match current
 840         implementations of LH, LW.
 841         (signal_exception): Don't print out incorrect hex value of illegal
 842         instruction.
 843
 844 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 845
 846         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 847         instruction.
 848
 849         * m16.igen: Implement MIPS16 instructions.
 850
 851         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 852         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 853         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 854         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 855         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 856         bodies of corresponding code from 32 bit insn to these.  Also used
 857         by MIPS16 versions of functions.
 858
 859         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 860         (IMEM16): Drop NR argument from macro.
 861
 862 start-sanitize-sky
 863 Mon Apr 13 16:28:52 1998  Frank Ch. Eigler  <fche@cygnus.com>
 864
 865         * interp.c (decode_coproc): Add proper 1000000 bit-string at top
 866         of VU lower instruction.
 867
 868 end-sanitize-sky
 869 start-sanitize-sky
 870 Thu Apr  9 16:38:23 1998  Frank Ch. Eigler  <fche@cygnus.com>
 871
 872         * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
 873         instead of QUADWORD.
 874
 875         * sim-main.h: Removed attempt at allowing 128-bit access.
 876
 877 end-sanitize-sky
 878 start-sanitize-sky
 879 Wed Apr  8 18:12:13 1998  Frank Ch. Eigler  <fche@cygnus.com>
 880
 881         * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
 882
 883         * interp.c (decode_coproc): Refer to VU CIA as a "special"
 884         register, not as a "misc" register.  Aha.  Add activity
 885         assertions after VCALLMS* instructions.
 886
 887 end-sanitize-sky
 888 start-sanitize-sky
 889 Tue Apr  7 18:32:49 1998  Frank Ch. Eigler  <fche@cygnus.com>
 890
 891         * interp.c (decode_coproc): Do not apply superfluous E (end) flag
 892         to upper code of generated VU instruction.
 893
 894 end-sanitize-sky
 895 start-sanitize-sky
 896 Mon Apr  6 19:55:56 1998  Frank Ch. Eigler  <fche@cygnus.com>
 897
 898         * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
 899
 900         * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
 901         for TARGET_SKY.
 902
 903         * r5900.igen (SQC2): Thinko.
 904
 905 end-sanitize-sky
 906 start-sanitize-sky
 907 Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 908
 909         * interp.c (*): Adapt code to merged VU device & state structs.
 910         (decode_coproc): Execute COP2 each macroinstruction without
 911         pipelining, by stepping VU to completion state.  Adapted to
 912         read_vu_*_reg style of register access.
 913
 914         * mips.igen ([SL]QC2): Removed these COP2 instructions.
 915
 916         * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
 917
 918         * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
 919
 920 end-sanitize-sky
 921 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 922
 923         * Makefile.in (SIM_OBJS): Add sim-main.o.
 924
 925         * sim-main.h (address_translation, load_memory, store_memory,
 926         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 927         as INLINE_SIM_MAIN.
 928         (pr_addr, pr_uword64): Declare.
 929         (sim-main.c): Include when H_REVEALS_MODULE_P.
 930
 931         * interp.c (address_translation, load_memory, store_memory,
 932         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 933         from here.
 934         * sim-main.c: To here. Fix compilation problems.
 935
 936         * configure.in: Enable inlining.
 937         * configure: Re-config.
 938
 939 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 940
 941         * configure: Regenerated to track ../common/aclocal.m4 changes.
 942
 943 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 944
 945         * mips.igen: Include tx.igen.
 946         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 947         * tx.igen: New file, contains MADD and MADDU.
 948
 949         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 950         the hardwired constant `7'.
 951         (store_memory): Ditto.
 952         (LOADDRMASK): Move definition to sim-main.h.
 953
 954         mips.igen (MTC0): Enable for r3900.
 955         (ADDU): Add trace.
 956
 957         mips.igen (do_load_byte): Delete.
 958         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 959         do_store_right): New functions.
 960         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 961
 962         configure.in: Let the tx39 use igen again.
 963         configure: Update.
 964
 965 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 966
 967         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 968         not an address sized quantity.  Return zero for cache sizes.
 969
 970 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 971
 972         * mips.igen (r3900): r3900 does not support 64 bit integer
 973         operations.
 974
 975 start-sanitize-sky
 976 Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>
 977
 978         * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
 979
 980 end-sanitize-sky
 981 start-sanitize-sky
 982 Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>
 983
 984         * interp.c (decode_coproc): Continuing COP2 work.
 985         (cop_[ls]q): Make sky-target-only.
 986
 987         * sim-main.h (COP_[LS]Q): Make sky-target-only.
 988 end-sanitize-sky
 989 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 990
 991         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 992         than igen one.
 993         * configure : Rebuild.
 994
 995 start-sanitize-sky
 996 Sun Mar 29 17:50:11       Frank Ch. Eigler  <fche@cygnus.com>
 997
 998         * interp.c (decode_coproc): Added a missing TARGET_SKY check
 999         around COP2 implementation skeleton.
1000
1001 end-sanitize-sky
1002 start-sanitize-sky
1003 Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>
1004
1005         * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
1006
1007         * interp.c (sim_{load,store}_register): Use new vu[01]_device
1008         static to access VU registers.
1009         (decode_coproc): Added skeleton of sky COP2 (VU) instruction
1010         decoding.  Work in progress.
1011
1012         * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
1013         overlapping/redundant bit pattern.
1014         (LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
1015         progress.
1016
1017         * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
1018         status register.
1019
1020         * interp.c (cop_lq, cop_sq): New functions for future 128-bit
1021         access to coprocessor registers.
1022
1023         * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
1024 end-sanitize-sky
1025 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1026
1027         * configure: Regenerated to track ../common/aclocal.m4 changes.
1028
1029 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1030
1031         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1032
1033 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1034
1035         * configure: Regenerated to track ../common/aclocal.m4 changes.
1036         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1037
1038 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1039
1040         * configure: Regenerated to track ../common/aclocal.m4 changes.
1041
1042 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1043
1044         * interp.c (Max, Min): Comment out functions. Not yet used.
1045
1046 start-sanitize-vr4320
1047 Wed Mar 25 10:04:13 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1048
1049         * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
1050
1051 end-sanitize-vr4320
1052 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1053
1054         * configure: Regenerated to track ../common/aclocal.m4 changes.
1055
1056 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1057
1058         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1059         configurable settings for stand-alone simulator.
1060
1061 start-sanitize-sky
1062         * configure.in: Added --with-sim-gpu2 option to specify path of
1063         sky GPU2 library.  Triggers -DSKY_GPU2 for sky-gpuif.c, and
1064         links/compiles stand-alone simulator with this library.
1065
1066         * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
1067 end-sanitize-sky
1068         * configure.in: Added X11 search, just in case.
1069
1070         * configure: Regenerated.
1071
1072 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1073
1074         * interp.c (sim_write, sim_read, load_memory, store_memory):
1075         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1076
1077 start-sanitize-vr4320
1078 Tue Mar 10 10:32:22 1998  Gavin Koch  <gavin@cygnus.com>
1079
1080         * vr4320.igen (clz,dclz) : Added.
1081         (dmac): Replaced 99, with LO.
1082
1083 end-sanitize-vr4320
1084 start-sanitize-cygnus
1085 Fri Mar  6 08:30:58 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1086
1087         * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
1088
1089 end-sanitize-cygnus
1090 start-sanitize-vr4320
1091 Tue Mar  3 11:56:29 1998  Gavin Koch  <gavin@cygnus.com>
1092
1093         * vr4320.igen: New file.
1094         * Makefile.in (vr4320.igen) : Added.
1095         * configure.in (mips64vr4320-*-*): Added.
1096         * configure : Rebuilt.
1097         * mips.igen : Correct the bfd-names in the mips-ISA model entries.
1098         Add the vr4320 model entry and mark the vr4320 insn as necessary.
1099
1100 end-sanitize-vr4320
1101 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1102
1103         * sim-main.h (GETFCC): Return an unsigned value.
1104
1105 start-sanitize-r5900
1106         * r5900.igen: Use an unsigned array index variable `i'.
1107         (QFSRV): Ditto for variable bytes.
1108
1109 end-sanitize-r5900
1110 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1111
1112         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1113         (DADD): Result destination is RD not RT.
1114
1115 start-sanitize-r5900
1116         * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
1117         (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
1118         divide.
1119
1120 end-sanitize-r5900
1121 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1122
1123         * sim-main.h (HIACCESS, LOACCESS): Always define.
1124
1125         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1126
1127         * interp.c (sim_info): Delete.
1128
1129 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1130
1131         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1132         (mips_option_handler): New argument `cpu'.
1133         (sim_open): Update call to sim_add_option_table.
1134
1135 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1136
1137         * mips.igen (CxC1): Add tracing.
1138
1139 start-sanitize-r5900
1140 Wed Feb 25 13:59:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1141
1142         * r5900.igen (StoreFP): Delete.
1143         (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
1144         New functions.
1145         (rsqrt.s, sqrt.s): Implement.
1146         (r59cond): New function.
1147         (C.COND.S): Call r59cond in assembler line.
1148         (cvt.w.s, cvt.s.w): Implement.
1149
1150         * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
1151         instruction set.
1152
1153         * sim-main.h: Define an enum of r5900 FCSR bit fields.
1154
1155 end-sanitize-r5900
1156 start-sanitize-r5900
1157 Tue Feb 24 14:44:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1158
1159         * r5900.igen: Add tracing to all p* instructions.
1160
1161 Tue Feb 24 02:47:33 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1162
1163         * interp.c (sim_store_register, sim_fetch_register): Pull swifty
1164         to get gdb talking to re-aranged sim_cpu register structure.
1165
1166 end-sanitize-r5900
1167 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1168
1169         * sim-main.h (Max, Min): Declare.
1170
1171         * interp.c (Max, Min): New functions.
1172
1173         * mips.igen (BC1): Add tracing.
1174
1175 start-sanitize-cygnus
1176 Fri Feb 20 16:27:17 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1177
1178         * mdmx.igen: Tag all functions as requiring either with mdmx or
1179         vr5400 processor.
1180
1181 end-sanitize-cygnus
1182 start-sanitize-r5900
1183 Fri Feb 20 15:55:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1184
1185         * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
1186         to 32.
1187         (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
1188
1189         * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
1190
1191         * r5900.igen: Rewrite.
1192
1193         * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
1194         struct.
1195         (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
1196         Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
1197
1198 end-sanitize-r5900
1199 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1200
1201         * interp.c Added memory map for stack in vr4100
1202
1203 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1204
1205         * interp.c (load_memory): Add missing "break"'s.
1206
1207 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1208
1209         * interp.c (sim_store_register, sim_fetch_register): Pass in
1210         length parameter.  Return -1.
1211
1212 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1213
1214         * interp.c: Added hardware init hook, fixed warnings.
1215
1216 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1217
1218         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1219
1220 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1221
1222         * interp.c (ifetch16): New function.
1223
1224         * sim-main.h (IMEM32): Rename IMEM.
1225         (IMEM16_IMMED): Define.
1226         (IMEM16): Define.
1227         (DELAY_SLOT): Update.
1228
1229         * m16run.c (sim_engine_run): New file.
1230
1231         * m16.igen: All instructions except LB.
1232         (LB): Call do_load_byte.
1233         * mips.igen (do_load_byte): New function.
1234         (LB): Call do_load_byte.
1235
1236         * mips.igen: Move spec for insn bit size and high bit from here.
1237         * Makefile.in (tmp-igen, tmp-m16): To here.
1238
1239         * m16.dc: New file, decode mips16 instructions.
1240
1241         * Makefile.in (SIM_NO_ALL): Define.
1242         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1243
1244 start-sanitize-tx19
1245         * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1246         set.
1247
1248 end-sanitize-tx19
1249 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1250
1251         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1252         point unit to 32 bit registers.
1253         * configure: Re-generate.
1254
1255 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1256
1257         * configure.in (sim_use_gen): Make IGEN the default simulator
1258         generator for generic 32 and 64 bit mips targets.
1259         * configure: Re-generate.
1260
1261 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1262
1263         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1264         bitsize.
1265
1266         * interp.c (sim_fetch_register, sim_store_register): Read/write
1267         FGR from correct location.
1268         (sim_open): Set size of FGR's according to
1269         WITH_TARGET_FLOATING_POINT_BITSIZE.
1270
1271         * sim-main.h (FGR): Store floating point registers in a separate
1272         array.
1273
1274 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1275
1276         * configure: Regenerated to track ../common/aclocal.m4 changes.
1277
1278 start-sanitize-cygnus
1279         * mdmx.igen: Mark all instructions as 64bit/fp specific.
1280
1281 end-sanitize-cygnus
1282 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1283
1284         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1285
1286         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1287
1288         * interp.c (pending_tick): New function.  Deliver pending writes.
1289
1290         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1291         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1292         it can handle mixed sized quantites and single bits.
1293
1294 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1295
1296         * interp.c (oengine.h): Do not include when building with IGEN.
1297         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1298         (sim_info): Ditto for PROCESSOR_64BIT.
1299         (sim_monitor): Replace ut_reg with unsigned_word.
1300         (*): Ditto for t_reg.
1301         (LOADDRMASK): Define.
1302         (sim_open): Remove defunct check that host FP is IEEE compliant,
1303         using software to emulate floating point.
1304         (value_fpr, ...): Always compile, was conditional on HASFPU.
1305
1306 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1307
1308         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1309         size.
1310
1311         * interp.c (SD, CPU): Define.
1312         (mips_option_handler): Set flags in each CPU.
1313         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1314         (sim_close): Do not clear STATE, deleted anyway.
1315         (sim_write, sim_read): Assume CPU zero's vm should be used for
1316         data transfers.
1317         (sim_create_inferior): Set the PC for all processors.
1318         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1319         argument.
1320         (mips16_entry): Pass correct nr of args to store_word, load_word.
1321         (ColdReset): Cold reset all cpu's.
1322         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1323         (sim_monitor, load_memory, store_memory, signal_exception): Use
1324         `CPU' instead of STATE_CPU.
1325
1326
1327         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1328         SD or CPU_.
1329
1330         * sim-main.h (signal_exception): Add sim_cpu arg.
1331         (SignalException*): Pass both SD and CPU to signal_exception.
1332         * interp.c (signal_exception): Update.
1333
1334         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1335         Ditto
1336         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1337         address_translation): Ditto
1338         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1339
1340 start-sanitize-cygnus
1341         * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1342         `sd'.
1343         (ByteAlign): Use StoreFPR, pass args in correct order.
1344
1345 end-sanitize-cygnus
1346 start-sanitize-r5900
1347 Sun Feb  1 10:59:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1348
1349         * configure.in (sim_igen_filter): For r5900, configure as SMP.
1350
1351 end-sanitize-r5900
1352 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1353
1354         * configure: Regenerated to track ../common/aclocal.m4 changes.
1355
1356 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1357
1358 start-sanitize-r5900
1359         * configure.in (sim_igen_filter): For r5900, use igen.
1360         * configure: Re-generate.
1361
1362 end-sanitize-r5900
1363         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1364
1365         * mips.igen (model): Map processor names onto BFD name.
1366
1367         * sim-main.h (CPU_CIA): Delete.
1368         (SET_CIA, GET_CIA): Define
1369
1370 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1371
1372         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1373         regiser.
1374
1375         * configure.in (default_endian): Configure a big-endian simulator
1376         by default.
1377         * configure: Re-generate.
1378
1379 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1380
1381         * configure: Regenerated to track ../common/aclocal.m4 changes.
1382
1383 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1384
1385         * interp.c (sim_monitor): Handle Densan monitor outbyte
1386         and inbyte functions.
1387
1388 1997-12-29  Felix Lee  <flee@cygnus.com>
1389
1390         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1391
1392 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1393
1394         * Makefile.in (tmp-igen): Arrange for $zero to always be
1395         reset to zero after every instruction.
1396
1397 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1398
1399         * configure: Regenerated to track ../common/aclocal.m4 changes.
1400         * config.in: Ditto.
1401
1402 start-sanitize-cygnus
1403 Sat Dec 13 15:18:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1404
1405         * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1406         bit values.
1407
1408 Fri Dec 12 12:26:07 1997  Jeffrey A Law  (law@cygnus.com)
1409
1410         * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1411         vr5400 with the vr5000 as the default.
1412
1413 end-sanitize-cygnus
1414 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1415
1416         * mips.igen (MSUB): Fix to work like MADD.
1417         * gencode.c (MSUB): Similarly.
1418
1419 start-sanitize-cygnus
1420 Tue Dec  9 12:02:12 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1421
1422         * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1423         vr5400.
1424
1425 end-sanitize-cygnus
1426 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1427
1428         * configure: Regenerated to track ../common/aclocal.m4 changes.
1429
1430 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1431
1432         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1433
1434 start-sanitize-cygnus
1435         * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1436         (value_cc, store_cc): Implement.
1437
1438         * sim-main.h: Add 8*3*8 bit accumulator.
1439
1440         * vr5400.igen: Move mdmx instructins from here
1441         * mdmx.igen: To here - new file. Add/fix missing instructions.
1442         * mips.igen: Include mdmx.igen.
1443         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1444
1445 end-sanitize-cygnus
1446 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1447
1448         * sim-main.h (sim-fpu.h): Include.
1449
1450         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1451         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1452         using host independant sim_fpu module.
1453
1454 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1455
1456         * interp.c (signal_exception): Report internal errors with SIGABRT
1457         not SIGQUIT.
1458
1459         * sim-main.h (C0_CONFIG): New register.
1460         (signal.h): No longer include.
1461
1462         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1463
1464 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1465
1466         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1467
1468 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1469
1470         * mips.igen: Tag vr5000 instructions.
1471         (ANDI): Was missing mipsIV model, fix assembler syntax.
1472         (do_c_cond_fmt): New function.
1473         (C.cond.fmt): Handle mips I-III which do not support CC field
1474         separatly.
1475         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1476         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1477         in IV3.2 spec.
1478         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1479         vr5000 which saves LO in a GPR separatly.
1480
1481         * configure.in (enable-sim-igen): For vr5000, select vr5000
1482         specific instructions.
1483         * configure: Re-generate.
1484
1485 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1486
1487         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1488
1489         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1490         fmt_uninterpreted_64 bit cases to switch.  Convert to
1491         fmt_formatted,
1492
1493         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1494
1495         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1496         as specified in IV3.2 spec.
1497         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1498
1499 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1500
1501         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1502         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1503         (start-sanitize-r5900):
1504         (LWXC1, SWXC1): Delete from r5900 instruction set.
1505         (end-sanitize-r5900):
1506         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1507         PENDING_FILL versions of instructions.  Simplify.
1508         (X): New function.
1509         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1510         instructions.
1511         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1512         a signed value.
1513         (MTHI, MFHI): Disable code checking HI-LO.
1514
1515         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1516         global.
1517         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1518
1519 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1520
1521         * gencode.c (build_mips16_operands): Replace IPC with cia.
1522
1523         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1524         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1525         IPC to `cia'.
1526         (UndefinedResult): Replace function with macro/function
1527         combination.
1528         (sim_engine_run): Don't save PC in IPC.
1529
1530         * sim-main.h (IPC): Delete.
1531
1532         start-sanitize-cygnus
1533         * vr5400.igen (vr): Add missing cia argument to value_fpr.
1534         (do_select): Rename function select.
1535         end-sanitize-cygnus
1536
1537         * interp.c (signal_exception, store_word, load_word,
1538         address_translation, load_memory, store_memory, cache_op,
1539         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1540         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1541         current instruction address - cia - argument.
1542         (sim_read, sim_write): Call address_translation directly.
1543         (sim_engine_run): Rename variable vaddr to cia.
1544         (signal_exception): Pass cia to sim_monitor
1545
1546         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1547         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1548         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1549
1550         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1551         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1552         SIM_ASSERT.
1553
1554         * interp.c (signal_exception): Pass restart address to
1555         sim_engine_restart.
1556
1557         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1558         idecode.o): Add dependency.
1559
1560         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1561         Delete definitions
1562         (DELAY_SLOT): Update NIA not PC with branch address.
1563         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1564
1565         * mips.igen: Use CIA not PC in branch calculations.
1566         (illegal): Call SignalException.
1567         (BEQ, ADDIU): Fix assembler.
1568
1569 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1570
1571         * m16.igen (JALX): Was missing.
1572
1573         * configure.in (enable-sim-igen): New configuration option.
1574         * configure: Re-generate.
1575
1576         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1577
1578         * interp.c (load_memory, store_memory): Delete parameter RAW.
1579         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1580         bypassing {load,store}_memory.
1581
1582         * sim-main.h (ByteSwapMem): Delete definition.
1583
1584         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1585
1586         * interp.c (sim_do_command, sim_commands): Delete mips specific
1587         commands.  Handled by module sim-options.
1588
1589         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1590         (WITH_MODULO_MEMORY): Define.
1591
1592         * interp.c (sim_info): Delete code printing memory size.
1593
1594         * interp.c (mips_size): Nee sim_size, delete function.
1595         (power2): Delete.
1596         (monitor, monitor_base, monitor_size): Delete global variables.
1597         (sim_open, sim_close): Delete code creating monitor and other
1598         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1599         manage memory regions.
1600         (load_memory, store_memory): Use sim-core for memory model.
1601
1602         * interp.c (address_translation): Delete all memory map code
1603         except line forcing 32 bit addresses.
1604
1605 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1606
1607         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1608         trace options.
1609
1610         * interp.c (logfh, logfile): Delete globals.
1611         (sim_open, sim_close): Delete code opening & closing log file.
1612         (mips_option_handler): Delete -l and -n options.
1613         (OPTION mips_options): Ditto.
1614
1615         * interp.c (OPTION mips_options): Rename option trace to dinero.
1616         (mips_option_handler): Update.
1617
1618 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1619
1620         * interp.c (fetch_str): New function.
1621         (sim_monitor): Rewrite using sim_read & sim_write.
1622         (sim_open): Check magic number.
1623         (sim_open): Write monitor vectors into memory using sim_write.
1624         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1625         (sim_read, sim_write): Simplify - transfer data one byte at a
1626         time.
1627         (load_memory, store_memory): Clarify meaning of parameter RAW.
1628
1629         * sim-main.h (isHOST): Defete definition.
1630         (isTARGET): Mark as depreciated.
1631         (address_translation): Delete parameter HOST.
1632
1633         * interp.c (address_translation): Delete parameter HOST.
1634
1635 start-sanitize-tx49
1636 Wed Oct 29 14:21:32 1997  Gavin Koch  <gavin@cygnus.com>
1637
1638         * gencode.c: Add tx49 configury and insns.
1639         * configure.in: Add tx49 configury.
1640         * configure: Update.
1641
1642 end-sanitize-tx49
1643 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1644
1645         * mips.igen:
1646
1647         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1648         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1649
1650 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1651
1652         * mips.igen: Add model filter field to records.
1653
1654 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1655
1656         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1657
1658         interp.c (sim_engine_run): Do not compile function sim_engine_run
1659         when WITH_IGEN == 1.
1660
1661         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1662         target architecture.
1663
1664         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1665         igen. Replace with configuration variables sim_igen_flags /
1666         sim_m16_flags.
1667
1668         start-sanitize-r5900
1669         * r5900.igen: New file. Copy r5900 insns here.
1670         end-sanitize-r5900
1671         start-sanitize-cygnus
1672         * vr5400.igen: New file.
1673         end-sanitize-cygnus
1674         * m16.igen: New file.  Copy mips16 insns here.
1675         * mips.igen: From here.
1676
1677 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1678
1679         start-sanitize-cygnus
1680         * mips.igen: Tag all mipsIV instructions with vr5400 model.
1681
1682         * configure.in: Add mips64vr5400 target.
1683         * configure: Re-generate.
1684
1685         end-sanitize-cygnus
1686         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1687         to top.
1688         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1689
1690 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1691
1692         * gencode.c (build_instruction): Follow sim_write's lead in using
1693         BigEndianMem instead of !ByteSwapMem.
1694
1695 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1696
1697         * configure.in (sim_gen): Dependent on target, select type of
1698         generator.  Always select old style generator.
1699
1700         configure: Re-generate.
1701
1702         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1703         targets.
1704         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1705         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1706         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1707         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1708         SIM_@sim_gen@_*, set by autoconf.
1709
1710 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1711
1712         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1713
1714         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1715         CURRENT_FLOATING_POINT instead.
1716
1717         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1718         (address_translation): Raise exception InstructionFetch when
1719         translation fails and isINSTRUCTION.
1720
1721         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1722         sim_engine_run): Change type of of vaddr and paddr to
1723         address_word.
1724         (address_translation, prefetch, load_memory, store_memory,
1725         cache_op): Change type of vAddr and pAddr to address_word.
1726
1727         * gencode.c (build_instruction): Change type of vaddr and paddr to
1728         address_word.
1729
1730 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1731
1732         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1733         macro to obtain result of ALU op.
1734
1735 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1736
1737         * interp.c (sim_info): Call profile_print.
1738
1739 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1740
1741         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1742
1743         * sim-main.h (WITH_PROFILE): Do not define, defined in
1744         common/sim-config.h.  Use sim-profile module.
1745         (simPROFILE): Delete defintion.
1746
1747         * interp.c (PROFILE): Delete definition.
1748         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1749         (sim_close): Delete code writing profile histogram.
1750         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1751         Delete.
1752         (sim_engine_run): Delete code profiling the PC.
1753
1754 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1755
1756         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1757
1758         * interp.c (sim_monitor): Make register pointers of type
1759         unsigned_word*.
1760
1761         * sim-main.h: Make registers of type unsigned_word not
1762         signed_word.
1763
1764 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1765
1766 start-sanitize-r5900
1767         * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1768         ...): Move to sim-main.h
1769
1770 end-sanitize-r5900
1771         * interp.c (sync_operation): Rename from SyncOperation, make
1772         global, add SD argument.
1773         (prefetch): Rename from Prefetch, make global, add SD argument.
1774         (decode_coproc): Make global.
1775
1776         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1777
1778         * gencode.c (build_instruction): Generate DecodeCoproc not
1779         decode_coproc calls.
1780
1781         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1782         (SizeFGR): Move to sim-main.h
1783         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1784         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1785         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1786         sim-main.h.
1787         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1788         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1789         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1790         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1791         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1792         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1793
1794         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1795         exception.
1796         (sim-alu.h): Include.
1797         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1798         (sim_cia): Typedef to instruction_address.
1799
1800 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1801
1802         * Makefile.in (interp.o): Rename generated file engine.c to
1803         oengine.c.
1804
1805         * interp.c: Update.
1806
1807 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1808
1809         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1810
1811 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1812
1813         * gencode.c (build_instruction): For "FPSQRT", output correct
1814         number of arguments to Recip.
1815
1816 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1817
1818         * Makefile.in (interp.o): Depends on sim-main.h
1819
1820         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1821
1822         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1823         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1824         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1825         STATE, DSSTATE): Define
1826         (GPR, FGRIDX, ..): Define.
1827
1828         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1829         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1830         (GPR, FGRIDX, ...): Delete macros.
1831
1832         * interp.c: Update names to match defines from sim-main.h
1833
1834 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1835
1836         * interp.c (sim_monitor): Add SD argument.
1837         (sim_warning): Delete.  Replace calls with calls to
1838         sim_io_eprintf.
1839         (sim_error): Delete. Replace calls with sim_io_error.
1840         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1841         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1842         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1843         argument.
1844         (mips_size): Rename from sim_size. Add SD argument.
1845
1846         * interp.c (simulator): Delete global variable.
1847         (callback): Delete global variable.
1848         (mips_option_handler, sim_open, sim_write, sim_read,
1849         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1850         sim_size,sim_monitor): Use sim_io_* not callback->*.
1851         (sim_open): ZALLOC simulator struct.
1852         (PROFILE): Do not define.
1853
1854 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1855
1856         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1857         support.h with corresponding code.
1858
1859         * sim-main.h (word64, uword64), support.h: Move definition to
1860         sim-main.h.
1861         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1862
1863         * support.h: Delete
1864         * Makefile.in: Update dependencies
1865         * interp.c: Do not include.
1866
1867 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1868
1869         * interp.c (address_translation, load_memory, store_memory,
1870         cache_op): Rename to from AddressTranslation et.al., make global,
1871         add SD argument
1872
1873         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1874         CacheOp): Define.
1875
1876         * interp.c (SignalException): Rename to signal_exception, make
1877         global.
1878
1879         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1880
1881         * sim-main.h (SignalException, SignalExceptionInterrupt,
1882         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1883         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1884         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1885         Define.
1886
1887         * interp.c, support.h: Use.
1888
1889 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1892         to value_fpr / store_fpr. Add SD argument.
1893         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1894         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1895
1896         * sim-main.h (ValueFPR, StoreFPR): Define.
1897
1898 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1899
1900         * interp.c (sim_engine_run): Check consistency between configure
1901         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1902         and HASFPU.
1903
1904         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1905         (mips_fpu): Configure WITH_FLOATING_POINT.
1906         (mips_endian): Configure WITH_TARGET_ENDIAN.
1907         * configure: Update.
1908
1909 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1910
1911         * configure: Regenerated to track ../common/aclocal.m4 changes.
1912
1913 start-sanitize-r5900
1914 Mon Aug 25 19:11:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1915
1916         * interp.c (MAX_REG): Allow up-to 128 registers.
1917         (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1918         (REGISTER_SA): Ditto.
1919         (sim_open): Initialize register_widths for r5900 specific
1920         registers.
1921         (sim_fetch_register, sim_store_register): Check for request of
1922         r5900 specific SA register.  Check for request for hi 64 bits of
1923         r5900 specific registers.
1924
1925 end-sanitize-r5900
1926 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1927
1928         * configure: Regenerated.
1929
1930 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1931
1932         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1933
1934 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1935
1936         * gencode.c (print_igen_insn_models): Assume certain architectures
1937         include all mips* instructions.
1938         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1939         instruction.
1940
1941         * Makefile.in (tmp.igen): Add target. Generate igen input from
1942         gencode file.
1943
1944         * gencode.c (FEATURE_IGEN): Define.
1945         (main): Add --igen option.  Generate output in igen format.
1946         (process_instructions): Format output according to igen option.
1947         (print_igen_insn_format): New function.
1948         (print_igen_insn_models): New function.
1949         (process_instructions): Only issue warnings and ignore
1950         instructions when no FEATURE_IGEN.
1951
1952 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1953
1954         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1955         MIPS targets.
1956
1957 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1958
1959         * configure: Regenerated to track ../common/aclocal.m4 changes.
1960
1961 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1962
1963         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1964         SIM_RESERVED_BITS): Delete, moved to common.
1965         (SIM_EXTRA_CFLAGS): Update.
1966
1967 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1968
1969         * configure.in: Configure non-strict memory alignment.
1970         * configure: Regenerated to track ../common/aclocal.m4 changes.
1971
1972 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1973
1974         * configure: Regenerated to track ../common/aclocal.m4 changes.
1975
1976 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1977
1978         * gencode.c (SDBBP,DERET): Added (3900) insns.
1979         (RFE): Turn on for 3900.
1980         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1981         (dsstate): Made global.
1982         (SUBTARGET_R3900): Added.
1983         (CANCELDELAYSLOT): New.
1984         (SignalException): Ignore SystemCall rather than ignore and
1985         terminate.  Add DebugBreakPoint handling.
1986         (decode_coproc): New insns RFE, DERET; and new registers Debug
1987         and DEPC protected by SUBTARGET_R3900.
1988         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1989         bits explicitly.
1990         * Makefile.in,configure.in: Add mips subtarget option.
1991         * configure: Update.
1992
1993 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1994
1995         * gencode.c: Add r3900 (tx39).
1996
1997 start-sanitize-tx19
1998         * gencode.c: Fix some configuration problems by improving
1999         the relationship between tx19 and tx39.
2000 end-sanitize-tx19
2001
2002 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2003
2004         * gencode.c (build_instruction): Don't need to subtract 4 for
2005         JALR, just 2.
2006
2007 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2008
2009         * interp.c: Correct some HASFPU problems.
2010
2011 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2012
2013         * configure: Regenerated to track ../common/aclocal.m4 changes.
2014
2015 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2016
2017         * interp.c (mips_options): Fix samples option short form, should
2018         be `x'.
2019
2020 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2021
2022         * interp.c (sim_info): Enable info code.  Was just returning.
2023
2024 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2025
2026         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2027         MFC0.
2028
2029 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2030
2031         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2032         constants.
2033         (build_instruction): Ditto for LL.
2034
2035 start-sanitize-tx19
2036 Sun Sep  7 16:05:46 1997  Gavin Koch  <gavin@cygnus.com>
2037
2038         * mips/configure.in, mips/gencode: Add tx19/r1900.
2039
2040 end-sanitize-tx19
2041 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2042
2043         * configure: Regenerated to track ../common/aclocal.m4 changes.
2044
2045 start-sanitize-r5900
2046 Mon Sep  1 18:43:30 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2047
2048         * gencode.c (build_instruction): For "pabsw" and "pabsh", check
2049         for overflow due to ABS of MININT, set result to MAXINT.
2050         (build_instruction): For "psrlvw", signextend bit 31.
2051
2052 end-sanitize-r5900
2053 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2054
2055         * configure: Regenerated to track ../common/aclocal.m4 changes.
2056         * config.in: Ditto.
2057
2058 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2059
2060         * interp.c (sim_open): Add call to sim_analyze_program, update
2061         call to sim_config.
2062
2063 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2064
2065         * interp.c (sim_kill): Delete.
2066         (sim_create_inferior): Add ABFD argument. Set PC from same.
2067         (sim_load): Move code initializing trap handlers from here.
2068         (sim_open): To here.
2069         (sim_load): Delete, use sim-hload.c.
2070
2071         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2072
2073 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2074
2075         * configure: Regenerated to track ../common/aclocal.m4 changes.
2076         * config.in: Ditto.
2077
2078 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2079
2080         * interp.c (sim_open): Add ABFD argument.
2081         (sim_load): Move call to sim_config from here.
2082         (sim_open): To here.  Check return status.
2083
2084 start-sanitize-r5900
2085         * gencode.c (build_instruction): Do not define x8000000000000000,
2086         x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
2087
2088 end-sanitize-r5900
2089 start-sanitize-r5900
2090 Mon Jul 28 19:49:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2091
2092         * gencode.c (build_instruction): For "pdivw", "pdivbw" and
2093         "pdivuw" check for overflow due to signed divide by -1.
2094
2095 end-sanitize-r5900
2096 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2097
2098         * gencode.c (build_instruction): Two arg MADD should
2099         not assign result to $0.
2100
2101 start-sanitize-r5900
2102 Thu Jul 10 11:58:48 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2103
2104         * gencode.c (build_instruction): For "ppac5" use unsigned
2105         arrithmetic so that the sign bit doesn't smear when right shifted.
2106         (build_instruction): For "pdiv" perform sign extension when
2107         storing results in HI and LO.
2108         (build_instructions): For "pdiv" and "pdivbw" check for
2109         divide-by-zero.
2110         (build_instruction): For "pmfhl.slw" update hi part of dest
2111         register as well as low part.
2112         (build_instruction): For "pmfhl" portably handle long long values.
2113         (build_instruction): For "pmfhl.sh" correctly negative values.
2114         Store half words 2 and three in the correct place.
2115         (build_instruction): For "psllvw", sign extend value after shift.
2116
2117 end-sanitize-r5900
2118 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2119
2120         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2121         * sim/mips/configure.in: Regenerate.
2122
2123 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2124
2125         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2126         signed8, unsigned8 et.al. types.
2127
2128 start-sanitize-r5900
2129         * gencode.c (build_instruction): For PMULTU* do not sign extend
2130         registers.  Make generated code easier to debug.
2131
2132 end-sanitize-r5900
2133         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2134         hosts when selecting subreg.
2135
2136 start-sanitize-r5900
2137 Tue Jul  8 18:07:20 1997  Andrew Cagney  <cagney@andros.cygnus.com>
2138
2139         * gencode.c (type_for_data_len): For 32bit operations concerned
2140         with overflow, perform op using 64bits.
2141         (build_instruction): For PADD, always compute operation using type
2142         returned by type_for_data_len.
2143         (build_instruction): For PSUBU, when overflow, saturate to zero as
2144         actually underflow.
2145
2146 end-sanitize-r5900
2147 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2148
2149 start-sanitize-r5900
2150         * gencode.c (build_instruction): Handle "pext5" according to
2151         version 1.95 of the r5900 ISA.
2152
2153         * gencode.c (build_instruction): Handle "ppac5" according to
2154         version 1.95 of the r5900 ISA.
2155
2156 end-sanitize-r5900
2157         * interp.c (sim_engine_run): Reset the ZERO register to zero
2158         regardless of FEATURE_WARN_ZERO.
2159         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2160
2161 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2162
2163         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2164         (SignalException): For BreakPoints ignore any mode bits and just
2165         save the PC.
2166         (SignalException): Always set the CAUSE register.
2167
2168 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2169
2170         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2171         exception has been taken.
2172
2173         * interp.c: Implement the ERET and mt/f sr instructions.
2174
2175 start-sanitize-r5900
2176 Mon Jun  2 23:28:19 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2177
2178         * gencode.c (build_instruction): For paddu, extract unsigned
2179         sub-fields.
2180
2181         * gencode.c (build_instruction): Saturate padds instead of padd
2182         instructions.
2183
2184 end-sanitize-r5900
2185 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2186
2187         * interp.c (SignalException): Don't bother restarting an
2188         interrupt.
2189
2190 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2191
2192         * interp.c (SignalException): Really take an interrupt.
2193         (interrupt_event): Only deliver interrupts when enabled.
2194
2195 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2196
2197         * interp.c (sim_info): Only print info when verbose.
2198         (sim_info) Use sim_io_printf for output.
2199
2200 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2201
2202         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2203         mips architectures.
2204
2205 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2206
2207         * interp.c (sim_do_command): Check for common commands if a
2208         simulator specific command fails.
2209
2210 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2211
2212         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2213         and simBE when DEBUG is defined.
2214
2215 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2216
2217         * interp.c (interrupt_event): New function.  Pass exception event
2218         onto exception handler.
2219
2220         * configure.in: Check for stdlib.h.
2221         * configure: Regenerate.
2222
2223         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2224         variable declaration.
2225         (build_instruction): Initialize memval1.
2226         (build_instruction): Add UNUSED attribute to byte, bigend,
2227         reverse.
2228         (build_operands): Ditto.
2229
2230         * interp.c: Fix GCC warnings.
2231         (sim_get_quit_code): Delete.
2232
2233         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2234         * Makefile.in: Ditto.
2235         * configure: Re-generate.
2236
2237         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2238
2239 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2240
2241         * interp.c (mips_option_handler): New function parse argumes using
2242         sim-options.
2243         (myname): Replace with STATE_MY_NAME.
2244         (sim_open): Delete check for host endianness - performed by
2245         sim_config.
2246         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2247         (sim_open): Move much of the initialization from here.
2248         (sim_load): To here.  After the image has been loaded and
2249         endianness set.
2250         (sim_open): Move ColdReset from here.
2251         (sim_create_inferior): To here.
2252         (sim_open): Make FP check less dependant on host endianness.
2253
2254         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2255         run.
2256         * interp.c (sim_set_callbacks): Delete.
2257
2258         * interp.c (membank, membank_base, membank_size): Replace with
2259         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2260         (sim_open): Remove call to callback->init. gdb/run do this.
2261
2262         * interp.c: Update
2263
2264         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2265
2266         * interp.c (big_endian_p): Delete, replaced by
2267         current_target_byte_order.
2268
2269 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2270
2271         * interp.c (host_read_long, host_read_word, host_swap_word,
2272         host_swap_long): Delete. Using common sim-endian.
2273         (sim_fetch_register, sim_store_register): Use H2T.
2274         (pipeline_ticks): Delete.  Handled by sim-events.
2275         (sim_info): Update.
2276         (sim_engine_run): Update.
2277
2278 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2279
2280         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2281         reason from here.
2282         (SignalException): To here. Signal using sim_engine_halt.
2283         (sim_stop_reason): Delete, moved to common.
2284
2285 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2286
2287         * interp.c (sim_open): Add callback argument.
2288         (sim_set_callbacks): Delete SIM_DESC argument.
2289         (sim_size): Ditto.
2290
2291 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2292
2293         * Makefile.in (SIM_OBJS): Add common modules.
2294
2295         * interp.c (sim_set_callbacks): Also set SD callback.
2296         (set_endianness, xfer_*, swap_*): Delete.
2297         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2298         Change to functions using sim-endian macros.
2299         (control_c, sim_stop): Delete, use common version.
2300         (simulate): Convert into.
2301         (sim_engine_run): This function.
2302         (sim_resume): Delete.
2303
2304         * interp.c (simulation): New variable - the simulator object.
2305         (sim_kind): Delete global - merged into simulation.
2306         (sim_load): Cleanup.  Move PC assignment from here.
2307         (sim_create_inferior): To here.
2308
2309         * sim-main.h: New file.
2310         * interp.c (sim-main.h): Include.
2311
2312 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2313
2314         * configure: Regenerated to track ../common/aclocal.m4 changes.
2315
2316 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2317
2318         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2319
2320 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2321
2322         * gencode.c (build_instruction): DIV instructions: check
2323         for division by zero and integer overflow before using
2324         host's division operation.
2325
2326 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2327
2328         * Makefile.in (SIM_OBJS): Add sim-load.o.
2329         * interp.c: #include bfd.h.
2330         (target_byte_order): Delete.
2331         (sim_kind, myname, big_endian_p): New static locals.
2332         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2333         after argument parsing.  Recognize -E arg, set endianness accordingly.
2334         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2335         load file into simulator.  Set PC from bfd.
2336         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2337         (set_endianness): Use big_endian_p instead of target_byte_order.
2338
2339 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2340
2341         * interp.c (sim_size): Delete prototype - conflicts with
2342         definition in remote-sim.h.  Correct definition.
2343
2344 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2345
2346         * configure: Regenerated to track ../common/aclocal.m4 changes.
2347         * config.in: Ditto.
2348
2349 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2350
2351         * interp.c (sim_open): New arg `kind'.
2352
2353         * configure: Regenerated to track ../common/aclocal.m4 changes.
2354
2355 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2356
2357         * configure: Regenerated to track ../common/aclocal.m4 changes.
2358
2359 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2360
2361         * interp.c (sim_open): Set optind to 0 before calling getopt.
2362
2363 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2364
2365         * configure: Regenerated to track ../common/aclocal.m4 changes.
2366
2367 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2368
2369         * interp.c : Replace uses of pr_addr with pr_uword64
2370         where the bit length is always 64 independent of SIM_ADDR.
2371         (pr_uword64) : added.
2372
2373 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2374
2375         * configure: Re-generate.
2376
2377 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2378
2379         * configure: Regenerate to track ../common/aclocal.m4 changes.
2380
2381 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2382
2383         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2384         in argv form.
2385         (other sim_*): New SIM_DESC argument.
2386
2387 start-sanitize-r5900
2388 Wed Feb 26 18:32:21 1997  Gavin Koch  <gavin@cygnus.com>
2389
2390         * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2391         Change values to avoid overloading DOUBLEWORD which is tested
2392         for all insns.
2393         * gencode.c: reinstate "offending code".
2394
2395 end-sanitize-r5900
2396 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2397
2398         * interp.c: Fix printing of addresses for non-64-bit targets.
2399         (pr_addr): Add function to print address based on size.
2400 start-sanitize-r5900
2401         * gencode.c: #ifdef out offending code until a permanent fix
2402         can be added.  Code is causing build errors for non-5900 mips targets.
2403 end-sanitize-r5900
2404
2405 start-sanitize-r5900
2406 Thu Feb 20 10:40:24 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2407
2408         * gencode.c (process_instructions): Correct test for ISA dependent
2409         architecture bits in isa field of MIPS_DECODE.
2410
2411 end-sanitize-r5900
2412 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2413
2414         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2415
2416 start-sanitize-r5900
2417 Tue Feb 18 17:03:47 1997  Gavin Koch  <gavin@cygnus.com>
2418
2419         * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2420         PMADDUW.
2421
2422 end-sanitize-r5900
2423 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2424
2425         * gencode.c (build_mips16_operands): Correct computation of base
2426         address for extended PC relative instruction.
2427
2428 start-sanitize-r5900
2429 Fri Feb  7 11:12:44 1997  Gavin Koch  <gavin@cygnus.com>
2430
2431         * Makefile.in, configure, configure.in, gencode.c,
2432         interp.c, support.h: add r5900.
2433
2434 end-sanitize-r5900
2435 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2436
2437         * interp.c (mips16_entry): Add support for floating point cases.
2438         (SignalException): Pass floating point cases to mips16_entry.
2439         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2440         registers.
2441         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2442         or fmt_word.
2443         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2444         and then set the state to fmt_uninterpreted.
2445         (COP_SW): Temporarily set the state to fmt_word while calling
2446         ValueFPR.
2447
2448 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2449
2450         * gencode.c (build_instruction): The high order may be set in the
2451         comparison flags at any ISA level, not just ISA 4.
2452
2453 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2454
2455         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2456         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2457         * configure.in: sinclude ../common/aclocal.m4.
2458         * configure: Regenerated.
2459
2460 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2461
2462         * configure: Rebuild after change to aclocal.m4.
2463
2464 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2465
2466         * configure configure.in Makefile.in:  Update to new configure
2467         scheme which is more compatible with WinGDB builds.
2468         * configure.in:  Improve comment on how to run autoconf.
2469         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2470         * Makefile.in:  Use autoconf substitution to install common
2471         makefile fragment.
2472
2473 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2474
2475         * gencode.c (build_instruction): Use BigEndianCPU instead of
2476         ByteSwapMem.
2477
2478 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2479
2480         * interp.c (sim_monitor): Make output to stdout visible in
2481         wingdb's I/O log window.
2482
2483 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2484
2485         * support.h: Undo previous change to SIGTRAP
2486         and SIGQUIT values.
2487
2488 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2489
2490         * interp.c (store_word, load_word): New static functions.
2491         (mips16_entry): New static function.
2492         (SignalException): Look for mips16 entry and exit instructions.
2493         (simulate): Use the correct index when setting fpr_state after
2494         doing a pending move.
2495
2496 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2497
2498         * interp.c: Fix byte-swapping code throughout to work on
2499         both little- and big-endian hosts.
2500
2501 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2502
2503         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2504         with gdb/config/i386/xm-windows.h.
2505
2506 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2507
2508         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2509         that messes up arithmetic shifts.
2510
2511 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2512
2513         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2514         SIGTRAP and SIGQUIT for _WIN32.
2515
2516 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2517
2518         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2519         force a 64 bit multiplication.
2520         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2521         destination register is 0, since that is the default mips16 nop
2522         instruction.
2523
2524 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2525
2526         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2527         (build_endian_shift): Don't check proc64.
2528         (build_instruction): Always set memval to uword64.  Cast op2 to
2529         uword64 when shifting it left in memory instructions.  Always use
2530         the same code for stores--don't special case proc64.
2531
2532         * gencode.c (build_mips16_operands): Fix base PC value for PC
2533         relative operands.
2534         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2535         jal instruction.
2536         * interp.c (simJALDELAYSLOT): Define.
2537         (JALDELAYSLOT): Define.
2538         (INDELAYSLOT, INJALDELAYSLOT): Define.
2539         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2540
2541 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2542
2543         * interp.c (sim_open): add flush_cache as a PMON routine
2544         (sim_monitor): handle flush_cache by ignoring it
2545
2546 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2547
2548         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2549         BigEndianMem.
2550         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2551         (BigEndianMem): Rename to ByteSwapMem and change sense.
2552         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2553         BigEndianMem references to !ByteSwapMem.
2554         (set_endianness): New function, with prototype.
2555         (sim_open): Call set_endianness.
2556         (sim_info): Use simBE instead of BigEndianMem.
2557         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2558         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2559         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2560         ifdefs, keeping the prototype declaration.
2561         (swap_word): Rewrite correctly.
2562         (ColdReset): Delete references to CONFIG.  Delete endianness related
2563         code; moved to set_endianness.
2564
2565 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2566
2567         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2568         * interp.c (CHECKHILO): Define away.
2569         (simSIGINT): New macro.
2570         (membank_size): Increase from 1MB to 2MB.
2571         (control_c): New function.
2572         (sim_resume): Rename parameter signal to signal_number.  Add local
2573         variable prev.  Call signal before and after simulate.
2574         (sim_stop_reason): Add simSIGINT support.
2575         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2576         functions always.
2577         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2578         if logfh is NULL.
2579         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2580         a call to sim_warning.
2581
2582 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2583
2584         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2585         16 bit instructions.
2586
2587 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2588
2589         Add support for mips16 (16 bit MIPS implementation):
2590         * gencode.c (inst_type): Add mips16 instruction encoding types.
2591         (GETDATASIZEINSN): Define.
2592         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2593         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2594         mtlo.
2595         (MIPS16_DECODE): New table, for mips16 instructions.
2596         (bitmap_val): New static function.
2597         (struct mips16_op): Define.
2598         (mips16_op_table): New table, for mips16 operands.
2599         (build_mips16_operands): New static function.
2600         (process_instructions): If PC is odd, decode a mips16
2601         instruction.  Break out instruction handling into new
2602         build_instruction function.
2603         (build_instruction): New static function, broken out of
2604         process_instructions.  Check modifiers rather than flags for SHIFT
2605         bit count and m[ft]{hi,lo} direction.
2606         (usage): Pass program name to fprintf.
2607         (main): Remove unused variable this_option_optind.  Change
2608         ``*loptarg++'' to ``loptarg++''.
2609         (my_strtoul): Parenthesize && within ||.
2610         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2611         (simulate): If PC is odd, fetch a 16 bit instruction, and
2612         increment PC by 2 rather than 4.
2613         * configure.in: Add case for mips16*-*-*.
2614         * configure: Rebuild.
2615
2616 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2617
2618         * interp.c: Allow -t to enable tracing in standalone simulator.
2619         Fix garbage output in trace file and error messages.
2620
2621 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2622
2623         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2624         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2625         * configure.in: Simplify using macros in ../common/aclocal.m4.
2626         * configure: Regenerated.
2627         * tconfig.in: New file.
2628
2629 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2630
2631         * interp.c: Fix bugs in 64-bit port.
2632         Use ansi function declarations for msvc compiler.
2633         Initialize and test file pointer in trace code.
2634         Prevent duplicate definition of LAST_EMED_REGNUM.
2635
2636 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2637
2638         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2639
2640 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2641
2642         * interp.c (SignalException): Check for explicit terminating
2643         breakpoint value.
2644         * gencode.c: Pass instruction value through SignalException()
2645         calls for Trap, Breakpoint and Syscall.
2646
2647 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2648
2649         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2650         only used on those hosts that provide it.
2651         * configure.in: Add sqrt() to list of functions to be checked for.
2652         * config.in: Re-generated.
2653         * configure: Re-generated.
2654
2655 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2656
2657         * gencode.c (process_instructions): Call build_endian_shift when
2658         expanding STORE RIGHT, to fix swr.
2659         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2660         clear the high bits.
2661         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2662         Fix float to int conversions to produce signed values.
2663
2664 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2665
2666         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2667         (process_instructions): Correct handling of nor instruction.
2668         Correct shift count for 32 bit shift instructions. Correct sign
2669         extension for arithmetic shifts to not shift the number of bits in
2670         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2671         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2672         Fix madd.
2673         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2674         It's OK to have a mult follow a mult.  What's not OK is to have a
2675         mult follow an mfhi.
2676         (Convert): Comment out incorrect rounding code.
2677
2678 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2679
2680         * interp.c (sim_monitor): Improved monitor printf
2681         simulation. Tidied up simulator warnings, and added "--log" option
2682         for directing warning message output.
2683         * gencode.c: Use sim_warning() rather than WARNING macro.
2684
2685 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2686
2687         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2688         getopt1.o, rather than on gencode.c.  Link objects together.
2689         Don't link against -liberty.
2690         (gencode.o, getopt.o, getopt1.o): New targets.
2691         * gencode.c: Include <ctype.h> and "ansidecl.h".
2692         (AND): Undefine after including "ansidecl.h".
2693         (ULONG_MAX): Define if not defined.
2694         (OP_*): Don't define macros; now defined in opcode/mips.h.
2695         (main): Call my_strtoul rather than strtoul.
2696         (my_strtoul): New static function.
2697
2698 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2699
2700         * gencode.c (process_instructions):  Generate word64 and uword64
2701         instead of `long long' and `unsigned long long' data types.
2702         * interp.c:  #include sysdep.h to get signals, and define default
2703         for SIGBUS.
2704         * (Convert):  Work around for Visual-C++ compiler bug with type
2705         conversion.
2706         * support.h:  Make things compile under Visual-C++ by using
2707         __int64 instead of `long long'.  Change many refs to long long
2708         into word64/uword64 typedefs.
2709
2710 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2711
2712         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2713         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2714         (docdir): Removed.
2715         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2716         (AC_PROG_INSTALL): Added.
2717         (AC_PROG_CC): Moved to before configure.host call.
2718         * configure: Rebuilt.
2719
2720 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2721
2722         * configure.in: Define @SIMCONF@ depending on mips target.
2723         * configure: Rebuild.
2724         * Makefile.in (run): Add @SIMCONF@ to control simulator
2725         construction.
2726         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2727         * interp.c: Remove some debugging, provide more detailed error
2728         messages, update memory accesses to use LOADDRMASK.
2729
2730 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2731
2732         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2733         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2734         stamp-h.
2735         * configure: Rebuild.
2736         * config.in: New file, generated by autoheader.
2737         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2738         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2739         HAVE_ANINT and HAVE_AINT, as appropriate.
2740         * Makefile.in (run): Use @LIBS@ rather than -lm.
2741         (interp.o): Depend upon config.h.
2742         (Makefile): Just rebuild Makefile.
2743         (clean): Remove stamp-h.
2744         (mostlyclean): Make the same as clean, not as distclean.
2745         (config.h, stamp-h): New targets.
2746
2747 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2748
2749         * interp.c (ColdReset): Fix boolean test. Make all simulator
2750         globals static.
2751
2752 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2753
2754         * interp.c (xfer_direct_word, xfer_direct_long,
2755         swap_direct_word, swap_direct_long, xfer_big_word,
2756         xfer_big_long, xfer_little_word, xfer_little_long,
2757         swap_word,swap_long): Added.
2758         * interp.c (ColdReset): Provide function indirection to
2759         host<->simulated_target transfer routines.
2760         * interp.c (sim_store_register, sim_fetch_register): Updated to
2761         make use of indirected transfer routines.
2762
2763 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2764
2765         * gencode.c (process_instructions): Ensure FP ABS instruction
2766         recognised.
2767         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2768         system call support.
2769
2770 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2771
2772         * interp.c (sim_do_command): Complain if callback structure not
2773         initialised.
2774
2775 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2776
2777         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2778         support for Sun hosts.
2779         * Makefile.in (gencode): Ensure the host compiler and libraries
2780         used for cross-hosted build.
2781
2782 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2783
2784         * interp.c, gencode.c: Some more (TODO) tidying.
2785
2786 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2787
2788         * gencode.c, interp.c: Replaced explicit long long references with
2789         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2790         * support.h (SET64LO, SET64HI): Macros added.
2791
2792 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2793
2794         * configure: Regenerate with autoconf 2.7.
2795
2796 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2797
2798         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2799         * support.h: Remove superfluous "1" from #if.
2800         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2801
2802 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2803
2804         * interp.c (StoreFPR): Control UndefinedResult() call on
2805         WARN_RESULT manifest.
2806
2807 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2808
2809         * gencode.c: Tidied instruction decoding, and added FP instruction
2810         support.
2811
2812         * interp.c: Added dineroIII, and BSD profiling support. Also
2813         run-time FP handling.
2814
2815 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2816
2817         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2818         gencode.c, interp.c, support.h: created.