sim/mips/mips.igen

   1 //    <insn> ::=
   2 //        <insn-word> { "+" <insn-word> }
   3 //        ":" <format-name>
   4 //        ":" <filter-flags>
   5 //        ":" <options>
   6 //        ":" <name>
   7 //        <nl>
   8 //        { <insn-model> }
   9 //        { <insn-mnemonic> }
  10 //        <code-block>
  11 //
  12
  13
  14 // IGEN config - mips16
  15 :option:16:insn-bit-size:16
  16 :option:16:hi-bit-nr:15
  17 :option:16:insn-specifying-widths:true
  18 :option:16:gen-delayed-branch:true
  19
  20 // IGEN config - mipsI..
  21 :option:32:insn-bit-size:32
  22 :option:32:hi-bit-nr:31
  23 :option:32:insn-specifying-widths:true
  24 :option:32:gen-delayed-branch:true
  25
  26
  27 // Generate separate simulators for each target
  28 :option::multi-sim:true
  29
  30
  31 // Models known by this simulator
  32 :model::mipsI:mipsI:
  33 :model::mipsII:mipsII:
  34 :model::mipsIII:mipsIII:
  35 :model::mipsIV:mipsIV:
  36 :model::mips16:mips16:
  37 // start-sanitize-r5900
  38 :model::r5900:r5900:
  39 // end-sanitize-r5900
  40 :model::r3900:r3900:
  41 // start-sanitize-tx19
  42 :model::tx19:tx19:
  43 // end-sanitize-tx19
  44
  45
  46
  47 // Pseudo instructions known by IGEN
  48 :internal:::illegal
  49 {
  50   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  51                   (unsigned long) CIA);
  52   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  53 }
  54
  55
  56
  57
  58 //
  59 // MIPS Architecture:
  60 //
  61 //        CPU Instruction Set (mipsI - mipsIV)
  62 //
  63
  64
  65 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  66 "add r<RD>, r<RS>, r<RT>"
  67 *mipsI:
  68 *mipsII:
  69 *mipsIII:
  70 *mipsIV:
  71 // start-sanitize-r5900
  72 *r5900:
  73 // end-sanitize-r5900
  74 *r3900:
  75 // start-sanitize-tx19
  76 *tx19:
  77 // end-sanitize-tx19
  78 {
  79   ALU32_BEGIN (GPR[RS]);
  80   ALU32_ADD (GPR[RT]);
  81   ALU32_END (GPR[RD]);
  82 }
  83
  84
  85 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
  86 "addi r<RT>, r<RS>, IMMEDIATE"
  87 *mipsI:
  88 *mipsII:
  89 *mipsIII:
  90 *mipsIV:
  91 // start-sanitize-r5900
  92 *r5900:
  93 // end-sanitize-r5900
  94 *r3900:
  95 // start-sanitize-tx19
  96 *tx19:
  97 // end-sanitize-tx19
  98 {
  99   ALU32_BEGIN (GPR[RS]);
 100   ALU32_ADD (EXTEND16 (IMMEDIATE));
 101   ALU32_END (GPR[RT]);
 102 }
 103
 104
 105 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 106 "add r<RT>, r<RS>, IMMEDIATE"
 107 *mipsI:
 108 *mipsII:
 109 *mipsIII:
 110 *mipsIV:
 111 // start-sanitize-r5900
 112 *r5900:
 113 // end-sanitize-r5900
 114 *r3900:
 115 // start-sanitize-tx19
 116 *tx19:
 117 // end-sanitize-tx19
 118 {
 119   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 120   GPR[RT] = EXTEND32 (temp);
 121 }
 122
 123
 124 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 125 *mipsI:
 126 *mipsII:
 127 *mipsIII:
 128 *mipsIV:
 129 // start-sanitize-r5900
 130 *r5900:
 131 // end-sanitize-r5900
 132 *r3900:
 133 // start-sanitize-tx19
 134 *tx19:
 135 // end-sanitize-tx19
 136 {
 137   signed32 temp = GPR[RS] + GPR[RT];
 138   GPR[RD] = EXTEND32 (temp);
 139 }
 140
 141
 142 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 143 "and r<RD>, r<RS>, r<RT>"
 144 *mipsI:
 145 *mipsII:
 146 *mipsIII:
 147 *mipsIV:
 148 // start-sanitize-r5900
 149 *r5900:
 150 // end-sanitize-r5900
 151 *r3900:
 152 // start-sanitize-tx19
 153 *tx19:
 154 // end-sanitize-tx19
 155 {
 156   GPR[RD] = GPR[RS] & GPR[RT];
 157 }
 158
 159
 160 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 161 "and r<RT>, r<RS>, IMMEDIATE"
 162 *mipsI:
 163 *mipsII:
 164 *mipsIII:
 165 // start-sanitize-r5900
 166 *r5900:
 167 // end-sanitize-r5900
 168 *r3900:
 169 // start-sanitize-tx19
 170 *tx19:
 171 // end-sanitize-tx19
 172 {
 173   GPR[RT] = GPR[RS] & IMMEDIATE;
 174 }
 175
 176
 177 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 178 "beq r<RS>, r<RT>, OFFSET"
 179 *mipsI:
 180 *mipsII:
 181 *mipsIII:
 182 *mipsIV:
 183 // start-sanitize-r5900
 184 *r5900:
 185 // end-sanitize-r5900
 186 *r3900:
 187 // start-sanitize-tx19
 188 *tx19:
 189 // end-sanitize-tx19
 190 {
 191   address_word offset = EXTEND16 (OFFSET) << 2;
 192   if (GPR[RS] == GPR[RT])
 193     DSPC = (PC + offset);
 194 }
 195
 196
 197 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 198 "beql r<RS>, r<RT>, <OFFSET>"
 199 *mipsII:
 200 *mipsIII:
 201 *mipsIV:
 202 // start-sanitize-r5900
 203 *r5900:
 204 // end-sanitize-r5900
 205 *r3900:
 206 // start-sanitize-tx19
 207 *tx19:
 208 // end-sanitize-tx19
 209 {
 210   address_word offset = EXTEND16 (OFFSET) << 2;
 211   if (GPR[RS] == GPR[RT])
 212     DSPC = (PC + offset);
 213   else
 214     NULLIFY_NIA ();
 215 }
 216
 217
 218 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 219 "bgez r<RS>, <OFFSET>"
 220 *mipsI:
 221 *mipsII:
 222 *mipsIII:
 223 *mipsIV:
 224 // start-sanitize-r5900
 225 *r5900:
 226 // end-sanitize-r5900
 227 *r3900:
 228 // start-sanitize-tx19
 229 *tx19:
 230 // end-sanitize-tx19
 231 {
 232   address_word offset = EXTEND16 (OFFSET) << 2;
 233   if (GPR[RS] >= 0)
 234     DSPC = (PC + offset);
 235 }
 236
 237
 238 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 239 "bgezal r<RS>, <OFFSET>"
 240 *mipsI:
 241 *mipsII:
 242 *mipsIII:
 243 *mipsIV:
 244 // start-sanitize-r5900
 245 *r5900:
 246 // end-sanitize-r5900
 247 *r3900:
 248 // start-sanitize-tx19
 249 *tx19:
 250 // end-sanitize-tx19
 251 {
 252   address_word offset = EXTEND16 (OFFSET) << 2;
 253   RA = (CIA + 8);
 254   if (GPR[RS] >= 0)
 255     DSPC = (PC + offset);
 256 }
 257
 258
 259 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 260 "bgezall r<RS>, <OFFSET>"
 261 *mipsII:
 262 *mipsIII:
 263 *mipsIV:
 264 // start-sanitize-r5900
 265 *r5900:
 266 // end-sanitize-r5900
 267 *r3900:
 268 // start-sanitize-tx19
 269 *tx19:
 270 // end-sanitize-tx19
 271 {
 272   address_word offset = EXTEND16 (OFFSET) << 2;
 273   RA = (CIA + 8);
 274   /* NOTE: The branch occurs AFTER the next instruction has been
 275      executed */
 276   if (GPR[RS] >= 0)
 277     DSPC = (PC + offset);
 278   else
 279     NULLIFY_NIA ();
 280 }
 281
 282
 283 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 284 "bgezl r<RS>, <OFFSET>"
 285 *mipsII:
 286 *mipsIII:
 287 *mipsIV:
 288 // start-sanitize-r5900
 289 *r5900:
 290 // end-sanitize-r5900
 291 *r3900:
 292 // start-sanitize-tx19
 293 *tx19:
 294 // end-sanitize-tx19
 295 {
 296   address_word offset = EXTEND16 (OFFSET) << 2;
 297   if (GPR[RS] >= 0)
 298     DSPC = (PC + offset);
 299   else
 300     NULLIFY_NIA ();
 301 }
 302
 303
 304 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 305 "bgtz r<RS>, <OFFSET>"
 306 *mipsI:
 307 *mipsII:
 308 *mipsIII:
 309 *mipsIV:
 310 // start-sanitize-r5900
 311 *r5900:
 312 // end-sanitize-r5900
 313 *r3900:
 314 // start-sanitize-tx19
 315 *tx19:
 316 // end-sanitize-tx19
 317 {
 318   address_word offset = EXTEND16 (OFFSET) << 2;
 319   if (GPR[RS] > 0)
 320     DSPC = (PC + offset);
 321 }
 322
 323
 324 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 325 "bgtzl r<RS>, <OFFSET>"
 326 *mipsII:
 327 *mipsIII:
 328 *mipsIV:
 329 // start-sanitize-r5900
 330 *r5900:
 331 // end-sanitize-r5900
 332 *r3900:
 333 // start-sanitize-tx19
 334 *tx19:
 335 // end-sanitize-tx19
 336 {
 337   address_word offset = EXTEND16 (OFFSET) << 2;
 338   /* NOTE: The branch occurs AFTER the next instruction has been
 339      executed */
 340   if (GPR[RS] > 0)
 341     DSPC = (PC + offset);
 342   else
 343     NULLIFY_NIA ();
 344 }
 345
 346
 347 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 348 "blez r<RS>, <OFFSET>"
 349 *mipsI:
 350 *mipsII:
 351 *mipsIII:
 352 *mipsIV:
 353 // start-sanitize-r5900
 354 *r5900:
 355 // end-sanitize-r5900
 356 *r3900:
 357 // start-sanitize-tx19
 358 *tx19:
 359 // end-sanitize-tx19
 360 {
 361   address_word offset = EXTEND16 (OFFSET) << 2;
 362   /* NOTE: The branch occurs AFTER the next instruction has been
 363      executed */
 364   if (GPR[RS] <= 0)
 365     DSPC = (PC + offset);
 366 }
 367
 368
 369 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 370 "bgezl r<RS>, <OFFSET>"
 371 *mipsII:
 372 *mipsIII:
 373 *mipsIV:
 374 // start-sanitize-r5900
 375 *r5900:
 376 // end-sanitize-r5900
 377 *r3900:
 378 // start-sanitize-tx19
 379 *tx19:
 380 // end-sanitize-tx19
 381 {
 382   address_word offset = EXTEND16 (OFFSET) << 2;
 383   /* NOTE: The branch occurs AFTER the next instruction has been
 384      executed */
 385   if (GPR[RS] <= 0)
 386     {
 387       DSPC = (PC + offset);
 388       DELAYSLOT ();
 389     }
 390   else
 391     NULLIFY ();
 392 }
 393
 394
 395 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 396 "bltz r<RS>, <OFFSET>"
 397 *mipsI:
 398 *mipsII:
 399 *mipsIII:
 400 *mipsIV:
 401 // start-sanitize-r5900
 402 *r5900:
 403 // end-sanitize-r5900
 404 *r3900:
 405 // start-sanitize-tx19
 406 *tx19:
 407 // end-sanitize-tx19
 408 {
 409   address_word offset = EXTEND16 (OFFSET) << 2;
 410   if (GPR[RS] < 0)
 411     DSPC = (PC + offset);
 412 }
 413
 414
 415 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 416 "bltzal r<RS>, <OFFSET>"
 417 *mipsI:
 418 *mipsII:
 419 *mipsIII:
 420 *mipsIV:
 421 // start-sanitize-r5900
 422 *r5900:
 423 // end-sanitize-r5900
 424 *r3900:
 425 // start-sanitize-tx19
 426 *tx19:
 427 // end-sanitize-tx19
 428 {
 429   address_word offset = EXTEND16 (OFFSET) << 2;
 430   RA = (CIA + 8);
 431   /* NOTE: The branch occurs AFTER the next instruction has been
 432      executed */
 433   if (GPR[RS] < 0)
 434     DSPC = (PC + offset);
 435 }
 436
 437
 438 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 439 "bltzall r<RS>, <OFFSET>"
 440 *mipsII:
 441 *mipsIII:
 442 *mipsIV:
 443 // start-sanitize-r5900
 444 *r5900:
 445 // end-sanitize-r5900
 446 *r3900:
 447 // start-sanitize-tx19
 448 *tx19:
 449 // end-sanitize-tx19
 450 {
 451   address_word offset = EXTEND16 (OFFSET) << 2;
 452   RA = (CIA + 8);
 453   if (GPR[RS] < 0)
 454     DSPC = (PC + offset);
 455   else
 456     NULLIFY_NIA ();
 457 }
 458
 459
 460 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 461 "bltzl r<RS>, <OFFSET>"
 462 *mipsII:
 463 *mipsIII:
 464 *mipsIV:
 465 // start-sanitize-r5900
 466 *r5900:
 467 // end-sanitize-r5900
 468 *r3900:
 469 // start-sanitize-tx19
 470 *tx19:
 471 // end-sanitize-tx19
 472 {
 473   address_word offset = EXTEND16 (OFFSET) << 2;
 474   /* NOTE: The branch occurs AFTER the next instruction has been
 475      executed */
 476   if (GPR[RS] < 0)
 477     DSPC = (PC + offset);
 478   else
 479     NULLIFY_NIA ();
 480 }
 481
 482
 483 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 484 "bne r<RS>, r<RT>, <OFFSET>"
 485 *mipsI:
 486 *mipsII:
 487 *mipsIII:
 488 *mipsIV:
 489 // start-sanitize-r5900
 490 *r5900:
 491 // end-sanitize-r5900
 492 *r3900:
 493 // start-sanitize-tx19
 494 *tx19:
 495 // end-sanitize-tx19
 496 {
 497   address_word offset = EXTEND16 (OFFSET) << 2;
 498   if (GPR[RS] != GPR[RT])
 499     DSPC = (PC + offset);
 500 }
 501
 502
 503 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 504 "bnel r<RS>, r<RT>, <OFFSET>"
 505 *mipsII:
 506 *mipsIII:
 507 *mipsIV:
 508 // start-sanitize-r5900
 509 *r5900:
 510 // end-sanitize-r5900
 511 *r3900:
 512 // start-sanitize-tx19
 513 *tx19:
 514 // end-sanitize-tx19
 515 {
 516   /* NOTE: The branch occurs AFTER the next instruction has been
 517      executed */
 518   if (GPR[RS] != GPR[RT])
 519     {
 520       DSPC = (PC + offset);
 521       DELAYSLOT ();
 522     }
 523   else
 524     NULLIFY ();
 525 }
 526
 527
 528 000000,20.CODE,001101:SPECIAL:32::BREAK
 529 "break"
 530 *mipsI:
 531 *mipsII:
 532 *mipsIII:
 533 *mipsIV:
 534 // start-sanitize-r5900
 535 *r5900:
 536 // end-sanitize-r5900
 537 *r3900:
 538 // start-sanitize-tx19
 539 *tx19:
 540 // end-sanitize-tx19
 541 {
 542   SignalException(BreakPoint, instruction_0);
 543 }
 544
 545
 546 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 547 "cop<ZZ> <COP_FUN>"
 548 *mipsI:
 549 *mipsII:
 550 *mipsIII:
 551 *mipsIV:
 552 // start-sanitize-r5900
 553 *r5900:
 554 // end-sanitize-r5900
 555 *r3900:
 556 // start-sanitize-tx19
 557 *tx19:
 558 // end-sanitize-tx19
 559 {
 560   decode_coproc (SD, instruction_0);
 561 }
 562
 563
 564 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 565 "dadd r<RD>, r<RS>, r<RT>"
 566 *mipsIII:
 567 *mipsIV:
 568 // start-sanitize-r5900
 569 *r5900:
 570 // end-sanitize-r5900
 571 *r3900:
 572 // start-sanitize-tx19
 573 *tx19:
 574 // end-sanitize-tx19
 575 {
 576   ALU64_BEGIN (GPR[RS]);
 577   ALU64_ADD (GPR[RT]);
 578   ALU64_END (GPR[RT]);
 579 }
 580
 581
 582 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 583 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 584 *mipsIII:
 585 *mipsIV:
 586 // start-sanitize-r5900
 587 *r5900:
 588 // end-sanitize-r5900
 589 *r3900:
 590 // start-sanitize-tx19
 591 *tx19:
 592 // end-sanitize-tx19
 593 {
 594   ALU64_BEGIN (GPR[RS]);
 595   ALU64_ADD (EXTEND16 (IMMEDIATE));
 596   ALU64_END (GPR[RT]);
 597 }
 598
 599
 600 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 601 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 602 *mipsIII:
 603 *mipsIV:
 604 // start-sanitize-r5900
 605 *r5900:
 606 // end-sanitize-r5900
 607 *r3900:
 608 // start-sanitize-tx19
 609 *tx19:
 610 // end-sanitize-tx19
 611 {
 612   GPR[RT] = GPR[RS] + EXTEND16 (immediate);
 613 }
 614
 615
 616 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 617 "daddu r<RD>, r<RS>, r<RT>"
 618 *mipsIII:
 619 *mipsIV:
 620 // start-sanitize-r5900
 621 *r5900:
 622 // end-sanitize-r5900
 623 *r3900:
 624 // start-sanitize-tx19
 625 *tx19:
 626 // end-sanitize-tx19
 627 {
 628   GPR[RD] = GPR[RS] + GPR[RT];
 629 }
 630
 631
 632 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 633 "ddiv r<RS>, r<RT>"
 634 *mipsIII:
 635 *mipsIV:
 636 // start-sanitize-r5900
 637 *r5900:
 638 // end-sanitize-r5900
 639 *r3900:
 640 // start-sanitize-tx19
 641 *tx19:
 642 // end-sanitize-tx19
 643 {
 644   CHECKHILO ("Division");
 645   {
 646     signed64 n = GPR[RS];
 647     signed64 d = GPR[RT];
 648     if (d == 0)
 649       {
 650         LO = SIGNED64 (0x8000000000000000);
 651         HI = 0;
 652       }
 653     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 654       {
 655         LO = SIGNED64 (0x8000000000000000);
 656         HI = 0;
 657       }
 658     else
 659       {
 660         LO = (n / d);
 661         HI = (n % d);
 662       }
 663   }
 664 }
 665
 666
 667
 668 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 669 "ddivu r<RS>, r<RT>"
 670 *mipsIII:
 671 *mipsIV:
 672 *r3900:
 673 // start-sanitize-tx19
 674 *tx19:
 675 // end-sanitize-tx19
 676 {
 677   CHECKHILO ("Division");
 678   {
 679     unsigned64 n = GPR[RS];
 680     unsigned64 d = GPR[RT];
 681     if (d == 0)
 682       {
 683         LO = SIGNED64 (0x8000000000000000);
 684         HI = 0;
 685       }
 686     else
 687       {
 688         LO = (n / d);
 689         HI = (n % d);
 690       }
 691   }
 692 }
 693
 694
 695 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 696 "div r<RS>, r<RT>"
 697 *mipsI:
 698 *mipsII:
 699 *mipsIII:
 700 *mipsIV:
 701 // start-sanitize-r5900
 702 *r5900:
 703 // end-sanitize-r5900
 704 *r3900:
 705 // start-sanitize-tx19
 706 *tx19:
 707 // end-sanitize-tx19
 708 {
 709   CHECKHILO("Division");
 710   {
 711     signed32 n = GPR[RS];
 712     signed32 d = GPR[RT];
 713     if (d == 0)
 714       {
 715         LO = EXTEND32 (0x80000000);
 716         HI = EXTEND32 (0);
 717       }
 718     else if (d == -1 && d == 0x80000000)
 719       {
 720         LO = EXTEND32 (0x80000000);
 721         HI = EXTEND32 (0);
 722       }
 723     else
 724       {
 725         LO = EXTEND32 (n / d);
 726         HI = EXTEND32 (n % d);
 727       }
 728   }
 729 }
 730
 731
 732 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 733 "divu r<RS>, r<RT>"
 734 *mipsI:
 735 *mipsII:
 736 *mipsIII:
 737 *mipsIV:
 738 // start-sanitize-r5900
 739 *r5900:
 740 // end-sanitize-r5900
 741 *r3900:
 742 // start-sanitize-tx19
 743 *tx19:
 744 // end-sanitize-tx19
 745 {
 746   CHECKHILO ("Division");
 747   {
 748     unsigned32 n = GPR[RS];
 749     unsigned32 d = GPR[RT];
 750     if (d == 0)
 751       {
 752         LO = EXTEND32 (0x80000000);
 753         HI = EXTEND32 (0);
 754       }
 755    else
 756      {
 757        LO = EXTEND32 (n / d);
 758        HI = EXTEND32 (n % d);
 759      }
 760   }
 761 }
 762
 763
 764 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 765 "dmult r<RS>, r<RT>"
 766 *mipsIII:
 767 *mipsIV:
 768 *r3900:
 769 // start-sanitize-tx19
 770 *tx19:
 771 // end-sanitize-tx19
 772 {
 773   CHECKHILO ("Multiplication");
 774   {
 775     signed64 op1 = GPR[RS];
 776     signed64 op2 = GPR[RT];
 777     unsigned64 lo;
 778     unsigned64 hi;
 779     unsigned64 m00;
 780     unsigned64 m01;
 781     unsigned64 m10;
 782     unsigned64 m11;
 783     unsigned64 mid;
 784     int sign = 0;
 785     /* make it unsigned */
 786     if (op1 < 0)
 787       {
 788         op1 = - op1;
 789         ++sign;
 790       }
 791     if (op2 < 0)
 792       {
 793         op2 = - op2;
 794         ++sign;
 795       }
 796     /* multuply out the 4 sub products */
 797     m00 = (VL4_8 (op1) * VL4_8 (op2));
 798     m10 = (VH4_8 (op1) * VL4_8 (op2));
 799     m01 = (VL4_8 (op1) * VH4_8 (op2));
 800     m11 = (VH4_8 (op1) * VH4_8 (op2));
 801     /* add the products */
 802     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 803     lo = U8_4 (mid, m00);
 804     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 805     /* save the result */
 806     if (sign & 1)
 807       {
 808         LO = -lo;
 809         if (lo == 0)
 810           HI = -hi;
 811         else
 812           HI = -hi - 1;
 813       }
 814     else
 815       {
 816         LO = lo;
 817         HI = hi;
 818       }
 819   }
 820 }
 821
 822
 823 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 824 "dmultu r<RS>, r<RT>"
 825 *mipsIII:
 826 *mipsIV:
 827 *r3900:
 828 // start-sanitize-tx19
 829 *tx19:
 830 // end-sanitize-tx19
 831 {
 832   CHECKHILO ("Multiplication");
 833   {
 834     signed64 op1 = GPR[RS];
 835     signed64 op2 = GPR[RT];
 836     unsigned64 lo;
 837     unsigned64 hi;
 838     unsigned64 m00;
 839     unsigned64 m01;
 840     unsigned64 m10;
 841     unsigned64 m11;
 842     unsigned64 mid;
 843     /* multuply out the 4 sub products */
 844     m00 = (VL4_8 (op1) * VL4_8 (op2));
 845     m10 = (VH4_8 (op1) * VL4_8 (op2));
 846     m01 = (VL4_8 (op1) * VH4_8 (op2));
 847     m11 = (VH4_8 (op1) * VH4_8 (op2));
 848     /* add the products */
 849     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 850     lo = U8_4 (mid, m00);
 851     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 852     /* save the result */
 853     LO = lo;
 854     HI = hi;
 855   }
 856 }
 857
 858
 859 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 860 "dsll r<RD>, r<RT>, <SA>"
 861 *mipsIII:
 862 *mipsIV:
 863 // start-sanitize-r5900
 864 *r5900:
 865 // end-sanitize-r5900
 866 *r3900:
 867 // start-sanitize-tx19
 868 *tx19:
 869 // end-sanitize-tx19
 870 {
 871   int s = SA;
 872   GPR[RD] = GPR[RT] << s;
 873 }
 874
 875
 876 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
 877 "dsll32 r<RD>, r<RT>, <SA>"
 878 *mipsIII:
 879 *mipsIV:
 880 // start-sanitize-r5900
 881 *r5900:
 882 // end-sanitize-r5900
 883 *r3900:
 884 // start-sanitize-tx19
 885 *tx19:
 886 // end-sanitize-tx19
 887 {
 888   int s = 32 + SA;
 889   GPR[RD] = GPR[RT] << s;
 890 }
 891
 892
 893 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 894 "dsllv r<RD>, r<RT>, r<RS>"
 895 *mipsIII:
 896 *mipsIV:
 897 // start-sanitize-r5900
 898 *r5900:
 899 // end-sanitize-r5900
 900 *r3900:
 901 // start-sanitize-tx19
 902 *tx19:
 903 // end-sanitize-tx19
 904 {
 905   int s = MASKED64 (GPR[RS], 5, 0);
 906   GPR[RD] = GPR[RT] << s;
 907 }
 908
 909
 910 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
 911 "dsra r<RD>, r<RT>, <SA>"
 912 *mipsIII:
 913 *mipsIV:
 914 // start-sanitize-r5900
 915 *r5900:
 916 // end-sanitize-r5900
 917 *r3900:
 918 // start-sanitize-tx19
 919 *tx19:
 920 // end-sanitize-tx19
 921 {
 922   int s = SA;
 923   GPR[RD] = ((signed64) GPR[RT]) >> s;
 924 }
 925
 926
 927 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
 928 "dsra32 r<RT>, r<RD>, <SA>"
 929 *mipsIII:
 930 *mipsIV:
 931 // start-sanitize-r5900
 932 *r5900:
 933 // end-sanitize-r5900
 934 *r3900:
 935 // start-sanitize-tx19
 936 *tx19:
 937 // end-sanitize-tx19
 938 {
 939   int s = 32 + SA;
 940   GPR[RD] = ((signed64) GPR[RT]) >> s;
 941 }
 942
 943
 944 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
 945 "dsra32 r<RT>, r<RD>, r<RS>"
 946 *mipsIII:
 947 *mipsIV:
 948 // start-sanitize-r5900
 949 *r5900:
 950 // end-sanitize-r5900
 951 *r3900:
 952 // start-sanitize-tx19
 953 *tx19:
 954 // end-sanitize-tx19
 955 {
 956   int s = MASKED64 (GPR[RS], 5, 0);
 957   GPR[RD] = ((signed64) GPR[RT]) >> s;
 958 }
 959
 960
 961 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
 962 "dsrav r<RD>, r<RT>, <SA>"
 963 *mipsIII:
 964 *mipsIV:
 965 // start-sanitize-r5900
 966 *r5900:
 967 // end-sanitize-r5900
 968 *r3900:
 969 // start-sanitize-tx19
 970 *tx19:
 971 // end-sanitize-tx19
 972 {
 973   int s = SA;
 974   GPR[RD] = (unsigned64) GPR[RT] >> s;
 975 }
 976
 977
 978 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
 979 "dsrl32 r<RD>, r<RT>, <SA>"
 980 *mipsIII:
 981 *mipsIV:
 982 // start-sanitize-r5900
 983 *r5900:
 984 // end-sanitize-r5900
 985 *r3900:
 986 // start-sanitize-tx19
 987 *tx19:
 988 // end-sanitize-tx19
 989 {
 990   int s = 32 + SA;
 991   GPR[RD] = (unsigned64) GPR[RT] >> s;
 992 }
 993
 994
 995 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
 996 "dsrl32 r<RD>, r<RT>, r<RS>"
 997 *mipsIII:
 998 *mipsIV:
 999 // start-sanitize-r5900
1000 *r5900:
1001 // end-sanitize-r5900
1002 *r3900:
1003 // start-sanitize-tx19
1004 *tx19:
1005 // end-sanitize-tx19
1006 {
1007   int s = MASKED64 (GPR[RS], 5, 0);
1008   GPR[RD] = (unsigned64) GPR[RT] >> s;
1009 }
1010
1011
1012 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1013 "dsub r<RD>, r<RS>, r<RT>"
1014 *mipsIII:
1015 *mipsIV:
1016 // start-sanitize-r5900
1017 *r5900:
1018 // end-sanitize-r5900
1019 *r3900:
1020 // start-sanitize-tx19
1021 *tx19:
1022 // end-sanitize-tx19
1023 {
1024   ALU64_BEGIN (GPR[RS]);
1025   ALU64_SUB (GPR[RT]);
1026   ALU64_END (GPR[RD]);
1027 }
1028
1029
1030 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1031 "dsubu r<RD>, r<RS>, r<RT>"
1032 *mipsIII:
1033 *mipsIV:
1034 // start-sanitize-r5900
1035 *r5900:
1036 // end-sanitize-r5900
1037 *r3900:
1038 // start-sanitize-tx19
1039 *tx19:
1040 // end-sanitize-tx19
1041 {
1042   GPR[RD] = GPR[RS] - GPR[RT];
1043 }
1044
1045
1046 000010,26.INSTR_INDEX:NORMAL:32::J
1047 "j <INSTR_INDEX>"
1048 *mipsI:
1049 *mipsII:
1050 *mipsIII:
1051 *mipsIV:
1052 // start-sanitize-r5900
1053 *r5900:
1054 // end-sanitize-r5900
1055 *r3900:
1056 // start-sanitize-tx19
1057 *tx19:
1058 // end-sanitize-tx19
1059 {
1060   /* NOTE: The region used is that of the delay slot and NOT the
1061      current instruction */
1062   address_word region = cia.dp & MASK (63, 28);
1063   DSPC = region | (INSTR_INDEX << 2);
1064 }
1065
1066
1067 000011,26.INSTR_INDEX:NORMAL:32::JAL
1068 "jal <INSTR_INDEX>"
1069 *mipsI:
1070 *mipsII:
1071 *mipsIII:
1072 *mipsIV:
1073 // start-sanitize-r5900
1074 *r5900:
1075 // end-sanitize-r5900
1076 *r3900:
1077 // start-sanitize-tx19
1078 *tx19:
1079 // end-sanitize-tx19
1080 {
1081   /* NOTE: The region used is that of the delay slot and NOT the
1082      current instruction */
1083   address_word region = cia.dp & MASK (63, 28);
1084   GPR[31] = CIA + 8;
1085   DSPC = region | (INSTR_INDEX << 2);
1086 }
1087
1088
1089 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1090 "jalr r<RS>":RD == 31
1091 "jalr r<RD>, r<RS>"
1092 *mipsI:
1093 *mipsII:
1094 *mipsIII:
1095 *mipsIV:
1096 // start-sanitize-r5900
1097 *r5900:
1098 // end-sanitize-r5900
1099 *r3900:
1100 // start-sanitize-tx19
1101 *tx19:
1102 // end-sanitize-tx19
1103 {
1104   address_word temp = GPR[RS];
1105   GPR[RD] = CIA + 8;
1106   DSPC = temp;
1107 }
1108
1109
1110 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1111 "jr r<RS>"
1112 *mipsI:
1113 *mipsII:
1114 *mipsIII:
1115 *mipsIV:
1116 // start-sanitize-r5900
1117 *r5900:
1118 // end-sanitize-r5900
1119 *r3900:
1120 // start-sanitize-tx19
1121 *tx19:
1122 // end-sanitize-tx19
1123 {
1124   DSPC = GPR[RS];
1125 }
1126
1127
1128 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1129 "lb r<RT>, <OFFSET>(r<BASE>)"
1130 *mipsI:
1131 *mipsII:
1132 *mipsIII:
1133 *mipsIV:
1134 // start-sanitize-r5900
1135 *r5900:
1136 // end-sanitize-r5900
1137 *r3900:
1138 // start-sanitize-tx19
1139 *tx19:
1140 // end-sanitize-tx19
1141 {
1142   unsigned32 instruction = instruction_0;
1143   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1144   int destreg = ((instruction >> 16) & 0x0000001F);
1145   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1146   {
1147     uword64 vaddr = ((uword64)op1 + offset);
1148     uword64 paddr;
1149     int uncached;
1150     {
1151       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1152         {
1153           uword64 memval = 0;
1154           uword64 memval1 = 0;
1155           uword64 mask = 0x7;
1156           unsigned int shift = 0;
1157           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1158           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1159           unsigned int byte;
1160           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1161           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1162           byte = ((vaddr & mask) ^ (bigend << shift));
1163           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1164         }
1165     }
1166   }
1167 }
1168
1169
1170 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1171 "lbu r<RT>, <OFFSET>(r<BASE>)"
1172 *mipsI:
1173 *mipsII:
1174 *mipsIII:
1175 *mipsIV:
1176 // start-sanitize-r5900
1177 *r5900:
1178 // end-sanitize-r5900
1179 *r3900:
1180 // start-sanitize-tx19
1181 *tx19:
1182 // end-sanitize-tx19
1183 {
1184   unsigned32 instruction = instruction_0;
1185   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1186   int destreg = ((instruction >> 16) & 0x0000001F);
1187   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1188   {
1189     unsigned64 vaddr = ((unsigned64)op1 + offset);
1190     unsigned64 paddr;
1191     int uncached;
1192     {
1193       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1194         {
1195           unsigned64 memval = 0;
1196           unsigned64 memval1 = 0;
1197           unsigned64 mask = 0x7;
1198           unsigned int shift = 0;
1199           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1200           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1201           unsigned int byte;
1202           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1203           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1204           byte = ((vaddr & mask) ^ (bigend << shift));
1205           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1206         }
1207     }
1208   }
1209 }
1210
1211
1212 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1213 "ld r<RT>, <OFFSET>(r<BASE>)"
1214 *mipsIII:
1215 *mipsIV:
1216 // start-sanitize-r5900
1217 *r5900:
1218 // end-sanitize-r5900
1219 *r3900:
1220 // start-sanitize-tx19
1221 *tx19:
1222 // end-sanitize-tx19
1223 {
1224   unsigned32 instruction = instruction_0;
1225   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1226   int destreg = ((instruction >> 16) & 0x0000001F);
1227   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1228   {
1229     unsigned64 vaddr = ((unsigned64)op1 + offset);
1230     unsigned64 paddr;
1231     int uncached;
1232     if ((vaddr & 7) != 0)
1233       SignalExceptionAddressLoad();
1234     else
1235       {
1236         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1237           {
1238             unsigned64 memval = 0;
1239             unsigned64 memval1 = 0;
1240             unsigned64 mask = 0x7;
1241             unsigned int shift = 4;
1242             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1243             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1244             unsigned int byte;
1245             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1246             GPR[destreg] = memval;
1247           }
1248       }
1249   }
1250 }
1251
1252
1253 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1254 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1255 *mipsII:
1256 *mipsIII:
1257 *mipsIV:
1258 // start-sanitize-r5900
1259 *r5900:
1260 // end-sanitize-r5900
1261 *r3900:
1262 // start-sanitize-tx19
1263 *tx19:
1264 // end-sanitize-tx19
1265 {
1266   unsigned32 instruction = instruction_0;
1267   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1268   int destreg = ((instruction >> 16) & 0x0000001F);
1269   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1270   {
1271     unsigned64 vaddr = ((unsigned64)op1 + offset);
1272     unsigned64 paddr;
1273     int uncached;
1274     if ((vaddr & 7) != 0)
1275       SignalExceptionAddressLoad();
1276     else
1277       {
1278         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1279           {
1280             unsigned64 memval = 0;
1281             unsigned64 memval1 = 0;
1282             unsigned64 mask = 0x7;
1283             unsigned int shift = 4;
1284             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1285             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1286             unsigned int byte;
1287             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1288             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1289           }
1290       }
1291   }
1292 }
1293
1294
1295 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1296 "ldl r<RT>, <OFFSET>(r<BASE>)"
1297 *mipsIII:
1298 *mipsIV:
1299 // start-sanitize-r5900
1300 *r5900:
1301 // end-sanitize-r5900
1302 *r3900:
1303 // start-sanitize-tx19
1304 *tx19:
1305 // end-sanitize-tx19
1306 {
1307   unsigned32 instruction = instruction_0;
1308   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1309   int destreg = ((instruction >> 16) & 0x0000001F);
1310   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1311   {
1312     unsigned64 vaddr = ((unsigned64)op1 + offset);
1313     unsigned64 paddr;
1314     int uncached;
1315     {
1316       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1317         {
1318           unsigned64 memval = 0;
1319           unsigned64 memval1 = 0;
1320           unsigned64 mask = 7;
1321           unsigned int reverse = (ReverseEndian ? mask : 0);
1322           unsigned int bigend = (BigEndianCPU ? mask : 0);
1323           int byte;
1324           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1325           byte = ((vaddr & mask) ^ bigend);
1326           if (!!ByteSwapMem)
1327             paddr &= ~mask;
1328           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1329           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1330         }
1331     }
1332   }
1333 }
1334
1335
1336 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1337 "ldr r<RT>, <OFFSET>(r<BASE>)"
1338 *mipsIII:
1339 *mipsIV:
1340 // start-sanitize-r5900
1341 *r5900:
1342 // end-sanitize-r5900
1343 *r3900:
1344 // start-sanitize-tx19
1345 *tx19:
1346 // end-sanitize-tx19
1347 {
1348   unsigned32 instruction = instruction_0;
1349   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1350   int destreg = ((instruction >> 16) & 0x0000001F);
1351   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1352   {
1353     unsigned64 vaddr = ((unsigned64)op1 + offset);
1354     unsigned64 paddr;
1355     int uncached;
1356     {
1357       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1358         {
1359           unsigned64 memval = 0;
1360           unsigned64 memval1 = 0;
1361           unsigned64 mask = 7;
1362           unsigned int reverse = (ReverseEndian ? mask : 0);
1363           unsigned int bigend = (BigEndianCPU ? mask : 0);
1364           int byte;
1365           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1366           byte = ((vaddr & mask) ^ bigend);
1367           if (!ByteSwapMem)
1368             paddr &= ~mask;
1369           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1370           {
1371             unsigned64 srcmask;
1372             if (byte == 0)
1373               srcmask = 0;
1374             else
1375               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1376             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1377           }
1378         }
1379     }
1380   }
1381 }
1382
1383
1384 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1385 "lh r<RT>, <OFFSET>(r<BASE>)"
1386 *mipsI:
1387 *mipsII:
1388 *mipsIII:
1389 *mipsIV:
1390 // start-sanitize-r5900
1391 *r5900:
1392 // end-sanitize-r5900
1393 *r3900:
1394 // start-sanitize-tx19
1395 *tx19:
1396 // end-sanitize-tx19
1397 {
1398   unsigned32 instruction = instruction_0;
1399   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1400   int destreg = ((instruction >> 16) & 0x0000001F);
1401   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1402   {
1403     unsigned64 vaddr = ((unsigned64)op1 + offset);
1404     unsigned64 paddr;
1405     int uncached;
1406     if ((vaddr & 1) != 0)
1407       SignalExceptionAddressLoad();
1408     else
1409       {
1410         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1411           {
1412             unsigned64 memval = 0;
1413             unsigned64 memval1 = 0;
1414             unsigned64 mask = 0x7;
1415             unsigned int shift = 1;
1416             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1417             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1418             unsigned int byte;
1419             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1420             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1421             byte = ((vaddr & mask) ^ (bigend << shift));
1422             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1423           }
1424       }
1425   }
1426 }
1427
1428
1429 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1430 "lhu r<RT>, <OFFSET>(r<BASE>)"
1431 *mipsI:
1432 *mipsII:
1433 *mipsIII:
1434 *mipsIV:
1435 // start-sanitize-r5900
1436 *r5900:
1437 // end-sanitize-r5900
1438 *r3900:
1439 // start-sanitize-tx19
1440 *tx19:
1441 // end-sanitize-tx19
1442 {
1443   unsigned32 instruction = instruction_0;
1444   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1445   int destreg = ((instruction >> 16) & 0x0000001F);
1446   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1447   {
1448     unsigned64 vaddr = ((unsigned64)op1 + offset);
1449     unsigned64 paddr;
1450     int uncached;
1451     if ((vaddr & 1) != 0)
1452       SignalExceptionAddressLoad();
1453     else
1454       {
1455         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1456           {
1457             unsigned64 memval = 0;
1458             unsigned64 memval1 = 0;
1459             unsigned64 mask = 0x7;
1460             unsigned int shift = 1;
1461             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1462             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1463             unsigned int byte;
1464             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1465             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1466             byte = ((vaddr & mask) ^ (bigend << shift));
1467             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1468           }
1469       }
1470   }
1471 }
1472
1473
1474 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1475 "ll r<RT>, <OFFSET>(r<BASE>)"
1476 *mipsII:
1477 *mipsIII:
1478 *mipsIV:
1479 // start-sanitize-r5900
1480 *r5900:
1481 // end-sanitize-r5900
1482 *r3900:
1483 // start-sanitize-tx19
1484 *tx19:
1485 // end-sanitize-tx19
1486 {
1487   unsigned32 instruction = instruction_0;
1488   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1489   int destreg = ((instruction >> 16) & 0x0000001F);
1490   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1491   {
1492     unsigned64 vaddr = ((unsigned64)op1 + offset);
1493     unsigned64 paddr;
1494     int uncached;
1495     if ((vaddr & 3) != 0)
1496       SignalExceptionAddressLoad();
1497     else
1498       {
1499         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1500           {
1501             unsigned64 memval = 0;
1502             unsigned64 memval1 = 0;
1503             unsigned64 mask = 0x7;
1504             unsigned int shift = 2;
1505             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1506             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1507             unsigned int byte;
1508             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1509             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1510             byte = ((vaddr & mask) ^ (bigend << shift));
1511             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1512             LLBIT = 1;
1513           }
1514       }
1515   }
1516 }
1517
1518
1519 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1520 "lld r<RT>, <OFFSET>(r<BASE>)"
1521 *mipsIII:
1522 *mipsIV:
1523 // start-sanitize-r5900
1524 *r5900:
1525 // end-sanitize-r5900
1526 *r3900:
1527 // start-sanitize-tx19
1528 *tx19:
1529 // end-sanitize-tx19
1530 {
1531   unsigned32 instruction = instruction_0;
1532   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1533   int destreg = ((instruction >> 16) & 0x0000001F);
1534   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1535   {
1536     unsigned64 vaddr = ((unsigned64)op1 + offset);
1537     unsigned64 paddr;
1538     int uncached;
1539     if ((vaddr & 7) != 0)
1540       SignalExceptionAddressLoad();
1541     else
1542       {
1543         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1544           {
1545             unsigned64 memval = 0;
1546             unsigned64 memval1 = 0;
1547             unsigned64 mask = 0x7;
1548             unsigned int shift = 4;
1549             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1550             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1551             unsigned int byte;
1552             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1553             GPR[destreg] = memval;
1554             LLBIT = 1;
1555           }
1556       }
1557   }
1558 }
1559
1560
1561 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1562 "lui r<RT>, <IMMEDIATE>"
1563 *mipsI:
1564 *mipsII:
1565 *mipsIII:
1566 *mipsIV:
1567 // start-sanitize-r5900
1568 *r5900:
1569 // end-sanitize-r5900
1570 *r3900:
1571 // start-sanitize-tx19
1572 *tx19:
1573 // end-sanitize-tx19
1574 {
1575   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1576 }
1577
1578
1579 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1580 "lw r<RT>, <OFFSET>(r<BASE>)"
1581 *mipsI:
1582 *mipsII:
1583 *mipsIII:
1584 *mipsIV:
1585 // start-sanitize-r5900
1586 *r5900:
1587 // end-sanitize-r5900
1588 *r3900:
1589 // start-sanitize-tx19
1590 *tx19:
1591 // end-sanitize-tx19
1592 {
1593   unsigned32 instruction = instruction_0;
1594   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1595   int destreg = ((instruction >> 16) & 0x0000001F);
1596   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1597   {
1598     unsigned64 vaddr = ((unsigned64)op1 + offset);
1599     unsigned64 paddr;
1600     int uncached;
1601     if ((vaddr & 3) != 0)
1602       SignalExceptionAddressLoad();
1603     else
1604       {
1605         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1606           {
1607             unsigned64 memval = 0;
1608             unsigned64 memval1 = 0;
1609             unsigned64 mask = 0x7;
1610             unsigned int shift = 2;
1611             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1612             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1613             unsigned int byte;
1614             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1615             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1616             byte = ((vaddr & mask) ^ (bigend << shift));
1617             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1618           }
1619       }
1620   }
1621 }
1622
1623
1624 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1625 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1626 *mipsI:
1627 *mipsII:
1628 *mipsIII:
1629 *mipsIV:
1630 // start-sanitize-r5900
1631 *r5900:
1632 // end-sanitize-r5900
1633 *r3900:
1634 // start-sanitize-tx19
1635 *tx19:
1636 // end-sanitize-tx19
1637 {
1638   unsigned32 instruction = instruction_0;
1639   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1640   int destreg = ((instruction >> 16) & 0x0000001F);
1641   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1642   {
1643     unsigned64 vaddr = ((unsigned64)op1 + offset);
1644     unsigned64 paddr;
1645     int uncached;
1646     if ((vaddr & 3) != 0)
1647       SignalExceptionAddressLoad();
1648     else
1649       {
1650         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1651           {
1652             unsigned64 memval = 0;
1653             unsigned64 memval1 = 0;
1654             unsigned64 mask = 0x7;
1655             unsigned int shift = 2;
1656             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1657             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1658             unsigned int byte;
1659             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1660             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1661             byte = ((vaddr & mask) ^ (bigend << shift));
1662             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1663           }
1664       }
1665   }
1666 }
1667
1668
1669 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1670 "lwl r<RT>, <OFFSET>(r<BASE>)"
1671 *mipsI:
1672 *mipsII:
1673 *mipsIII:
1674 *mipsIV:
1675 // start-sanitize-r5900
1676 *r5900:
1677 // end-sanitize-r5900
1678 *r3900:
1679 // start-sanitize-tx19
1680 *tx19:
1681 // end-sanitize-tx19
1682 {
1683   unsigned32 instruction = instruction_0;
1684   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1685   int destreg = ((instruction >> 16) & 0x0000001F);
1686   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1687   {
1688     unsigned64 vaddr = ((unsigned64)op1 + offset);
1689     unsigned64 paddr;
1690     int uncached;
1691     {
1692       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1693         {
1694           unsigned64 memval = 0;
1695           unsigned64 memval1 = 0;
1696           unsigned64 mask = 3;
1697           unsigned int reverse = (ReverseEndian ? mask : 0);
1698           unsigned int bigend = (BigEndianCPU ? mask : 0);
1699           int byte;
1700           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1701           byte = ((vaddr & mask) ^ bigend);
1702           if (!!ByteSwapMem)
1703             paddr &= ~mask;
1704           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1705           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1706             memval >>= 32;
1707           }
1708           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1709           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1710         }
1711     }
1712   }
1713 }
1714
1715
1716 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1717 "lwr r<RT>, <OFFSET>(r<BASE>)"
1718 *mipsI:
1719 *mipsII:
1720 *mipsIII:
1721 *mipsIV:
1722 // start-sanitize-r5900
1723 *r5900:
1724 // end-sanitize-r5900
1725 *r3900:
1726 // start-sanitize-tx19
1727 *tx19:
1728 // end-sanitize-tx19
1729 {
1730   unsigned32 instruction = instruction_0;
1731   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1732   int destreg = ((instruction >> 16) & 0x0000001F);
1733   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1734   {
1735     unsigned64 vaddr = ((unsigned64)op1 + offset);
1736     unsigned64 paddr;
1737     int uncached;
1738     {
1739       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1740         {
1741           unsigned64 memval = 0;
1742           unsigned64 memval1 = 0;
1743           unsigned64 mask = 3;
1744           unsigned int reverse = (ReverseEndian ? mask : 0);
1745           unsigned int bigend = (BigEndianCPU ? mask : 0);
1746           int byte;
1747           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1748           byte = ((vaddr & mask) ^ bigend);
1749           if (!ByteSwapMem)
1750             paddr &= ~mask;
1751           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1752           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1753             memval >>= 32;
1754           }
1755           {
1756             unsigned64 srcmask;
1757             if (byte == 0)
1758               srcmask = 0;
1759             else
1760               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1761             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1762           }
1763           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1764         }
1765     }
1766   }
1767 }
1768
1769
1770 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1771 "lwu r<RT>, <OFFSET>(r<BASE>)"
1772 *mipsIII:
1773 *mipsIV:
1774 // start-sanitize-r5900
1775 *r5900:
1776 // end-sanitize-r5900
1777 *r3900:
1778 // start-sanitize-tx19
1779 *tx19:
1780 // end-sanitize-tx19
1781 {
1782   unsigned32 instruction = instruction_0;
1783   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1784   int destreg = ((instruction >> 16) & 0x0000001F);
1785   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1786   {
1787     unsigned64 vaddr = ((unsigned64)op1 + offset);
1788     unsigned64 paddr;
1789     int uncached;
1790     if ((vaddr & 3) != 0)
1791       SignalExceptionAddressLoad();
1792     else
1793       {
1794         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1795           {
1796             unsigned64 memval = 0;
1797             unsigned64 memval1 = 0;
1798             unsigned64 mask = 0x7;
1799             unsigned int shift = 2;
1800             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1801             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1802             unsigned int byte;
1803             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1804             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1805             byte = ((vaddr & mask) ^ (bigend << shift));
1806             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1807           }
1808       }
1809   }
1810 }
1811
1812
1813 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1814 "mfhi r<RD>"
1815 *mipsI:
1816 *mipsII:
1817 *mipsIII:
1818 *mipsIV:
1819 // start-sanitize-r5900
1820 *r5900:
1821 // end-sanitize-r5900
1822 *r3900:
1823 // start-sanitize-tx19
1824 *tx19:
1825 // end-sanitize-tx19
1826 {
1827   GPR[RD] = HI;
1828   HIACCESS = 3;
1829 }
1830
1831
1832 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1833 "mflo r<RD>"
1834 *mipsI:
1835 *mipsII:
1836 *mipsIII:
1837 *mipsIV:
1838 // start-sanitize-r5900
1839 *r5900:
1840 // end-sanitize-r5900
1841 *r3900:
1842 // start-sanitize-tx19
1843 *tx19:
1844 // end-sanitize-tx19
1845 {
1846   GPR[RD] = LO;
1847   LOACCESS = 3; /* 3rd instruction will be safe */
1848 }
1849
1850
1851 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1852 "movn r<RD>, r<RS>, r<RT>"
1853 *mipsIV:
1854 // start-sanitize-r5900
1855 *r5900:
1856 // end-sanitize-r5900
1857 {
1858   if (GPR[RT] != 0)
1859     GPR[RD] = GPR[RS];
1860 }
1861
1862
1863 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1864 "movz r<RD>, r<RS>, r<RT>"
1865 *mipsIV:
1866 // start-sanitize-r5900
1867 *r5900:
1868 // end-sanitize-r5900
1869 {
1870   if (GPR[RT] == 0)
1871     GPR[RD] = GPR[RS];
1872 }
1873
1874
1875 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1876 "mthi r<RS>"
1877 *mipsI:
1878 *mipsII:
1879 *mipsIII:
1880 *mipsIV:
1881 // start-sanitize-r5900
1882 *r5900:
1883 // end-sanitize-r5900
1884 *r3900:
1885 // start-sanitize-tx19
1886 *tx19:
1887 // end-sanitize-tx19
1888 {
1889   if (HIACCESS != 0)
1890     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
1891   HI = GPR[RS];
1892   HIACCESS = 3; /* 3rd instruction will be safe */
1893 }
1894
1895
1896 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1897 "mtlo r<RS>"
1898 *mipsI:
1899 *mipsII:
1900 *mipsIII:
1901 *mipsIV:
1902 // start-sanitize-r5900
1903 *r5900:
1904 // end-sanitize-r5900
1905 *r3900:
1906 // start-sanitize-tx19
1907 *tx19:
1908 // end-sanitize-tx19
1909 {
1910   if (LOACCESS != 0)
1911     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
1912   LO = GPR[RS];
1913   LOACCESS = 3; /* 3rd instruction will be safe */
1914 }
1915
1916
1917 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
1918 "mult r<RS>, r<RT>"
1919 *mipsI:
1920 *mipsII:
1921 *mipsIII:
1922 *mipsIV:
1923 // start-sanitize-r5900
1924 *r5900:
1925 // end-sanitize-r5900
1926 *r3900:
1927 // start-sanitize-tx19
1928 *tx19:
1929 // end-sanitize-tx19
1930 {
1931   signed64 prod;
1932   CHECKHILO ("Multiplication");
1933   prod = (((signed64)(signed32) GPR[RS])
1934           * ((signed64)(signed32) GPR[RT]));
1935   LO = EXTEND32 (VL4_8 (prod));
1936   HI = EXTEND32 (VH4_8 (prod));
1937 }
1938
1939
1940 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
1941 "multu r<RS>, r<RT>"
1942 *mipsI:
1943 *mipsII:
1944 *mipsIII:
1945 *mipsIV:
1946 // start-sanitize-r5900
1947 *r5900:
1948 // end-sanitize-r5900
1949 *r3900:
1950 // start-sanitize-tx19
1951 *tx19:
1952 // end-sanitize-tx19
1953 {
1954   unsigned64 prod;
1955   CHECKHILO ("Multiplication");
1956   prod = (((unsigned64)(unsigned32) GPR[RS])
1957           * ((unsigned64)(unsigned32) GPR[RT]));
1958   LO = EXTEND32 (VL4_8 (prod));
1959   HI = EXTEND32 (VH4_8 (prod));
1960 }
1961
1962
1963 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1964 "nor r<RD>, r<RS>, r<RT>"
1965 *mipsI:
1966 *mipsII:
1967 *mipsIII:
1968 *mipsIV:
1969 // start-sanitize-r5900
1970 *r5900:
1971 // end-sanitize-r5900
1972 *r3900:
1973 // start-sanitize-tx19
1974 *tx19:
1975 // end-sanitize-tx19
1976 {
1977   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
1978 }
1979
1980
1981 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1982 "or r<RD>, r<RS>, r<RT>"
1983 *mipsI:
1984 *mipsII:
1985 *mipsIII:
1986 *mipsIV:
1987 // start-sanitize-r5900
1988 *r5900:
1989 // end-sanitize-r5900
1990 *r3900:
1991 // start-sanitize-tx19
1992 *tx19:
1993 // end-sanitize-tx19
1994 {
1995   GPR[RD] = (GPR[RS] | GPR[RT]);
1996 }
1997
1998
1999 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2000 "ori r<RT>, r<RS>, <IMMEDIATE>"
2001 *mipsI:
2002 *mipsII:
2003 *mipsIII:
2004 *mipsIV:
2005 // start-sanitize-r5900
2006 *r5900:
2007 // end-sanitize-r5900
2008 *r3900:
2009 // start-sanitize-tx19
2010 *tx19:
2011 // end-sanitize-tx19
2012 {
2013   GPR[RT] = (GPR[RS] | IMMEDIATE);
2014 }
2015
2016
2017 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2018 *mipsIV:
2019 // start-sanitize-r5900
2020 *r5900:
2021 // end-sanitize-r5900
2022 {
2023   unsigned32 instruction = instruction_0;
2024   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2025   int hint = ((instruction >> 16) & 0x0000001F);
2026   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2027   {
2028     unsigned64 vaddr = ((unsigned64)op1 + offset);
2029     unsigned64 paddr;
2030     int uncached;
2031     {
2032       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2033         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2034     }
2035   }
2036 }
2037
2038 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2039 "sb r<RT>, <OFFSET>(r<BASE>)"
2040 *mipsI:
2041 *mipsII:
2042 *mipsIII:
2043 *mipsIV:
2044 // start-sanitize-r5900
2045 *r5900:
2046 // end-sanitize-r5900
2047 *r3900:
2048 // start-sanitize-tx19
2049 *tx19:
2050 // end-sanitize-tx19
2051 {
2052   unsigned32 instruction = instruction_0;
2053   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2054   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2055   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2056   {
2057     unsigned64 vaddr = ((unsigned64)op1 + offset);
2058     unsigned64 paddr;
2059     int uncached;
2060     {
2061       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2062         {
2063           unsigned64 memval = 0;
2064           unsigned64 memval1 = 0;
2065           unsigned64 mask = 0x7;
2066           unsigned int shift = 0;
2067           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2068           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2069           unsigned int byte;
2070           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2071           byte = ((vaddr & mask) ^ (bigend << shift));
2072           memval = ((unsigned64) op2 << (8 * byte));
2073           {
2074             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2075           }
2076         }
2077     }
2078   }
2079 }
2080
2081
2082 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2083 "sc r<RT>, <OFFSET>(r<BASE>)"
2084 *mipsII:
2085 *mipsIII:
2086 *mipsIV:
2087 // start-sanitize-r5900
2088 *r5900:
2089 // end-sanitize-r5900
2090 *r3900:
2091 // start-sanitize-tx19
2092 *tx19:
2093 // end-sanitize-tx19
2094 {
2095   unsigned32 instruction = instruction_0;
2096   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2097   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2098   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2099   {
2100     unsigned64 vaddr = ((unsigned64)op1 + offset);
2101     unsigned64 paddr;
2102     int uncached;
2103     if ((vaddr & 3) != 0)
2104       SignalExceptionAddressStore();
2105     else
2106       {
2107         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2108           {
2109             unsigned64 memval = 0;
2110             unsigned64 memval1 = 0;
2111             unsigned64 mask = 0x7;
2112             unsigned int byte;
2113             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2114             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2115             memval = ((unsigned64) op2 << (8 * byte));
2116             if (LLBIT)
2117               {
2118                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2119               }
2120             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2121           }
2122       }
2123   }
2124 }
2125
2126
2127 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2128 "scd r<RT>, <OFFSET>(r<BASE>)"
2129 *mipsIII:
2130 *mipsIV:
2131 // start-sanitize-r5900
2132 *r5900:
2133 // end-sanitize-r5900
2134 *r3900:
2135 // start-sanitize-tx19
2136 *tx19:
2137 // end-sanitize-tx19
2138 {
2139   unsigned32 instruction = instruction_0;
2140   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2141   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2142   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2143   {
2144     unsigned64 vaddr = ((unsigned64)op1 + offset);
2145     unsigned64 paddr;
2146     int uncached;
2147     if ((vaddr & 7) != 0)
2148       SignalExceptionAddressStore();
2149     else
2150       {
2151         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2152           {
2153             unsigned64 memval = 0;
2154             unsigned64 memval1 = 0;
2155             memval = op2;
2156             if (LLBIT)
2157               {
2158                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2159               }
2160             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2161           }
2162       }
2163   }
2164 }
2165
2166
2167 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2168 "sd r<RT>, <OFFSET>(r<BASE>)"
2169 *mipsIII:
2170 *mipsIV:
2171 // start-sanitize-r5900
2172 *r5900:
2173 // end-sanitize-r5900
2174 *r3900:
2175 // start-sanitize-tx19
2176 *tx19:
2177 // end-sanitize-tx19
2178 {
2179   unsigned32 instruction = instruction_0;
2180   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2181   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2182   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2183   {
2184     unsigned64 vaddr = ((unsigned64)op1 + offset);
2185     unsigned64 paddr;
2186     int uncached;
2187     if ((vaddr & 7) != 0)
2188       SignalExceptionAddressStore();
2189     else
2190       {
2191         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2192           {
2193             unsigned64 memval = 0;
2194             unsigned64 memval1 = 0;
2195             memval = op2;
2196             {
2197               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2198             }
2199           }
2200       }
2201   }
2202 }
2203
2204
2205 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2206 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2207 *mipsII:
2208 *mipsIII:
2209 *mipsIV:
2210 // start-sanitize-r5900
2211 *r5900:
2212 // end-sanitize-r5900
2213 *r3900:
2214 // start-sanitize-tx19
2215 *tx19:
2216 // end-sanitize-tx19
2217 {
2218   unsigned32 instruction = instruction_0;
2219   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2220   int destreg = ((instruction >> 16) & 0x0000001F);
2221   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2222   {
2223     unsigned64 vaddr = ((unsigned64)op1 + offset);
2224     unsigned64 paddr;
2225     int uncached;
2226     if ((vaddr & 7) != 0)
2227       SignalExceptionAddressStore();
2228     else
2229       {
2230         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2231           {
2232             unsigned64 memval = 0;
2233             unsigned64 memval1 = 0;
2234             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2235             {
2236               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2237             }
2238           }
2239       }
2240   }
2241 }
2242
2243
2244 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2245 "sdl r<RT>, <OFFSET>(r<BASE>)"
2246 *mipsIII:
2247 *mipsIV:
2248 // start-sanitize-r5900
2249 *r5900:
2250 // end-sanitize-r5900
2251 *r3900:
2252 // start-sanitize-tx19
2253 *tx19:
2254 // end-sanitize-tx19
2255 {
2256   unsigned32 instruction = instruction_0;
2257   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2258   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2259   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2260   {
2261     unsigned64 vaddr = ((unsigned64)op1 + offset);
2262     unsigned64 paddr;
2263     int uncached;
2264     {
2265       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2266         {
2267           unsigned64 memval = 0;
2268           unsigned64 memval1 = 0;
2269           unsigned64 mask = 7;
2270           unsigned int reverse = (ReverseEndian ? mask : 0);
2271           unsigned int bigend = (BigEndianCPU ? mask : 0);
2272           int byte;
2273           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2274           byte = ((vaddr & mask) ^ bigend);
2275           if (!!ByteSwapMem)
2276             paddr &= ~mask;
2277           memval = (op2 >> (8 * (7 - byte)));
2278           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2279         }
2280     }
2281   }
2282 }
2283
2284
2285 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2286 "sdr r<RT>, <OFFSET>(r<BASE>)"
2287 *mipsIII:
2288 *mipsIV:
2289 // start-sanitize-r5900
2290 *r5900:
2291 // end-sanitize-r5900
2292 *r3900:
2293 // start-sanitize-tx19
2294 *tx19:
2295 // end-sanitize-tx19
2296 {
2297   unsigned32 instruction = instruction_0;
2298   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2299   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2300   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2301   {
2302     unsigned64 vaddr = ((unsigned64)op1 + offset);
2303     unsigned64 paddr;
2304     int uncached;
2305     {
2306       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2307         {
2308           unsigned64 memval = 0;
2309           unsigned64 memval1 = 0;
2310           unsigned64 mask = 7;
2311           unsigned int reverse = (ReverseEndian ? mask : 0);
2312           unsigned int bigend = (BigEndianCPU ? mask : 0);
2313           int byte;
2314           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2315           byte = ((vaddr & mask) ^ bigend);
2316           if (!ByteSwapMem)
2317             paddr &= ~mask;
2318           memval = ((unsigned64) op2 << (byte * 8));
2319           StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2320         }
2321     }
2322   }
2323 }
2324
2325
2326 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2327 "sh r<RT>, <OFFSET>(r<BASE>)"
2328 *mipsI:
2329 *mipsII:
2330 *mipsIII:
2331 *mipsIV:
2332 // start-sanitize-r5900
2333 *r5900:
2334 // end-sanitize-r5900
2335 *r3900:
2336 // start-sanitize-tx19
2337 *tx19:
2338 // end-sanitize-tx19
2339 {
2340   unsigned32 instruction = instruction_0;
2341   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2342   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2343   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2344   {
2345     unsigned64 vaddr = ((unsigned64)op1 + offset);
2346     unsigned64 paddr;
2347     int uncached;
2348     if ((vaddr & 1) != 0)
2349       SignalExceptionAddressStore();
2350     else
2351       {
2352         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2353           {
2354             unsigned64 memval = 0;
2355             unsigned64 memval1 = 0;
2356             unsigned64 mask = 0x7;
2357             unsigned int shift = 1;
2358             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2359             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2360             unsigned int byte;
2361             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2362             byte = ((vaddr & mask) ^ (bigend << shift));
2363             memval = ((unsigned64) op2 << (8 * byte));
2364             {
2365               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2366             }
2367           }
2368       }
2369   }
2370 }
2371
2372
2373 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2374 "sll r<RD>, r<RT>, <SHIFT>"
2375 *mipsI:
2376 *mipsII:
2377 *mipsIII:
2378 *mipsIV:
2379 // start-sanitize-r5900
2380 *r5900:
2381 // end-sanitize-r5900
2382 *r3900:
2383 // start-sanitize-tx19
2384 *tx19:
2385 // end-sanitize-tx19
2386 {
2387   int s = SHIFT;
2388   unsigned32 temp = (GPR[RT] << s);
2389   GPR[RD] = EXTEND32 (temp);
2390 }
2391
2392
2393 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2394 "sllv r<RD>, r<RT>, r<RS>"
2395 *mipsI:
2396 *mipsII:
2397 *mipsIII:
2398 *mipsIV:
2399 // start-sanitize-r5900
2400 *r5900:
2401 // end-sanitize-r5900
2402 *r3900:
2403 // start-sanitize-tx19
2404 *tx19:
2405 // end-sanitize-tx19
2406 {
2407   int s = MASKED (GPR[RS], 4, 0);
2408   unsigned32 temp = (GPR[RT] << s);
2409   GPR[RD] = EXTEND32 (temp);
2410 }
2411
2412
2413 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2414 "slt r<RD>, r<RS>, r<RT>"
2415 *mipsI:
2416 *mipsII:
2417 *mipsIII:
2418 *mipsIV:
2419 // start-sanitize-r5900
2420 *r5900:
2421 // end-sanitize-r5900
2422 *r3900:
2423 // start-sanitize-tx19
2424 *tx19:
2425 // end-sanitize-tx19
2426 {
2427   GPR[RD] = (GPR[RS] < GPR[RT]);
2428 }
2429
2430
2431 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2432 "slti r<RT>, r<RS>, <IMMEDIATE>"
2433 *mipsI:
2434 *mipsII:
2435 *mipsIII:
2436 *mipsIV:
2437 // start-sanitize-r5900
2438 *r5900:
2439 // end-sanitize-r5900
2440 *r3900:
2441 // start-sanitize-tx19
2442 *tx19:
2443 // end-sanitize-tx19
2444 {
2445   GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
2446 }
2447
2448
2449 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2450 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2451 *mipsI:
2452 *mipsII:
2453 *mipsIII:
2454 *mipsIV:
2455 // start-sanitize-r5900
2456 *r5900:
2457 // end-sanitize-r5900
2458 *r3900:
2459 // start-sanitize-tx19
2460 *tx19:
2461 // end-sanitize-tx19
2462 {
2463   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2464 }
2465
2466 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2467 "sltu r<RD>, r<RS>, r<RT>"
2468 *mipsI:
2469 *mipsII:
2470 *mipsIII:
2471 *mipsIV:
2472 // start-sanitize-r5900
2473 *r5900:
2474 // end-sanitize-r5900
2475 *r3900:
2476 // start-sanitize-tx19
2477 *tx19:
2478 // end-sanitize-tx19
2479 {
2480   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2481 }
2482
2483
2484 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2485 "sra r<RD>, r<RT>, <SHIFT>"
2486 *mipsI:
2487 *mipsII:
2488 *mipsIII:
2489 *mipsIV:
2490 // start-sanitize-r5900
2491 *r5900:
2492 // end-sanitize-r5900
2493 *r3900:
2494 // start-sanitize-tx19
2495 *tx19:
2496 // end-sanitize-tx19
2497 {
2498   int s = SHIFT;
2499   signed32 temp = (signed32) GPR[RT] >> s;
2500   GPR[RD] = EXTEND32 (temp);
2501 }
2502
2503
2504 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2505 "srav r<RD>, r<RT>, r<RS>"
2506 *mipsI:
2507 *mipsII:
2508 *mipsIII:
2509 *mipsIV:
2510 // start-sanitize-r5900
2511 *r5900:
2512 // end-sanitize-r5900
2513 *r3900:
2514 // start-sanitize-tx19
2515 *tx19:
2516 // end-sanitize-tx19
2517 {
2518   int s = MASKED (GPR[RS], 4, 0);
2519   signed32 temp = (signed32) GPR[RT] >> s;
2520   GPR[RD] = EXTEND32 (temp);
2521 }
2522
2523
2524 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2525 "srl r<RD>, r<RT>, <SHIFT>"
2526 *mipsI:
2527 *mipsII:
2528 *mipsIII:
2529 *mipsIV:
2530 // start-sanitize-r5900
2531 *r5900:
2532 // end-sanitize-r5900
2533 *r3900:
2534 // start-sanitize-tx19
2535 *tx19:
2536 // end-sanitize-tx19
2537 {
2538   int s = SHIFT;
2539   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2540   GPR[RD] = EXTEND32 (temp);
2541 }
2542
2543
2544 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2545 "srlv r<RD>, r<RT>, r<RS>"
2546 *mipsI:
2547 *mipsII:
2548 *mipsIII:
2549 *mipsIV:
2550 // start-sanitize-r5900
2551 *r5900:
2552 // end-sanitize-r5900
2553 *r3900:
2554 // start-sanitize-tx19
2555 *tx19:
2556 // end-sanitize-tx19
2557 {
2558   int s = MASKED (GPR[RS], 4, 0);
2559   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2560   GPR[RD] = EXTEND32 (temp);
2561 }
2562
2563
2564 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2565 "sub r<RD>, r<RS>, r<RT>"
2566 *mipsI:
2567 *mipsII:
2568 *mipsIII:
2569 *mipsIV:
2570 // start-sanitize-r5900
2571 *r5900:
2572 // end-sanitize-r5900
2573 *r3900:
2574 // start-sanitize-tx19
2575 *tx19:
2576 // end-sanitize-tx19
2577 {
2578   ALU32_BEGIN (GPR[RS]);
2579   ALU32_SUB (GPR[RT]);
2580   ALU32_END (GPR[RD]);
2581 }
2582
2583
2584 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2585 "subu r<RD>, r<RS>, r<RT>"
2586 *mipsI:
2587 *mipsII:
2588 *mipsIII:
2589 *mipsIV:
2590 // start-sanitize-r5900
2591 *r5900:
2592 // end-sanitize-r5900
2593 *r3900:
2594 // start-sanitize-tx19
2595 *tx19:
2596 // end-sanitize-tx19
2597 {
2598   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2599 }
2600
2601
2602 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2603 "sw r<RT>, <OFFSET>(r<BASE>)"
2604 *mipsI:
2605 *mipsII:
2606 *mipsIII:
2607 *mipsIV:
2608 // start-sanitize-r5900
2609 *r5900:
2610 // end-sanitize-r5900
2611 *r3900:
2612 // start-sanitize-tx19
2613 *tx19:
2614 // end-sanitize-tx19
2615 {
2616   unsigned32 instruction = instruction_0;
2617   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2618   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2619   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2620   {
2621     unsigned64 vaddr = ((unsigned64)op1 + offset);
2622     unsigned64 paddr;
2623     int uncached;
2624     if ((vaddr & 3) != 0)
2625       SignalExceptionAddressStore();
2626     else
2627       {
2628         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2629           {
2630             unsigned64 memval = 0;
2631             unsigned64 memval1 = 0;
2632             unsigned64 mask = 0x7;
2633             unsigned int byte;
2634             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2635             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2636             memval = ((unsigned64) op2 << (8 * byte));
2637             {
2638               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2639             }
2640           }
2641       }
2642   }
2643 }
2644
2645
2646 1110,ZZ!0!1!3,5.RS,5.RT,16.OFFSET:NORMAL:32::SWCz
2647 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2648 *mipsI:
2649 *mipsII:
2650 *mipsIII:
2651 *mipsIV:
2652 // start-sanitize-r5900
2653 *r5900:
2654 // end-sanitize-r5900
2655 *r3900:
2656 // start-sanitize-tx19
2657 *tx19:
2658 // end-sanitize-tx19
2659 {
2660   unsigned32 instruction = instruction_0;
2661   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2662   int destreg = ((instruction >> 16) & 0x0000001F);
2663   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2664   {
2665     unsigned64 vaddr = ((unsigned64)op1 + offset);
2666     unsigned64 paddr;
2667     int uncached;
2668     if ((vaddr & 3) != 0)
2669       SignalExceptionAddressStore();
2670     else
2671       {
2672         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2673           {
2674             unsigned64 memval = 0;
2675             unsigned64 memval1 = 0;
2676             unsigned64 mask = 0x7;
2677             unsigned int byte;
2678             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2679             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2680             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2681             {
2682               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2683             }
2684           }
2685       }
2686   }
2687 }
2688
2689
2690 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2691 "swl r<RT>, <OFFSET>(r<BASE>)"
2692 *mipsI:
2693 *mipsII:
2694 *mipsIII:
2695 *mipsIV:
2696 // start-sanitize-r5900
2697 *r5900:
2698 // end-sanitize-r5900
2699 *r3900:
2700 // start-sanitize-tx19
2701 *tx19:
2702 // end-sanitize-tx19
2703 {
2704   unsigned32 instruction = instruction_0;
2705   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2706   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2707   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2708   {
2709     unsigned64 vaddr = ((unsigned64)op1 + offset);
2710     unsigned64 paddr;
2711     int uncached;
2712     {
2713       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2714         {
2715           unsigned64 memval = 0;
2716           unsigned64 memval1 = 0;
2717           unsigned64 mask = 3;
2718           unsigned int reverse = (ReverseEndian ? mask : 0);
2719           unsigned int bigend = (BigEndianCPU ? mask : 0);
2720           int byte;
2721           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2722           byte = ((vaddr & mask) ^ bigend);
2723           if (!!ByteSwapMem)
2724             paddr &= ~mask;
2725           memval = (op2 >> (8 * (3 - byte)));
2726           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2727             memval <<= 32;
2728           }
2729           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2730         }
2731     }
2732   }
2733 }
2734
2735
2736 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2737 "swr r<RT>, <OFFSET>(r<BASE>)"
2738 *mipsI:
2739 *mipsII:
2740 *mipsIII:
2741 *mipsIV:
2742 // start-sanitize-r5900
2743 *r5900:
2744 // end-sanitize-r5900
2745 *r3900:
2746 // start-sanitize-tx19
2747 *tx19:
2748 // end-sanitize-tx19
2749 {
2750   unsigned32 instruction = instruction_0;
2751   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2752   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2753   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2754   {
2755     unsigned64 vaddr = ((unsigned64)op1 + offset);
2756     unsigned64 paddr;
2757     int uncached;
2758     {
2759       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2760         {
2761           unsigned64 memval = 0;
2762           unsigned64 memval1 = 0;
2763           unsigned64 mask = 3;
2764           unsigned int reverse = (ReverseEndian ? mask : 0);
2765           unsigned int bigend = (BigEndianCPU ? mask : 0);
2766           int byte;
2767           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2768           byte = ((vaddr & mask) ^ bigend);
2769           if (!ByteSwapMem)
2770             paddr &= ~mask;
2771           memval = ((unsigned64) op2 << (byte * 8));
2772           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2773             memval <<= 32;
2774           }
2775           StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
2776         }
2777     }
2778   }
2779 }
2780
2781
2782 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2783 "sync":STYPE == 0
2784 "sync <STYPE>"
2785 *mipsII:
2786 *mipsIII:
2787 *mipsIV:
2788 // start-sanitize-r5900
2789 *r5900:
2790 // end-sanitize-r5900
2791 *r3900:
2792 // start-sanitize-tx19
2793 *tx19:
2794 // end-sanitize-tx19
2795 {
2796   SyncOperation (sd, STYPE);
2797 }
2798
2799
2800 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2801 "syscall <CODE>"
2802 *mipsI:
2803 *mipsII:
2804 *mipsIII:
2805 *mipsIV:
2806 // start-sanitize-r5900
2807 *r5900:
2808 // end-sanitize-r5900
2809 *r3900:
2810 // start-sanitize-tx19
2811 *tx19:
2812 // end-sanitize-tx19
2813 {
2814   SignalException(SystemCall, instruction_0);
2815 }
2816
2817
2818 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2819 "teq r<RS>, r<RT>"
2820 *mipsII:
2821 *mipsIII:
2822 *mipsIV:
2823 // start-sanitize-r5900
2824 *r5900:
2825 // end-sanitize-r5900
2826 *r3900:
2827 // start-sanitize-tx19
2828 *tx19:
2829 // end-sanitize-tx19
2830 {
2831   if (GPR[RS] == GPR[RT])
2832     SignalException(Trap, instruction_0);
2833 }
2834
2835
2836 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2837 "teqi r<RS>, <IMMEDIATE>"
2838 *mipsII:
2839 *mipsIII:
2840 *mipsIV:
2841 // start-sanitize-r5900
2842 *r5900:
2843 // end-sanitize-r5900
2844 *r3900:
2845 // start-sanitize-tx19
2846 *tx19:
2847 // end-sanitize-tx19
2848 {
2849   if (GPR[RS] == EXTEND16 (IMMEDIATE))
2850     SignalException(Trap, instruction_0);
2851 }
2852
2853
2854 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2855 "tge r<RS>, r<RT>"
2856 *mipsII:
2857 *mipsIII:
2858 *mipsIV:
2859 // start-sanitize-r5900
2860 *r5900:
2861 // end-sanitize-r5900
2862 *r3900:
2863 // start-sanitize-tx19
2864 *tx19:
2865 // end-sanitize-tx19
2866 {
2867   if (GPR[RS] >= GPR[RT])
2868     SignalException(Trap, instruction_0);
2869 }
2870
2871
2872 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2873 "tgei r<RS>, <IMMEDIATE>"
2874 *mipsII:
2875 *mipsIII:
2876 *mipsIV:
2877 // start-sanitize-r5900
2878 *r5900:
2879 // end-sanitize-r5900
2880 *r3900:
2881 // start-sanitize-tx19
2882 *tx19:
2883 // end-sanitize-tx19
2884 {
2885   if (GPR[RS] >= EXTEND16 (IMMEDIATE))
2886     SignalException(Trap, instruction_0);
2887 }
2888
2889
2890 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2891 "tgeiu r<RS>, <IMMEDIATE>"
2892 *mipsII:
2893 *mipsIII:
2894 *mipsIV:
2895 // start-sanitize-r5900
2896 *r5900:
2897 // end-sanitize-r5900
2898 *r3900:
2899 // start-sanitize-tx19
2900 *tx19:
2901 // end-sanitize-tx19
2902 {
2903   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2904     SignalException(Trap, instruction_0);
2905 }
2906
2907
2908 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2909 "tgeu r<RS>, r<RT>"
2910 *mipsII:
2911 *mipsIII:
2912 *mipsIV:
2913 // start-sanitize-r5900
2914 *r5900:
2915 // end-sanitize-r5900
2916 *r3900:
2917 // start-sanitize-tx19
2918 *tx19:
2919 // end-sanitize-tx19
2920 {
2921   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2922     SignalException(Trap, instruction_0);
2923 }
2924
2925
2926 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2927 "tlt r<RS>, r<RT>"
2928 *mipsII:
2929 *mipsIII:
2930 *mipsIV:
2931 // start-sanitize-r5900
2932 *r5900:
2933 // end-sanitize-r5900
2934 *r3900:
2935 // start-sanitize-tx19
2936 *tx19:
2937 // end-sanitize-tx19
2938 {
2939   if (GPR[RS] < GPR[RT])
2940     SignalException(Trap, instruction_0);
2941 }
2942
2943
2944 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2945 "tlti r<RS>, <IMMEDIATE>"
2946 *mipsII:
2947 *mipsIII:
2948 *mipsIV:
2949 // start-sanitize-r5900
2950 *r5900:
2951 // end-sanitize-r5900
2952 *r3900:
2953 // start-sanitize-tx19
2954 *tx19:
2955 // end-sanitize-tx19
2956 {
2957   if (GPR[RS] < EXTEND16 (IMMEDIATE))
2958     SignalException(Trap, instruction_0);
2959 }
2960
2961
2962 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2963 "tltiu r<RS>, <IMMEDIATE>"
2964 *mipsII:
2965 *mipsIII:
2966 *mipsIV:
2967 // start-sanitize-r5900
2968 *r5900:
2969 // end-sanitize-r5900
2970 *r3900:
2971 // start-sanitize-tx19
2972 *tx19:
2973 // end-sanitize-tx19
2974 {
2975   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2976     SignalException(Trap, instruction_0);
2977 }
2978
2979
2980 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2981 "tltu r<RS>, r<RT>"
2982 *mipsII:
2983 *mipsIII:
2984 *mipsIV:
2985 // start-sanitize-r5900
2986 *r5900:
2987 // end-sanitize-r5900
2988 *r3900:
2989 // start-sanitize-tx19
2990 *tx19:
2991 // end-sanitize-tx19
2992 {
2993   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2994     SignalException(Trap, instruction_0);
2995 }
2996
2997
2998 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2999 "tne r<RS>, r<RT>"
3000 *mipsII:
3001 *mipsIII:
3002 *mipsIV:
3003 // start-sanitize-r5900
3004 *r5900:
3005 // end-sanitize-r5900
3006 *r3900:
3007 // start-sanitize-tx19
3008 *tx19:
3009 // end-sanitize-tx19
3010 {
3011   if (GPR[RS] != GPR[RT])
3012     SignalException(Trap, instruction_0);
3013 }
3014
3015
3016 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3017 "tne r<RS>, <IMMEDIATE>"
3018 *mipsII:
3019 *mipsIII:
3020 *mipsIV:
3021 // start-sanitize-r5900
3022 *r5900:
3023 // end-sanitize-r5900
3024 *r3900:
3025 // start-sanitize-tx19
3026 *tx19:
3027 // end-sanitize-tx19
3028 {
3029   if (GPR[RS] != EXTEND16 (IMMEDIATE))
3030     SignalException(Trap, instruction_0);
3031 }
3032
3033
3034 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3035 "xor r<RD>, r<RS>, r<RT>"
3036 *mipsI:
3037 *mipsII:
3038 *mipsIII:
3039 *mipsIV:
3040 // start-sanitize-r5900
3041 *r5900:
3042 // end-sanitize-r5900
3043 *r3900:
3044 // start-sanitize-tx19
3045 *tx19:
3046 // end-sanitize-tx19
3047 {
3048   GPR[RD] = GPR[RS] ^ GPR[RT];
3049 }
3050
3051
3052 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3053 "xori r<RT>, r<RS>, <IMMEDIATE>"
3054 *mipsI:
3055 *mipsII:
3056 *mipsIII:
3057 *mipsIV:
3058 // start-sanitize-r5900
3059 *r5900:
3060 // end-sanitize-r5900
3061 *r3900:
3062 // start-sanitize-tx19
3063 *tx19:
3064 // end-sanitize-tx19
3065 {
3066   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3067 }
3068
3069 \f
3070 //
3071 // MIPS Architecture:
3072 //
3073 //        FPU Instruction Set (COP1 & COP1X)
3074 //
3075
3076
3077 :%s:::FMT:int fmt
3078 {
3079   switch (fmt)
3080     {
3081     case fmt_single: return "s";
3082     case fmt_double: return "d";
3083     case fmt_word: return "w";
3084     case fmt_long: return "l";
3085     default: return "?";
3086     }
3087 }
3088
3089 :%s:::TF:int tf
3090 {
3091   if (tf)
3092     return "t";
3093   else
3094     return "f";
3095 }
3096
3097 :%s:::ND:int nd
3098 {
3099   if (nd)
3100     return "l";
3101   else
3102     return "";
3103 }
3104
3105 :%s:::COND:int cond
3106 {
3107   switch (cond)
3108     {
3109     case 00: return "f";
3110     case 01: return "un";
3111     case 02: return "eq";
3112     case 03: return "ueq";
3113     case 04: return "olt";
3114     case 05: return "ult";
3115     case 06: return "ole";
3116     case 07: return "ule";
3117     case 010: return "sf";
3118     case 011: return "ngle";
3119     case 012: return "seq";
3120     case 013: return "ngl";
3121     case 014: return "lt";
3122     case 015: return "nge";
3123     case 016: return "le";
3124     case 017: return "ngt";
3125     default: return "?";
3126     }
3127 }
3128
3129
3130 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3131 "abs.%s<FMT> f<FD>, f<FS>"
3132 *mipsI:
3133 *mipsII:
3134 *mipsIII:
3135 *mipsIV:
3136 // start-sanitize-r5900
3137 *r5900:
3138 // end-sanitize-r5900
3139 *r3900:
3140 // start-sanitize-tx19
3141 *tx19:
3142 // end-sanitize-tx19
3143 {
3144   unsigned32 instruction = instruction_0;
3145   int destreg = ((instruction >> 6) & 0x0000001F);
3146   int fs = ((instruction >> 11) & 0x0000001F);
3147   int format = ((instruction >> 21) & 0x00000007);
3148   {
3149     if ((format != fmt_single) && (format != fmt_double))
3150       SignalException(ReservedInstruction,instruction);
3151     else
3152       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3153   }
3154 }
3155
3156
3157
3158
3159 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3160 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3161 *mipsI:
3162 *mipsII:
3163 *mipsIII:
3164 *mipsIV:
3165 // start-sanitize-r5900
3166 *r5900:
3167 // end-sanitize-r5900
3168 *r3900:
3169 // start-sanitize-tx19
3170 *tx19:
3171 // end-sanitize-tx19
3172 {
3173   unsigned32 instruction = instruction_0;
3174   int destreg = ((instruction >> 6) & 0x0000001F);
3175   int fs = ((instruction >> 11) & 0x0000001F);
3176   int ft = ((instruction >> 16) & 0x0000001F);
3177   int format = ((instruction >> 21) & 0x00000007);
3178   {
3179     if ((format != fmt_single) && (format != fmt_double))
3180       SignalException(ReservedInstruction, instruction);
3181     else
3182       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3183   }
3184 }
3185
3186
3187 //
3188 // FIXME: This does not correctly resolve mipsI-mipsIV differences.
3189 //
3190 // BC1F
3191 // BC1FL
3192 // BC1T
3193 // BC1TL
3194 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3195 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3196 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3197 *mipsI:
3198 *mipsII:
3199 *mipsIII:
3200 *mipsIV:
3201 // start-sanitize-r5900
3202 *r5900:
3203 // end-sanitize-r5900
3204 *r3900:
3205 // start-sanitize-tx19
3206 *tx19:
3207 // end-sanitize-tx19
3208 {
3209   unsigned32 instruction = instruction_0;
3210   signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3211   int boolean = ((instruction >> 16) & 0x00000001);
3212   int likely = ((instruction >> 17) & 0x00000001);
3213   int condition_code = ((instruction >> 18) & 0x00000007);
3214   {
3215     if (condition_code != 0)
3216       SignalException(ReservedInstruction,instruction);
3217     else {
3218       int condition = (PREVCOC1() == boolean);
3219       /* NOTE: The branch occurs AFTER the next instruction has been executed */
3220       if (condition) {
3221         DSPC = (PC + offset);
3222       }
3223       else if (likely) {
3224         NULLIFY_NIA ();
3225       }
3226     }
3227   }
3228 }
3229
3230
3231 //
3232 // FIXME: This does not correctly differentiate between mips*
3233 //
3234 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3235 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3236 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3237 *mipsI:
3238 *mipsII:
3239 *mipsIII:
3240 *mipsIV:
3241 // start-sanitize-r5900
3242 *r5900:
3243 // end-sanitize-r5900
3244 *r3900:
3245 // start-sanitize-tx19
3246 *tx19:
3247 // end-sanitize-tx19
3248 {
3249   unsigned32 instruction = instruction_0;
3250   int cmpflags = ((instruction >> 0) & 0x0000000F);
3251   int condition_code = ((instruction >> 8) & 0x00000007);
3252   int fs = ((instruction >> 11) & 0x0000001F);
3253   int ft = ((instruction >> 16) & 0x0000001F);
3254   int format = ((instruction >> 21) & 0x00000007);
3255   if (condition_code != 0)
3256     {
3257       SignalException(ReservedInstruction,instruction);
3258     }
3259   else
3260     {
3261       if ((format != fmt_single) && (format != fmt_double))
3262         SignalException(ReservedInstruction,instruction);
3263       else {
3264         if (condition_code != 0)
3265           SignalException(ReservedInstruction,instruction);
3266         else
3267           {
3268             int ignore = 0;
3269             int less = 0;
3270             int equal = 0;
3271             int unordered = 1;
3272             unsigned64 ofs = ValueFPR(fs,format);
3273             unsigned64 oft = ValueFPR(ft,format);
3274             if (NaN(ofs,format) || NaN(oft,format)) {
3275               if (FCSR & FP_ENABLE(IO)) {
3276                 FCSR |= FP_CAUSE(IO);
3277                 SignalExceptionFPE();
3278                 ignore = 1;
3279               }
3280             } else {
3281               less = Less(ofs,oft,format);
3282               equal = Equal(ofs,oft,format);
3283               unordered = 0;
3284             }
3285             if (!ignore) {
3286               int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3287               SETFCC(condition_code,condition);
3288             }
3289           }
3290       }
3291     }
3292 }
3293
3294
3295 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3296 "ceil.l.%s<FMT> f<FD>, f<FS>"
3297 *mipsIII:
3298 *mipsIV:
3299 // start-sanitize-r5900
3300 *r5900:
3301 // end-sanitize-r5900
3302 *r3900:
3303 // start-sanitize-tx19
3304 *tx19:
3305 // end-sanitize-tx19
3306 {
3307   unsigned32 instruction = instruction_0;
3308   int destreg = ((instruction >> 6) & 0x0000001F);
3309   int fs = ((instruction >> 11) & 0x0000001F);
3310   int format = ((instruction >> 21) & 0x00000007);
3311   {
3312     if ((format != fmt_single) && (format != fmt_double))
3313       SignalException(ReservedInstruction,instruction);
3314     else
3315       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3316   }
3317 }
3318
3319
3320 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3321 *mipsII:
3322 *mipsIII:
3323 *mipsIV:
3324 // start-sanitize-r5900
3325 *r5900:
3326 // end-sanitize-r5900
3327 *r3900:
3328 // start-sanitize-tx19
3329 *tx19:
3330 // end-sanitize-tx19
3331 {
3332   unsigned32 instruction = instruction_0;
3333   int destreg = ((instruction >> 6) & 0x0000001F);
3334   int fs = ((instruction >> 11) & 0x0000001F);
3335   int format = ((instruction >> 21) & 0x00000007);
3336   {
3337   if ((format != fmt_single) && (format != fmt_double))
3338    SignalException(ReservedInstruction,instruction);
3339   else
3340    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3341   }
3342 }
3343
3344
3345 // CFC1
3346 // CTC1
3347 01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
3348 *mipsI:
3349 *mipsII:
3350 *mipsIII:
3351 *mipsIV:
3352 // start-sanitize-r5900
3353 *r5900:
3354 // end-sanitize-r5900
3355 *r3900:
3356 // start-sanitize-tx19
3357 *tx19:
3358 // end-sanitize-tx19
3359 {
3360   unsigned32 instruction = instruction_0;
3361   int fs = ((instruction >> 11) & 0x0000001F);
3362   int ft = ((instruction >> 16) & 0x0000001F);
3363   int to = ((instruction >> 23) & 0x00000001);
3364   {
3365     if (to) {
3366       if (fs == 0) {
3367         PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
3368       } else if (fs == 31) {
3369         PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
3370       } /* else NOP */
3371       PENDING_FILL(COCIDX,0); /* special case */
3372     } else { /* control from */
3373       if (fs == 0) {
3374         PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
3375       } else if (fs == 31) {
3376         PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
3377       } /* else NOP */
3378     }
3379   }
3380 }
3381
3382
3383 //
3384 // FIXME: Does not correctly differentiate between mips*
3385 //
3386 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3387 "cvt.d.%s<FMT> f<FD>, f<FS>"
3388 *mipsI:
3389 *mipsII:
3390 *mipsIII:
3391 *mipsIV:
3392 // start-sanitize-r5900
3393 *r5900:
3394 // end-sanitize-r5900
3395 *r3900:
3396 // start-sanitize-tx19
3397 *tx19:
3398 // end-sanitize-tx19
3399 {
3400   unsigned32 instruction = instruction_0;
3401   int destreg = ((instruction >> 6) & 0x0000001F);
3402   int fs = ((instruction >> 11) & 0x0000001F);
3403   int format = ((instruction >> 21) & 0x00000007);
3404   {
3405     if ((format == fmt_double) | 0)
3406       SignalException(ReservedInstruction,instruction);
3407     else
3408       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3409   }
3410 }
3411
3412
3413 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3414 "cvt.l.%s<FMT> f<FD>, f<FS>"
3415 *mipsIII:
3416 *mipsIV:
3417 // start-sanitize-r5900
3418 *r5900:
3419 // end-sanitize-r5900
3420 *r3900:
3421 // start-sanitize-tx19
3422 *tx19:
3423 // end-sanitize-tx19
3424 {
3425   unsigned32 instruction = instruction_0;
3426   int destreg = ((instruction >> 6) & 0x0000001F);
3427   int fs = ((instruction >> 11) & 0x0000001F);
3428   int format = ((instruction >> 21) & 0x00000007);
3429   {
3430     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3431       SignalException(ReservedInstruction,instruction);
3432     else
3433       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3434   }
3435 }
3436
3437
3438 //
3439 // FIXME: Does not correctly differentiate between mips*
3440 //
3441 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3442 "cvt.s.%s<FMT> f<FD>, f<FS>"
3443 *mipsI:
3444 *mipsII:
3445 *mipsIII:
3446 *mipsIV:
3447 // start-sanitize-r5900
3448 *r5900:
3449 // end-sanitize-r5900
3450 *r3900:
3451 // start-sanitize-tx19
3452 *tx19:
3453 // end-sanitize-tx19
3454 {
3455   unsigned32 instruction = instruction_0;
3456   int destreg = ((instruction >> 6) & 0x0000001F);
3457   int fs = ((instruction >> 11) & 0x0000001F);
3458   int format = ((instruction >> 21) & 0x00000007);
3459   {
3460     if ((format == fmt_single) | 0)
3461       SignalException(ReservedInstruction,instruction);
3462     else
3463       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3464   }
3465 }
3466
3467
3468 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3469 "cvt.w.%s<FMT> f<FD>, f<FS>"
3470 *mipsI:
3471 *mipsII:
3472 *mipsIII:
3473 *mipsIV:
3474 // start-sanitize-r5900
3475 *r5900:
3476 // end-sanitize-r5900
3477 *r3900:
3478 // start-sanitize-tx19
3479 *tx19:
3480 // end-sanitize-tx19
3481 {
3482   unsigned32 instruction = instruction_0;
3483   int destreg = ((instruction >> 6) & 0x0000001F);
3484   int fs = ((instruction >> 11) & 0x0000001F);
3485   int format = ((instruction >> 21) & 0x00000007);
3486   {
3487     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3488       SignalException(ReservedInstruction,instruction);
3489     else
3490       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3491   }
3492 }
3493
3494
3495 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3496 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3497 *mipsI:
3498 *mipsII:
3499 *mipsIII:
3500 *mipsIV:
3501 // start-sanitize-r5900
3502 *r5900:
3503 // end-sanitize-r5900
3504 *r3900:
3505 // start-sanitize-tx19
3506 *tx19:
3507 // end-sanitize-tx19
3508 {
3509   unsigned32 instruction = instruction_0;
3510   int destreg = ((instruction >> 6) & 0x0000001F);
3511   int fs = ((instruction >> 11) & 0x0000001F);
3512   int ft = ((instruction >> 16) & 0x0000001F);
3513   int format = ((instruction >> 21) & 0x00000007);
3514   {
3515     if ((format != fmt_single) && (format != fmt_double))
3516       SignalException(ReservedInstruction,instruction);
3517     else
3518       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3519   }
3520 }
3521
3522
3523 // DMFC1
3524 // DMTC1
3525 01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
3526 *mipsIII:
3527 *mipsIV:
3528 // start-sanitize-r5900
3529 *r5900:
3530 // end-sanitize-r5900
3531 *r3900:
3532 // start-sanitize-tx19
3533 *tx19:
3534 // end-sanitize-tx19
3535 {
3536   unsigned32 instruction = instruction_0;
3537   int fs = ((instruction >> 11) & 0x0000001F);
3538   int ft = ((instruction >> 16) & 0x0000001F);
3539   int to = ((instruction >> 23) & 0x00000001);
3540   {
3541     if (to) {
3542       if (SizeFGR() == 64) {
3543         PENDING_FILL((fs + FGRIDX),GPR[ft]);
3544       } else
3545         if ((fs & 0x1) == 0)
3546           {
3547             PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
3548             PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
3549           }
3550     } else {
3551       if (SizeFGR() == 64) {
3552         PENDING_FILL(ft,FGR[fs]);
3553       } else
3554         if ((fs & 0x1) == 0) {
3555           PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
3556         } else {
3557           PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3558         }
3559     }
3560   }
3561 }
3562
3563
3564 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3565 "floor.l.%s<FMT> f<FD>, f<FS>"
3566 *mipsIII:
3567 *mipsIV:
3568 // start-sanitize-r5900
3569 *r5900:
3570 // end-sanitize-r5900
3571 *r3900:
3572 // start-sanitize-tx19
3573 *tx19:
3574 // end-sanitize-tx19
3575 {
3576   unsigned32 instruction = instruction_0;
3577   int destreg = ((instruction >> 6) & 0x0000001F);
3578   int fs = ((instruction >> 11) & 0x0000001F);
3579   int format = ((instruction >> 21) & 0x00000007);
3580   {
3581     if ((format != fmt_single) && (format != fmt_double))
3582       SignalException(ReservedInstruction,instruction);
3583     else
3584       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3585   }
3586 }
3587
3588
3589 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3590 "floor.w.%s<FMT> f<FD>, f<FS>"
3591 *mipsII:
3592 *mipsIII:
3593 *mipsIV:
3594 // start-sanitize-r5900
3595 *r5900:
3596 // end-sanitize-r5900
3597 *r3900:
3598 // start-sanitize-tx19
3599 *tx19:
3600 // end-sanitize-tx19
3601 {
3602   unsigned32 instruction = instruction_0;
3603   int destreg = ((instruction >> 6) & 0x0000001F);
3604   int fs = ((instruction >> 11) & 0x0000001F);
3605   int format = ((instruction >> 21) & 0x00000007);
3606   {
3607     if ((format != fmt_single) && (format != fmt_double))
3608       SignalException(ReservedInstruction,instruction);
3609     else
3610       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3611   }
3612 }
3613
3614
3615 // LDC1
3616 110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
3617
3618
3619 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3620 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3621 *mipsIV:
3622 // start-sanitize-r5900
3623 *r5900:
3624 // end-sanitize-r5900
3625 {
3626   unsigned32 instruction = instruction_0;
3627   int destreg = ((instruction >> 6) & 0x0000001F);
3628   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3629   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3630   {
3631     unsigned64 vaddr = ((unsigned64)op1 + op2);
3632     unsigned64 paddr;
3633     int uncached;
3634     if ((vaddr & 7) != 0)
3635       SignalExceptionAddressLoad();
3636     else
3637       {
3638         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3639           {
3640             unsigned64 memval = 0;
3641             unsigned64 memval1 = 0;
3642             unsigned64 mask = 0x7;
3643             unsigned int shift = 4;
3644             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
3645             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
3646             unsigned int byte;
3647             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
3648             COP_LD(1,destreg,memval);;
3649           }
3650       }
3651   }
3652 }
3653
3654
3655 // LWC1
3656 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3657
3658
3659 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3660 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3661 *mipsIV:
3662 // start-sanitize-r5900
3663 *r5900:
3664 // end-sanitize-r5900
3665 {
3666   unsigned32 instruction = instruction_0;
3667   int destreg = ((instruction >> 6) & 0x0000001F);
3668   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3669   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3670   {
3671    unsigned64 vaddr = ((unsigned64)op1 + op2);
3672    unsigned64 paddr;
3673    int uncached;
3674    if ((vaddr & 3) != 0)
3675     SignalExceptionAddressLoad();
3676    else
3677    {
3678     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3679     {
3680      unsigned64 memval = 0;
3681      unsigned64 memval1 = 0;
3682      unsigned64 mask = 0x7;
3683      unsigned int shift = 2;
3684      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
3685      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
3686      unsigned int byte;
3687      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
3688      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
3689      byte = ((vaddr & mask) ^ (bigend << shift));
3690      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
3691     }
3692    }
3693   }
3694 }
3695
3696
3697
3698 //
3699 // FIXME: Not correct for mips*
3700 //
3701 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
3702 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3703 *mipsIV:
3704 // start-sanitize-r5900
3705 *r5900:
3706 // end-sanitize-r5900
3707 {
3708   unsigned32 instruction = instruction_0;
3709   int destreg = ((instruction >> 6) & 0x0000001F);
3710   int fs = ((instruction >> 11) & 0x0000001F);
3711   int ft = ((instruction >> 16) & 0x0000001F);
3712   int fr = ((instruction >> 21) & 0x0000001F);
3713   {
3714     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3715   }
3716 }
3717
3718
3719 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
3720 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3721 *mipsIV:
3722 // start-sanitize-r5900
3723 *r5900:
3724 // end-sanitize-r5900
3725 {
3726   unsigned32 instruction = instruction_0;
3727   int destreg = ((instruction >> 6) & 0x0000001F);
3728   int fs = ((instruction >> 11) & 0x0000001F);
3729   int ft = ((instruction >> 16) & 0x0000001F);
3730   int fr = ((instruction >> 21) & 0x0000001F);
3731   {
3732     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3733   }
3734 }
3735
3736
3737 // MFC1
3738 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
3739 "m<X>c1 r<RT>, f<FS>"
3740 *mipsI:
3741 *mipsII:
3742 *mipsIII:
3743 *mipsIV:
3744 // start-sanitize-r5900
3745 *r5900:
3746 // end-sanitize-r5900
3747 *r3900:
3748 // start-sanitize-tx19
3749 *tx19:
3750 // end-sanitize-tx19
3751 {
3752   unsigned32 instruction = instruction_0;
3753   int fs = ((instruction >> 11) & 0x0000001F);
3754   int ft = ((instruction >> 16) & 0x0000001F);
3755   int to = ((instruction >> 23) & 0x00000001);
3756   {
3757     if (to) {
3758       if (SizeFGR() == 64) {
3759         PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
3760       } else {
3761         PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
3762       }
3763     } else {
3764       PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
3765     }
3766   }
3767 }
3768
3769
3770 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3771 "mov.%s<FMT> f<FD>, f<FS>"
3772 *mipsI:
3773 *mipsII:
3774 *mipsIII:
3775 *mipsIV:
3776 // start-sanitize-r5900
3777 *r5900:
3778 // end-sanitize-r5900
3779 *r3900:
3780 // start-sanitize-tx19
3781 *tx19:
3782 // end-sanitize-tx19
3783 {
3784   unsigned32 instruction = instruction_0;
3785   int destreg = ((instruction >> 6) & 0x0000001F);
3786   int fs = ((instruction >> 11) & 0x0000001F);
3787   int format = ((instruction >> 21) & 0x00000007);
3788   {
3789     StoreFPR(destreg,format,ValueFPR(fs,format));
3790   }
3791 }
3792
3793
3794 // MOVF
3795 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
3796 "mov%s<TF> r<RD>, r<RS>, <CC>"
3797 *mipsIV:
3798 // start-sanitize-r5900
3799 *r5900:
3800 // end-sanitize-r5900
3801 {
3802   if (GETFCC(CC) == TF)
3803     GPR[RD] = GPR[RS];
3804 }
3805
3806
3807 // MOVF.fmt
3808 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3809 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3810 *mipsIV:
3811 // start-sanitize-r5900
3812 *r5900:
3813 // end-sanitize-r5900
3814 {
3815   unsigned32 instruction = instruction_0;
3816   int format = ((instruction >> 21) & 0x00000007);
3817   {
3818    if (GETFCC(CC) == TF)
3819      StoreFPR (FD, format, ValueFPR (FS, format));
3820    else
3821      StoreFPR (FD, format, ValueFPR (FD, format));
3822   }
3823 }
3824
3825
3826 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3827 *mipsIV:
3828 // start-sanitize-r5900
3829 *r5900:
3830 // end-sanitize-r5900
3831 {
3832   unsigned32 instruction = instruction_0;
3833   int destreg = ((instruction >> 6) & 0x0000001F);
3834   int fs = ((instruction >> 11) & 0x0000001F);
3835   int format = ((instruction >> 21) & 0x00000007);
3836   {
3837     StoreFPR(destreg,format,ValueFPR(fs,format));
3838   }
3839 }
3840
3841
3842 // MOVT see MOVtf
3843
3844
3845 // MOVT.fmt see MOVtf.fmt
3846
3847
3848
3849 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3850 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3851 *mipsIV:
3852 // start-sanitize-r5900
3853 *r5900:
3854 // end-sanitize-r5900
3855 {
3856   unsigned32 instruction = instruction_0;
3857   int destreg = ((instruction >> 6) & 0x0000001F);
3858   int fs = ((instruction >> 11) & 0x0000001F);
3859   int format = ((instruction >> 21) & 0x00000007);
3860   {
3861    StoreFPR(destreg,format,ValueFPR(fs,format));
3862   }
3863 }
3864
3865
3866 // MSUB.fmt
3867 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3868 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3869 *mipsIV:
3870 // start-sanitize-r5900
3871 *r5900:
3872 // end-sanitize-r5900
3873 {
3874   unsigned32 instruction = instruction_0;
3875   int destreg = ((instruction >> 6) & 0x0000001F);
3876   int fs = ((instruction >> 11) & 0x0000001F);
3877   int ft = ((instruction >> 16) & 0x0000001F);
3878   int fr = ((instruction >> 21) & 0x0000001F);
3879   {
3880     StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3881   }
3882 }
3883
3884
3885 // MSUB.fmt
3886 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3887 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3888 *mipsIV:
3889 // start-sanitize-r5900
3890 *r5900:
3891 // end-sanitize-r5900
3892 {
3893   unsigned32 instruction = instruction_0;
3894   int destreg = ((instruction >> 6) & 0x0000001F);
3895   int fs = ((instruction >> 11) & 0x0000001F);
3896   int ft = ((instruction >> 16) & 0x0000001F);
3897   int fr = ((instruction >> 21) & 0x0000001F);
3898   {
3899    StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3900   }
3901 }
3902
3903
3904 // MTC1 see MxC1
3905
3906
3907 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3908 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3909 *mipsI:
3910 *mipsII:
3911 *mipsIII:
3912 *mipsIV:
3913 // start-sanitize-r5900
3914 *r5900:
3915 // end-sanitize-r5900
3916 *r3900:
3917 // start-sanitize-tx19
3918 *tx19:
3919 // end-sanitize-tx19
3920 {
3921   unsigned32 instruction = instruction_0;
3922   int destreg = ((instruction >> 6) & 0x0000001F);
3923   int fs = ((instruction >> 11) & 0x0000001F);
3924   int ft = ((instruction >> 16) & 0x0000001F);
3925   int format = ((instruction >> 21) & 0x00000007);
3926   {
3927     if ((format != fmt_single) && (format != fmt_double))
3928       SignalException(ReservedInstruction,instruction);
3929     else
3930       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3931   }
3932 }
3933
3934
3935 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3936 "neg.%s<FMT> f<FD>, f<FS>"
3937 *mipsI:
3938 *mipsII:
3939 *mipsIII:
3940 *mipsIV:
3941 // start-sanitize-r5900
3942 *r5900:
3943 // end-sanitize-r5900
3944 *r3900:
3945 // start-sanitize-tx19
3946 *tx19:
3947 // end-sanitize-tx19
3948 {
3949   unsigned32 instruction = instruction_0;
3950   int destreg = ((instruction >> 6) & 0x0000001F);
3951   int fs = ((instruction >> 11) & 0x0000001F);
3952   int format = ((instruction >> 21) & 0x00000007);
3953   {
3954     if ((format != fmt_single) && (format != fmt_double))
3955       SignalException(ReservedInstruction,instruction);
3956     else
3957       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3958   }
3959 }
3960
3961
3962 // NMADD.fmt
3963 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3964 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3965 *mipsIV:
3966 {
3967   unsigned32 instruction = instruction_0;
3968   int destreg = ((instruction >> 6) & 0x0000001F);
3969   int fs = ((instruction >> 11) & 0x0000001F);
3970   int ft = ((instruction >> 16) & 0x0000001F);
3971   int fr = ((instruction >> 21) & 0x0000001F);
3972   {
3973    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3974   }
3975 }
3976
3977
3978 // NMADD.fmt
3979 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3980 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3981 *mipsIV:
3982 {
3983   unsigned32 instruction = instruction_0;
3984   int destreg = ((instruction >> 6) & 0x0000001F);
3985   int fs = ((instruction >> 11) & 0x0000001F);
3986   int ft = ((instruction >> 16) & 0x0000001F);
3987   int fr = ((instruction >> 21) & 0x0000001F);
3988   {
3989    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3990   }
3991 }
3992
3993
3994 // NMSUB.fmt
3995 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3996 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3997 *mipsIV:
3998 {
3999   unsigned32 instruction = instruction_0;
4000   int destreg = ((instruction >> 6) & 0x0000001F);
4001   int fs = ((instruction >> 11) & 0x0000001F);
4002   int ft = ((instruction >> 16) & 0x0000001F);
4003   int fr = ((instruction >> 21) & 0x0000001F);
4004   {
4005    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4006   }
4007 }
4008
4009
4010 // NMSUB.fmt
4011 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4012 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4013 *mipsIV:
4014 {
4015   unsigned32 instruction = instruction_0;
4016   int destreg = ((instruction >> 6) & 0x0000001F);
4017   int fs = ((instruction >> 11) & 0x0000001F);
4018   int ft = ((instruction >> 16) & 0x0000001F);
4019   int fr = ((instruction >> 21) & 0x0000001F);
4020   {
4021     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4022   }
4023 }
4024
4025
4026 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4027 "prefx <HINT>, r<INDEX>(r<BASE>)"
4028 *mipsIV:
4029 {
4030   unsigned32 instruction = instruction_0;
4031   int fs = ((instruction >> 11) & 0x0000001F);
4032   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4033   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4034   {
4035     unsigned64 vaddr = ((unsigned64)op1 + (unsigned64)op2);
4036     unsigned64 paddr;
4037     int uncached;
4038     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4039       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4040   }
4041 }
4042
4043 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4044 *mipsIV:
4045 "recip.%s<FMT> f<FD>, f<FS>"
4046 {
4047   unsigned32 instruction = instruction_0;
4048   int destreg = ((instruction >> 6) & 0x0000001F);
4049   int fs = ((instruction >> 11) & 0x0000001F);
4050   int format = ((instruction >> 21) & 0x00000007);
4051   {
4052   if ((format != fmt_single) && (format != fmt_double))
4053    SignalException(ReservedInstruction,instruction);
4054   else
4055    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4056   }
4057 }
4058
4059
4060 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4061 "round.l.%s<FMT> f<FD>, f<FS>"
4062 *mipsIII:
4063 *mipsIV:
4064 // start-sanitize-r5900
4065 *r5900:
4066 // end-sanitize-r5900
4067 *r3900:
4068 // start-sanitize-tx19
4069 *tx19:
4070 // end-sanitize-tx19
4071 {
4072   unsigned32 instruction = instruction_0;
4073   int destreg = ((instruction >> 6) & 0x0000001F);
4074   int fs = ((instruction >> 11) & 0x0000001F);
4075   int format = ((instruction >> 21) & 0x00000007);
4076   {
4077     if ((format != fmt_single) && (format != fmt_double))
4078       SignalException(ReservedInstruction,instruction);
4079     else
4080       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4081   }
4082 }
4083
4084
4085 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4086 "round.w.%s<FMT> f<FD>, f<FS>"
4087 *mipsII:
4088 *mipsIII:
4089 *mipsIV:
4090 // start-sanitize-r5900
4091 *r5900:
4092 // end-sanitize-r5900
4093 *r3900:
4094 // start-sanitize-tx19
4095 *tx19:
4096 // end-sanitize-tx19
4097 {
4098   unsigned32 instruction = instruction_0;
4099   int destreg = ((instruction >> 6) & 0x0000001F);
4100   int fs = ((instruction >> 11) & 0x0000001F);
4101   int format = ((instruction >> 21) & 0x00000007);
4102   {
4103   if ((format != fmt_single) && (format != fmt_double))
4104    SignalException(ReservedInstruction,instruction);
4105   else
4106    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4107   }
4108 }
4109
4110
4111 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4112 *mipsIV:
4113 "rsqrt.%s<FMT> f<FD>, f<FS>"
4114 {
4115   unsigned32 instruction = instruction_0;
4116   int destreg = ((instruction >> 6) & 0x0000001F);
4117   int fs = ((instruction >> 11) & 0x0000001F);
4118   int format = ((instruction >> 21) & 0x00000007);
4119   {
4120   if ((format != fmt_single) && (format != fmt_double))
4121    SignalException(ReservedInstruction,instruction);
4122   else
4123    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format)));
4124   }
4125 }
4126
4127
4128 // SDC1
4129
4130
4131 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4132 *mipsIV:
4133 // start-sanitize-r5900
4134 *r5900:
4135 // end-sanitize-r5900
4136 {
4137   unsigned32 instruction = instruction_0;
4138   int fs = ((instruction >> 11) & 0x0000001F);
4139   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4140   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4141   {
4142     unsigned64 vaddr = ((unsigned64)op1 + op2);
4143     unsigned64 paddr;
4144     int uncached;
4145     if ((vaddr & 7) != 0)
4146       SignalExceptionAddressStore();
4147     else
4148       {
4149         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4150           {
4151             unsigned64 memval = 0;
4152             unsigned64 memval1 = 0;
4153             memval = (unsigned64)COP_SD(1,fs);
4154             {
4155               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4156             }
4157           }
4158       }
4159   }
4160 }
4161
4162
4163 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4164 "sqrt.%s<FMT> f<FD>, f<FS>"
4165 *mipsII:
4166 *mipsIII:
4167 *mipsIV:
4168 // start-sanitize-r5900
4169 *r5900:
4170 // end-sanitize-r5900
4171 *r3900:
4172 // start-sanitize-tx19
4173 *tx19:
4174 // end-sanitize-tx19
4175 {
4176   unsigned32 instruction = instruction_0;
4177   int destreg = ((instruction >> 6) & 0x0000001F);
4178   int fs = ((instruction >> 11) & 0x0000001F);
4179   int format = ((instruction >> 21) & 0x00000007);
4180   {
4181     if ((format != fmt_single) && (format != fmt_double))
4182       SignalException(ReservedInstruction,instruction);
4183     else
4184       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4185   }
4186 }
4187
4188
4189 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4190 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4191 *mipsI:
4192 *mipsII:
4193 *mipsIII:
4194 *mipsIV:
4195 // start-sanitize-r5900
4196 *r5900:
4197 // end-sanitize-r5900
4198 *r3900:
4199 // start-sanitize-tx19
4200 *tx19:
4201 // end-sanitize-tx19
4202 {
4203   unsigned32 instruction = instruction_0;
4204   int destreg = ((instruction >> 6) & 0x0000001F);
4205   int fs = ((instruction >> 11) & 0x0000001F);
4206   int ft = ((instruction >> 16) & 0x0000001F);
4207   int format = ((instruction >> 21) & 0x00000007);
4208   {
4209     if ((format != fmt_single) && (format != fmt_double))
4210       SignalException(ReservedInstruction,instruction);
4211     else
4212       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4213   }
4214 }
4215
4216
4217 // SWC1
4218
4219
4220 010011,5.BASE,5.FT,5.FS,00000,001000:COP1X:32::SWXC1
4221 "swxc1 f<FT>, r<OFFSET>(r<BASE>)"
4222 *mipsIV:
4223 // start-sanitize-r5900
4224 *r5900:
4225 // end-sanitize-r5900
4226 {
4227   unsigned32 instruction = instruction_0;
4228   int fs = ((instruction >> 11) & 0x0000001F);
4229   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4230   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4231   {
4232    unsigned64 vaddr = ((unsigned64)op1 + op2);
4233    unsigned64 paddr;
4234    int uncached;
4235    if ((vaddr & 3) != 0)
4236     SignalExceptionAddressStore();
4237    else
4238    {
4239     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4240     {
4241      unsigned64 memval = 0;
4242      unsigned64 memval1 = 0;
4243      unsigned64 mask = 0x7;
4244      unsigned int byte;
4245      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4246      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4247      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4248       {
4249        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4250       }
4251     }
4252    }
4253   }
4254 }
4255
4256
4257 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4258 "trunc.l.%s<FMT> f<FD>, f<FS>"
4259 *mipsIII:
4260 *mipsIV:
4261 // start-sanitize-r5900
4262 *r5900:
4263 // end-sanitize-r5900
4264 *r3900:
4265 // start-sanitize-tx19
4266 *tx19:
4267 // end-sanitize-tx19
4268 {
4269   unsigned32 instruction = instruction_0;
4270   int destreg = ((instruction >> 6) & 0x0000001F);
4271   int fs = ((instruction >> 11) & 0x0000001F);
4272   int format = ((instruction >> 21) & 0x00000007);
4273   {
4274   if ((format != fmt_single) && (format != fmt_double))
4275    SignalException(ReservedInstruction,instruction);
4276   else
4277    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4278   }
4279 }
4280
4281
4282 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4283 "trunc.w.%s<FMT> f<FD>, f<FS>"
4284 *mipsII:
4285 *mipsIII:
4286 *mipsIV:
4287 // start-sanitize-r5900
4288 *r5900:
4289 // end-sanitize-r5900
4290 *r3900:
4291 // start-sanitize-tx19
4292 *tx19:
4293 // end-sanitize-tx19
4294 {
4295   unsigned32 instruction = instruction_0;
4296   int destreg = ((instruction >> 6) & 0x0000001F);
4297   int fs = ((instruction >> 11) & 0x0000001F);
4298   int format = ((instruction >> 21) & 0x00000007);
4299   {
4300   if ((format != fmt_single) && (format != fmt_double))
4301    SignalException(ReservedInstruction,instruction);
4302   else
4303    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4304   }
4305 }
4306
4307 \f
4308 //
4309 // MIPS Architecture:
4310 //
4311 //        System Control Instruction Set (COP0)
4312 //
4313
4314
4315 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4316 "bc0f <OFFSET>"
4317 *mipsI:
4318 *mipsII:
4319 *mipsIII:
4320 *mipsIV:
4321 // start-sanitize-r5900
4322 *r5900:
4323 // end-sanitize-r5900
4324
4325
4326 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4327 "bc0fl <OFFSET>"
4328 *mipsI:
4329 *mipsII:
4330 *mipsIII:
4331 *mipsIV:
4332 // start-sanitize-r5900
4333 *r5900:
4334 // end-sanitize-r5900
4335
4336
4337 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4338 "bc0t <OFFSET>"
4339 *mipsI:
4340 *mipsII:
4341 *mipsIII:
4342 *mipsIV:
4343 // start-sanitize-r5900
4344 *r5900:
4345 // end-sanitize-r5900
4346
4347
4348
4349 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4350 "bc0tl <OFFSET>"
4351 *mipsI:
4352 *mipsII:
4353 *mipsIII:
4354 *mipsIV:
4355 // start-sanitize-r5900
4356 *r5900:
4357 // end-sanitize-r5900
4358
4359
4360 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4361 *mipsIII:
4362 *mipsIV:
4363 // start-sanitize-r5900
4364 *r5900:
4365 // end-sanitize-r5900
4366 *r3900:
4367 // start-sanitize-tx19
4368 *tx19:
4369 // end-sanitize-tx19
4370 {
4371   unsigned32 instruction = instruction_0;
4372   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4373   int hint = ((instruction >> 16) & 0x0000001F);
4374   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4375   {
4376     unsigned64 vaddr = (op1 + offset);
4377     unsigned64 paddr;
4378     int uncached;
4379     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4380       CacheOp(hint,vaddr,paddr,instruction);
4381   }
4382 }
4383
4384
4385 010000,10000,000000000000000,111001:COP0:32::DI
4386 "di"
4387 *mipsI:
4388 *mipsII:
4389 *mipsIII:
4390 *mipsIV:
4391 // start-sanitize-r5900
4392 *r5900:
4393 // end-sanitize-r5900
4394
4395
4396 010000,10000,000000000000000,111000:COP0:32::EI
4397 "ei"
4398 *mipsI:
4399 *mipsII:
4400 *mipsIII:
4401 *mipsIV:
4402 // start-sanitize-r5900
4403 *r5900:
4404 // end-sanitize-r5900
4405
4406
4407 010000,10000,000000000000000,011000:COP0:32::ERET
4408 "eret"
4409 *mipsIII:
4410 *mipsIV:
4411 // start-sanitize-r5900
4412 *r5900:
4413 // end-sanitize-r5900
4414
4415
4416 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4417 "mfc0 r<RT>, r<RD> # <REGX>"
4418 *mipsI:
4419 *mipsII:
4420 *mipsIII:
4421 *mipsIV:
4422 // start-sanitize-r5900
4423 *r5900:
4424 // end-sanitize-r5900
4425
4426
4427 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4428 "mtc0 r<RT>, r<RD> # <REGX>"
4429 *mipsI:
4430 *mipsII:
4431 *mipsIII:
4432 *mipsIV:
4433 // start-sanitize-r5900
4434 *r5900:
4435 // end-sanitize-r5900
4436
4437
4438 010000,10000,000000000000000,001000:COP0:32::TLBP
4439 "tlbp"
4440 *mipsI:
4441 *mipsII:
4442 *mipsIII:
4443 *mipsIV:
4444 // start-sanitize-r5900
4445 *r5900:
4446 // end-sanitize-r5900
4447
4448
4449 010000,10000,000000000000000,000001:COP0:32::TLBR
4450 "tlbr"
4451 *mipsI:
4452 *mipsII:
4453 *mipsIII:
4454 *mipsIV:
4455 // start-sanitize-r5900
4456 *r5900:
4457 // end-sanitize-r5900
4458
4459
4460 010000,10000,000000000000000,000010:COP0:32::TLBWI
4461 "tlbwi"
4462 *mipsI:
4463 *mipsII:
4464 *mipsIII:
4465 *mipsIV:
4466 // start-sanitize-r5900
4467 *r5900:
4468 // end-sanitize-r5900
4469
4470
4471 010000,10000,000000000000000,000110:COP0:32::TLBWR
4472 "tlbwr"
4473 *mipsI:
4474 *mipsII:
4475 *mipsIII:
4476 *mipsIV:
4477 // start-sanitize-r5900
4478 *r5900:
4479 // end-sanitize-r5900
4480
4481 \f
4482 //
4483 // MIPS Architecture:
4484 //
4485 //        CPU Instruction Set (mips16)
4486 //
4487
4488 // The instructions in this section are ordered according
4489 // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
4490
4491
4492 // Load and Store Instructions
4493
4494
4495 10000,xxx,ddd,55555:RRI:16::LB
4496 *mips16:
4497 {
4498   unsigned32 instruction = instruction_0;
4499   signed_word op1 = (instruction >> 8) & 0x7;
4500   int destreg = (instruction >> 5) & 0x7;
4501   int offset = (instruction >> 0) & 0x1f;
4502   if (op1 < 2)
4503     op1 += 16;
4504   op1 = GPR[op1];
4505   if (destreg < 2)
4506     destreg += 16;
4507   if (have_extendval)
4508     {
4509       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4510       if (offset >= 0x8000)
4511         offset -= 0x10000;
4512       have_extendval = 0;
4513     }
4514   else
4515     {
4516     }
4517   if (have_extendval)
4518     SignalException (ReservedInstruction, instruction);
4519   {
4520     unsigned64 vaddr = ((unsigned64)op1 + offset);
4521     unsigned64 paddr;
4522     int uncached;
4523     {
4524       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4525         {
4526           unsigned64 memval = 0;
4527           unsigned64 memval1 = 0;
4528           unsigned64 mask = 0x7;
4529           unsigned int shift = 0;
4530           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4531           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4532           unsigned int byte;
4533           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4534           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
4535           byte = ((vaddr & mask) ^ (bigend << shift));
4536           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
4537         }
4538     }
4539   }
4540 }
4541
4542
4543 10100,xxx,ddd,55555:RRI:16::LBU
4544 *mips16:
4545 {
4546   unsigned32 instruction = instruction_0;
4547   signed_word op1 = (instruction >> 8) & 0x7;
4548   int destreg = (instruction >> 5) & 0x7;
4549   int offset = (instruction >> 0) & 0x1f;
4550   if (op1 < 2)
4551     op1 += 16;
4552   op1 = GPR[op1];
4553   if (destreg < 2)
4554     destreg += 16;
4555   if (have_extendval)
4556     {
4557       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4558       if (offset >= 0x8000)
4559         offset -= 0x10000;
4560       have_extendval = 0;
4561     }
4562   else
4563     {
4564     }
4565   if (have_extendval)
4566     SignalException (ReservedInstruction, instruction);
4567   {
4568     unsigned64 vaddr = ((unsigned64)op1 + offset);
4569     unsigned64 paddr;
4570     int uncached;
4571     {
4572       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4573         {
4574           unsigned64 memval = 0;
4575           unsigned64 memval1 = 0;
4576           unsigned64 mask = 0x7;
4577           unsigned int shift = 0;
4578           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4579           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4580           unsigned int byte;
4581           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4582           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
4583           byte = ((vaddr & mask) ^ (bigend << shift));
4584           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
4585         }
4586     }
4587   }
4588 }
4589
4590
4591 10001,xxx,ddd,HHHHH:RRI:16::LH
4592 *mips16:
4593 {
4594   unsigned32 instruction = instruction_0;
4595   signed_word op1 = (instruction >> 8) & 0x7;
4596   int destreg = (instruction >> 5) & 0x7;
4597   int offset = (instruction >> 0) & 0x1f;
4598   if (op1 < 2)
4599     op1 += 16;
4600   op1 = GPR[op1];
4601   if (destreg < 2)
4602     destreg += 16;
4603   if (have_extendval)
4604     {
4605       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4606       if (offset >= 0x8000)
4607         offset -= 0x10000;
4608       have_extendval = 0;
4609     }
4610   else
4611     {
4612       offset <<= 1;
4613     }
4614   if (have_extendval)
4615     SignalException (ReservedInstruction, instruction);
4616   {
4617     unsigned64 vaddr = ((unsigned64)op1 + offset);
4618     unsigned64 paddr;
4619     int uncached;
4620     if ((vaddr & 1) != 0)
4621       SignalExceptionAddressLoad();
4622     else
4623       {
4624         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4625           {
4626             unsigned64 memval = 0;
4627             unsigned64 memval1 = 0;
4628             unsigned64 mask = 0x7;
4629             unsigned int shift = 1;
4630             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4631             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4632             unsigned int byte;
4633             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4634             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
4635             byte = ((vaddr & mask) ^ (bigend << shift));
4636             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
4637           }
4638       }
4639   }
4640 }
4641
4642
4643 10101,xxx,ddd,HHHHH:RRI:16::LHU
4644 *mips16:
4645 {
4646   unsigned32 instruction = instruction_0;
4647   signed_word op1 = (instruction >> 8) & 0x7;
4648   int destreg = (instruction >> 5) & 0x7;
4649   int offset = (instruction >> 0) & 0x1f;
4650   if (op1 < 2)
4651     op1 += 16;
4652   op1 = GPR[op1];
4653   if (destreg < 2)
4654     destreg += 16;
4655   if (have_extendval)
4656     {
4657       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4658       if (offset >= 0x8000)
4659         offset -= 0x10000;
4660       have_extendval = 0;
4661     }
4662   else
4663     {
4664       offset <<= 1;
4665     }
4666   if (have_extendval)
4667     SignalException (ReservedInstruction, instruction);
4668   {
4669     unsigned64 vaddr = ((unsigned64)op1 + offset);
4670     unsigned64 paddr;
4671     int uncached;
4672     if ((vaddr & 1) != 0)
4673       SignalExceptionAddressLoad();
4674     else
4675       {
4676         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4677           {
4678             unsigned64 memval = 0;
4679             unsigned64 memval1 = 0;
4680             unsigned64 mask = 0x7;
4681             unsigned int shift = 1;
4682             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4683             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4684             unsigned int byte;
4685             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4686             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
4687             byte = ((vaddr & mask) ^ (bigend << shift));
4688             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
4689           }
4690       }
4691   }
4692 }
4693
4694
4695 10011,xxx,ddd,WWWWW:RRI:16::LW
4696 *mips16:
4697 {
4698   unsigned32 instruction = instruction_0;
4699   signed_word op1 = (instruction >> 8) & 0x7;
4700   int destreg = (instruction >> 5) & 0x7;
4701   int offset = (instruction >> 0) & 0x1f;
4702   if (op1 < 2)
4703     op1 += 16;
4704   op1 = GPR[op1];
4705   if (destreg < 2)
4706     destreg += 16;
4707   if (have_extendval)
4708     {
4709       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4710       if (offset >= 0x8000)
4711         offset -= 0x10000;
4712       have_extendval = 0;
4713     }
4714   else
4715     {
4716       offset <<= 2;
4717     }
4718   if (have_extendval)
4719     SignalException (ReservedInstruction, instruction);
4720   {
4721     unsigned64 vaddr = ((unsigned64)op1 + offset);
4722     unsigned64 paddr;
4723     int uncached;
4724     if ((vaddr & 3) != 0)
4725       SignalExceptionAddressLoad();
4726     else
4727       {
4728         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4729           {
4730             unsigned64 memval = 0;
4731             unsigned64 memval1 = 0;
4732             unsigned64 mask = 0x7;
4733             unsigned int shift = 2;
4734             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4735             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4736             unsigned int byte;
4737             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4738             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4739             byte = ((vaddr & mask) ^ (bigend << shift));
4740             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4741           }
4742       }
4743   }
4744 }
4745
4746
4747 10110,ddd,VVVVVVVV,P:RI:16::LWPC
4748 *mips16:
4749 {
4750   unsigned32 instruction = instruction_0;
4751   int destreg = (instruction >> 8) & 0x7;
4752   int offset = (instruction >> 0) & 0xff;
4753   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
4754   if (destreg < 2)
4755     destreg += 16;
4756   if (have_extendval)
4757     {
4758       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4759       if (offset >= 0x8000)
4760         offset -= 0x10000;
4761       have_extendval = 0;
4762     }
4763   else
4764     {
4765       offset <<= 2;
4766     }
4767   if (have_extendval)
4768     SignalException (ReservedInstruction, instruction);
4769   {
4770     unsigned64 vaddr = ((unsigned64)op1 + offset);
4771     unsigned64 paddr;
4772     int uncached;
4773     if ((vaddr & 3) != 0)
4774       SignalExceptionAddressLoad();
4775     else
4776       {
4777         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4778           {
4779             unsigned64 memval = 0;
4780             unsigned64 memval1 = 0;
4781             unsigned64 mask = 0x7;
4782             unsigned int shift = 2;
4783             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4784             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4785             unsigned int byte;
4786             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4787             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4788             byte = ((vaddr & mask) ^ (bigend << shift));
4789             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4790           }
4791       }
4792   }
4793 }
4794
4795
4796 10010,ddd,VVVVVVVV,s:RI:16::LWSP
4797 *mips16:
4798 {
4799   unsigned32 instruction = instruction_0;
4800   int destreg = (instruction >> 8) & 0x7;
4801   int offset = (instruction >> 0) & 0xff;
4802   signed_word op1 = 29;
4803   if (destreg < 2)
4804     destreg += 16;
4805   if (have_extendval)
4806     {
4807       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4808       if (offset >= 0x8000)
4809         offset -= 0x10000;
4810       have_extendval = 0;
4811     }
4812   else
4813     {
4814       offset <<= 2;
4815     }
4816   op1 = GPR[op1];
4817   if (have_extendval)
4818     SignalException (ReservedInstruction, instruction);
4819   {
4820     unsigned64 vaddr = ((unsigned64)op1 + offset);
4821     unsigned64 paddr;
4822     int uncached;
4823     if ((vaddr & 3) != 0)
4824       SignalExceptionAddressLoad();
4825     else
4826       {
4827         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4828           {
4829             unsigned64 memval = 0;
4830             unsigned64 memval1 = 0;
4831             unsigned64 mask = 0x7;
4832             unsigned int shift = 2;
4833             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4834             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4835             unsigned int byte;
4836             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4837             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4838             byte = ((vaddr & mask) ^ (bigend << shift));
4839             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4840           }
4841       }
4842   }
4843 }
4844
4845
4846 10111,xxx,ddd,WWWWW:RRI:16::LWU
4847 *mips16:
4848 {
4849   unsigned32 instruction = instruction_0;
4850   signed_word op1 = (instruction >> 8) & 0x7;
4851   int destreg = (instruction >> 5) & 0x7;
4852   int offset = (instruction >> 0) & 0x1f;
4853   if (op1 < 2)
4854     op1 += 16;
4855   op1 = GPR[op1];
4856   if (destreg < 2)
4857     destreg += 16;
4858   if (have_extendval)
4859     {
4860       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4861       if (offset >= 0x8000)
4862         offset -= 0x10000;
4863       have_extendval = 0;
4864     }
4865   else
4866     {
4867       offset <<= 2;
4868     }
4869   if (have_extendval)
4870     SignalException (ReservedInstruction, instruction);
4871   {
4872     unsigned64 vaddr = ((unsigned64)op1 + offset);
4873     unsigned64 paddr;
4874     int uncached;
4875     if ((vaddr & 3) != 0)
4876       SignalExceptionAddressLoad();
4877     else
4878       {
4879         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4880           {
4881             unsigned64 memval = 0;
4882             unsigned64 memval1 = 0;
4883             unsigned64 mask = 0x7;
4884             unsigned int shift = 2;
4885             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4886             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4887             unsigned int byte;
4888             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4889             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4890             byte = ((vaddr & mask) ^ (bigend << shift));
4891             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
4892           }
4893       }
4894   }
4895 }
4896
4897
4898 00111,xxx,ddd,DDDDD:RRI:16::LD
4899 *mips16:
4900 {
4901   unsigned32 instruction = instruction_0;
4902   signed_word op1 = (instruction >> 8) & 0x7;
4903   int destreg = (instruction >> 5) & 0x7;
4904   int offset = (instruction >> 0) & 0x1f;
4905   if (op1 < 2)
4906     op1 += 16;
4907   op1 = GPR[op1];
4908   if (destreg < 2)
4909     destreg += 16;
4910   if (have_extendval)
4911     {
4912       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4913       if (offset >= 0x8000)
4914         offset -= 0x10000;
4915       have_extendval = 0;
4916     }
4917   else
4918     {
4919       offset <<= 3;
4920     }
4921   if (have_extendval)
4922     SignalException (ReservedInstruction, instruction);
4923   {
4924     unsigned64 vaddr = ((unsigned64)op1 + offset);
4925     unsigned64 paddr;
4926     int uncached;
4927     if ((vaddr & 7) != 0)
4928       SignalExceptionAddressLoad();
4929     else
4930       {
4931         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4932           {
4933             unsigned64 memval = 0;
4934             unsigned64 memval1 = 0;
4935             unsigned64 mask = 0x7;
4936             unsigned int shift = 4;
4937             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4938             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4939             unsigned int byte;
4940             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4941             GPR[destreg] = memval;
4942           }
4943       }
4944   }
4945 }
4946
4947
4948 11111100,ddd,5.RD,P:RI64:16::LDPC
4949 *mips16:
4950 {
4951   unsigned32 instruction = instruction_0;
4952   int destreg = (instruction >> 5) & 0x7;
4953   int offset = (instruction >> 0) & 0x1f;
4954   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7;
4955   if (destreg < 2)
4956     destreg += 16;
4957   if (have_extendval)
4958     {
4959       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4960       if (offset >= 0x8000)
4961         offset -= 0x10000;
4962       have_extendval = 0;
4963     }
4964   else
4965     {
4966       offset <<= 3;
4967     }
4968   if (have_extendval)
4969     SignalException (ReservedInstruction, instruction);
4970   {
4971     unsigned64 vaddr = ((unsigned64)op1 + offset);
4972     unsigned64 paddr;
4973     int uncached;
4974     if ((vaddr & 7) != 0)
4975       SignalExceptionAddressLoad();
4976     else
4977       {
4978         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4979           {
4980             unsigned64 memval = 0;
4981             unsigned64 memval1 = 0;
4982             unsigned64 mask = 0x7;
4983             unsigned int shift = 4;
4984             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4985             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4986             unsigned int byte;
4987             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4988             GPR[destreg] = memval;
4989           }
4990       }
4991   }
4992 }
4993
4994
4995 11111000,ddd,5.RD,s:RI64:16::LDSP
4996 *mips16:
4997 {
4998   unsigned32 instruction = instruction_0;
4999   int destreg = (instruction >> 5) & 0x7;
5000   int offset = (instruction >> 0) & 0x1f;
5001   signed_word op1 = 29;
5002   if (destreg < 2)
5003     destreg += 16;
5004   if (have_extendval)
5005     {
5006       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5007       if (offset >= 0x8000)
5008         offset -= 0x10000;
5009       have_extendval = 0;
5010     }
5011   else
5012     {
5013       offset <<= 3;
5014     }
5015   op1 = GPR[op1];
5016   if (have_extendval)
5017     SignalException (ReservedInstruction, instruction);
5018   {
5019     unsigned64 vaddr = ((unsigned64)op1 + offset);
5020     unsigned64 paddr;
5021     int uncached;
5022     if ((vaddr & 7) != 0)
5023       SignalExceptionAddressLoad();
5024     else
5025       {
5026         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5027           {
5028             unsigned64 memval = 0;
5029             unsigned64 memval1 = 0;
5030             unsigned64 mask = 0x7;
5031             unsigned int shift = 4;
5032             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5033             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5034             unsigned int byte;
5035             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
5036             GPR[destreg] = memval;
5037           }
5038       }
5039   }
5040 }
5041
5042
5043 11000,xxx,yyy,55555:RRI:16::SB
5044 *mips16:
5045 {
5046   unsigned32 instruction = instruction_0;
5047   signed_word op1 = (instruction >> 8) & 0x7;
5048   signed_word op2 = (instruction >> 5) & 0x7;
5049   int offset = (instruction >> 0) & 0x1f;
5050   if (op1 < 2)
5051     op1 += 16;
5052   op1 = GPR[op1];
5053   if (op2 < 2)
5054     op2 += 16;
5055   op2 = GPR[op2];
5056   if (have_extendval)
5057     {
5058       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5059       if (offset >= 0x8000)
5060         offset -= 0x10000;
5061       have_extendval = 0;
5062     }
5063   else
5064     {
5065     }
5066   if (have_extendval)
5067     SignalException (ReservedInstruction, instruction);
5068   {
5069     unsigned64 vaddr = ((unsigned64)op1 + offset);
5070     unsigned64 paddr;
5071     int uncached;
5072     {
5073       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5074         {
5075           unsigned64 memval = 0;
5076           unsigned64 memval1 = 0;
5077           unsigned64 mask = 0x7;
5078           unsigned int shift = 0;
5079           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5080           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5081           unsigned int byte;
5082           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5083           byte = ((vaddr & mask) ^ (bigend << shift));
5084           memval = ((unsigned64) op2 << (8 * byte));
5085           {
5086             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
5087           }
5088         }
5089     }
5090   }
5091 }
5092
5093
5094 11001,xxx,yyy,HHHHH:RRI:16::SH
5095 *mips16:
5096 {
5097   unsigned32 instruction = instruction_0;
5098   signed_word op1 = (instruction >> 8) & 0x7;
5099   signed_word op2 = (instruction >> 5) & 0x7;
5100   int offset = (instruction >> 0) & 0x1f;
5101   if (op1 < 2)
5102     op1 += 16;
5103   op1 = GPR[op1];
5104   if (op2 < 2)
5105     op2 += 16;
5106   op2 = GPR[op2];
5107   if (have_extendval)
5108     {
5109       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5110       if (offset >= 0x8000)
5111         offset -= 0x10000;
5112       have_extendval = 0;
5113     }
5114   else
5115     {
5116       offset <<= 1;
5117     }
5118   if (have_extendval)
5119     SignalException (ReservedInstruction, instruction);
5120   {
5121     unsigned64 vaddr = ((unsigned64)op1 + offset);
5122     unsigned64 paddr;
5123     int uncached;
5124     if ((vaddr & 1) != 0)
5125       SignalExceptionAddressStore();
5126     else
5127       {
5128         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5129           {
5130             unsigned64 memval = 0;
5131             unsigned64 memval1 = 0;
5132             unsigned64 mask = 0x7;
5133             unsigned int shift = 1;
5134             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5135             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5136             unsigned int byte;
5137             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5138             byte = ((vaddr & mask) ^ (bigend << shift));
5139             memval = ((unsigned64) op2 << (8 * byte));
5140             {
5141               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
5142             }
5143           }
5144       }
5145   }
5146 }
5147
5148
5149 11011,xxx,yyy,WWWWW:RRI:16::SW
5150 *mips16:
5151 {
5152   unsigned32 instruction = instruction_0;
5153   signed_word op1 = (instruction >> 8) & 0x7;
5154   signed_word op2 = (instruction >> 5) & 0x7;
5155   int offset = (instruction >> 0) & 0x1f;
5156   if (op1 < 2)
5157     op1 += 16;
5158   op1 = GPR[op1];
5159   if (op2 < 2)
5160     op2 += 16;
5161   op2 = GPR[op2];
5162   if (have_extendval)
5163     {
5164       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5165       if (offset >= 0x8000)
5166         offset -= 0x10000;
5167       have_extendval = 0;
5168     }
5169   else
5170     {
5171       offset <<= 2;
5172     }
5173   if (have_extendval)
5174     SignalException (ReservedInstruction, instruction);
5175   {
5176     unsigned64 vaddr = ((unsigned64)op1 + offset);
5177     unsigned64 paddr;
5178     int uncached;
5179     if ((vaddr & 3) != 0)
5180       SignalExceptionAddressStore();
5181     else
5182       {
5183         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5184           {
5185             unsigned64 memval = 0;
5186             unsigned64 memval1 = 0;
5187             unsigned64 mask = 0x7;
5188             unsigned int byte;
5189             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5190             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5191             memval = ((unsigned64) op2 << (8 * byte));
5192             {
5193               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5194             }
5195           }
5196       }
5197   }
5198 }
5199
5200
5201 11010,yyy,VVVVVVVV,s:RI:16::SWSP
5202 *mips16:
5203 {
5204   unsigned32 instruction = instruction_0;
5205   signed_word op2 = (instruction >> 8) & 0x7;
5206   int offset = (instruction >> 0) & 0xff;
5207   signed_word op1 = 29;
5208   if (op2 < 2)
5209     op2 += 16;
5210   op2 = GPR[op2];
5211   if (have_extendval)
5212     {
5213       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5214       if (offset >= 0x8000)
5215         offset -= 0x10000;
5216       have_extendval = 0;
5217     }
5218   else
5219     {
5220       offset <<= 2;
5221     }
5222   op1 = GPR[op1];
5223   if (have_extendval)
5224     SignalException (ReservedInstruction, instruction);
5225   {
5226     unsigned64 vaddr = ((unsigned64)op1 + offset);
5227     unsigned64 paddr;
5228     int uncached;
5229     if ((vaddr & 3) != 0)
5230       SignalExceptionAddressStore();
5231     else
5232       {
5233         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5234           {
5235             unsigned64 memval = 0;
5236             unsigned64 memval1 = 0;
5237             unsigned64 mask = 0x7;
5238             unsigned int byte;
5239             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5240             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5241             memval = ((unsigned64) op2 << (8 * byte));
5242             {
5243               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5244             }
5245           }
5246       }
5247   }
5248 }
5249
5250
5251 01100010,VVVVVVVV,Q,s:I8:16::SWRASP
5252 *mips16:
5253 {
5254   unsigned32 instruction = instruction_0;
5255   int offset = (instruction >> 0) & 0xff;
5256   signed_word op2 = 31;
5257   signed_word op1 = 29;
5258   if (have_extendval)
5259     {
5260       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5261       if (offset >= 0x8000)
5262         offset -= 0x10000;
5263       have_extendval = 0;
5264     }
5265   else
5266     {
5267       offset <<= 2;
5268     }
5269   op2 = GPR[op2];
5270   op1 = GPR[op1];
5271   if (have_extendval)
5272     SignalException (ReservedInstruction, instruction);
5273   {
5274     unsigned64 vaddr = ((unsigned64)op1 + offset);
5275     unsigned64 paddr;
5276     int uncached;
5277     if ((vaddr & 3) != 0)
5278       SignalExceptionAddressStore();
5279     else
5280       {
5281         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5282           {
5283             unsigned64 memval = 0;
5284             unsigned64 memval1 = 0;
5285             unsigned64 mask = 0x7;
5286             unsigned int byte;
5287             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5288             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5289             memval = ((unsigned64) op2 << (8 * byte));
5290             {
5291               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5292             }
5293           }
5294       }
5295   }
5296 }
5297
5298
5299 01111,xxx,yyy,DDDDD:RRI:16::SD
5300 *mips16:
5301 {
5302   unsigned32 instruction = instruction_0;
5303   signed_word op1 = (instruction >> 8) & 0x7;
5304   signed_word op2 = (instruction >> 5) & 0x7;
5305   int offset = (instruction >> 0) & 0x1f;
5306   if (op1 < 2)
5307     op1 += 16;
5308   op1 = GPR[op1];
5309   if (op2 < 2)
5310     op2 += 16;
5311   op2 = GPR[op2];
5312   if (have_extendval)
5313     {
5314       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5315       if (offset >= 0x8000)
5316         offset -= 0x10000;
5317       have_extendval = 0;
5318     }
5319   else
5320     {
5321       offset <<= 3;
5322     }
5323   if (have_extendval)
5324     SignalException (ReservedInstruction, instruction);
5325   {
5326     unsigned64 vaddr = ((unsigned64)op1 + offset);
5327     unsigned64 paddr;
5328     int uncached;
5329     if ((vaddr & 7) != 0)
5330       SignalExceptionAddressStore();
5331     else
5332       {
5333         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5334           {
5335             unsigned64 memval = 0;
5336             unsigned64 memval1 = 0;
5337             memval = op2;
5338             {
5339               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5340             }
5341           }
5342       }
5343   }
5344 }
5345
5346
5347 11111001,yyy,5.RD,s:RI64:16::SDSP
5348 *mips16:
5349 {
5350   unsigned32 instruction = instruction_0;
5351   signed_word op2 = (instruction >> 5) & 0x7;
5352   int offset = (instruction >> 0) & 0x1f;
5353   signed_word op1 = 29;
5354   if (op2 < 2)
5355     op2 += 16;
5356   op2 = GPR[op2];
5357   if (have_extendval)
5358     {
5359       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5360       if (offset >= 0x8000)
5361         offset -= 0x10000;
5362       have_extendval = 0;
5363     }
5364   else
5365     {
5366       offset <<= 3;
5367     }
5368   op1 = GPR[op1];
5369   if (have_extendval)
5370     SignalException (ReservedInstruction, instruction);
5371   {
5372     unsigned64 vaddr = ((unsigned64)op1 + offset);
5373     unsigned64 paddr;
5374     int uncached;
5375     if ((vaddr & 7) != 0)
5376       SignalExceptionAddressStore();
5377     else
5378       {
5379         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5380           {
5381             unsigned64 memval = 0;
5382             unsigned64 memval1 = 0;
5383             memval = op2;
5384             {
5385               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5386             }
5387           }
5388       }
5389   }
5390 }
5391
5392
5393 11111010,CCCCCCCC,s,Q:I64:16::SDRASP
5394 *mips16:
5395 {
5396   unsigned32 instruction = instruction_0;
5397   int offset = (instruction >> 0) & 0xff;
5398   signed_word op1 = 29;
5399   signed_word op2 = 31;
5400   if (have_extendval)
5401     {
5402       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5403       if (offset >= 0x8000)
5404         offset -= 0x10000;
5405       have_extendval = 0;
5406     }
5407   else
5408     {
5409       offset <<= 3;
5410     }
5411   op1 = GPR[op1];
5412   op2 = GPR[op2];
5413   if (have_extendval)
5414     SignalException (ReservedInstruction, instruction);
5415   {
5416     unsigned64 vaddr = ((unsigned64)op1 + offset);
5417     unsigned64 paddr;
5418     int uncached;
5419     if ((vaddr & 7) != 0)
5420       SignalExceptionAddressStore();
5421     else
5422       {
5423         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5424           {
5425             unsigned64 memval = 0;
5426             unsigned64 memval1 = 0;
5427             memval = op2;
5428             {
5429               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5430             }
5431           }
5432       }
5433   }
5434 }
5435
5436
5437 // ALU Immediate Instructions
5438
5439
5440 01101,ddd,UUUUUUUU,Z:RI:16::LI
5441 *mips16:
5442 {
5443   unsigned32 instruction = instruction_0;
5444   int destreg = (instruction >> 8) & 0x7;
5445   int op2 = (instruction >> 0) & 0xff;
5446   signed_word op1 = 0;
5447   if (destreg < 2)
5448     destreg += 16;
5449   if (have_extendval)
5450     {
5451       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5452       have_extendval = 0;
5453     }
5454   else
5455     {
5456     }
5457   if (have_extendval)
5458     SignalException (ReservedInstruction, instruction);
5459   {
5460     if (destreg != 0)
5461       GPR[destreg] = (op1 | op2);
5462   }
5463 }
5464
5465
5466 01000,xxx,ddd,04444:RRI_A:16::ADDIU
5467 *mips16:
5468 {
5469   unsigned32 instruction = instruction_0;
5470   signed_word op1 = (instruction >> 8) & 0x7;
5471   int destreg = (instruction >> 5) & 0x7;
5472   int op2 = (instruction >> 0) & 0xf;
5473   if (op1 < 2)
5474     op1 += 16;
5475   op1 = GPR[op1];
5476   if (destreg < 2)
5477     destreg += 16;
5478   if (have_extendval)
5479     {
5480       op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5481       if (op2 >= 0x4000)
5482         op2 -= 0x8000;
5483       have_extendval = 0;
5484     }
5485   else
5486     {
5487       if (op2 >= 0x8)
5488         op2 -= 0x10;
5489     }
5490   if (have_extendval)
5491     SignalException (ReservedInstruction, instruction);
5492   {
5493     unsigned int temp = (unsigned int)(op1 + op2);
5494     signed int tempS = (signed int)temp;
5495     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5496   }
5497 }
5498
5499
5500 01001,www,kkkkkkkk:RI:16::ADDIU8
5501 *mips16:
5502 {
5503   unsigned32 instruction = instruction_0;
5504   signed_word op1 = (instruction >> 8) & 0x7;
5505   int destreg;
5506   int op2 = (instruction >> 0) & 0xff;
5507   if (op1 < 2)
5508     op1 += 16;
5509   destreg = op1;
5510   op1 = GPR[op1];
5511   if (have_extendval)
5512     {
5513       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5514       if (op2 >= 0x8000)
5515         op2 -= 0x10000;
5516       have_extendval = 0;
5517     }
5518   else
5519     {
5520       if (op2 >= 0x80)
5521         op2 -= 0x100;
5522     }
5523   if (have_extendval)
5524     SignalException (ReservedInstruction, instruction);
5525   {
5526     unsigned int temp = (unsigned int)(op1 + op2);
5527     signed int tempS = (signed int)temp;
5528     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5529   }
5530 }
5531
5532
5533 01100011,KKKKKKKK,S:I8:16::ADJSP
5534 *mips16:
5535 {
5536   unsigned32 instruction = instruction_0;
5537   int op2 = (instruction >> 0) & 0xff;
5538   signed_word op1 = 29;
5539   int destreg;
5540   if (have_extendval)
5541     {
5542       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5543       if (op2 >= 0x8000)
5544         op2 -= 0x10000;
5545       have_extendval = 0;
5546     }
5547   else
5548     {
5549       if (op2 >= 0x80)
5550         op2 -= 0x100;
5551       op2 <<= 3;
5552     }
5553   destreg = op1;
5554   op1 = GPR[op1];
5555   if (have_extendval)
5556     SignalException (ReservedInstruction, instruction);
5557   {
5558     unsigned int temp = (unsigned int)(op1 + op2);
5559     signed int tempS = (signed int)temp;
5560     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5561   }
5562 }
5563
5564
5565 00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC
5566 *mips16:
5567 {
5568   unsigned32 instruction = instruction_0;
5569   int destreg = (instruction >> 8) & 0x7;
5570   int op2 = (instruction >> 0) & 0xff;
5571   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
5572   if (destreg < 2)
5573     destreg += 16;
5574   if (have_extendval)
5575     {
5576       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5577       if (op2 >= 0x8000)
5578         op2 -= 0x10000;
5579       have_extendval = 0;
5580     }
5581   else
5582     {
5583       op2 <<= 2;
5584     }
5585   if (have_extendval)
5586     SignalException (ReservedInstruction, instruction);
5587   {
5588     unsigned int temp = (unsigned int)(op1 + op2);
5589     signed int tempS = (signed int)temp;
5590     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5591   }
5592 }
5593
5594
5595 00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP
5596 *mips16:
5597 {
5598   unsigned32 instruction = instruction_0;
5599   int destreg = (instruction >> 8) & 0x7;
5600   int op2 = (instruction >> 0) & 0xff;
5601   signed_word op1 = 29;
5602   if (destreg < 2)
5603     destreg += 16;
5604   if (have_extendval)
5605     {
5606       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5607       if (op2 >= 0x8000)
5608         op2 -= 0x10000;
5609       have_extendval = 0;
5610     }
5611   else
5612     {
5613       op2 <<= 2;
5614     }
5615   op1 = GPR[op1];
5616   if (have_extendval)
5617     SignalException (ReservedInstruction, instruction);
5618   {
5619     unsigned int temp = (unsigned int)(op1 + op2);
5620     signed int tempS = (signed int)temp;
5621     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5622   }
5623 }
5624
5625
5626 01000,xxx,ddd,14444:RRI_A:16::DADDIU
5627 *mips16:
5628 {
5629   unsigned32 instruction = instruction_0;
5630   signed_word op1 = (instruction >> 8) & 0x7;
5631   int destreg = (instruction >> 5) & 0x7;
5632   int op2 = (instruction >> 0) & 0xf;
5633   if (op1 < 2)
5634     op1 += 16;
5635   op1 = GPR[op1];
5636   if (destreg < 2)
5637     destreg += 16;
5638   if (have_extendval)
5639     {
5640       op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5641       if (op2 >= 0x4000)
5642         op2 -= 0x8000;
5643       have_extendval = 0;
5644     }
5645   else
5646     {
5647       if (op2 >= 0x8)
5648         op2 -= 0x10;
5649     }
5650   if (have_extendval)
5651     SignalException (ReservedInstruction, instruction);
5652   {
5653     unsigned64 temp = (unsigned64)(op1 + op2);
5654     word64 tempS = (word64)temp;
5655     GPR[destreg] = (unsigned64)temp;
5656   }
5657 }
5658
5659
5660 11111101,www,jjjjj:RI64:16::DADDIU5
5661 *mips16:
5662 {
5663   unsigned32 instruction = instruction_0;
5664   signed_word op1 = (instruction >> 5) & 0x7;
5665   int destreg;
5666   int op2 = (instruction >> 0) & 0x1f;
5667   if (op1 < 2)
5668     op1 += 16;
5669   destreg = op1;
5670   op1 = GPR[op1];
5671   if (have_extendval)
5672     {
5673       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5674       if (op2 >= 0x8000)
5675         op2 -= 0x10000;
5676       have_extendval = 0;
5677     }
5678   else
5679     {
5680       if (op2 >= 0x10)
5681         op2 -= 0x20;
5682     }
5683   if (have_extendval)
5684     SignalException (ReservedInstruction, instruction);
5685   {
5686     unsigned64 temp = (unsigned64)(op1 + op2);
5687     word64 tempS = (word64)temp;
5688     GPR[destreg] = (unsigned64)temp;
5689   }
5690 }
5691
5692
5693 11111011,KKKKKKKK,S:I64:16::DADJSP
5694 *mips16:
5695 {
5696   unsigned32 instruction = instruction_0;
5697   int op2 = (instruction >> 0) & 0xff;
5698   signed_word op1 = 29;
5699   int destreg;
5700   if (have_extendval)
5701     {
5702       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5703       if (op2 >= 0x8000)
5704         op2 -= 0x10000;
5705       have_extendval = 0;
5706     }
5707   else
5708     {
5709       if (op2 >= 0x80)
5710         op2 -= 0x100;
5711       op2 <<= 3;
5712     }
5713   destreg = op1;
5714   op1 = GPR[op1];
5715   if (have_extendval)
5716     SignalException (ReservedInstruction, instruction);
5717   {
5718     unsigned64 temp = (unsigned64)(op1 + op2);
5719     word64 tempS = (word64)temp;
5720     GPR[destreg] = (unsigned64)temp;
5721   }
5722 }
5723
5724
5725 11111110,ddd,EEEEE,P:RI64:16::DADDIUPC
5726 *mips16:
5727 {
5728   unsigned32 instruction = instruction_0;
5729   int destreg = (instruction >> 5) & 0x7;
5730   int op2 = (instruction >> 0) & 0x1f;
5731   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
5732   if (destreg < 2)
5733     destreg += 16;
5734   if (have_extendval)
5735     {
5736       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5737       if (op2 >= 0x8000)
5738         op2 -= 0x10000;
5739       have_extendval = 0;
5740     }
5741   else
5742     {
5743       op2 <<= 2;
5744     }
5745   if (have_extendval)
5746     SignalException (ReservedInstruction, instruction);
5747   {
5748     unsigned64 temp = (unsigned64)(op1 + op2);
5749     word64 tempS = (word64)temp;
5750     GPR[destreg] = (unsigned64)temp;
5751   }
5752 }
5753
5754
5755 11111111,ddd,EEEEE,s:RI64:16::DADDIUSP
5756 *mips16:
5757 {
5758   unsigned32 instruction = instruction_0;
5759   int destreg = (instruction >> 5) & 0x7;
5760   int op2 = (instruction >> 0) & 0x1f;
5761   signed_word op1 = 29;
5762   if (destreg < 2)
5763     destreg += 16;
5764   if (have_extendval)
5765     {
5766       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5767       if (op2 >= 0x8000)
5768         op2 -= 0x10000;
5769       have_extendval = 0;
5770     }
5771   else
5772     {
5773       op2 <<= 2;
5774     }
5775   op1 = GPR[op1];
5776   if (have_extendval)
5777     SignalException (ReservedInstruction, instruction);
5778   {
5779     unsigned64 temp = (unsigned64)(op1 + op2);
5780     word64 tempS = (word64)temp;
5781     GPR[destreg] = (unsigned64)temp;
5782   }
5783 }
5784
5785
5786 01010,xxx,88888888,T:RI:16::SLTI
5787 *mips16:
5788 {
5789   unsigned32 instruction = instruction_0;
5790   signed_word op1 = (instruction >> 8) & 0x7;
5791   int op2 = (instruction >> 0) & 0xff;
5792   int destreg = 24;
5793   if (op1 < 2)
5794     op1 += 16;
5795   op1 = GPR[op1];
5796   if (have_extendval)
5797     {
5798       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5799       if (op2 >= 0x8000)
5800         op2 -= 0x10000;
5801       have_extendval = 0;
5802     }
5803   else
5804     {
5805     }
5806   if (have_extendval)
5807     SignalException (ReservedInstruction, instruction);
5808   {
5809     if ((word64)op1 < (word64)op2)
5810       GPR[destreg] = 1;
5811     else
5812       GPR[destreg] = 0;
5813   }
5814 }
5815
5816
5817 01011,xxx,88888888,T:RI:16::SLTIU
5818 *mips16:
5819 {
5820   unsigned32 instruction = instruction_0;
5821   signed_word op1 = (instruction >> 8) & 0x7;
5822   int op2 = (instruction >> 0) & 0xff;
5823   int destreg = 24;
5824   if (op1 < 2)
5825     op1 += 16;
5826   op1 = GPR[op1];
5827   if (have_extendval)
5828     {
5829       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5830       if (op2 >= 0x8000)
5831         op2 -= 0x10000;
5832       have_extendval = 0;
5833     }
5834   else
5835     {
5836     }
5837   if (have_extendval)
5838     SignalException (ReservedInstruction, instruction);
5839   {
5840     if ((unsigned64)op1 < (unsigned64)op2)
5841       GPR[destreg] = 1;
5842     else
5843       GPR[destreg] = 0;
5844   }
5845 }
5846
5847
5848 11101,xxx,yyy,01010,T:RR:16::CMP
5849 *mips16:
5850 {
5851   unsigned32 instruction = instruction_0;
5852   signed_word op1 = (instruction >> 8) & 0x7;
5853   signed_word op2 = (instruction >> 5) & 0x7;
5854   int destreg = 24;
5855   if (op1 < 2)
5856     op1 += 16;
5857   op1 = GPR[op1];
5858   if (op2 < 2)
5859     op2 += 16;
5860   op2 = GPR[op2];
5861   if (have_extendval)
5862     SignalException (ReservedInstruction, instruction);
5863   {
5864     GPR[destreg] = (op1 ^ op2);
5865   }
5866 }
5867
5868
5869 01110,xxx,UUUUUUUU,T:RI:16::CMPI
5870 *mips16:
5871 {
5872   unsigned32 instruction = instruction_0;
5873   signed_word op1 = (instruction >> 8) & 0x7;
5874   int op2 = (instruction >> 0) & 0xff;
5875   int destreg = 24;
5876   if (op1 < 2)
5877     op1 += 16;
5878   op1 = GPR[op1];
5879   if (have_extendval)
5880     {
5881       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5882       have_extendval = 0;
5883     }
5884   else
5885     {
5886     }
5887   if (have_extendval)
5888     SignalException (ReservedInstruction, instruction);
5889   {
5890     GPR[destreg] = (op1 ^ op2);
5891   }
5892 }
5893
5894
5895 // Two/Three Operand, Register-Type
5896
5897
5898 11100,xxx,yyy,ddd,01:RRR:16::ADDU
5899 *mips16:
5900 {
5901   unsigned32 instruction = instruction_0;
5902   signed_word op1 = (instruction >> 8) & 0x7;
5903   signed_word op2 = (instruction >> 5) & 0x7;
5904   int destreg = (instruction >> 2) & 0x7;
5905   if (op1 < 2)
5906     op1 += 16;
5907   op1 = GPR[op1];
5908   if (op2 < 2)
5909     op2 += 16;
5910   op2 = GPR[op2];
5911   if (destreg < 2)
5912     destreg += 16;
5913   if (have_extendval)
5914     SignalException (ReservedInstruction, instruction);
5915   {
5916     unsigned int temp = (unsigned int)(op1 + op2);
5917     signed int tempS = (signed int)temp;
5918     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5919   }
5920 }
5921
5922
5923 11100,xxx,yyy,ddd,11:RRR:16::SUBU
5924 *mips16:
5925 {
5926   unsigned32 instruction = instruction_0;
5927   signed_word op1 = (instruction >> 8) & 0x7;
5928   signed_word op2 = (instruction >> 5) & 0x7;
5929   int destreg = (instruction >> 2) & 0x7;
5930   if (op1 < 2)
5931     op1 += 16;
5932   op1 = GPR[op1];
5933   if (op2 < 2)
5934     op2 += 16;
5935   op2 = GPR[op2];
5936   if (destreg < 2)
5937     destreg += 16;
5938   if (have_extendval)
5939     SignalException (ReservedInstruction, instruction);
5940   {
5941     unsigned int temp = (unsigned int)(op1 - op2);
5942     signed int tempS = (signed int)temp;
5943     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5944   }
5945 }
5946
5947
5948 11100,xxx,yyy,ddd,00:RRR:16::DADDU
5949 *mips16:
5950 {
5951   unsigned32 instruction = instruction_0;
5952   signed_word op1 = (instruction >> 8) & 0x7;
5953   signed_word op2 = (instruction >> 5) & 0x7;
5954   int destreg = (instruction >> 2) & 0x7;
5955   if (op1 < 2)
5956     op1 += 16;
5957   op1 = GPR[op1];
5958   if (op2 < 2)
5959     op2 += 16;
5960   op2 = GPR[op2];
5961   if (destreg < 2)
5962     destreg += 16;
5963   if (have_extendval)
5964     SignalException (ReservedInstruction, instruction);
5965   {
5966     unsigned64 temp = (unsigned64)(op1 + op2);
5967     word64 tempS = (word64)temp;
5968     GPR[destreg] = (unsigned64)temp;
5969   }
5970 }
5971
5972
5973 11100,xxx,yyy,ddd,10:RRR:16::DSUBU
5974 *mips16:
5975 {
5976   unsigned32 instruction = instruction_0;
5977   signed_word op1 = (instruction >> 8) & 0x7;
5978   signed_word op2 = (instruction >> 5) & 0x7;
5979   int destreg = (instruction >> 2) & 0x7;
5980   if (op1 < 2)
5981     op1 += 16;
5982   op1 = GPR[op1];
5983   if (op2 < 2)
5984     op2 += 16;
5985   op2 = GPR[op2];
5986   if (destreg < 2)
5987     destreg += 16;
5988   if (have_extendval)
5989     SignalException (ReservedInstruction, instruction);
5990   {
5991     unsigned64 temp = (unsigned64)(op1 - op2);
5992     word64 tempS = (word64)temp;
5993     GPR[destreg] = (unsigned64)temp;
5994   }
5995 }
5996
5997
5998 11101,xxx,yyy,00010,T:RR:16::SLT
5999 *mips16:
6000 {
6001   unsigned32 instruction = instruction_0;
6002   signed_word op1 = (instruction >> 8) & 0x7;
6003   signed_word op2 = (instruction >> 5) & 0x7;
6004   int destreg = 24;
6005   if (op1 < 2)
6006     op1 += 16;
6007   op1 = GPR[op1];
6008   if (op2 < 2)
6009     op2 += 16;
6010   op2 = GPR[op2];
6011   if (have_extendval)
6012     SignalException (ReservedInstruction, instruction);
6013   {
6014     if ((word64)op1 < (word64)op2)
6015       GPR[destreg] = 1;
6016     else
6017       GPR[destreg] = 0;
6018   }
6019 }
6020
6021
6022 11101,xxx,yyy,00011,T:RR:16::SLTU
6023 *mips16:
6024 {
6025   unsigned32 instruction = instruction_0;
6026   signed_word op1 = (instruction >> 8) & 0x7;
6027   signed_word op2 = (instruction >> 5) & 0x7;
6028   int destreg = 24;
6029   if (op1 < 2)
6030     op1 += 16;
6031   op1 = GPR[op1];
6032   if (op2 < 2)
6033     op2 += 16;
6034   op2 = GPR[op2];
6035   if (have_extendval)
6036     SignalException (ReservedInstruction, instruction);
6037   {
6038     if ((unsigned64)op1 < (unsigned64)op2)
6039       GPR[destreg] = 1;
6040     else
6041       GPR[destreg] = 0;
6042   }
6043 }
6044
6045
6046 11101,ddd,yyy,01011,Z:RR:16::NEG
6047 *mips16:
6048 {
6049   unsigned32 instruction = instruction_0;
6050   int destreg = (instruction >> 8) & 0x7;
6051   signed_word op2 = (instruction >> 5) & 0x7;
6052   signed_word op1 = 0;
6053   if (destreg < 2)
6054     destreg += 16;
6055   if (op2 < 2)
6056     op2 += 16;
6057   op2 = GPR[op2];
6058   if (have_extendval)
6059     SignalException (ReservedInstruction, instruction);
6060   {
6061     unsigned int temp = (unsigned int)(op1 - op2);
6062     signed int tempS = (signed int)temp;
6063     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6064   }
6065 }
6066
6067
6068 11101,www,yyy,01100:RR:16::AND
6069 *mips16:
6070 {
6071   unsigned32 instruction = instruction_0;
6072   signed_word op1 = (instruction >> 8) & 0x7;
6073   int destreg;
6074   signed_word op2 = (instruction >> 5) & 0x7;
6075   if (op1 < 2)
6076     op1 += 16;
6077   destreg = op1;
6078   op1 = GPR[op1];
6079   if (op2 < 2)
6080     op2 += 16;
6081   op2 = GPR[op2];
6082   if (have_extendval)
6083     SignalException (ReservedInstruction, instruction);
6084   {
6085     GPR[destreg] = (op1 & op2);
6086   }
6087 }
6088
6089
6090 11101,www,yyy,01101:RR:16::OR
6091 *mips16:
6092 {
6093   unsigned32 instruction = instruction_0;
6094   signed_word op1 = (instruction >> 8) & 0x7;
6095   int destreg;
6096   signed_word op2 = (instruction >> 5) & 0x7;
6097   if (op1 < 2)
6098     op1 += 16;
6099   destreg = op1;
6100   op1 = GPR[op1];
6101   if (op2 < 2)
6102     op2 += 16;
6103   op2 = GPR[op2];
6104   if (have_extendval)
6105     SignalException (ReservedInstruction, instruction);
6106   {
6107     if (destreg != 0)
6108       GPR[destreg] = (op1 | op2);
6109   }
6110 }
6111
6112
6113 11101,www,yyy,01110:RR:16::XOR
6114 *mips16:
6115 {
6116   unsigned32 instruction = instruction_0;
6117   signed_word op1 = (instruction >> 8) & 0x7;
6118   int destreg;
6119   signed_word op2 = (instruction >> 5) & 0x7;
6120   if (op1 < 2)
6121     op1 += 16;
6122   destreg = op1;
6123   op1 = GPR[op1];
6124   if (op2 < 2)
6125     op2 += 16;
6126   op2 = GPR[op2];
6127   if (have_extendval)
6128     SignalException (ReservedInstruction, instruction);
6129   {
6130     GPR[destreg] = (op1 ^ op2);
6131   }
6132 }
6133
6134
6135 11101,ddd,yyy,01111,Z:RR:16::NOT
6136 *mips16:
6137 {
6138   unsigned32 instruction = instruction_0;
6139   int destreg = (instruction >> 8) & 0x7;
6140   signed_word op2 = (instruction >> 5) & 0x7;
6141   signed_word op1 = 0;
6142   if (destreg < 2)
6143     destreg += 16;
6144   if (op2 < 2)
6145     op2 += 16;
6146   op2 = GPR[op2];
6147   if (have_extendval)
6148     SignalException (ReservedInstruction, instruction);
6149   {
6150     if (destreg != 0)
6151       GPR[destreg] = ~(op1 | op2);
6152   }
6153 }
6154
6155
6156 01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32
6157 *mips16:
6158 {
6159   unsigned32 instruction = instruction_0;
6160   int destreg = (instruction >> 5) & 0x7;
6161   signed_word op1 = (instruction >> 0) & 0x1f;
6162   signed_word op2 = 0;
6163   if (destreg < 2)
6164     destreg += 16;
6165   op1 = GPR[op1];
6166   if (have_extendval)
6167     SignalException (ReservedInstruction, instruction);
6168   {
6169     if (destreg != 0)
6170       GPR[destreg] = (op1 | op2);
6171   }
6172 }
6173
6174
6175 01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R
6176 *mips16:
6177 {
6178   unsigned32 instruction = instruction_0;
6179   int destreg = (instruction >> 3) & 0x1f;
6180   signed_word op1 = (instruction >> 0) & 0x7;
6181   signed_word op2 = 0;
6182   destreg = (destreg >> 2) | ((destreg & 3) << 3);
6183   if (op1 < 2)
6184     op1 += 16;
6185   op1 = GPR[op1];
6186   if (have_extendval)
6187     SignalException (ReservedInstruction, instruction);
6188   {
6189     if (destreg != 0)
6190       GPR[destreg] = (op1 | op2);
6191   }
6192 }
6193
6194
6195 00110,ddd,yyy,sss,00:ISHIFT:16::SLL
6196 *mips16:
6197 {
6198   unsigned32 instruction = instruction_0;
6199   int destreg = (instruction >> 8) & 0x7;
6200   signed_word op2 = (instruction >> 5) & 0x7;
6201   int op1 = (instruction >> 2) & 0x7;
6202   if (destreg < 2)
6203     destreg += 16;
6204   if (op2 < 2)
6205     op2 += 16;
6206   op2 = GPR[op2];
6207   if (have_extendval)
6208     {
6209       op1 = (extendval >> 6) & 0x1f;
6210       have_extendval = 0;
6211     }
6212   else
6213     {
6214       if (op1 == 0)
6215         op1 = 8;
6216     }
6217   if (have_extendval)
6218     SignalException (ReservedInstruction, instruction);
6219   {
6220     GPR[destreg] = ((unsigned64)op2 << op1);
6221     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6222   }
6223 }
6224
6225
6226 00110,ddd,yyy,sss,10:ISHIFT:16::SRL
6227 *mips16:
6228 {
6229   unsigned32 instruction = instruction_0;
6230   int destreg = (instruction >> 8) & 0x7;
6231   signed_word op2 = (instruction >> 5) & 0x7;
6232   int op1 = (instruction >> 2) & 0x7;
6233   if (destreg < 2)
6234     destreg += 16;
6235   if (op2 < 2)
6236     op2 += 16;
6237   op2 = GPR[op2];
6238   if (have_extendval)
6239     {
6240       op1 = (extendval >> 6) & 0x1f;
6241       have_extendval = 0;
6242     }
6243   else
6244     {
6245       if (op1 == 0)
6246         op1 = 8;
6247     }
6248   if (have_extendval)
6249     SignalException (ReservedInstruction, instruction);
6250   {
6251     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6252     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6253   }
6254 }
6255
6256
6257 00110,ddd,yyy,sss,11:ISHIFT:16::SRA
6258 *mips16:
6259 {
6260   unsigned32 instruction = instruction_0;
6261   int destreg = (instruction >> 8) & 0x7;
6262   signed_word op2 = (instruction >> 5) & 0x7;
6263   int op1 = (instruction >> 2) & 0x7;
6264   if (destreg < 2)
6265     destreg += 16;
6266   if (op2 < 2)
6267     op2 += 16;
6268   op2 = GPR[op2];
6269   if (have_extendval)
6270     {
6271       op1 = (extendval >> 6) & 0x1f;
6272       have_extendval = 0;
6273     }
6274   else
6275     {
6276       if (op1 == 0)
6277         op1 = 8;
6278     }
6279   if (have_extendval)
6280     SignalException (ReservedInstruction, instruction);
6281   {
6282     unsigned int highbit = (unsigned int)1 << 31;
6283     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6284     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6285     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6286   }
6287 }
6288
6289
6290 11101,xxx,vvv,00100:RR:16::SLLV
6291 *mips16:
6292 {
6293   unsigned32 instruction = instruction_0;
6294   signed_word op1 = (instruction >> 8) & 0x7;
6295   signed_word op2 = (instruction >> 5) & 0x7;
6296   int destreg;
6297   if (op1 < 2)
6298     op1 += 16;
6299   op1 = GPR[op1];
6300   if (op2 < 2)
6301     op2 += 16;
6302   destreg = op2;
6303   op2 = GPR[op2];
6304   if (have_extendval)
6305     SignalException (ReservedInstruction, instruction);
6306   {
6307     op1 &= 0x1F;
6308     GPR[destreg] = ((unsigned64)op2 << op1);
6309     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6310   }
6311 }
6312
6313
6314 11101,xxx,vvv,00110:RR:16::SRLV
6315 *mips16:
6316 {
6317   unsigned32 instruction = instruction_0;
6318   signed_word op1 = (instruction >> 8) & 0x7;
6319   signed_word op2 = (instruction >> 5) & 0x7;
6320   int destreg;
6321   if (op1 < 2)
6322     op1 += 16;
6323   op1 = GPR[op1];
6324   if (op2 < 2)
6325     op2 += 16;
6326   destreg = op2;
6327   op2 = GPR[op2];
6328   if (have_extendval)
6329     SignalException (ReservedInstruction, instruction);
6330   {
6331     op1 &= 0x1F;
6332     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6333     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6334   }
6335 }
6336
6337
6338 11101,xxx,vvv,00111:RR:16::SRAV
6339 *mips16:
6340 {
6341   unsigned32 instruction = instruction_0;
6342   signed_word op1 = (instruction >> 8) & 0x7;
6343   signed_word op2 = (instruction >> 5) & 0x7;
6344   int destreg;
6345   if (op1 < 2)
6346     op1 += 16;
6347   op1 = GPR[op1];
6348   if (op2 < 2)
6349     op2 += 16;
6350   destreg = op2;
6351   op2 = GPR[op2];
6352   if (have_extendval)
6353     SignalException (ReservedInstruction, instruction);
6354   {
6355     unsigned int highbit = (unsigned int)1 << 31;
6356     op1 &= 0x1F;
6357     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6358     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6359     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6360   }
6361 }
6362
6363
6364 00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL
6365 *mips16:
6366 {
6367   unsigned32 instruction = instruction_0;
6368   int destreg = (instruction >> 8) & 0x7;
6369   signed_word op2 = (instruction >> 5) & 0x7;
6370   int op1 = (instruction >> 2) & 0x7;
6371   if (destreg < 2)
6372     destreg += 16;
6373   if (op2 < 2)
6374     op2 += 16;
6375   op2 = GPR[op2];
6376   if (have_extendval)
6377     {
6378       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6379       have_extendval = 0;
6380     }
6381   else
6382     {
6383       if (op1 == 0)
6384         op1 = 8;
6385     }
6386   if (have_extendval)
6387     SignalException (ReservedInstruction, instruction);
6388   {
6389     GPR[destreg] = ((unsigned64)op2 << op1);
6390   }
6391 }
6392
6393
6394 11101,XXX,vvv,01000:RR:16::DSRL
6395 *mips16:
6396 {
6397   unsigned32 instruction = instruction_0;
6398   int op1 = (instruction >> 8) & 0x7;
6399   signed_word op2 = (instruction >> 5) & 0x7;
6400   int destreg;
6401   if (have_extendval)
6402     {
6403       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6404       have_extendval = 0;
6405     }
6406   else
6407     {
6408       if (op1 == 0)
6409         op1 = 8;
6410     }
6411   if (op2 < 2)
6412     op2 += 16;
6413   destreg = op2;
6414   op2 = GPR[op2];
6415   if (have_extendval)
6416     SignalException (ReservedInstruction, instruction);
6417   {
6418     GPR[destreg] = ((unsigned64)(op2) >> op1);
6419   }
6420 }
6421
6422
6423 11101,xxx,vvv,10011:RR:16::DSRA
6424 *mips16:
6425 {
6426   unsigned32 instruction = instruction_0;
6427   int op1 = (instruction >> 8) & 0x7;
6428   signed_word op2 = (instruction >> 5) & 0x7;
6429   int destreg;
6430   if (have_extendval)
6431     {
6432       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6433       have_extendval = 0;
6434     }
6435   else
6436     {
6437       if (op1 == 0)
6438         op1 = 8;
6439     }
6440   if (op2 < 2)
6441     op2 += 16;
6442   destreg = op2;
6443   op2 = GPR[op2];
6444   if (have_extendval)
6445     SignalException (ReservedInstruction, instruction);
6446   {
6447     unsigned64 highbit = (unsigned64)1 << 63;
6448     GPR[destreg] = ((unsigned64)(op2) >> op1);
6449     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6450   }
6451 }
6452
6453
6454 11101,xxx,vvv,10100:RR:16::DSLLV
6455 *mips16:
6456 {
6457   unsigned32 instruction = instruction_0;
6458   signed_word op1 = (instruction >> 8) & 0x7;
6459   signed_word op2 = (instruction >> 5) & 0x7;
6460   int destreg;
6461   if (op1 < 2)
6462     op1 += 16;
6463   op1 = GPR[op1];
6464   if (op2 < 2)
6465     op2 += 16;
6466   destreg = op2;
6467   op2 = GPR[op2];
6468   if (have_extendval)
6469     SignalException (ReservedInstruction, instruction);
6470   {
6471     op1 &= 0x3F;
6472     GPR[destreg] = ((unsigned64)op2 << op1);
6473   }
6474 }
6475
6476
6477 11101,xxx,vvv,10110:RR:16::DSRLV
6478 *mips16:
6479 {
6480   unsigned32 instruction = instruction_0;
6481   signed_word op1 = (instruction >> 8) & 0x7;
6482   signed_word op2 = (instruction >> 5) & 0x7;
6483   int destreg;
6484   if (op1 < 2)
6485     op1 += 16;
6486   op1 = GPR[op1];
6487   if (op2 < 2)
6488     op2 += 16;
6489   destreg = op2;
6490   op2 = GPR[op2];
6491   if (have_extendval)
6492     SignalException (ReservedInstruction, instruction);
6493   {
6494     op1 &= 0x3F;
6495     GPR[destreg] = ((unsigned64)(op2) >> op1);
6496   }
6497 }
6498
6499
6500 11101,xxx,vvv,10111:RR:16::DSRAV
6501 *mips16:
6502 {
6503   unsigned32 instruction = instruction_0;
6504   signed_word op1 = (instruction >> 8) & 0x7;
6505   signed_word op2 = (instruction >> 5) & 0x7;
6506   int destreg;
6507   if (op1 < 2)
6508     op1 += 16;
6509   op1 = GPR[op1];
6510   if (op2 < 2)
6511     op2 += 16;
6512   destreg = op2;
6513   op2 = GPR[op2];
6514   if (have_extendval)
6515     SignalException (ReservedInstruction, instruction);
6516   {
6517     unsigned64 highbit = (unsigned64)1 << 63;
6518     op1 &= 0x3F;
6519     GPR[destreg] = ((unsigned64)(op2) >> op1);
6520     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6521   }
6522 }
6523
6524
6525 // Multiply /Divide Instructions
6526
6527
6528 11101,xxx,yyy,11000:RR:16::MULT
6529 *mips16:
6530 {
6531   unsigned32 instruction = instruction_0;
6532   signed_word op1 = (instruction >> 8) & 0x7;
6533   signed_word op2 = (instruction >> 5) & 0x7;
6534   if (op1 < 2)
6535     op1 += 16;
6536   op1 = GPR[op1];
6537   if (op2 < 2)
6538     op2 += 16;
6539   op2 = GPR[op2];
6540   if (have_extendval)
6541     SignalException (ReservedInstruction, instruction);
6542   {
6543     CHECKHILO("Multiplication");
6544     {
6545       unsigned64 temp = ((word64) op1 * (word64) op2);
6546       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
6547       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
6548     }
6549   }
6550 }
6551
6552
6553 11101,xxx,yyy,11001:RR:16::MULTU
6554 *mips16:
6555 {
6556   unsigned32 instruction = instruction_0;
6557   signed_word op1 = (instruction >> 8) & 0x7;
6558   signed_word op2 = (instruction >> 5) & 0x7;
6559   if (op1 < 2)
6560     op1 += 16;
6561   op1 = GPR[op1];
6562   if (op2 < 2)
6563     op2 += 16;
6564   op2 = GPR[op2];
6565   if (have_extendval)
6566     SignalException (ReservedInstruction, instruction);
6567   {
6568     CHECKHILO("Multiplication");
6569     {
6570       unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
6571       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
6572       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
6573     }
6574   }
6575 }
6576
6577
6578 11101,xxx,yyy,11010:RR:16::DIV
6579 *mips16:
6580 {
6581   unsigned32 instruction = instruction_0;
6582   signed_word op1 = (instruction >> 8) & 0x7;
6583   signed_word op2 = (instruction >> 5) & 0x7;
6584   if (op1 < 2)
6585     op1 += 16;
6586   op1 = GPR[op1];
6587   if (op2 < 2)
6588     op2 += 16;
6589   op2 = GPR[op2];
6590   if (have_extendval)
6591     SignalException (ReservedInstruction, instruction);
6592   {
6593     CHECKHILO("Division");
6594     {
6595       int d1 = op1;
6596       int d2 = op2;
6597       if (d2 == 0)
6598         {
6599           LO = SIGNEXTEND(0x80000000,32);
6600           HI = SIGNEXTEND(0,32);
6601         }
6602       else if (d2 == -1 && d1 == 0x80000000)
6603         {
6604           LO = SIGNEXTEND(0x80000000,32);
6605           HI = SIGNEXTEND(0,32);
6606         }
6607       else
6608         {
6609           LO = SIGNEXTEND((d1 / d2),32);
6610           HI = SIGNEXTEND((d1 % d2),32);
6611         }
6612     }
6613   }
6614 }
6615
6616
6617 11101,xxx,yyy,11011:RR:16::DIVU
6618 *mips16:
6619 {
6620   unsigned32 instruction = instruction_0;
6621   signed_word op1 = (instruction >> 8) & 0x7;
6622   signed_word op2 = (instruction >> 5) & 0x7;
6623   if (op1 < 2)
6624     op1 += 16;
6625   op1 = GPR[op1];
6626   if (op2 < 2)
6627     op2 += 16;
6628   op2 = GPR[op2];
6629   if (have_extendval)
6630     SignalException (ReservedInstruction, instruction);
6631   {
6632     CHECKHILO("Division");
6633     {
6634       unsigned int d1 = op1;
6635       unsigned int d2 = op2;
6636       if (d2 == 0)
6637         {
6638           LO = SIGNEXTEND(0x80000000,32);
6639           HI = SIGNEXTEND(0,32);
6640         }
6641       else if (d2 == -1 && d1 == 0x80000000)
6642         {
6643           LO = SIGNEXTEND(0x80000000,32);
6644           HI = SIGNEXTEND(0,32);
6645         }
6646       else
6647         {
6648           LO = SIGNEXTEND((d1 / d2),32);
6649           HI = SIGNEXTEND((d1 % d2),32);
6650         }
6651     }
6652   }
6653 }
6654
6655
6656 11101,ddd,00010000:RR:16::MFHI
6657 *mips16:
6658 {
6659   unsigned32 instruction = instruction_0;
6660   int destreg = (instruction >> 8) & 0x7;
6661   if (destreg < 2)
6662     destreg += 16;
6663   if (have_extendval)
6664     SignalException (ReservedInstruction, instruction);
6665   {
6666     GPR[destreg] = HI;
6667     HIACCESS = 3; /* 3rd instruction will be safe */
6668   }
6669 }
6670
6671
6672 11101,ddd,00010010:RR:16::MFLO
6673 *mips16:
6674 {
6675   unsigned32 instruction = instruction_0;
6676   int destreg = (instruction >> 8) & 0x7;
6677   if (destreg < 2)
6678     destreg += 16;
6679   if (have_extendval)
6680     SignalException (ReservedInstruction, instruction);
6681   {
6682     GPR[destreg] = LO;
6683     LOACCESS = 3; /* 3rd instruction will be safe */
6684   }
6685 }
6686
6687
6688 11101,xxx,yyy,11100:RR:16::DMULT
6689 *mips16:
6690 {
6691   unsigned32 instruction = instruction_0;
6692   signed_word op1 = (instruction >> 8) & 0x7;
6693   signed_word op2 = (instruction >> 5) & 0x7;
6694   if (op1 < 2)
6695     op1 += 16;
6696   op1 = GPR[op1];
6697   if (op2 < 2)
6698     op2 += 16;
6699   op2 = GPR[op2];
6700   if (have_extendval)
6701     SignalException (ReservedInstruction, instruction);
6702   {
6703     CHECKHILO("Multiplication");
6704     {
6705       unsigned64 mid;
6706       unsigned64 midhi;
6707       unsigned64 temp;
6708       int sign = 0;
6709       if (op1 < 0) { op1 = - op1; ++sign; }
6710       if (op2 < 0) { op2 = - op2; ++sign; }
6711       LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
6712       HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
6713       mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
6714       midhi = SET64HI(VL4_8(mid));
6715       temp = (LO + midhi);
6716       if ((temp == midhi) ? (LO != 0) : (temp < midhi))
6717         HI += 1;
6718       HI += VH4_8(mid);
6719       mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
6720       midhi = SET64HI(VL4_8(mid));
6721       LO = (temp + midhi);
6722       if ((LO == midhi) ? (temp != 0) : (LO < midhi))
6723         HI += 1;
6724       HI += VH4_8(mid);
6725       if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; }
6726     }
6727   }
6728 }
6729
6730
6731 11101,xxx,yyy,11101:RR:16::DMULTU
6732 *mips16:
6733 {
6734   unsigned32 instruction = instruction_0;
6735   signed_word op1 = (instruction >> 8) & 0x7;
6736   signed_word op2 = (instruction >> 5) & 0x7;
6737   if (op1 < 2)
6738     op1 += 16;
6739   op1 = GPR[op1];
6740   if (op2 < 2)
6741     op2 += 16;
6742   op2 = GPR[op2];
6743   if (have_extendval)
6744     SignalException (ReservedInstruction, instruction);
6745   {
6746     CHECKHILO("Multiplication");
6747     {
6748       unsigned64 mid;
6749       unsigned64 midhi;
6750       unsigned64 temp;
6751       LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
6752       HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
6753       mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
6754       midhi = SET64HI(VL4_8(mid));
6755       temp = (LO + midhi);
6756       if ((temp == midhi) ? (LO != 0) : (temp < midhi))
6757         HI += 1;
6758       HI += VH4_8(mid);
6759       mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
6760       midhi = SET64HI(VL4_8(mid));
6761       LO = (temp + midhi);
6762       if ((LO == midhi) ? (temp != 0) : (LO < midhi))
6763         HI += 1;
6764       HI += VH4_8(mid);
6765     }
6766   }
6767 }
6768
6769
6770 11101,xxx,yyy,11110:RR:16::DDIV
6771 *mips16:
6772 {
6773   unsigned32 instruction = instruction_0;
6774   signed_word op1 = (instruction >> 8) & 0x7;
6775   signed_word op2 = (instruction >> 5) & 0x7;
6776   if (op1 < 2)
6777     op1 += 16;
6778   op1 = GPR[op1];
6779   if (op2 < 2)
6780     op2 += 16;
6781   op2 = GPR[op2];
6782   if (have_extendval)
6783     SignalException (ReservedInstruction, instruction);
6784   {
6785     CHECKHILO("Division");
6786     {
6787       word64 d1 = op1;
6788       word64 d2 = op2;
6789       if (d2 == 0)
6790         {
6791           LO = SIGNED64 (0x8000000000000000);
6792           HI = 0;
6793         }
6794       else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
6795         {
6796           LO = SIGNED64 (0x8000000000000000);
6797           HI = 0;
6798         }
6799       else
6800         {
6801           LO = (d1 / d2);
6802           HI = (d1 % d2);
6803         }
6804     }
6805   }
6806 }
6807
6808
6809 11101,xxx,yyy,11111:RR:16::DDIVU
6810 *mips16:
6811 {
6812   unsigned32 instruction = instruction_0;
6813   signed_word op1 = (instruction >> 8) & 0x7;
6814   signed_word op2 = (instruction >> 5) & 0x7;
6815   if (op1 < 2)
6816     op1 += 16;
6817   op1 = GPR[op1];
6818   if (op2 < 2)
6819     op2 += 16;
6820   op2 = GPR[op2];
6821   if (have_extendval)
6822     SignalException (ReservedInstruction, instruction);
6823   {
6824     CHECKHILO("Division");
6825     {
6826       unsigned64 d1 = op1;
6827       unsigned64 d2 = op2;
6828       if (d2 == 0)
6829         {
6830           LO = SIGNED64 (0x8000000000000000);
6831           HI = 0;
6832         }
6833       else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
6834         {
6835           LO = SIGNED64 (0x8000000000000000);
6836           HI = 0;
6837         }
6838       else
6839         {
6840           LO = (d1 / d2);
6841           HI = (d1 % d2);
6842         }
6843     }
6844   }
6845 }
6846
6847
6848 // Jump and Branch Instructions
6849
6850
6851 // JALX
6852 // JAL
6853 00011,aaaaaaaaaaa:I:16::JAL
6854 *mips16:
6855 {
6856   unsigned32 instruction = instruction_0;
6857   unsigned_word op1 = (instruction >> 0) & 0x7ff;
6858   {
6859     unsigned64 paddr;
6860     int uncached;
6861     if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))
6862       {
6863         unsigned64 memval;
6864         unsigned int reverse = (ReverseEndian ? 3 : 0);
6865         unsigned int bigend = (BigEndianCPU ? 3 : 0);
6866         unsigned int byte;
6867         paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1)));
6868         LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL);
6869         byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1));
6870         memval = (memval >> (8 * byte)) & 0xffff;
6871         op1 = (((op1 & 0x1f) << 23)
6872                | ((op1 & 0x3e0) << 13)
6873                | (memval << 2));
6874         if ((instruction & 0x400) == 0)
6875           op1 |= 1;
6876         PC += 2;
6877       }
6878   }
6879   op1 |= PC & ~ (unsigned64) 0x0fffffff;
6880   if (have_extendval)
6881     SignalException (ReservedInstruction, instruction);
6882   {
6883     int destreg = 31;
6884     GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
6885     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6886        so we just truncate it to 32 bits here.  */
6887     op1 = VL4_8(op1);
6888     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6889     DSPC = op1;
6890     JALDELAYSLOT();
6891   }
6892 }
6893
6894
6895 11101,xxx,00000000:RR:16::JR
6896 *mips16:
6897 {
6898   unsigned32 instruction = instruction_0;
6899   signed_word op1 = (instruction >> 8) & 0x7;
6900   if (op1 < 2)
6901     op1 += 16;
6902   op1 = GPR[op1];
6903   if (have_extendval)
6904     SignalException (ReservedInstruction, instruction);
6905   {
6906     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6907        so we just truncate it to 32 bits here.  */
6908     op1 = VL4_8(op1);
6909     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6910     DSPC = op1;
6911     DELAYSLOT();
6912   }
6913 }
6914
6915
6916 1110100000100000,r:RR:16::JRRA
6917 *mips16:
6918 {
6919   unsigned32 instruction = instruction_0;
6920   signed_word op1 = 31;
6921   op1 = GPR[op1];
6922   if (have_extendval)
6923     SignalException (ReservedInstruction, instruction);
6924   {
6925     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6926        so we just truncate it to 32 bits here.  */
6927     op1 = VL4_8(op1);
6928     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6929     DSPC = op1;
6930     DELAYSLOT();
6931   }
6932 }
6933
6934
6935 11101,xxx,01000000,R:RR:16::JALR
6936 *mips16:
6937 {
6938   unsigned32 instruction = instruction_0;
6939   signed_word op1 = (instruction >> 8) & 0x7;
6940   int destreg = 31;
6941   if (op1 < 2)
6942     op1 += 16;
6943   op1 = GPR[op1];
6944   if (have_extendval)
6945     SignalException (ReservedInstruction, instruction);
6946   {
6947     GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
6948     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6949        so we just truncate it to 32 bits here.  */
6950     op1 = VL4_8(op1);
6951     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6952     DSPC = op1;
6953     DELAYSLOT();
6954   }
6955 }
6956
6957
6958 00100,xxx,pppppppp,z:RI:16::BEQZ
6959 *mips16:
6960 {
6961   unsigned32 instruction = instruction_0;
6962   signed_word op1 = (instruction >> 8) & 0x7;
6963   int offset = (instruction >> 0) & 0xff;
6964   signed_word op2 = 0;
6965   if (op1 < 2)
6966     op1 += 16;
6967   op1 = GPR[op1];
6968   if (have_extendval)
6969     {
6970       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6971       if (offset >= 0x8000)
6972         offset -= 0x10000;
6973       have_extendval = 0;
6974     }
6975   else
6976     {
6977       if (offset >= 0x80)
6978         offset -= 0x100;
6979     }
6980   offset *= 2;
6981   if (have_extendval)
6982     SignalException (ReservedInstruction, instruction);
6983   {
6984     int condition = (op1 == op2);
6985     if (condition)
6986       PC = PC + offset;
6987   }
6988 }
6989
6990
6991 00101,xxx,pppppppp,z:RI:16::BNEZ
6992 *mips16:
6993 {
6994   unsigned32 instruction = instruction_0;
6995   signed_word op1 = (instruction >> 8) & 0x7;
6996   int offset = (instruction >> 0) & 0xff;
6997   signed_word op2 = 0;
6998   if (op1 < 2)
6999     op1 += 16;
7000   op1 = GPR[op1];
7001   if (have_extendval)
7002     {
7003       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7004       if (offset >= 0x8000)
7005         offset -= 0x10000;
7006       have_extendval = 0;
7007     }
7008   else
7009     {
7010       if (offset >= 0x80)
7011         offset -= 0x100;
7012     }
7013   offset *= 2;
7014   if (have_extendval)
7015     SignalException (ReservedInstruction, instruction);
7016   {
7017     int condition = (op1 != op2);
7018     if (condition)
7019       PC = PC + offset;
7020   }
7021 }
7022
7023
7024 01100000,pppppppp,t,z:I8:16::BTEQZ
7025 *mips16:
7026 {
7027   unsigned32 instruction = instruction_0;
7028   int offset = (instruction >> 0) & 0xff;
7029   signed_word op1 = 24;
7030   signed_word op2 = 0;
7031   if (have_extendval)
7032     {
7033       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7034       if (offset >= 0x8000)
7035         offset -= 0x10000;
7036       have_extendval = 0;
7037     }
7038   else
7039     {
7040       if (offset >= 0x80)
7041         offset -= 0x100;
7042     }
7043   offset *= 2;
7044   op1 = GPR[op1];
7045   if (have_extendval)
7046     SignalException (ReservedInstruction, instruction);
7047   {
7048     int condition = (op1 == op2);
7049     if (condition)
7050       PC = PC + offset;
7051   }
7052 }
7053
7054
7055 01100001,pppppppp,t,z:I8:16::BTNEZ
7056 *mips16:
7057 {
7058   unsigned32 instruction = instruction_0;
7059   int offset = (instruction >> 0) & 0xff;
7060   signed_word op1 = 24;
7061   signed_word op2 = 0;
7062   if (have_extendval)
7063     {
7064       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7065       if (offset >= 0x8000)
7066         offset -= 0x10000;
7067       have_extendval = 0;
7068     }
7069   else
7070     {
7071       if (offset >= 0x80)
7072         offset -= 0x100;
7073     }
7074   offset *= 2;
7075   op1 = GPR[op1];
7076   if (have_extendval)
7077     SignalException (ReservedInstruction, instruction);
7078   {
7079     int condition = (op1 != op2);
7080     if (condition)
7081       PC = PC + offset;
7082   }
7083 }
7084
7085
7086 00010,qqqqqqqqqqq,z,Z:I:16::B
7087 *mips16:
7088 {
7089   unsigned32 instruction = instruction_0;
7090   int offset = (instruction >> 0) & 0x7ff;
7091   signed_word op2 = 0;
7092   signed_word op1 = 0;
7093   if (have_extendval)
7094     {
7095       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7096       if (offset >= 0x8000)
7097         offset -= 0x10000;
7098       have_extendval = 0;
7099     }
7100   else
7101     {
7102       if (offset >= 0x400)
7103         offset -= 0x800;
7104     }
7105   offset *= 2;
7106   if (have_extendval)
7107     SignalException (ReservedInstruction, instruction);
7108   {
7109     int condition = (op1 == op2);
7110     if (condition)
7111       PC = PC + offset;
7112   }
7113 }
7114
7115
7116 // Special Instructions
7117
7118
7119 // See the front of the mips16 doc
7120 11110,eeeeeeeeeee:I:16::EXTEND
7121 *mips16:
7122 {
7123   unsigned32 instruction = instruction_0;
7124   int ext = (instruction >> 0) & 0x7ff;
7125   if (have_extendval)
7126     SignalException (ReservedInstruction, instruction);
7127   {
7128     extendval = ext;
7129     have_extendval = 1;
7130   }
7131 }
7132
7133
7134 01100,******,00101:RR:16::BREAK
7135 *mips16:
7136 {
7137   unsigned32 instruction = instruction_0;
7138   if (have_extendval)
7139     SignalException (ReservedInstruction, instruction);
7140   {
7141     SignalException(BreakPoint,instruction);
7142   }
7143 }
7144
7145 \f
7146 // start-sanitize-r5900
7147
7148 // FIXME: The instructions below which are typically r5900 specific
7149 //        need to be merged back into the above.
7150
7151 // end-sanitize-r5900
7152 // start-sanitize-r5900
7153
7154 011100,5.RS,5.RT,0000000000011010:MMINORM:32::DIV1
7155 *r5900:
7156 {
7157   unsigned32 instruction = instruction_0;
7158   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7159   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7160   {
7161     CHECKHILO("Division");
7162     {
7163       int d1 = op1;
7164       int d2 = op2;
7165       if (d2 == 0)
7166         {
7167           LO1 = SIGNEXTEND(0x80000000,32);
7168           HI1 = SIGNEXTEND(0,32);
7169         }
7170       else if (d2 == -1 && d1 == 0x80000000)
7171         {
7172           LO1 = SIGNEXTEND(0x80000000,32);
7173           HI1 = SIGNEXTEND(0,32);
7174         }
7175       else
7176         {
7177           LO1 = SIGNEXTEND((d1 / d2),32);
7178           HI1 = SIGNEXTEND((d1 % d2),32);
7179         }
7180     }
7181   }
7182 }
7183
7184 // end-sanitize-r5900
7185 // start-sanitize-r5900
7186
7187 011100,5.RS,5.RT,0000000000011011:MMINORM:32::DIVU1
7188 *r5900:
7189 {
7190   unsigned32 instruction = instruction_0;
7191   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7192   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7193   {
7194     CHECKHILO("Division");
7195     {
7196       unsigned int d1 = op1;
7197       unsigned int d2 = op2;
7198       if (d2 == 0)
7199         {
7200           LO1 = SIGNEXTEND(0x80000000,32);
7201           HI1 = SIGNEXTEND(0,32);
7202         }
7203       else if (d2 == -1 && d1 == 0x80000000)
7204         {
7205           LO1 = SIGNEXTEND(0x80000000,32);
7206           HI1 = SIGNEXTEND(0,32);
7207         }
7208       else
7209         {
7210           LO1 = SIGNEXTEND((d1 / d2),32);
7211           HI1 = SIGNEXTEND((d1 % d2),32);
7212         }
7213     }
7214   }
7215 }
7216
7217 // end-sanitize-r5900
7218
7219 011101,26.INSTR_INDEX:NORMAL:32::JALX
7220 // start-sanitize-r5900
7221 *r5900:
7222 // end-sanitize-r5900
7223 *r3900:
7224 // start-sanitize-tx19
7225 *tx19:
7226 // end-sanitize-tx19
7227 {
7228   unsigned32 instruction = instruction_0;
7229   unsigned_word op1 = (((instruction >> 0) & 0x03FFFFFF) << 2);
7230   op1 |= (PC & ~0x0FFFFFFF); /* address of instruction in delay slot for the jump */
7231   {
7232     int destreg = 31;
7233     GPR[destreg] = (PC + 4); /* NOTE: The PC is already 4 ahead within the simulator */
7234     op1 ^= 1;
7235     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7236        so we just truncate it to 32 bits here.  */
7237     op1 = VL4_8(op1);
7238     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7239     DSPC = op1;
7240     JALDELAYSLOT();
7241   }
7242 }
7243
7244 // start-sanitize-r5900
7245
7246 011110,5.RS,5.RT,16.OFFSET:NORMAL:128::LQ
7247 *r5900:
7248 {
7249   unsigned32 instruction = instruction_0;
7250   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
7251   int destreg = ((instruction >> 16) & 0x0000001F);
7252   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7253   {
7254     unsigned64 vaddr = ((unsigned64)op1 + offset);
7255     unsigned64 paddr;
7256     int uncached;
7257     if ((vaddr & 15) != 0)
7258       SignalExceptionAddressLoad();
7259     else
7260       {
7261         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
7262           {
7263             unsigned64 memval = 0;
7264             unsigned64 memval1 = 0;
7265             unsigned64 mask = 0x7;
7266             unsigned int shift = 8;
7267             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
7268             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
7269             unsigned int byte;
7270             LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
7271             GPR[destreg] = memval;
7272             GPR1[destreg] = memval1;
7273           }
7274       }
7275   }
7276 }
7277
7278 // end-sanitize-r5900
7279 // start-sanitize-r5900
7280
7281 011100,5.RS,5.RT,5.RD,00000000000:MMINORM:32::MADD
7282 *r5900:
7283 *r3900:
7284 {
7285   unsigned32 instruction = instruction_0;
7286   int destreg = ((instruction >> 11) & 0x0000001F);
7287   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7288   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7289   {
7290     word64 prod = (word64)WORD64(VL4_8(HI),VL4_8(LO)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7291     LO = SIGNEXTEND(prod,32);
7292     HI = SIGNEXTEND( VH4_8(prod), 32);
7293     if( destreg != 0 ) GPR[destreg] = LO;
7294   }
7295 }
7296
7297 // end-sanitize-r5900
7298 // start-sanitize-r5900
7299
7300 011100,5.RS,5.RT,5.RD,00000000001:MMINORM:32::MADDU
7301 *r5900:
7302 *r3900:
7303 {
7304   unsigned32 instruction = instruction_0;
7305   int destreg = ((instruction >> 11) & 0x0000001F);
7306   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7307   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7308   {
7309     unsigned64 prod = (unsigned64)WORD64(VL4_8(HI),VL4_8(LO)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7310     LO = SIGNEXTEND(prod,32);
7311     HI = SIGNEXTEND( VH4_8(prod), 32);
7312     if( destreg != 0 ) GPR[destreg] = LO;
7313   }
7314 }
7315
7316 // end-sanitize-r5900
7317 // start-sanitize-r5900
7318
7319 011100,5.RS,5.RT,5.RD,00000100000:MMINORM:32::MADD1
7320 *r5900:
7321 {
7322   unsigned32 instruction = instruction_0;
7323   int destreg = ((instruction >> 11) & 0x0000001F);
7324   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7325   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7326   {
7327     word64 prod = (word64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7328     LO1 = SIGNEXTEND(prod,32);
7329     HI1 = SIGNEXTEND( VH4_8(prod), 32);
7330     if( destreg != 0 ) GPR[destreg] = LO1;
7331   }
7332 }
7333
7334 // end-sanitize-r5900
7335 // start-sanitize-r5900
7336
7337 011100,5.RS,5.RT,5.RD,00000100001:MMINORM:32::MADDU1
7338 *r5900:
7339 {
7340   unsigned32 instruction = instruction_0;
7341   int destreg = ((instruction >> 11) & 0x0000001F);
7342   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7343   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7344   {
7345     unsigned64 prod = (unsigned64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7346     LO1 = SIGNEXTEND(prod,32);
7347     HI1 = SIGNEXTEND( VH4_8(prod), 32);
7348     if( destreg != 0 ) GPR[destreg] = LO1;
7349   }
7350 }
7351
7352 // end-sanitize-r5900
7353 // start-sanitize-r5900
7354
7355 0111000000000000,5.RD,00000010000:MMINORM:32::MFHI1
7356 *r5900:
7357 {
7358   unsigned32 instruction = instruction_0;
7359   int destreg = ((instruction >> 11) & 0x0000001F);
7360   {
7361     GPR[destreg] = HI1;
7362     HI1ACCESS = 3; /* 3rd instruction will be safe */
7363   }
7364 }
7365
7366 // end-sanitize-r5900
7367 // start-sanitize-r5900
7368
7369 0111000000000000,5.RD,00000010010:MMINORM:32::MFLO1
7370 *r5900:
7371 {
7372   unsigned32 instruction = instruction_0;
7373   int destreg = ((instruction >> 11) & 0x0000001F);
7374   {
7375     GPR[destreg] = LO1;
7376     LO1ACCESS = 3; /* 3rd instruction will be safe */
7377   }
7378 }
7379
7380 // end-sanitize-r5900
7381 // start-sanitize-r5900
7382
7383 0000000000000000,5.RD,00000101000:SPECIAL:32::MFSA
7384 *r5900:
7385 {
7386   unsigned32 instruction = instruction_0;
7387   int destreg = ((instruction >> 11) & 0x0000001F);
7388   {
7389     GPR[destreg] = SA;
7390   }
7391 }
7392
7393 // end-sanitize-r5900
7394 // start-sanitize-r5900
7395
7396 011100,5.RS,000000000000000010001:MMINORM:32::MTHI1
7397 *r5900:
7398 {
7399   unsigned32 instruction = instruction_0;
7400   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7401   {
7402     if (HI1ACCESS != 0)
7403       sim_warning("MT (move-to) over-writing HI register value");
7404     HI1 = op1;
7405     HI1ACCESS = 3; /* 3rd instruction will be safe */
7406   }
7407 }
7408
7409 // end-sanitize-r5900
7410 // start-sanitize-r5900
7411
7412 011100,5.RS,000000000000000010011:MMINORM:32::MTLO1
7413 *r5900:
7414 {
7415   unsigned32 instruction = instruction_0;
7416   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7417   {
7418     if (LO1ACCESS != 0)
7419       sim_warning("MT (move-to) over-writing LO register value");
7420     LO1 = op1;
7421     LO1ACCESS = 3; /* 3rd instruction will be safe */
7422   }
7423 }
7424
7425 // end-sanitize-r5900
7426 // start-sanitize-r5900
7427
7428 000000,5.RS,000000000000000101001:SPECIAL:32::MTSA
7429 *r5900:
7430 {
7431   unsigned32 instruction = instruction_0;
7432   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7433   {
7434     SA = op1;
7435   }
7436 }
7437
7438 // end-sanitize-r5900
7439 // start-sanitize-r5900
7440
7441 000001,5.RS,11000,16.IMMEDIATE:REGIMM:32::MTSAB
7442 *r5900:
7443 {
7444   SA = ((GPR[RA] & 0xF) ^ (IMMEDIATE & 0xF)) * 8;
7445 }
7446
7447 // end-sanitize-r5900
7448 // start-sanitize-r5900
7449
7450 000001,5.RS,11001,16.IMMEDIATE:REGIMM:32::MTSAH
7451 *r5900:
7452 {
7453   SA = ((GPR[RS] & 0x7) ^ (IMMEDIATE & 0x7)) * 16;
7454 }
7455
7456 // end-sanitize-r5900
7457 // start-sanitize-r5900
7458
7459 011100,5.RS,5.RT,5.RD,00000011000:MMINORM:32::MULT1
7460 *r5900:
7461 {
7462   unsigned32 instruction = instruction_0;
7463   int destreg = ((instruction >> 11) & 0x0000001F);
7464   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7465   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7466   {
7467     CHECKHILO("Multiplication");
7468     {
7469       unsigned64 temp = ((word64) op1 * (word64) op2);
7470       LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7471       HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7472       if ( destreg != 0 )
7473         GPR[destreg] = LO1;
7474     }
7475   }
7476 }
7477
7478 // end-sanitize-r5900
7479 // start-sanitize-r5900
7480
7481 011100,5.RS,5.RT,5.RD,00000011001:MMINORM:32::MULTU1
7482 *r5900:
7483 {
7484   unsigned32 instruction = instruction_0;
7485   int destreg = ((instruction >> 11) & 0x0000001F);
7486   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7487   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7488   {
7489     CHECKHILO("Multiplication");
7490     {
7491       unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
7492       LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7493       HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7494       if ( destreg != 0 )
7495         GPR[destreg] = LO1;
7496     }
7497   }
7498 }
7499
7500 // end-sanitize-r5900
7501 // start-sanitize-r5900
7502
7503 01110000000,5.RT,5.RD,00101101000:MMI1:32::PABSH
7504 *r5900:
7505 {
7506   unsigned32 instruction = instruction_0;
7507   int destreg = ((instruction >> 11) & 0x0000001F);
7508   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7509   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7510   {
7511     int i;
7512     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7513       {
7514         if (RT_SH(i) >= 0)
7515           GPR_SH(destreg,i) =  RT_SH(i);
7516         else if (RT_SH(i) == -32768)
7517           GPR_SH(destreg,i) = 32767;
7518         else
7519           GPR_SH(destreg,i) = -RT_SH(i);
7520       }
7521   }
7522 }
7523
7524 // end-sanitize-r5900
7525 // start-sanitize-r5900
7526
7527 01110000000,5.RT,5.RD,00001101000:MMI1:32::PABSW
7528 *r5900:
7529 {
7530   unsigned32 instruction = instruction_0;
7531   int destreg = ((instruction >> 11) & 0x0000001F);
7532   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7533   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7534   {
7535     int i;
7536     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7537       {
7538         if (RT_SW(i) >= 0)
7539           GPR_SW(destreg,i) =  RT_SW(i);
7540         else if (RT_SW(i) == (int)0x80000000)
7541           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
7542         else
7543           GPR_SW(destreg,i) = -RT_SW(i);
7544       }
7545   }
7546 }
7547
7548 // end-sanitize-r5900
7549 // start-sanitize-r5900
7550
7551 011100,5.RS,5.RT,5.RD,01000001000:MMI0:32::PADDB
7552 *r5900:
7553 {
7554   unsigned32 instruction = instruction_0;
7555   int destreg = ((instruction >> 11) & 0x0000001F);
7556   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7557   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7558   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7559   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7560   {
7561     int i;
7562     for (i=0; i < BYTES_IN_MMI_REGS; i++)
7563       {
7564         int s = RS_SB(i);
7565         int t = RT_SB(i);
7566         int r = s + t;
7567         GPR_SB(destreg,i) = r;
7568       }
7569   }
7570 }
7571
7572 // end-sanitize-r5900
7573 // start-sanitize-r5900
7574
7575 011100,5.RS,5.RT,5.RD,00100001000:MMI0:32::PADDH
7576 *r5900:
7577 {
7578   unsigned32 instruction = instruction_0;
7579   int destreg = ((instruction >> 11) & 0x0000001F);
7580   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7581   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7582   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7583   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7584   {
7585     int i;
7586     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7587       {
7588         int s = RS_SH(i);
7589         int t = RT_SH(i);
7590         int r = s + t;
7591         GPR_SH(destreg,i) = r;
7592       }
7593   }
7594 }
7595
7596 // end-sanitize-r5900
7597 // start-sanitize-r5900
7598
7599 011100,5.RS,5.RT,5.RD,00000001000:MMI0:32::PADDW
7600 *r5900:
7601 {
7602   unsigned32 instruction = instruction_0;
7603   int destreg = ((instruction >> 11) & 0x0000001F);
7604   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7605   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7606   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7607   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7608   {
7609     int i;
7610     for (i=0; i < WORDS_IN_MMI_REGS; i++)
7611       {
7612         signed64 s = RS_SW(i);
7613         signed64 t = RT_SW(i);
7614         signed64 r = s + t;
7615         GPR_SW(destreg,i) = r;
7616       }
7617   }
7618 }
7619
7620 // end-sanitize-r5900
7621 // start-sanitize-r5900
7622
7623 011100,5.RS,5.RT,5.RD,11000001000:MMI0:32::PADDSB
7624 *r5900:
7625 {
7626   unsigned32 instruction = instruction_0;
7627   int destreg = ((instruction >> 11) & 0x0000001F);
7628   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7629   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7630   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7631   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7632   {
7633     int i;
7634     for (i=0; i < BYTES_IN_MMI_REGS; i++)
7635       {
7636         int s = RS_SB(i);
7637         int t = RT_SB(i);
7638         int r = s + t;
7639         if (r > 127)
7640           GPR_SB(destreg,i) = 127;
7641         else if (r < -128)
7642           GPR_SB(destreg,i) = -128;
7643         else
7644           GPR_SB(destreg,i) = r;
7645       }
7646   }
7647 }
7648
7649 // end-sanitize-r5900
7650 // start-sanitize-r5900
7651
7652 011100,5.RS,5.RT,5.RD,10100001000:MMI0:32::PADDSH
7653 *r5900:
7654 {
7655   unsigned32 instruction = instruction_0;
7656   int destreg = ((instruction >> 11) & 0x0000001F);
7657   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7658   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7659   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7660   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7661   {
7662     int i;
7663     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7664       {
7665         int s = RS_SH(i);
7666         int t = RT_SH(i);
7667         int r = s + t;
7668         if (r > 32767)
7669           GPR_SH(destreg,i) = 32767;
7670         else if (r < -32768)
7671           GPR_SH(destreg,i) = -32768;
7672         else
7673           GPR_SH(destreg,i) = r;
7674       }
7675   }
7676 }
7677
7678 // end-sanitize-r5900
7679 // start-sanitize-r5900
7680
7681 011100,5.RS,5.RT,5.RD,10000001000:MMI0:32::PADDSW
7682 *r5900:
7683 {
7684   unsigned32 instruction = instruction_0;
7685   int destreg = ((instruction >> 11) & 0x0000001F);
7686   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7687   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7688   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7689   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7690   {
7691     int i;
7692     for (i=0; i < WORDS_IN_MMI_REGS; i++)
7693       {
7694         signed64 s = RS_SW(i);
7695         signed64 t = RT_SW(i);
7696         signed64 r = s + t;
7697         if (r > (int)0x7FFFFFFF)
7698           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
7699         else if (r < (int)0x80000000)
7700           GPR_SW(destreg,i) = (int)0x80000000;
7701         else
7702           GPR_SW(destreg,i) = r;
7703       }
7704   }
7705 }
7706
7707 // end-sanitize-r5900
7708 // start-sanitize-r5900
7709
7710 011100,5.RS,5.RT,5.RD,11000101000:MMI1:32::PADDUB
7711 *r5900:
7712 {
7713   unsigned32 instruction = instruction_0;
7714   int destreg = ((instruction >> 11) & 0x0000001F);
7715   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7716   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7717   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7718   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7719   {
7720     int i;
7721     for (i=0; i < BYTES_IN_MMI_REGS; i++)
7722       {
7723         unsigned int s = RS_UB(i);
7724         unsigned int t = RT_UB(i);
7725         unsigned int r = s + t;
7726         if (r > 0xFF)
7727           GPR_UB(destreg,i) = 0xFF;
7728         else
7729           GPR_UB(destreg,i) = r;
7730       }
7731   }
7732 }
7733
7734 // end-sanitize-r5900
7735 // start-sanitize-r5900
7736
7737 011100,5.RS,5.RT,5.RD,10100101000:MMI1:32::PADDUH
7738 *r5900:
7739 {
7740   unsigned32 instruction = instruction_0;
7741   int destreg = ((instruction >> 11) & 0x0000001F);
7742   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7743   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7744   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7745   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7746   {
7747     int i;
7748     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7749       {
7750         unsigned int s = RS_UH(i);
7751         unsigned int t = RT_UH(i);
7752         unsigned int r = s + t;
7753         if (r > 0xFFFF)
7754           GPR_UH(destreg,i) = 0xFFFF;
7755         else
7756           GPR_UH(destreg,i) = r;
7757       }
7758   }
7759 }
7760
7761 // end-sanitize-r5900
7762 // start-sanitize-r5900
7763
7764 011100,5.RS,5.RT,5.RD,10000101000:MMI1:32::PADDUW
7765 *r5900:
7766 {
7767   unsigned32 instruction = instruction_0;
7768   int destreg = ((instruction >> 11) & 0x0000001F);
7769   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7770   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7771   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7772   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7773   {
7774     int i;
7775     for (i=0; i < WORDS_IN_MMI_REGS; i++)
7776       {
7777         unsigned64 s = RS_UW(i);
7778         unsigned64 t = RT_UW(i);
7779         unsigned64 r = s + t;
7780         if (r > 0xFFFFFFFF)
7781           GPR_UW(destreg,i) = 0xFFFFFFFF;
7782         else
7783           GPR_UW(destreg,i) = r;
7784       }
7785   }
7786 }
7787
7788 // end-sanitize-r5900
7789 // start-sanitize-r5900
7790
7791 011100,5.RS,5.RT,5.RD,00100101000:MMI1:32::PADSBH
7792 *r5900:
7793 {
7794   unsigned32 instruction = instruction_0;
7795   int destreg = ((instruction >> 11) & 0x0000001F);
7796   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7797   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7798   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7799   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7800   {
7801     int i;
7802     for(i=0;i<HALFWORDS_IN_MMI_REGS/2;i++)
7803       GPR_SH(destreg,i) = RS_SH(i) - RT_SH(i);
7804     for(;i<HALFWORDS_IN_MMI_REGS;i++)
7805       GPR_SH(destreg,i) = RS_SH(i) + RT_SH(i);
7806   }
7807 }
7808
7809 // end-sanitize-r5900
7810 // start-sanitize-r5900
7811
7812 011100,5.RS,5.RT,5.RD,10010001001:MMI2:32::PAND
7813 *r5900:
7814 {
7815   unsigned32 instruction = instruction_0;
7816   int destreg = ((instruction >> 11) & 0x0000001F);
7817   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7818   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7819   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7820   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7821   {
7822     int i;
7823     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7824       GPR_UW(destreg,i) = (RS_UW(i) & RT_UW(i));
7825   }
7826 }
7827
7828 // end-sanitize-r5900
7829 // start-sanitize-r5900
7830
7831 011100,5.RS,5.RT,5.RD,01010101000:MMI1:32::PCEQB
7832 *r5900:
7833 {
7834   unsigned32 instruction = instruction_0;
7835   int destreg = ((instruction >> 11) & 0x0000001F);
7836   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7837   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7838   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7839   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7840   {
7841     int i;
7842     for(i=0;i<BYTES_IN_MMI_REGS;i++)
7843       {
7844         if (RS_SB(i) == RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
7845         else                        GPR_SB(destreg,i) = 0;
7846       }
7847   }
7848 }
7849
7850 // end-sanitize-r5900
7851 // start-sanitize-r5900
7852
7853 011100,5.RS,5.RT,5.RD,00110101000:MMI1:32::PCEQH
7854 *r5900:
7855 {
7856   unsigned32 instruction = instruction_0;
7857   int destreg = ((instruction >> 11) & 0x0000001F);
7858   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7859   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7860   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7861   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7862   {
7863     int i;
7864     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7865       {
7866         if (RS_SH(i) == RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
7867         else                        GPR_SH(destreg,i) = 0;
7868       }
7869   }
7870 }
7871
7872 // end-sanitize-r5900
7873 // start-sanitize-r5900
7874
7875 011100,5.RS,5.RT,5.RD,00010101000:MMI1:32::PCEQW
7876 *r5900:
7877 {
7878   unsigned32 instruction = instruction_0;
7879   int destreg = ((instruction >> 11) & 0x0000001F);
7880   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7881   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7882   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7883   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7884   {
7885     int i;
7886     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7887       {
7888         if (RS_SW(i) == RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
7889         else                        GPR_SW(destreg,i) = 0;
7890       }
7891   }
7892 }
7893
7894 // end-sanitize-r5900
7895 // start-sanitize-r5900
7896
7897 011100,5.RS,5.RT,5.RD,01010001000:MMI0:32::PCGTB
7898 *r5900:
7899 {
7900   unsigned32 instruction = instruction_0;
7901   int destreg = ((instruction >> 11) & 0x0000001F);
7902   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7903   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7904   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7905   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7906   {
7907     int i;
7908     for(i=0;i<BYTES_IN_MMI_REGS;i++)
7909       {
7910         if (RS_SB(i) > RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
7911         else                        GPR_SB(destreg,i) = 0;
7912       }
7913   }
7914 }
7915
7916 // end-sanitize-r5900
7917 // start-sanitize-r5900
7918
7919 011100,5.RS,5.RT,5.RD,00110001000:MMI0:32::PCGTH
7920 *r5900:
7921 {
7922   unsigned32 instruction = instruction_0;
7923   int destreg = ((instruction >> 11) & 0x0000001F);
7924   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7925   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7926   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7927   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7928   {
7929     int i;
7930     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7931       {
7932         if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
7933         else                        GPR_SH(destreg,i) = 0;
7934       }
7935   }
7936 }
7937
7938 // end-sanitize-r5900
7939 // start-sanitize-r5900
7940
7941 011100,5.RS,5.RT,5.RD,00010001000:MMI0:32::PCGTW
7942 *r5900:
7943 {
7944   unsigned32 instruction = instruction_0;
7945   int destreg = ((instruction >> 11) & 0x0000001F);
7946   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7947   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7948   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7949   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7950   {
7951     int i;
7952     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7953       {
7954         if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
7955         else                        GPR_SW(destreg,i) = 0;
7956       }
7957   }
7958 }
7959
7960 // end-sanitize-r5900
7961 // start-sanitize-r5900
7962
7963 01110000000,5.RT,5.RD,11011101001:MMI3:32::PCPYH
7964 *r5900:
7965 {
7966   unsigned32 instruction = instruction_0;
7967   int destreg = ((instruction >> 11) & 0x0000001F);
7968   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7969   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7970   {
7971     GPR_UH(destreg,7) = GPR_UH(destreg,6) = GPR_UH(destreg,5) = GPR_UH(destreg,4) = RT_UH(4);
7972     GPR_UH(destreg,3) = GPR_UH(destreg,2) = GPR_UH(destreg,1) = GPR_UH(destreg,0) = RT_UH(0);
7973   }
7974 }
7975
7976 // end-sanitize-r5900
7977 // start-sanitize-r5900
7978
7979 011100,5.RS,5.RT,5.RD,01110001001:MMI2:32::PCPYLD
7980 *r5900:
7981 {
7982   unsigned32 instruction = instruction_0;
7983   int destreg = ((instruction >> 11) & 0x0000001F);
7984   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
7985   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
7986   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7987   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7988   {
7989     GPR_UD(destreg,0) = RT_UD(0);
7990     GPR_UD(destreg,1) = RS_UD(0);
7991   }
7992 }
7993
7994 // end-sanitize-r5900
7995 // start-sanitize-r5900
7996
7997 011100,5.RS,5.RT,5.RD,01110101001:MMI3:32::PCPYUD
7998 *r5900:
7999 {
8000   unsigned32 instruction = instruction_0;
8001   int destreg = ((instruction >> 11) & 0x0000001F);
8002   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8003   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8004   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8005   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8006   {
8007     GPR_UD(destreg,0) = RS_UD(1);
8008     GPR_UD(destreg,1) = RT_UD(1);
8009   }
8010 }
8011
8012 // end-sanitize-r5900
8013 // start-sanitize-r5900
8014
8015 011100,5.RS,5.RT,0000011101001001:MMI2:32::PDIVBW
8016 *r5900:
8017 {
8018   unsigned32 instruction = instruction_0;
8019   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8020   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8021   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8022   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8023   {
8024     signed32 devisor = RT_SH(0);
8025     if (devisor == -1)
8026       {
8027         LO_SW(0) = -RS_SW(0);
8028         HI_SW(0) = 0;
8029         LO_SW(1) = -RS_SW(1);
8030         HI_SW(1) = 0;
8031         LO_SW(2) = -RS_SW(2);
8032         HI_SW(2) = 0;
8033         LO_SW(3) = -RS_SW(3);
8034         HI_SW(3) = 0;
8035       }
8036     else if (devisor != 0)
8037       {
8038         LO_SW(0) = RS_SW(0) / devisor;
8039         HI_SW(0) = SIGNEXTEND( (RS_SW(0) % devisor), 16 );
8040         LO_SW(1) = RS_SW(1) / devisor;
8041         HI_SW(1) = SIGNEXTEND( (RS_SW(1) % devisor), 16 );
8042         LO_SW(2) = RS_SW(2) / devisor;
8043         HI_SW(2) = SIGNEXTEND( (RS_SW(2) % devisor), 16 );
8044         LO_SW(3) = RS_SW(3) / devisor;
8045         HI_SW(3) = SIGNEXTEND( (RS_SW(3) % devisor), 16 );
8046       }
8047   }
8048 }
8049
8050 // end-sanitize-r5900
8051 // start-sanitize-r5900
8052
8053 011100,5.RS,5.RT,0000001101101001:MMI3:32::PDIVUW
8054 *r5900:
8055 {
8056   unsigned32 instruction = instruction_0;
8057   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8058   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8059   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8060   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8061   {
8062     if (RT_UW(0) != 0)
8063       {
8064         LO  = (signed32)(RS_UW(0) / RT_UW(0));
8065         HI  = (signed32)(RS_UW(0) % RT_UW(0));
8066       }
8067     if (RT_UW(2) != 0)
8068       {
8069         LO1 = (signed32)(RS_UW(2) / RT_UW(2));
8070         HI1 = (signed32)(RS_UW(2) % RT_UW(2));
8071       }
8072   }
8073 }
8074
8075 // end-sanitize-r5900
8076 // start-sanitize-r5900
8077
8078 011100,5.RS,5.RT,0000001101001001:MMI2:32::PDIVW
8079 *r5900:
8080 {
8081   unsigned32 instruction = instruction_0;
8082   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8083   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8084   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8085   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8086   {
8087     if (RT_SW(0) == -1)
8088       {
8089         LO  = -RS_SW(0);
8090         HI  = 0;
8091       }
8092     else if (RT_UW(0) != 0)
8093       {
8094         LO  = (signed32)(RS_SW(0) / RT_SW(0));
8095         HI  = (signed32)(RS_SW(0) % RT_SW(0));
8096       }
8097     if (RT_SW(2) == -1)
8098       {
8099         LO1 = -RS_SW(2);
8100         HI1 = 0;
8101       }
8102     else if (RT_UW(2) != 0)
8103       {
8104         LO1 = (signed32)(RS_SW(2) / RT_SW(2));
8105         HI1 = (signed32)(RS_SW(2) % RT_SW(2));
8106       }
8107   }
8108 }
8109
8110 // end-sanitize-r5900
8111 // start-sanitize-r5900
8112
8113 01110000000,5.RT,5.RD,11010101001:MMI3:32::PEXCH
8114 *r5900:
8115 {
8116   unsigned32 instruction = instruction_0;
8117   int destreg = ((instruction >> 11) & 0x0000001F);
8118   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8119   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8120   {
8121     GPR_UH(destreg,0) = RT_UH(0);
8122     GPR_UH(destreg,1) = RT_UH(2);
8123     GPR_UH(destreg,2) = RT_UH(1);
8124     GPR_UH(destreg,3) = RT_UH(3);
8125     GPR_UH(destreg,4) = RT_UH(4);
8126     GPR_UH(destreg,5) = RT_UH(6);
8127     GPR_UH(destreg,6) = RT_UH(5);
8128     GPR_UH(destreg,7) = RT_UH(7);
8129   }
8130 }
8131
8132 // end-sanitize-r5900
8133 // start-sanitize-r5900
8134
8135 01110000000,5.RT,5.RD,11110101001:MMI3:32::PEXCW
8136 *r5900:
8137 {
8138   unsigned32 instruction = instruction_0;
8139   int destreg = ((instruction >> 11) & 0x0000001F);
8140   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8141   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8142   {
8143     GPR_UW(destreg,0) = RT_UW(0);
8144     GPR_UW(destreg,1) = RT_UW(2);
8145     GPR_UW(destreg,2) = RT_UW(1);
8146     GPR_UW(destreg,3) = RT_UW(3);
8147   }
8148 }
8149
8150 // end-sanitize-r5900
8151 // start-sanitize-r5900
8152
8153 01110000000,5.RT,5.RD,11010001001:MMI2:32::PEXOH
8154 *r5900:
8155 {
8156   unsigned32 instruction = instruction_0;
8157   int destreg = ((instruction >> 11) & 0x0000001F);
8158   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8159   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8160   {
8161     GPR_UH(destreg,0) = RT_UH(2);
8162     GPR_UH(destreg,1) = RT_UH(1);
8163     GPR_UH(destreg,2) = RT_UH(0);
8164     GPR_UH(destreg,3) = RT_UH(3);
8165     GPR_UH(destreg,4) = RT_UH(6);
8166     GPR_UH(destreg,5) = RT_UH(5);
8167     GPR_UH(destreg,6) = RT_UH(4);
8168     GPR_UH(destreg,7) = RT_UH(7);
8169   }
8170 }
8171
8172 // end-sanitize-r5900
8173 // start-sanitize-r5900
8174
8175 01110000000,5.RT,5.RD,11110001001:MMI2:32::PEXOW
8176 *r5900:
8177 {
8178   unsigned32 instruction = instruction_0;
8179   int destreg = ((instruction >> 11) & 0x0000001F);
8180   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8181   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8182   {
8183     GPR_UW(destreg,0) = RT_UW(2);
8184     GPR_UW(destreg,1) = RT_UW(1);
8185     GPR_UW(destreg,2) = RT_UW(0);
8186     GPR_UW(destreg,3) = RT_UW(3);
8187   }
8188 }
8189
8190 // end-sanitize-r5900
8191 // start-sanitize-r5900
8192
8193 01110000000,5.RT,5.RD,11110001000:MMI0:32::PEXT5
8194 *r5900:
8195 {
8196   unsigned32 instruction = instruction_0;
8197   int destreg = ((instruction >> 11) & 0x0000001F);
8198   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8199   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8200   {
8201     int i;
8202     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8203       {
8204         unsigned32 x = RT_UW(i);
8205         GPR_UW(destreg,i) = ((x & (1  << 15)) << (31 - 15))
8206           | ((x & (31 << 10)) << (19 - 10))
8207           | ((x & (31 << 5))  << (11 - 5))
8208           | ((x & (31 << 0))  << (3  - 0));
8209       }
8210   }
8211 }
8212
8213 // end-sanitize-r5900
8214 // start-sanitize-r5900
8215
8216 011100,5.RS,5.RT,5.RD,11010001000:MMI0:32::PEXTLB
8217 *r5900:
8218 {
8219   unsigned32 instruction = instruction_0;
8220   int destreg = ((instruction >> 11) & 0x0000001F);
8221   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8222   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8223   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8224   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8225   {
8226     GPR_UB(destreg,0)  = RT_UB(0);
8227     GPR_UB(destreg,1)  = RS_UB(0);
8228     GPR_UB(destreg,2)  = RT_UB(1);
8229     GPR_UB(destreg,3)  = RS_UB(1);
8230     GPR_UB(destreg,4)  = RT_UB(2);
8231     GPR_UB(destreg,5)  = RS_UB(2);
8232     GPR_UB(destreg,6)  = RT_UB(3);
8233     GPR_UB(destreg,7)  = RS_UB(3);
8234     GPR_UB(destreg,8)  = RT_UB(4);
8235     GPR_UB(destreg,9)  = RS_UB(4);
8236     GPR_UB(destreg,10) = RT_UB(5);
8237     GPR_UB(destreg,11) = RS_UB(5);
8238     GPR_UB(destreg,12) = RT_UB(6);
8239     GPR_UB(destreg,13) = RS_UB(6);
8240     GPR_UB(destreg,14) = RT_UB(7);
8241     GPR_UB(destreg,15) = RS_UB(7);
8242   }
8243 }
8244
8245 // end-sanitize-r5900
8246 // start-sanitize-r5900
8247
8248 011100,5.RS,5.RT,5.RD,10110001000:MMI0:32::PEXTLH
8249 *r5900:
8250 {
8251   unsigned32 instruction = instruction_0;
8252   int destreg = ((instruction >> 11) & 0x0000001F);
8253   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8254   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8255   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8256   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8257   {
8258     GPR_UH(destreg,0)  = RT_UH(0);
8259     GPR_UH(destreg,1)  = RS_UH(0);
8260     GPR_UH(destreg,2)  = RT_UH(1);
8261     GPR_UH(destreg,3)  = RS_UH(1);
8262     GPR_UH(destreg,4)  = RT_UH(2);
8263     GPR_UH(destreg,5)  = RS_UH(2);
8264     GPR_UH(destreg,6)  = RT_UH(3);
8265     GPR_UH(destreg,7)  = RS_UH(3);
8266   }
8267 }
8268
8269 // end-sanitize-r5900
8270 // start-sanitize-r5900
8271
8272 011100,5.RS,5.RT,5.RD,10010001000:MMI0:32::PEXTLW
8273 *r5900:
8274 {
8275   unsigned32 instruction = instruction_0;
8276   int destreg = ((instruction >> 11) & 0x0000001F);
8277   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8278   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8279   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8280   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8281   {
8282     GPR_UW(destreg,0)  = RT_UW(0);
8283     GPR_UW(destreg,1)  = RS_UW(0);
8284     GPR_UW(destreg,2)  = RT_UW(1);
8285     GPR_UW(destreg,3)  = RS_UW(1);
8286   }
8287 }
8288
8289 // end-sanitize-r5900
8290 // start-sanitize-r5900
8291
8292 011100,5.RS,5.RT,5.RD,11010101000:MMI1:32::PEXTUB
8293 *r5900:
8294 {
8295   unsigned32 instruction = instruction_0;
8296   int destreg = ((instruction >> 11) & 0x0000001F);
8297   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8298   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8299   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8300   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8301   {
8302     GPR_UB(destreg,0)  = RT_UB(8);
8303     GPR_UB(destreg,1)  = RS_UB(8);
8304     GPR_UB(destreg,2)  = RT_UB(9);
8305     GPR_UB(destreg,3)  = RS_UB(9);
8306     GPR_UB(destreg,4)  = RT_UB(10);
8307     GPR_UB(destreg,5)  = RS_UB(10);
8308     GPR_UB(destreg,6)  = RT_UB(11);
8309     GPR_UB(destreg,7)  = RS_UB(11);
8310     GPR_UB(destreg,8)  = RT_UB(12);
8311     GPR_UB(destreg,9)  = RS_UB(12);
8312     GPR_UB(destreg,10) = RT_UB(13);
8313     GPR_UB(destreg,11) = RS_UB(13);
8314     GPR_UB(destreg,12) = RT_UB(14);
8315     GPR_UB(destreg,13) = RS_UB(14);
8316     GPR_UB(destreg,14) = RT_UB(15);
8317     GPR_UB(destreg,15) = RS_UB(15);
8318   }
8319 }
8320
8321 // end-sanitize-r5900
8322 // start-sanitize-r5900
8323
8324 011100,5.RS,5.RT,5.RD,10110101000:MMI1:32::PEXTUH
8325 *r5900:
8326 {
8327   unsigned32 instruction = instruction_0;
8328   int destreg = ((instruction >> 11) & 0x0000001F);
8329   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8330   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8331   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8332   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8333   {
8334     GPR_UH(destreg,0)  = RT_UH(4);
8335     GPR_UH(destreg,1)  = RS_UH(4);
8336     GPR_UH(destreg,2)  = RT_UH(5);
8337     GPR_UH(destreg,3)  = RS_UH(5);
8338     GPR_UH(destreg,4)  = RT_UH(6);
8339     GPR_UH(destreg,5)  = RS_UH(6);
8340     GPR_UH(destreg,6)  = RT_UH(7);
8341     GPR_UH(destreg,7)  = RS_UH(7);
8342   }
8343 }
8344
8345 // end-sanitize-r5900
8346 // start-sanitize-r5900
8347
8348 011100,5.RS,5.RT,5.RD,10010101000:MMI1:32::PEXTUW
8349 *r5900:
8350 {
8351   unsigned32 instruction = instruction_0;
8352   int destreg = ((instruction >> 11) & 0x0000001F);
8353   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8354   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8355   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8356   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8357   {
8358     GPR_UW(destreg,0)  = RT_UW(2);
8359     GPR_UW(destreg,1)  = RS_UW(2);
8360     GPR_UW(destreg,2)  = RT_UW(3);
8361     GPR_UW(destreg,3)  = RS_UW(3);
8362   }
8363 }
8364
8365 // end-sanitize-r5900
8366 // start-sanitize-r5900
8367
8368 011100,5.RS,5.RT,5.RD,10001001001:MMI2:32::PHMADDH
8369 *r5900:
8370 {
8371   unsigned32 instruction = instruction_0;
8372   int destreg = ((instruction >> 11) & 0x0000001F);
8373   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8374   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8375   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8376   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8377   {
8378     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) + (RS_SH(0) * RT_SH(0));
8379     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) + (RS_SH(2) * RT_SH(2));
8380     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) + (RS_SH(4) * RT_SH(4));
8381     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) + (RS_SH(6) * RT_SH(6));
8382   }
8383 }
8384
8385 // end-sanitize-r5900
8386 // start-sanitize-r5900
8387
8388 011100,5.RS,5.RT,5.RD,10101001001:MMI2:32::PHMSUBH
8389 *r5900:
8390 {
8391   unsigned32 instruction = instruction_0;
8392   int destreg = ((instruction >> 11) & 0x0000001F);
8393   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8394   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8395   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8396   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8397   {
8398     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) - (RS_SH(0) * RT_SH(0));
8399     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) - (RS_SH(2) * RT_SH(2));
8400     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) - (RS_SH(4) * RT_SH(4));
8401     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) - (RS_SH(6) * RT_SH(6));
8402   }
8403 }
8404
8405 // end-sanitize-r5900
8406 // start-sanitize-r5900
8407
8408 011100,5.RS,5.RT,5.RD,01010001001:MMI2:32::PINTH
8409 *r5900:
8410 {
8411   unsigned32 instruction = instruction_0;
8412   int destreg = ((instruction >> 11) & 0x0000001F);
8413   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8414   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8415   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8416   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8417   {
8418     GPR_UH(destreg,0)  = RT_UH(0);
8419     GPR_UH(destreg,1)  = RS_UH(4);
8420     GPR_UH(destreg,2)  = RT_UH(1);
8421     GPR_UH(destreg,3)  = RS_UH(5);
8422     GPR_UH(destreg,4)  = RT_UH(2);
8423     GPR_UH(destreg,5)  = RS_UH(6);
8424     GPR_UH(destreg,6)  = RT_UH(3);
8425     GPR_UH(destreg,7)  = RS_UH(7);
8426   }
8427 }
8428
8429 // end-sanitize-r5900
8430 // start-sanitize-r5900
8431
8432 011100,5.RS,5.RT,5.RD,01010101001:MMI3:32::PINTOH
8433 *r5900:
8434 {
8435   unsigned32 instruction = instruction_0;
8436   int destreg = ((instruction >> 11) & 0x0000001F);
8437   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8438   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8439   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8440   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8441   {
8442     GPR_UH(destreg,0) = RT_UH(0);
8443     GPR_UH(destreg,1) = RS_UH(0);
8444     GPR_UH(destreg,2) = RT_UH(2);
8445     GPR_UH(destreg,3) = RS_UH(2);
8446     GPR_UH(destreg,4) = RT_UH(4);
8447     GPR_UH(destreg,5) = RS_UH(4);
8448     GPR_UH(destreg,6) = RT_UH(6);
8449     GPR_UH(destreg,7) = RS_UH(6);
8450   }
8451 }
8452
8453 // end-sanitize-r5900
8454 // start-sanitize-r5900
8455
8456 011100,5.RS,00000,5.RD,00000000100:MMINORM:32::PLZCW
8457 *r5900:
8458 {
8459   unsigned32 instruction = instruction_0;
8460   int destreg = ((instruction >> 11) & 0x0000001F);
8461   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8462   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8463   {
8464     unsigned long value;
8465     int test;
8466     int count;
8467     int i;
8468     value = RS_UW(0);
8469     count = 0;
8470     test = !!(value & (1 << 31));
8471     for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8472       count++;
8473     GPR_UW(destreg,0) = count;
8474     value = RS_UW(1);
8475     count = 0;
8476     test = !!(value & (1 << 31));
8477     for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8478       count++;
8479     GPR_UW(destreg,1) = count;
8480   }
8481 }
8482
8483 // end-sanitize-r5900
8484 // start-sanitize-r5900
8485
8486 011100,5.RS,5.RT,5.RD,10000001001:MMI2:32::PMADDH
8487 *r5900:
8488 {
8489   unsigned32 instruction = instruction_0;
8490   int destreg = ((instruction >> 11) & 0x0000001F);
8491   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8492   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8493   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8494   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8495   {
8496     GPR_SW(destreg,0) = LO_SW(0) += (RS_SH(0) * RT_SH(0));
8497     LO_SW(1) += (RS_SH(1) * RT_SH(1));
8498     GPR_SW(destreg,1) = HI_SW(0) += (RS_SH(2) * RT_SH(2));
8499     HI_SW(1) += (RS_SH(3) * RT_SH(3));
8500     GPR_SW(destreg,2) = LO_SW(2) += (RS_SH(4) * RT_SH(4));
8501     LO_SW(3) += (RS_SH(5) * RT_SH(5));
8502     GPR_SW(destreg,3) = HI_SW(2) += (RS_SH(6) * RT_SH(6));
8503     HI_SW(3) += (RS_SH(7) * RT_SH(7));
8504   }
8505 }
8506
8507 // end-sanitize-r5900
8508 // start-sanitize-r5900
8509
8510 011100,5.RS,5.RT,5.RD,00000101001:MMI3:32::PMADDUW
8511 *r5900:
8512 {
8513   unsigned32 instruction = instruction_0;
8514   int destreg = ((instruction >> 11) & 0x0000001F);
8515   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8516   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8517   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8518   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8519   {
8520     unsigned64 sum0 = U8_4 (HI_SW(0), LO_SW(0));
8521     unsigned64 sum1 = u8_4 (HI_SW(2), LO_SW(2));
8522     unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
8523     unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
8524     sum0 += prod0;
8525     sum1 += prod1;
8526     GPR_UD(destreg,0) = sum0;
8527     GPR_UD(destreg,1) = sum1;
8528     LO  = SIGNEXTEND( sum0, 32 );
8529     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8530     LO1 = SIGNEXTEND( sum1, 32 );
8531     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8532   }
8533 }
8534
8535 // end-sanitize-r5900
8536 // start-sanitize-r5900
8537
8538 011100,5.RS,5.RT,5.RD,00000001001:MMI2:32::PMADDW
8539 *r5900:
8540 {
8541   unsigned32 instruction = instruction_0;
8542   int destreg = ((instruction >> 11) & 0x0000001F);
8543   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8544   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8545   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8546   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8547   {
8548     signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
8549     signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
8550     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8551     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8552     sum0 += prod0;
8553     sum1 += prod1;
8554     GPR_SD(destreg,0) = sum0;
8555     GPR_SD(destreg,1) = sum1;
8556     LO  = SIGNEXTEND( sum0, 32 );
8557     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8558     LO1 = SIGNEXTEND( sum1, 32 );
8559     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8560   }
8561 }
8562
8563 // end-sanitize-r5900
8564 // start-sanitize-r5900
8565
8566 011100,5.RS,5.RT,5.RD,00111001000:MMI0:32::PMAXH
8567 *r5900:
8568 {
8569   unsigned32 instruction = instruction_0;
8570   int destreg = ((instruction >> 11) & 0x0000001F);
8571   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8572   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8573   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8574   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8575   {
8576     int i;
8577     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8578       {
8579         if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
8580         else                        GPR_SH(destreg,i) = RT_SH(i);
8581       }
8582   }
8583 }
8584
8585 // end-sanitize-r5900
8586 // start-sanitize-r5900
8587
8588 011100,5.RS,5.RT,5.RD,00011001000:MMI0:32::PMAXW
8589 *r5900:
8590 {
8591   unsigned32 instruction = instruction_0;
8592   int destreg = ((instruction >> 11) & 0x0000001F);
8593   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8594   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8595   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8596   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8597   {
8598     int i;
8599     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8600       {
8601         if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
8602         else                        GPR_SW(destreg,i) = RT_SW(i);
8603       }
8604   }
8605 }
8606
8607 // end-sanitize-r5900
8608 // start-sanitize-r5900
8609
8610 0111000000000000,5.RD,01000001001:MMI2:32::PMFHI
8611 *r5900:
8612 {
8613   unsigned32 instruction = instruction_0;
8614   int destreg = ((instruction >> 11) & 0x0000001F);
8615   {
8616     GPR_SD(destreg,0) = HI;
8617     GPR_SD(destreg,1) = HI1;
8618   }
8619 }
8620
8621 // end-sanitize-r5900
8622 // start-sanitize-r5900
8623
8624 0111000000000000,5.RD,01001001001:MMI2:32::PMFLO
8625 *r5900:
8626 {
8627   unsigned32 instruction = instruction_0;
8628   int destreg = ((instruction >> 11) & 0x0000001F);
8629   {
8630     GPR_SD(destreg,0) = LO;
8631     GPR_SD(destreg,1) = LO1;
8632   }
8633 }
8634
8635 // end-sanitize-r5900
8636 // start-sanitize-r5900
8637
8638 0111000000000000,5.RD,5.SHIFT,110000:MMINORM:32::PMFHL
8639 *r5900:
8640 {
8641   unsigned32 instruction = instruction_0;
8642   int op1 = ((instruction >> 6) & 0x0000001F);
8643   int destreg = ((instruction >> 11) & 0x0000001F);
8644   {
8645     if (op1 == 0)
8646       {
8647         GPR_UW(destreg,0) = LO_UW(0);
8648         GPR_UW(destreg,1) = HI_UW(0);
8649         GPR_UW(destreg,2) = LO_UW(2);
8650         GPR_UW(destreg,3) = HI_UW(2);
8651       }
8652     else if (op1 == 1)
8653       {
8654         GPR_UW(destreg,0) = LO_UW(1);
8655         GPR_UW(destreg,1) = HI_UW(1);
8656         GPR_UW(destreg,2) = LO_UW(3);
8657         GPR_UW(destreg,3) = HI_UW(3);
8658       }
8659     else if (op1 == 2)
8660       {
8661         /* NOTE: This code implements a saturate according to the
8662            figure on page B-115 and not according to the
8663            definition on page B-113 */
8664         signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0);
8665         signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2);
8666         if ( t > SIGNED64 (0x000000007FFFFFFF) )
8667           GPR_SD(destreg,0) = SIGNED64 (0x000000007FFFFFFF);
8668         else if ( t < - SIGNED64 (0x0000000080000000) )
8669           GPR_SD(destreg,0) = - SIGNED64 (0x0000000080000000);
8670         else
8671           GPR_SD(destreg,0) = t;
8672         if ( u > SIGNED64 (0x000000007FFFFFFF) )
8673           GPR_SD(destreg,1) = SIGNED64 (0x000000007FFFFFFF);
8674         else if ( u < - SIGNED64 (0x0000000080000000) )
8675           GPR_SD(destreg,1) = - SIGNED64 (0x0000000080000000);
8676         else
8677           GPR_SD(destreg,1) = u;
8678       }
8679     else if (op1 == 3)
8680       {
8681         GPR_UH(destreg,0) = LO_UH(0);
8682         GPR_UH(destreg,1) = LO_UH(2);
8683         GPR_UH(destreg,2) = HI_UH(0);
8684         GPR_UH(destreg,3) = HI_UH(2);
8685         GPR_UH(destreg,4) = LO_UH(4);
8686         GPR_UH(destreg,5) = LO_UH(6);
8687         GPR_UH(destreg,6) = HI_UH(4);
8688         GPR_UH(destreg,7) = HI_UH(6);
8689       }
8690     else if (op1 == 4)
8691       {
8692         if (LO_SW(0) > 0x7FFF)
8693           GPR_UH(destreg,0) = 0x7FFF;
8694         else if (LO_SW(0) < -0x8000)
8695           GPR_UH(destreg,0) = 0x8000;
8696         else
8697           GPR_UH(destreg,0) = LO_UH(0);
8698         if (LO_SW(1) > 0x7FFF)
8699           GPR_UH(destreg,1) = 0x7FFF;
8700         else if (LO_SW(1) < -0x8000)
8701           GPR_UH(destreg,1) = 0x8000;
8702         else
8703           GPR_UH(destreg,1) = LO_UH(2);
8704         if (HI_SW(0) > 0x7FFF)
8705           GPR_UH(destreg,2) = 0x7FFF;
8706         else if (HI_SW(0) < -0x8000)
8707           GPR_UH(destreg,2) = 0x8000;
8708         else
8709           GPR_UH(destreg,2) = HI_UH(0);
8710         if (HI_SW(1) > 0x7FFF)
8711           GPR_UH(destreg,3) = 0x7FFF;
8712         else if (HI_SW(1) < -0x8000)
8713           GPR_UH(destreg,3) = 0x8000;
8714         else
8715           GPR_UH(destreg,3) = HI_UH(2);
8716         if (LO_SW(2) > 0x7FFF)
8717           GPR_UH(destreg,4) = 0x7FFF;
8718         else if (LO_SW(2) < -0x8000)
8719           GPR_UH(destreg,4) = 0x8000;
8720         else
8721           GPR_UH(destreg,4) = LO_UH(4);
8722         if (LO_SW(3) > 0x7FFF)
8723           GPR_UH(destreg,5) = 0x7FFF;
8724         else if (LO_SW(3) < -0x8000)
8725           GPR_UH(destreg,5) = 0x8000;
8726         else
8727           GPR_UH(destreg,5) = LO_UH(6);
8728         if (HI_SW(2) > 0x7FFF)
8729           GPR_UH(destreg,6) = 0x7FFF;
8730         else if (HI_SW(2) < -0x8000)
8731           GPR_UH(destreg,6) = 0x8000;
8732         else
8733           GPR_UH(destreg,6) = HI_UH(4);
8734         if (HI_SW(3) > 0x7FFF)
8735           GPR_UH(destreg,7) = 0x7FFF;
8736         else if (HI_SW(3) < -0x8000)
8737           GPR_UH(destreg,7) = 0x8000;
8738         else
8739           GPR_UH(destreg,7) = HI_UH(6);
8740       }
8741   }
8742 }
8743
8744 // end-sanitize-r5900
8745 // start-sanitize-r5900
8746
8747 011100,5.RS,5.RT,5.RD,00111101000:MMI1:32::PMINH
8748 *r5900:
8749 {
8750   unsigned32 instruction = instruction_0;
8751   int destreg = ((instruction >> 11) & 0x0000001F);
8752   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8753   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8754   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8755   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8756   {
8757     int i;
8758     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8759       {
8760         if (RS_SH(i) < RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
8761         else                        GPR_SH(destreg,i) = RT_SH(i);
8762       }
8763   }
8764 }
8765
8766 // end-sanitize-r5900
8767 // start-sanitize-r5900
8768
8769 011100,5.RS,5.RT,5.RD,00011101000:MMI1:32::PMINW
8770 *r5900:
8771 {
8772   unsigned32 instruction = instruction_0;
8773   int destreg = ((instruction >> 11) & 0x0000001F);
8774   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8775   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8776   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8777   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8778   {
8779     int i;
8780     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8781       {
8782         if (RS_SW(i) < RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
8783         else                        GPR_SW(destreg,i) = RT_SW(i);
8784       }
8785   }
8786 }
8787
8788 // end-sanitize-r5900
8789 // start-sanitize-r5900
8790
8791 011100,5.RS,5.RT,5.RD,10100001001:MMI2:32::PMSUBH
8792 *r5900:
8793 {
8794   unsigned32 instruction = instruction_0;
8795   int destreg = ((instruction >> 11) & 0x0000001F);
8796   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8797   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8798   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8799   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8800   {
8801     GPR_SW(destreg,0) = LO_SW(0) -= (RS_SH(0) * RT_SH(0));
8802     LO_SW(1) -= (RS_SH(1) * RT_SH(1));
8803     GPR_SW(destreg,1) = HI_SW(0) -= (RS_SH(2) * RT_SH(2));
8804     HI_SW(1) -= (RS_SH(3) * RT_SH(3));
8805     GPR_SW(destreg,2) = LO_SW(2) -= (RS_SH(4) * RT_SH(4));
8806     LO_SW(3) -= (RS_SH(5) * RT_SH(5));
8807     GPR_SW(destreg,3) = HI_SW(2) -= (RS_SH(6) * RT_SH(6));
8808     HI_SW(3) -= (RS_SH(7) * RT_SH(7));
8809   }
8810 }
8811
8812 // end-sanitize-r5900
8813 // start-sanitize-r5900
8814
8815 011100,5.RS,5.RT,5.RD,00100001001:MMI2:32::PMSUBW
8816 *r5900:
8817 {
8818   unsigned32 instruction = instruction_0;
8819   int destreg = ((instruction >> 11) & 0x0000001F);
8820   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8821   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8822   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8823   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8824   {
8825     signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
8826     signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
8827     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8828     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8829     sum0 -= prod0;
8830     sum1 -= prod1;
8831     GPR_SD(destreg,0) = sum0;
8832     GPR_SD(destreg,1) = sum1;
8833     LO  = SIGNEXTEND( sum0, 32 );
8834     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8835     LO1 = SIGNEXTEND( sum1, 32 );
8836     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8837   }
8838 }
8839
8840 // end-sanitize-r5900
8841 // start-sanitize-r5900
8842
8843 011100,5.RS,000000000001000101001:MMI3:32::PMTHI
8844 *r5900:
8845 {
8846   unsigned32 instruction = instruction_0;
8847   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8848   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8849   {
8850     HI  = RS_SD(0);
8851     HI1 = RS_SD(1);
8852   }
8853 }
8854
8855 // end-sanitize-r5900
8856 // start-sanitize-r5900
8857
8858 011100,5.RS,000000000001001101001:MMI3:32::PMTLO
8859 *r5900:
8860 {
8861   unsigned32 instruction = instruction_0;
8862   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8863   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8864   {
8865     LO  = RS_SD(0);
8866     LO1 = RS_SD(1);
8867   }
8868 }
8869
8870 // end-sanitize-r5900
8871 // start-sanitize-r5900
8872
8873 011100,5.RS,000000000000000110001:MMINORM:32::PMTHL.LW
8874 *r5900:
8875 {
8876   unsigned32 instruction = instruction_0;
8877   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8878   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8879   {
8880     LO_UW(0) = RS_UW(0);
8881     HI_UW(0) = RS_UW(1);
8882     LO_UW(2) = RS_UW(2);
8883     HI_UW(2) = RS_UW(3);
8884   }
8885 }
8886
8887 // end-sanitize-r5900
8888 // start-sanitize-r5900
8889
8890 011100,5.RS,5.RT,5.RD,11100001001:MMI2:32::PMULTH
8891 *r5900:
8892 {
8893   unsigned32 instruction = instruction_0;
8894   int destreg = ((instruction >> 11) & 0x0000001F);
8895   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8896   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8897   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8898   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8899   {
8900     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(0) * RT_SH(0));
8901     LO_SW(1) = (RS_SH(1) * RT_SH(1));
8902     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(2) * RT_SH(2));
8903     HI_SW(1) = (RS_SH(3) * RT_SH(3));
8904     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(4) * RT_SH(4));
8905     LO_SW(3) = (RS_SH(5) * RT_SH(5));
8906     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(6) * RT_SH(6));
8907     HI_SW(3) = (RS_SH(7) * RT_SH(7));
8908   }
8909 }
8910
8911 // end-sanitize-r5900
8912 // start-sanitize-r5900
8913
8914 011100,5.RS,5.RT,5.RD,01100101001:MMI3:32::PMULTUW
8915 *r5900:
8916 {
8917   unsigned32 instruction = instruction_0;
8918   int destreg = ((instruction >> 11) & 0x0000001F);
8919   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8920   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8921   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8922   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8923   {
8924     unsigned64 sum0 = 0;
8925     unsigned64 sum1 = 0;
8926     unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
8927     unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
8928     sum0 = prod0;
8929     sum1 = prod1;
8930     GPR_UD(destreg,0) = sum0;
8931     GPR_UD(destreg,1) = sum1;
8932     LO  = SIGNEXTEND( sum0, 32 );
8933     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8934     LO1 = SIGNEXTEND( sum1, 32 );
8935     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8936   }
8937 }
8938
8939 // end-sanitize-r5900
8940 // start-sanitize-r5900
8941
8942 011100,5.RS,5.RT,5.RD,01100001001:MMI2:32::PMULTW
8943 *r5900:
8944 {
8945   unsigned32 instruction = instruction_0;
8946   int destreg = ((instruction >> 11) & 0x0000001F);
8947   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8948   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8949   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8950   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8951   {
8952     signed64 sum0 = 0;
8953     signed64 sum1 = 0;
8954     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8955     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8956     sum0 = prod0;
8957     sum1 = prod1;
8958     GPR_SD(destreg,0) = sum0;
8959     GPR_SD(destreg,1) = sum1;
8960     LO  = SIGNEXTEND( sum0, 32 );
8961     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8962     LO1 = SIGNEXTEND( sum1, 32 );
8963     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8964   }
8965 }
8966
8967 // end-sanitize-r5900
8968 // start-sanitize-r5900
8969
8970 011100,5.RS,5.RT,5.RD,10011101001:MMI3:32::PNOR
8971 *r5900:
8972 {
8973   unsigned32 instruction = instruction_0;
8974   int destreg = ((instruction >> 11) & 0x0000001F);
8975   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8976   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8977   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8978   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8979   {
8980     int i;
8981     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8982       GPR_UW(destreg,i) = ~(RS_UW(i) | RT_UW(i));
8983   }
8984 }
8985
8986 // end-sanitize-r5900
8987 // start-sanitize-r5900
8988
8989 011100,5.RS,5.RT,5.RD,10010101001:MMI3:32::POR
8990 *r5900:
8991 {
8992   unsigned32 instruction = instruction_0;
8993   int destreg = ((instruction >> 11) & 0x0000001F);
8994   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
8995   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
8996   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8997   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8998   {
8999     int i;
9000     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9001       GPR_UW(destreg,i) = (RS_UW(i) | RT_UW(i));
9002   }
9003 }
9004
9005 // end-sanitize-r5900
9006 // start-sanitize-r5900
9007
9008 01110000000,5.RT,5.RD,11111001000:MMI0:32::PPAC5
9009 *r5900:
9010 {
9011   unsigned32 instruction = instruction_0;
9012   int destreg = ((instruction >> 11) & 0x0000001F);
9013   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9014   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9015   {
9016     int i;
9017     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9018       {
9019         unsigned32 x = RT_UW(i);
9020         GPR_UW(destreg,i) = ((x & (1  << 31)) >> (31 - 15))
9021           | ((x & (31 << 19)) >> (19 - 10))
9022           | ((x & (31 << 11)) >> (11 - 5))
9023           | ((x & (31 <<  3)) >> (3  - 0));
9024       }
9025   }
9026 }
9027
9028 // end-sanitize-r5900
9029 // start-sanitize-r5900
9030
9031 011100,5.RS,5.RT,5.RD,11011001000:MMI0:32::PPACB
9032 *r5900:
9033 {
9034   unsigned32 instruction = instruction_0;
9035   int destreg = ((instruction >> 11) & 0x0000001F);
9036   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9037   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9038   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9039   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9040   {
9041     GPR_UB(destreg,0)  = RT_UB(0);
9042     GPR_UB(destreg,1)  = RT_UB(2);
9043     GPR_UB(destreg,2)  = RT_UB(4);
9044     GPR_UB(destreg,3)  = RT_UB(6);
9045     GPR_UB(destreg,4)  = RT_UB(8);
9046     GPR_UB(destreg,5)  = RT_UB(10);
9047     GPR_UB(destreg,6)  = RT_UB(12);
9048     GPR_UB(destreg,7)  = RT_UB(14);
9049     GPR_UB(destreg,8)  = RS_UB(0);
9050     GPR_UB(destreg,9)  = RS_UB(2);
9051     GPR_UB(destreg,10) = RS_UB(4);
9052     GPR_UB(destreg,11) = RS_UB(6);
9053     GPR_UB(destreg,12) = RS_UB(8);
9054     GPR_UB(destreg,13) = RS_UB(10);
9055     GPR_UB(destreg,14) = RS_UB(12);
9056     GPR_UB(destreg,15) = RS_UB(14);
9057   }
9058 }
9059
9060 // end-sanitize-r5900
9061 // start-sanitize-r5900
9062
9063 011100,5.RS,5.RT,5.RD,10111001000:MMI0:32::PPACH
9064 *r5900:
9065 {
9066   unsigned32 instruction = instruction_0;
9067   int destreg = ((instruction >> 11) & 0x0000001F);
9068   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9069   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9070   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9071   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9072   {
9073     GPR_UH(destreg,0)  = RT_UH(0);
9074     GPR_UH(destreg,1)  = RT_UH(2);
9075     GPR_UH(destreg,2)  = RT_UH(4);
9076     GPR_UH(destreg,3)  = RT_UH(6);
9077     GPR_UH(destreg,4)  = RS_UH(0);
9078     GPR_UH(destreg,5)  = RS_UH(2);
9079     GPR_UH(destreg,6)  = RS_UH(4);
9080     GPR_UH(destreg,7)  = RS_UH(6);
9081   }
9082 }
9083
9084 // end-sanitize-r5900
9085 // start-sanitize-r5900
9086
9087 011100,5.RS,5.RT,5.RD,10011001000:MMI0:32::PPACW
9088 *r5900:
9089 {
9090   unsigned32 instruction = instruction_0;
9091   int destreg = ((instruction >> 11) & 0x0000001F);
9092   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9093   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9094   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9095   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9096   {
9097     GPR_UW(destreg,0)  = RT_UW(0);
9098     GPR_UW(destreg,1)  = RT_UW(2);
9099     GPR_UW(destreg,2)  = RS_UW(0);
9100     GPR_UW(destreg,3)  = RS_UW(2);
9101   }
9102 }
9103
9104 // end-sanitize-r5900
9105 // start-sanitize-r5900
9106
9107 01110000000,5.RT,5.RD,11011001001:MMI2:32::PREVH
9108 *r5900:
9109 {
9110   unsigned32 instruction = instruction_0;
9111   int destreg = ((instruction >> 11) & 0x0000001F);
9112   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9113   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9114   {
9115     GPR_UH(destreg,0)  = RT_UH(3);
9116     GPR_UH(destreg,1)  = RT_UH(2);
9117     GPR_UH(destreg,2)  = RT_UH(1);
9118     GPR_UH(destreg,3)  = RT_UH(0);
9119     GPR_UH(destreg,4)  = RT_UH(7);
9120     GPR_UH(destreg,5)  = RT_UH(6);
9121     GPR_UH(destreg,6)  = RT_UH(5);
9122     GPR_UH(destreg,7)  = RT_UH(4);
9123   }
9124 }
9125
9126 // end-sanitize-r5900
9127 // start-sanitize-r5900
9128
9129 01110000000,5.RT,5.RD,11111001001:MMI2:32::PROT3W
9130 *r5900:
9131 {
9132   unsigned32 instruction = instruction_0;
9133   int destreg = ((instruction >> 11) & 0x0000001F);
9134   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9135   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9136   {
9137     GPR_UW(destreg,0)  = RT_UW(0);
9138     GPR_UW(destreg,1)  = RT_UW(3);
9139     GPR_UW(destreg,2)  = RT_UW(1);
9140     GPR_UW(destreg,3)  = RT_UW(2);
9141   }
9142 }
9143
9144 // end-sanitize-r5900
9145 // start-sanitize-r5900
9146
9147 01110000000,5.RT,5.RD,5.SHIFT,110100:MMINORM:32::PSLLH
9148 *r5900:
9149 {
9150   unsigned32 instruction = instruction_0;
9151   int op1 = ((instruction >> 6) & 0x0000001F);
9152   int destreg = ((instruction >> 11) & 0x0000001F);
9153   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9154   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9155   {
9156     int shift_by = op1 & (16-1);
9157     int i;
9158     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9159       GPR_UH(destreg,i) = (RT_UH(i) << shift_by);
9160   }
9161 }
9162
9163 // end-sanitize-r5900
9164 // start-sanitize-r5900
9165
9166 011100,5.RS,5.RT,5.RD,00010001001:MMI2:32::PSLLVW
9167 *r5900:
9168 {
9169   unsigned32 instruction = instruction_0;
9170   int destreg = ((instruction >> 11) & 0x0000001F);
9171   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9172   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9173   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9174   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9175   {
9176     int s0 = (RS_UB(0) & 0x1F);
9177     int s1 = (RS_UB(8) & 0x1F);
9178     signed32 temp0 = RT_UW(0) << s0;
9179     signed32 temp1 = RT_UW(2) << s1;
9180     GPR_SD(destreg,0) = (signed64)temp0;
9181     GPR_SD(destreg,1) = (signed64)temp1;
9182   }
9183 }
9184
9185 // end-sanitize-r5900
9186 // start-sanitize-r5900
9187
9188 01110000000,5.RT,5.RD,5.SHIFT,111100:MMINORM:32::PSLLW
9189 *r5900:
9190 {
9191   unsigned32 instruction = instruction_0;
9192   int op1 = ((instruction >> 6) & 0x0000001F);
9193   int destreg = ((instruction >> 11) & 0x0000001F);
9194   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9195   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9196   {
9197     int shift_by = op1 & (32-1);
9198     int i;
9199     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9200       GPR_UW(destreg,i) = (RT_UW(i) << shift_by);
9201   }
9202 }
9203
9204 // end-sanitize-r5900
9205 // start-sanitize-r5900
9206
9207 01110000000,5.RT,5.RD,5.SHIFT,110111:MMINORM:32::PSRAH
9208 *r5900:
9209 {
9210   unsigned32 instruction = instruction_0;
9211   int op1 = ((instruction >> 6) & 0x0000001F);
9212   int destreg = ((instruction >> 11) & 0x0000001F);
9213   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9214   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9215   {
9216     int shift_by = op1 & (16-1);
9217     int i;
9218     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9219       GPR_SH(destreg,i) = SIGNEXTEND( (RT_SH(i) >> shift_by), (16-shift_by) );
9220   }
9221 }
9222
9223 // end-sanitize-r5900
9224 // start-sanitize-r5900
9225
9226 011100,5.RS,5.RT,5.RD,00011101001:MMI3:32::PSRAVW
9227 *r5900:
9228 {
9229   unsigned32 instruction = instruction_0;
9230   int destreg = ((instruction >> 11) & 0x0000001F);
9231   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9232   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9233   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9234   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9235   {
9236     GPR_SD(destreg,0) = SIGNEXTEND( (RT_SW (0) >> (RS_UB(0) & 0x1F)), 32-(RS_UB(0) & 0x1F) );
9237     GPR_SD(destreg,1) = SIGNEXTEND( (RT_SW (2) >> (RS_UB(8) & 0x1F)), 32-(RS_UB(8) & 0x1F) );
9238   }
9239 }
9240
9241 // end-sanitize-r5900
9242 // start-sanitize-r5900
9243
9244 01110000000,5.RT,5.RD,5.SHIFT,111111:MMINORM:32::PSRAW
9245 *r5900:
9246 {
9247   unsigned32 instruction = instruction_0;
9248   int op1 = ((instruction >> 6) & 0x0000001F);
9249   int destreg = ((instruction >> 11) & 0x0000001F);
9250   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9251   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9252   {
9253     int shift_by = op1 & (32-1);
9254     int i;
9255     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9256       GPR_SW(destreg,i) = SIGNEXTEND( (RT_SW(i) >> shift_by), (32-shift_by) );
9257   }
9258 }
9259
9260 // end-sanitize-r5900
9261 // start-sanitize-r5900
9262
9263 01110000000,5.RT,5.RD,5.SHIFT,110110:MMINORM:32::PSRLH
9264 *r5900:
9265 {
9266   unsigned32 instruction = instruction_0;
9267   int op1 = ((instruction >> 6) & 0x0000001F);
9268   int destreg = ((instruction >> 11) & 0x0000001F);
9269   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9270   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9271   {
9272     int shift_by = op1 & (16-1);
9273     int i;
9274     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9275       GPR_UH(destreg,i) = (RT_UH(i) >> shift_by);
9276   }
9277 }
9278
9279 // end-sanitize-r5900
9280 // start-sanitize-r5900
9281
9282 011100,5.RS,5.RT,5.RD,00011001001:MMI2:32::PSRLVW
9283 *r5900:
9284 {
9285   unsigned32 instruction = instruction_0;
9286   int destreg = ((instruction >> 11) & 0x0000001F);
9287   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9288   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9289   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9290   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9291   {
9292     GPR_UD(destreg,0) = SIGNEXTEND ( RT_UW(0) >> (RS_UB(0) & 0x1F), 31);
9293     GPR_UD(destreg,1) = SIGNEXTEND ( RT_UW(2) >> (RS_UB(8) & 0x1F), 31);
9294   }
9295 }
9296
9297 // end-sanitize-r5900
9298 // start-sanitize-r5900
9299
9300 01110000000,5.RT,5.RD,5.SHIFT,111110:MMINORM:32::PSRLW
9301 *r5900:
9302 {
9303   unsigned32 instruction = instruction_0;
9304   int op1 = ((instruction >> 6) & 0x0000001F);
9305   int destreg = ((instruction >> 11) & 0x0000001F);
9306   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9307   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9308   {
9309     int shift_by = op1 & (32-1);
9310     int i;
9311     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9312       GPR_UW(destreg,i) = (RT_UW(i) >> shift_by);
9313   }
9314 }
9315
9316 // end-sanitize-r5900
9317 // start-sanitize-r5900
9318
9319 011100,5.RS,5.RT,5.RD,01001001000:MMI0:32::PSUBB
9320 *r5900:
9321 {
9322   unsigned32 instruction = instruction_0;
9323   int destreg = ((instruction >> 11) & 0x0000001F);
9324   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9325   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9326   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9327   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9328   {
9329     int i;
9330     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9331       {
9332         int s = RS_SB(i);
9333         int t = RT_SB(i);
9334         int r = s - t;
9335         GPR_SB(destreg,i) = r;
9336       }
9337   }
9338 }
9339
9340 // end-sanitize-r5900
9341 // start-sanitize-r5900
9342
9343 011100,5.RS,5.RT,5.RD,00101001000:MMI0:32::PSUBH
9344 *r5900:
9345 {
9346   unsigned32 instruction = instruction_0;
9347   int destreg = ((instruction >> 11) & 0x0000001F);
9348   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9349   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9350   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9351   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9352   {
9353     int i;
9354     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9355       {
9356         int s = RS_SH(i);
9357         int t = RT_SH(i);
9358         int r = s - t;
9359         GPR_SH(destreg,i) = r;
9360       }
9361   }
9362 }
9363
9364 // end-sanitize-r5900
9365 // start-sanitize-r5900
9366
9367 011100,5.RS,5.RT,5.RD,11001001000:MMI0:32::PSUBSB
9368 *r5900:
9369 {
9370   unsigned32 instruction = instruction_0;
9371   int destreg = ((instruction >> 11) & 0x0000001F);
9372   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9373   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9374   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9375   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9376   {
9377     int i;
9378     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9379       {
9380         int s = RS_SB(i);
9381         int t = RT_SB(i);
9382         int r = s - t;
9383         if (r > 127)
9384           GPR_SB(destreg,i) = 127;
9385         else if (r < -128)
9386           GPR_SB(destreg,i) = -128;
9387         else
9388           GPR_SB(destreg,i) = r;
9389       }
9390   }
9391 }
9392
9393 // end-sanitize-r5900
9394 // start-sanitize-r5900
9395
9396 011100,5.RS,5.RT,5.RD,10101001000:MMI0:32::PSUBSH
9397 *r5900:
9398 {
9399   unsigned32 instruction = instruction_0;
9400   int destreg = ((instruction >> 11) & 0x0000001F);
9401   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9402   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9403   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9404   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9405   {
9406     int i;
9407     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9408       {
9409         int s = RS_SH(i);
9410         int t = RT_SH(i);
9411         int r = s - t;
9412         if (r > 32767)
9413           GPR_SH(destreg,i) = 32767;
9414         else if (r < -32768)
9415           GPR_SH(destreg,i) = -32768;
9416         else
9417           GPR_SH(destreg,i) = r;
9418       }
9419   }
9420 }
9421
9422 // end-sanitize-r5900
9423 // start-sanitize-r5900
9424
9425 011100,5.RS,5.RT,5.RD,10001001000:MMI0:32::PSUBSW
9426 *r5900:
9427 {
9428   unsigned32 instruction = instruction_0;
9429   int destreg = ((instruction >> 11) & 0x0000001F);
9430   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9431   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9432   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9433   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9434   {
9435     int i;
9436     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9437       {
9438         signed64 s = RS_SW(i);
9439         signed64 t = RT_SW(i);
9440         signed64 r = s - t;
9441         if (r > (int)0x7FFFFFFF)
9442           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
9443         else if (r < (int)0x80000000)
9444           GPR_SW(destreg,i) = (int)0x80000000;
9445         else
9446           GPR_SW(destreg,i) = r;
9447       }
9448   }
9449 }
9450
9451 // end-sanitize-r5900
9452 // start-sanitize-r5900
9453
9454 011100,5.RS,5.RT,5.RD,11001101000:MMI1:32::PSUBUB
9455 *r5900:
9456 {
9457   unsigned32 instruction = instruction_0;
9458   int destreg = ((instruction >> 11) & 0x0000001F);
9459   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9460   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9461   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9462   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9463   {
9464     int i;
9465     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9466       {
9467         unsigned int s = RS_UB(i);
9468         unsigned int t = RT_UB(i);
9469         unsigned int r = s - t;
9470         if (r > 0xFF)
9471           GPR_UB(destreg,i) = 0;
9472         else
9473           GPR_UB(destreg,i) = r;
9474       }
9475   }
9476 }
9477
9478 // end-sanitize-r5900
9479 // start-sanitize-r5900
9480
9481 011100,5.RS,5.RT,5.RD,10101101000:MMI1:32::PSUBUH
9482 *r5900:
9483 {
9484   unsigned32 instruction = instruction_0;
9485   int destreg = ((instruction >> 11) & 0x0000001F);
9486   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9487   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9488   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9489   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9490   {
9491     int i;
9492     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9493       {
9494         unsigned int s = RS_UH(i);
9495         unsigned int t = RT_UH(i);
9496         unsigned int r = s - t;
9497         if (r > 0xFFFF)
9498           GPR_UH(destreg,i) = 0;
9499         else
9500           GPR_UH(destreg,i) = r;
9501       }
9502   }
9503 }
9504
9505 // end-sanitize-r5900
9506 // start-sanitize-r5900
9507
9508 011100,5.RS,5.RT,5.RD,10001101000:MMI1:32::PSUBUW
9509 *r5900:
9510 {
9511   unsigned32 instruction = instruction_0;
9512   int destreg = ((instruction >> 11) & 0x0000001F);
9513   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9514   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9515   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9516   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9517   {
9518     int i;
9519     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9520       {
9521         unsigned64 s = RS_UW(i);
9522         unsigned64 t = RT_UW(i);
9523         unsigned64 r = s - t;
9524         if (r > 0xFFFFFFFF)
9525           GPR_UW(destreg,i) = 0;
9526         else
9527           GPR_UW(destreg,i) = r;
9528       }
9529   }
9530 }
9531
9532 // end-sanitize-r5900
9533 // start-sanitize-r5900
9534
9535 011100,5.RS,5.RT,5.RD,00001001000:MMI0:32::PSUBW
9536 *r5900:
9537 {
9538   unsigned32 instruction = instruction_0;
9539   int destreg = ((instruction >> 11) & 0x0000001F);
9540   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9541   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9542   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9543   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9544   {
9545     int i;
9546     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9547       {
9548         signed64 s = RS_SW(i);
9549         signed64 t = RT_SW(i);
9550         signed64 r = s - t;
9551         GPR_SW(destreg,i) = r;
9552       }
9553   }
9554 }
9555
9556 // end-sanitize-r5900
9557 // start-sanitize-r5900
9558
9559 011100,5.RS,5.RT,5.RD,10011001001:MMI2:32::PXOR
9560 *r5900:
9561 {
9562   unsigned32 instruction = instruction_0;
9563   int destreg = ((instruction >> 11) & 0x0000001F);
9564   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9565   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9566   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9567   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9568   {
9569     int i;
9570     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9571       GPR_UW(destreg,i) = (RS_UW(i) ^ RT_UW(i));
9572   }
9573 }
9574
9575 // end-sanitize-r5900
9576 // start-sanitize-r5900
9577
9578 011100,5.RS,5.RT,5.RD,11011101000:MMI1:32::QFSRV
9579 *r5900:
9580 {
9581   unsigned32 instruction = instruction_0;
9582   int destreg = ((instruction >> 11) & 0x0000001F);
9583   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9584   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9585   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9586   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9587   {
9588     int bytes = (SA / 8) % 16;
9589     if (SA % 8)
9590       SignalException(ReservedInstruction,instruction);
9591     else
9592       {
9593         int i;
9594         for(i=0;i<(16-bytes);i++)
9595           GPR_SB(destreg,i) = RT_SB(bytes+i);
9596         for(;i<16;i++)
9597           GPR_SB(destreg,i) = RS_SB(i-(16-bytes));
9598       }
9599   }
9600 }
9601
9602 // end-sanitize-r5900
9603 // start-sanitize-r5900
9604
9605 011111,5.RS,5.RT,16.OFFSET:NORMAL:128::SQ
9606 *r5900:
9607 {
9608   unsigned32 instruction = instruction_0;
9609   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
9610   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9611   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9612   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9613   {
9614     unsigned64 vaddr = ((unsigned64)op1 + offset);
9615     unsigned64 paddr;
9616     int uncached;
9617     if ((vaddr & 15) != 0)
9618       SignalExceptionAddressStore();
9619     else
9620       {
9621         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
9622           {
9623             unsigned64 memval = 0;
9624             unsigned64 memval1 = 0;
9625             memval  = rsigned_word;
9626             memval1 = rsigned_word1;
9627             {
9628               StoreMemory(uncached,AccessLength_QUADWORD,memval,memval1,paddr,vaddr,isREAL);
9629             }
9630           }
9631       }
9632   }
9633 }
9634
9635 // end-sanitize-r5900
9636 \f
9637 // start-sanitize-cygnus-never
9638
9639 // // FIXME FIXME FIXME What is this instruction?
9640 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
9641 // *mipsI:
9642 // *mipsII:
9643 // *mipsIII:
9644 // *mipsIV:
9645 // // start-sanitize-r5900
9646 // *r5900:
9647 // // end-sanitize-r5900
9648 // *r3900:
9649 // // start-sanitize-tx19
9650 // *tx19:
9651 // // end-sanitize-tx19
9652 // {
9653 //   unsigned32 instruction = instruction_0;
9654 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
9655 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9656 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9657 //   {
9658 //     if (CoProcPresent(3))
9659 //       SignalException(CoProcessorUnusable);
9660 //     else
9661 //       SignalException(ReservedInstruction,instruction);
9662 //   }
9663 // }
9664
9665 // end-sanitize-cygnus-never
9666 // start-sanitize-cygnus-never
9667
9668 // // FIXME FIXME FIXME What is this?
9669 // 11100,******,00001:RR:16::SDBBP
9670 // *mips16:
9671 // {
9672 //   unsigned32 instruction = instruction_0;
9673 //   if (have_extendval)
9674 //     SignalException (ReservedInstruction, instruction);
9675 //   {
9676 //     SignalException(DebugBreakPoint,instruction);
9677 //   }
9678 // }
9679
9680 // end-sanitize-cygnus-never
9681 // start-sanitize-cygnus-never
9682
9683 // // FIXME FIXME FIXME What is this?
9684 // 000000,********************,001110:SPECIAL:32::SDBBP
9685 // *r3900:
9686 // {
9687 //   unsigned32 instruction = instruction_0;
9688 //   {
9689 //     SignalException(DebugBreakPoint,instruction);
9690 //   }
9691 // }
9692
9693 // end-sanitize-cygnus-never
9694 // start-sanitize-cygnus-never
9695
9696 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
9697 // // isn't yet reconized by this simulator.
9698 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
9699 // *vr4100:
9700 // {
9701 //   unsigned32 instruction = instruction_0;
9702 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9703 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9704 //   {
9705 //     CHECKHILO("Multiply-Add");
9706 //     {
9707 //       unsigned64 temp = (op1 * op2);
9708 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
9709 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
9710 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
9711 //     }
9712 //   }
9713 // }
9714
9715 // end-sanitize-cygnus-never
9716 // start-sanitize-cygnus-never
9717
9718 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
9719 // // isn't yet reconized by this simulator.
9720 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
9721 // *vr4100:
9722 // {
9723 //   unsigned32 instruction = instruction_0;
9724 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9725 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9726 //   {
9727 //     CHECKHILO("Multiply-Add");
9728 //     {
9729 //       unsigned64 temp = (op1 * op2);
9730 //       LO = LO + temp;
9731 //     }
9732 //   }
9733 // }
9734
9735 // start-sanitize-cygnus-never