sim/mips/mips.igen

   1 //    <insn> ::=
   2 //        <insn-word> { "+" <insn-word> }
   3 //        ":" <format-name>
   4 //        ":" <filter-flags>
   5 //        ":" <options>
   6 //        ":" <name>
   7 //        <nl>
   8 //        { <insn-model> }
   9 //        { <insn-mnemonic> }
  10 //        <code-block>
  11 //
  12
  13
  14 // IGEN config - mips16
  15 :option:16:insn-bit-size:16
  16 :option:16:hi-bit-nr:15
  17 :option:16:insn-specifying-widths:true
  18 :option:16:gen-delayed-branch:false
  19
  20 // IGEN config - mipsI..
  21 :option:32:insn-bit-size:32
  22 :option:32:hi-bit-nr:31
  23 :option:32:insn-specifying-widths:true
  24 :option:32:gen-delayed-branch:false
  25
  26
  27 // Generate separate simulators for each target
  28 // :option::multi-sim:true
  29
  30
  31 // Models known by this simulator
  32 :model::mipsI:mipsI:
  33 :model::mipsII:mipsII:
  34 :model::mipsIII:mipsIII:
  35 :model::mipsIV:mipsIV:
  36 :model::mips16:mips16:
  37 // start-sanitize-r5900
  38 :model::r5900:r5900:
  39 // end-sanitize-r5900
  40 :model::r3900:r3900:
  41 // start-sanitize-tx19
  42 :model::tx19:tx19:
  43 // end-sanitize-tx19
  44
  45
  46
  47 // Pseudo instructions known by IGEN
  48 :internal:::illegal
  49 {
  50   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  51                   (unsigned long) CIA);
  52   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  53 }
  54
  55
  56
  57
  58 //
  59 // MIPS Architecture:
  60 //
  61 //        CPU Instruction Set (mipsI - mipsIV)
  62 //
  63
  64
  65 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  66 "add r<RD>, r<RS>, r<RT>"
  67 *mipsI:
  68 *mipsII:
  69 *mipsIII:
  70 *mipsIV:
  71 // start-sanitize-r5900
  72 *r5900:
  73 // end-sanitize-r5900
  74 *r3900:
  75 // start-sanitize-tx19
  76 *tx19:
  77 // end-sanitize-tx19
  78 {
  79   ALU32_BEGIN (GPR[RS]);
  80   ALU32_ADD (GPR[RT]);
  81   ALU32_END (GPR[RD]);
  82 }
  83
  84
  85 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
  86 "addi r<RT>, r<RS>, IMMEDIATE"
  87 *mipsI:
  88 *mipsII:
  89 *mipsIII:
  90 *mipsIV:
  91 // start-sanitize-r5900
  92 *r5900:
  93 // end-sanitize-r5900
  94 *r3900:
  95 // start-sanitize-tx19
  96 *tx19:
  97 // end-sanitize-tx19
  98 {
  99   ALU32_BEGIN (GPR[RS]);
 100   ALU32_ADD (EXTEND16 (IMMEDIATE));
 101   ALU32_END (GPR[RT]);
 102 }
 103
 104
 105 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 106 "add r<RT>, r<RS>, IMMEDIATE"
 107 *mipsI:
 108 *mipsII:
 109 *mipsIII:
 110 *mipsIV:
 111 // start-sanitize-r5900
 112 *r5900:
 113 // end-sanitize-r5900
 114 *r3900:
 115 // start-sanitize-tx19
 116 *tx19:
 117 // end-sanitize-tx19
 118 {
 119   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 120   GPR[RT] = EXTEND32 (temp);
 121 }
 122
 123
 124 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 125 *mipsI:
 126 *mipsII:
 127 *mipsIII:
 128 *mipsIV:
 129 // start-sanitize-r5900
 130 *r5900:
 131 // end-sanitize-r5900
 132 *r3900:
 133 // start-sanitize-tx19
 134 *tx19:
 135 // end-sanitize-tx19
 136 {
 137   signed32 temp = GPR[RS] + GPR[RT];
 138   GPR[RD] = EXTEND32 (temp);
 139 }
 140
 141
 142 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 143 "and r<RD>, r<RS>, r<RT>"
 144 *mipsI:
 145 *mipsII:
 146 *mipsIII:
 147 *mipsIV:
 148 // start-sanitize-r5900
 149 *r5900:
 150 // end-sanitize-r5900
 151 *r3900:
 152 // start-sanitize-tx19
 153 *tx19:
 154 // end-sanitize-tx19
 155 {
 156   GPR[RD] = GPR[RS] & GPR[RT];
 157 }
 158
 159
 160 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 161 "and r<RT>, r<RS>, IMMEDIATE"
 162 *mipsI:
 163 *mipsII:
 164 *mipsIII:
 165 // start-sanitize-r5900
 166 *r5900:
 167 // end-sanitize-r5900
 168 *r3900:
 169 // start-sanitize-tx19
 170 *tx19:
 171 // end-sanitize-tx19
 172 {
 173   GPR[RT] = GPR[RS] & IMMEDIATE;
 174 }
 175
 176
 177 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 178 "beq r<RS>, r<RT>, OFFSET"
 179 *mipsI:
 180 *mipsII:
 181 *mipsIII:
 182 *mipsIV:
 183 // start-sanitize-r5900
 184 *r5900:
 185 // end-sanitize-r5900
 186 *r3900:
 187 // start-sanitize-tx19
 188 *tx19:
 189 // end-sanitize-tx19
 190 {
 191   address_word offset = EXTEND16 (OFFSET) << 2;
 192   if (GPR[RS] == GPR[RT])
 193     DELAY_SLOT (PC + offset);
 194 }
 195
 196
 197 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 198 "beql r<RS>, r<RT>, <OFFSET>"
 199 *mipsII:
 200 *mipsIII:
 201 *mipsIV:
 202 // start-sanitize-r5900
 203 *r5900:
 204 // end-sanitize-r5900
 205 *r3900:
 206 // start-sanitize-tx19
 207 *tx19:
 208 // end-sanitize-tx19
 209 {
 210   address_word offset = EXTEND16 (OFFSET) << 2;
 211   if (GPR[RS] == GPR[RT])
 212     DELAY_SLOT (PC + offset);
 213   else
 214     NULLIFY_NEXT_INSTRUCTION ();
 215 }
 216
 217
 218 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 219 "bgez r<RS>, <OFFSET>"
 220 *mipsI:
 221 *mipsII:
 222 *mipsIII:
 223 *mipsIV:
 224 // start-sanitize-r5900
 225 *r5900:
 226 // end-sanitize-r5900
 227 *r3900:
 228 // start-sanitize-tx19
 229 *tx19:
 230 // end-sanitize-tx19
 231 {
 232   address_word offset = EXTEND16 (OFFSET) << 2;
 233   if (GPR[RS] >= 0)
 234     DELAY_SLOT (PC + offset);
 235 }
 236
 237
 238 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 239 "bgezal r<RS>, <OFFSET>"
 240 *mipsI:
 241 *mipsII:
 242 *mipsIII:
 243 *mipsIV:
 244 // start-sanitize-r5900
 245 *r5900:
 246 // end-sanitize-r5900
 247 *r3900:
 248 // start-sanitize-tx19
 249 *tx19:
 250 // end-sanitize-tx19
 251 {
 252   address_word offset = EXTEND16 (OFFSET) << 2;
 253   RA = (CIA + 8);
 254   if (GPR[RS] >= 0)
 255     DELAY_SLOT (PC + offset);
 256 }
 257
 258
 259 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 260 "bgezall r<RS>, <OFFSET>"
 261 *mipsII:
 262 *mipsIII:
 263 *mipsIV:
 264 // start-sanitize-r5900
 265 *r5900:
 266 // end-sanitize-r5900
 267 *r3900:
 268 // start-sanitize-tx19
 269 *tx19:
 270 // end-sanitize-tx19
 271 {
 272   address_word offset = EXTEND16 (OFFSET) << 2;
 273   RA = (CIA + 8);
 274   /* NOTE: The branch occurs AFTER the next instruction has been
 275      executed */
 276   if (GPR[RS] >= 0)
 277     DELAY_SLOT (PC + offset);
 278   else
 279     NULLIFY_NEXT_INSTRUCTION ();
 280 }
 281
 282
 283 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 284 "bgezl r<RS>, <OFFSET>"
 285 *mipsII:
 286 *mipsIII:
 287 *mipsIV:
 288 // start-sanitize-r5900
 289 *r5900:
 290 // end-sanitize-r5900
 291 *r3900:
 292 // start-sanitize-tx19
 293 *tx19:
 294 // end-sanitize-tx19
 295 {
 296   address_word offset = EXTEND16 (OFFSET) << 2;
 297   if (GPR[RS] >= 0)
 298     DELAY_SLOT (PC + offset);
 299   else
 300     NULLIFY_NEXT_INSTRUCTION ();
 301 }
 302
 303
 304 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 305 "bgtz r<RS>, <OFFSET>"
 306 *mipsI:
 307 *mipsII:
 308 *mipsIII:
 309 *mipsIV:
 310 // start-sanitize-r5900
 311 *r5900:
 312 // end-sanitize-r5900
 313 *r3900:
 314 // start-sanitize-tx19
 315 *tx19:
 316 // end-sanitize-tx19
 317 {
 318   address_word offset = EXTEND16 (OFFSET) << 2;
 319   if (GPR[RS] > 0)
 320     DELAY_SLOT (PC + offset);
 321 }
 322
 323
 324 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 325 "bgtzl r<RS>, <OFFSET>"
 326 *mipsII:
 327 *mipsIII:
 328 *mipsIV:
 329 // start-sanitize-r5900
 330 *r5900:
 331 // end-sanitize-r5900
 332 *r3900:
 333 // start-sanitize-tx19
 334 *tx19:
 335 // end-sanitize-tx19
 336 {
 337   address_word offset = EXTEND16 (OFFSET) << 2;
 338   /* NOTE: The branch occurs AFTER the next instruction has been
 339      executed */
 340   if (GPR[RS] > 0)
 341     DELAY_SLOT (PC + offset);
 342   else
 343     NULLIFY_NEXT_INSTRUCTION ();
 344 }
 345
 346
 347 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 348 "blez r<RS>, <OFFSET>"
 349 *mipsI:
 350 *mipsII:
 351 *mipsIII:
 352 *mipsIV:
 353 // start-sanitize-r5900
 354 *r5900:
 355 // end-sanitize-r5900
 356 *r3900:
 357 // start-sanitize-tx19
 358 *tx19:
 359 // end-sanitize-tx19
 360 {
 361   address_word offset = EXTEND16 (OFFSET) << 2;
 362   /* NOTE: The branch occurs AFTER the next instruction has been
 363      executed */
 364   if (GPR[RS] <= 0)
 365     DELAY_SLOT (PC + offset);
 366 }
 367
 368
 369 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 370 "bgezl r<RS>, <OFFSET>"
 371 *mipsII:
 372 *mipsIII:
 373 *mipsIV:
 374 // start-sanitize-r5900
 375 *r5900:
 376 // end-sanitize-r5900
 377 *r3900:
 378 // start-sanitize-tx19
 379 *tx19:
 380 // end-sanitize-tx19
 381 {
 382   address_word offset = EXTEND16 (OFFSET) << 2;
 383   if (GPR[RS] <= 0)
 384     DELAY_SLOT (PC + offset);
 385   else
 386     NULLIFY_NEXT_INSTRUCTION ();
 387 }
 388
 389
 390 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 391 "bltz r<RS>, <OFFSET>"
 392 *mipsI:
 393 *mipsII:
 394 *mipsIII:
 395 *mipsIV:
 396 // start-sanitize-r5900
 397 *r5900:
 398 // end-sanitize-r5900
 399 *r3900:
 400 // start-sanitize-tx19
 401 *tx19:
 402 // end-sanitize-tx19
 403 {
 404   address_word offset = EXTEND16 (OFFSET) << 2;
 405   if (GPR[RS] < 0)
 406     DELAY_SLOT (PC + offset);
 407 }
 408
 409
 410 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 411 "bltzal r<RS>, <OFFSET>"
 412 *mipsI:
 413 *mipsII:
 414 *mipsIII:
 415 *mipsIV:
 416 // start-sanitize-r5900
 417 *r5900:
 418 // end-sanitize-r5900
 419 *r3900:
 420 // start-sanitize-tx19
 421 *tx19:
 422 // end-sanitize-tx19
 423 {
 424   address_word offset = EXTEND16 (OFFSET) << 2;
 425   RA = (CIA + 8);
 426   /* NOTE: The branch occurs AFTER the next instruction has been
 427      executed */
 428   if (GPR[RS] < 0)
 429     DELAY_SLOT (PC + offset);
 430 }
 431
 432
 433 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 434 "bltzall r<RS>, <OFFSET>"
 435 *mipsII:
 436 *mipsIII:
 437 *mipsIV:
 438 // start-sanitize-r5900
 439 *r5900:
 440 // end-sanitize-r5900
 441 *r3900:
 442 // start-sanitize-tx19
 443 *tx19:
 444 // end-sanitize-tx19
 445 {
 446   address_word offset = EXTEND16 (OFFSET) << 2;
 447   RA = (CIA + 8);
 448   if (GPR[RS] < 0)
 449     DELAY_SLOT (PC + offset);
 450   else
 451     NULLIFY_NEXT_INSTRUCTION ();
 452 }
 453
 454
 455 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 456 "bltzl r<RS>, <OFFSET>"
 457 *mipsII:
 458 *mipsIII:
 459 *mipsIV:
 460 // start-sanitize-r5900
 461 *r5900:
 462 // end-sanitize-r5900
 463 *r3900:
 464 // start-sanitize-tx19
 465 *tx19:
 466 // end-sanitize-tx19
 467 {
 468   address_word offset = EXTEND16 (OFFSET) << 2;
 469   /* NOTE: The branch occurs AFTER the next instruction has been
 470      executed */
 471   if (GPR[RS] < 0)
 472     DELAY_SLOT (PC + offset);
 473   else
 474     NULLIFY_NEXT_INSTRUCTION ();
 475 }
 476
 477
 478 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 479 "bne r<RS>, r<RT>, <OFFSET>"
 480 *mipsI:
 481 *mipsII:
 482 *mipsIII:
 483 *mipsIV:
 484 // start-sanitize-r5900
 485 *r5900:
 486 // end-sanitize-r5900
 487 *r3900:
 488 // start-sanitize-tx19
 489 *tx19:
 490 // end-sanitize-tx19
 491 {
 492   address_word offset = EXTEND16 (OFFSET) << 2;
 493   if (GPR[RS] != GPR[RT])
 494     DELAY_SLOT (PC + offset);
 495 }
 496
 497
 498 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 499 "bnel r<RS>, r<RT>, <OFFSET>"
 500 *mipsII:
 501 *mipsIII:
 502 *mipsIV:
 503 // start-sanitize-r5900
 504 *r5900:
 505 // end-sanitize-r5900
 506 *r3900:
 507 // start-sanitize-tx19
 508 *tx19:
 509 // end-sanitize-tx19
 510 {
 511   address_word offset = EXTEND16 (OFFSET) << 2;
 512   if (GPR[RS] != GPR[RT])
 513     DELAY_SLOT (PC + offset);
 514   else
 515     NULLIFY_NEXT_INSTRUCTION ();
 516 }
 517
 518
 519 000000,20.CODE,001101:SPECIAL:32::BREAK
 520 "break"
 521 *mipsI:
 522 *mipsII:
 523 *mipsIII:
 524 *mipsIV:
 525 // start-sanitize-r5900
 526 *r5900:
 527 // end-sanitize-r5900
 528 *r3900:
 529 // start-sanitize-tx19
 530 *tx19:
 531 // end-sanitize-tx19
 532 {
 533   SignalException(BreakPoint, instruction_0);
 534 }
 535
 536
 537 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 538 "cop<ZZ> <COP_FUN>"
 539 *mipsI:
 540 *mipsII:
 541 *mipsIII:
 542 *mipsIV:
 543 // start-sanitize-r5900
 544 *r5900:
 545 // end-sanitize-r5900
 546 *r3900:
 547 // start-sanitize-tx19
 548 *tx19:
 549 // end-sanitize-tx19
 550 {
 551   DecodeCoproc (instruction_0);
 552 }
 553
 554
 555 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 556 "dadd r<RD>, r<RS>, r<RT>"
 557 *mipsIII:
 558 *mipsIV:
 559 // start-sanitize-r5900
 560 *r5900:
 561 // end-sanitize-r5900
 562 *r3900:
 563 // start-sanitize-tx19
 564 *tx19:
 565 // end-sanitize-tx19
 566 {
 567   ALU64_BEGIN (GPR[RS]);
 568   ALU64_ADD (GPR[RT]);
 569   ALU64_END (GPR[RT]);
 570 }
 571
 572
 573 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 574 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 575 *mipsIII:
 576 *mipsIV:
 577 // start-sanitize-r5900
 578 *r5900:
 579 // end-sanitize-r5900
 580 *r3900:
 581 // start-sanitize-tx19
 582 *tx19:
 583 // end-sanitize-tx19
 584 {
 585   ALU64_BEGIN (GPR[RS]);
 586   ALU64_ADD (EXTEND16 (IMMEDIATE));
 587   ALU64_END (GPR[RT]);
 588 }
 589
 590
 591 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 592 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 593 *mipsIII:
 594 *mipsIV:
 595 // start-sanitize-r5900
 596 *r5900:
 597 // end-sanitize-r5900
 598 *r3900:
 599 // start-sanitize-tx19
 600 *tx19:
 601 // end-sanitize-tx19
 602 {
 603   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 604 }
 605
 606
 607 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 608 "daddu r<RD>, r<RS>, r<RT>"
 609 *mipsIII:
 610 *mipsIV:
 611 // start-sanitize-r5900
 612 *r5900:
 613 // end-sanitize-r5900
 614 *r3900:
 615 // start-sanitize-tx19
 616 *tx19:
 617 // end-sanitize-tx19
 618 {
 619   GPR[RD] = GPR[RS] + GPR[RT];
 620 }
 621
 622
 623 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 624 "ddiv r<RS>, r<RT>"
 625 *mipsIII:
 626 *mipsIV:
 627 // start-sanitize-r5900
 628 *r5900:
 629 // end-sanitize-r5900
 630 *r3900:
 631 // start-sanitize-tx19
 632 *tx19:
 633 // end-sanitize-tx19
 634 {
 635   CHECKHILO ("Division");
 636   {
 637     signed64 n = GPR[RS];
 638     signed64 d = GPR[RT];
 639     if (d == 0)
 640       {
 641         LO = SIGNED64 (0x8000000000000000);
 642         HI = 0;
 643       }
 644     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 645       {
 646         LO = SIGNED64 (0x8000000000000000);
 647         HI = 0;
 648       }
 649     else
 650       {
 651         LO = (n / d);
 652         HI = (n % d);
 653       }
 654   }
 655 }
 656
 657
 658
 659 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 660 "ddivu r<RS>, r<RT>"
 661 *mipsIII:
 662 *mipsIV:
 663 *r3900:
 664 // start-sanitize-tx19
 665 *tx19:
 666 // end-sanitize-tx19
 667 {
 668   CHECKHILO ("Division");
 669   {
 670     unsigned64 n = GPR[RS];
 671     unsigned64 d = GPR[RT];
 672     if (d == 0)
 673       {
 674         LO = SIGNED64 (0x8000000000000000);
 675         HI = 0;
 676       }
 677     else
 678       {
 679         LO = (n / d);
 680         HI = (n % d);
 681       }
 682   }
 683 }
 684
 685
 686 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 687 "div r<RS>, r<RT>"
 688 *mipsI:
 689 *mipsII:
 690 *mipsIII:
 691 *mipsIV:
 692 // start-sanitize-r5900
 693 *r5900:
 694 // end-sanitize-r5900
 695 *r3900:
 696 // start-sanitize-tx19
 697 *tx19:
 698 // end-sanitize-tx19
 699 {
 700   CHECKHILO("Division");
 701   {
 702     signed32 n = GPR[RS];
 703     signed32 d = GPR[RT];
 704     if (d == 0)
 705       {
 706         LO = EXTEND32 (0x80000000);
 707         HI = EXTEND32 (0);
 708       }
 709     else if (d == -1 && d == 0x80000000)
 710       {
 711         LO = EXTEND32 (0x80000000);
 712         HI = EXTEND32 (0);
 713       }
 714     else
 715       {
 716         LO = EXTEND32 (n / d);
 717         HI = EXTEND32 (n % d);
 718       }
 719   }
 720 }
 721
 722
 723 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 724 "divu r<RS>, r<RT>"
 725 *mipsI:
 726 *mipsII:
 727 *mipsIII:
 728 *mipsIV:
 729 // start-sanitize-r5900
 730 *r5900:
 731 // end-sanitize-r5900
 732 *r3900:
 733 // start-sanitize-tx19
 734 *tx19:
 735 // end-sanitize-tx19
 736 {
 737   CHECKHILO ("Division");
 738   {
 739     unsigned32 n = GPR[RS];
 740     unsigned32 d = GPR[RT];
 741     if (d == 0)
 742       {
 743         LO = EXTEND32 (0x80000000);
 744         HI = EXTEND32 (0);
 745       }
 746    else
 747      {
 748        LO = EXTEND32 (n / d);
 749        HI = EXTEND32 (n % d);
 750      }
 751   }
 752 }
 753
 754
 755 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 756 "dmult r<RS>, r<RT>"
 757 *mipsIII:
 758 *mipsIV:
 759 *r3900:
 760 // start-sanitize-tx19
 761 *tx19:
 762 // end-sanitize-tx19
 763 {
 764   CHECKHILO ("Multiplication");
 765   {
 766     signed64 op1 = GPR[RS];
 767     signed64 op2 = GPR[RT];
 768     unsigned64 lo;
 769     unsigned64 hi;
 770     unsigned64 m00;
 771     unsigned64 m01;
 772     unsigned64 m10;
 773     unsigned64 m11;
 774     unsigned64 mid;
 775     int sign = 0;
 776     /* make it unsigned */
 777     if (op1 < 0)
 778       {
 779         op1 = - op1;
 780         ++sign;
 781       }
 782     if (op2 < 0)
 783       {
 784         op2 = - op2;
 785         ++sign;
 786       }
 787     /* multuply out the 4 sub products */
 788     m00 = (VL4_8 (op1) * VL4_8 (op2));
 789     m10 = (VH4_8 (op1) * VL4_8 (op2));
 790     m01 = (VL4_8 (op1) * VH4_8 (op2));
 791     m11 = (VH4_8 (op1) * VH4_8 (op2));
 792     /* add the products */
 793     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 794     lo = U8_4 (mid, m00);
 795     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 796     /* save the result */
 797     if (sign & 1)
 798       {
 799         LO = -lo;
 800         if (lo == 0)
 801           HI = -hi;
 802         else
 803           HI = -hi - 1;
 804       }
 805     else
 806       {
 807         LO = lo;
 808         HI = hi;
 809       }
 810   }
 811 }
 812
 813
 814 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 815 "dmultu r<RS>, r<RT>"
 816 *mipsIII:
 817 *mipsIV:
 818 *r3900:
 819 // start-sanitize-tx19
 820 *tx19:
 821 // end-sanitize-tx19
 822 {
 823   CHECKHILO ("Multiplication");
 824   {
 825     signed64 op1 = GPR[RS];
 826     signed64 op2 = GPR[RT];
 827     unsigned64 lo;
 828     unsigned64 hi;
 829     unsigned64 m00;
 830     unsigned64 m01;
 831     unsigned64 m10;
 832     unsigned64 m11;
 833     unsigned64 mid;
 834     /* multuply out the 4 sub products */
 835     m00 = (VL4_8 (op1) * VL4_8 (op2));
 836     m10 = (VH4_8 (op1) * VL4_8 (op2));
 837     m01 = (VL4_8 (op1) * VH4_8 (op2));
 838     m11 = (VH4_8 (op1) * VH4_8 (op2));
 839     /* add the products */
 840     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 841     lo = U8_4 (mid, m00);
 842     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 843     /* save the result */
 844     LO = lo;
 845     HI = hi;
 846   }
 847 }
 848
 849
 850 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 851 "dsll r<RD>, r<RT>, <SA>"
 852 *mipsIII:
 853 *mipsIV:
 854 // start-sanitize-r5900
 855 *r5900:
 856 // end-sanitize-r5900
 857 *r3900:
 858 // start-sanitize-tx19
 859 *tx19:
 860 // end-sanitize-tx19
 861 {
 862   int s = SA;
 863   GPR[RD] = GPR[RT] << s;
 864 }
 865
 866
 867 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
 868 "dsll32 r<RD>, r<RT>, <SA>"
 869 *mipsIII:
 870 *mipsIV:
 871 // start-sanitize-r5900
 872 *r5900:
 873 // end-sanitize-r5900
 874 *r3900:
 875 // start-sanitize-tx19
 876 *tx19:
 877 // end-sanitize-tx19
 878 {
 879   int s = 32 + SA;
 880   GPR[RD] = GPR[RT] << s;
 881 }
 882
 883
 884 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 885 "dsllv r<RD>, r<RT>, r<RS>"
 886 *mipsIII:
 887 *mipsIV:
 888 // start-sanitize-r5900
 889 *r5900:
 890 // end-sanitize-r5900
 891 *r3900:
 892 // start-sanitize-tx19
 893 *tx19:
 894 // end-sanitize-tx19
 895 {
 896   int s = MASKED64 (GPR[RS], 5, 0);
 897   GPR[RD] = GPR[RT] << s;
 898 }
 899
 900
 901 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
 902 "dsra r<RD>, r<RT>, <SA>"
 903 *mipsIII:
 904 *mipsIV:
 905 // start-sanitize-r5900
 906 *r5900:
 907 // end-sanitize-r5900
 908 *r3900:
 909 // start-sanitize-tx19
 910 *tx19:
 911 // end-sanitize-tx19
 912 {
 913   int s = SA;
 914   GPR[RD] = ((signed64) GPR[RT]) >> s;
 915 }
 916
 917
 918 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
 919 "dsra32 r<RT>, r<RD>, <SA>"
 920 *mipsIII:
 921 *mipsIV:
 922 // start-sanitize-r5900
 923 *r5900:
 924 // end-sanitize-r5900
 925 *r3900:
 926 // start-sanitize-tx19
 927 *tx19:
 928 // end-sanitize-tx19
 929 {
 930   int s = 32 + SA;
 931   GPR[RD] = ((signed64) GPR[RT]) >> s;
 932 }
 933
 934
 935 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
 936 "dsra32 r<RT>, r<RD>, r<RS>"
 937 *mipsIII:
 938 *mipsIV:
 939 // start-sanitize-r5900
 940 *r5900:
 941 // end-sanitize-r5900
 942 *r3900:
 943 // start-sanitize-tx19
 944 *tx19:
 945 // end-sanitize-tx19
 946 {
 947   int s = MASKED64 (GPR[RS], 5, 0);
 948   GPR[RD] = ((signed64) GPR[RT]) >> s;
 949 }
 950
 951
 952 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
 953 "dsrav r<RD>, r<RT>, <SA>"
 954 *mipsIII:
 955 *mipsIV:
 956 // start-sanitize-r5900
 957 *r5900:
 958 // end-sanitize-r5900
 959 *r3900:
 960 // start-sanitize-tx19
 961 *tx19:
 962 // end-sanitize-tx19
 963 {
 964   int s = SA;
 965   GPR[RD] = (unsigned64) GPR[RT] >> s;
 966 }
 967
 968
 969 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
 970 "dsrl32 r<RD>, r<RT>, <SA>"
 971 *mipsIII:
 972 *mipsIV:
 973 // start-sanitize-r5900
 974 *r5900:
 975 // end-sanitize-r5900
 976 *r3900:
 977 // start-sanitize-tx19
 978 *tx19:
 979 // end-sanitize-tx19
 980 {
 981   int s = 32 + SA;
 982   GPR[RD] = (unsigned64) GPR[RT] >> s;
 983 }
 984
 985
 986 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
 987 "dsrl32 r<RD>, r<RT>, r<RS>"
 988 *mipsIII:
 989 *mipsIV:
 990 // start-sanitize-r5900
 991 *r5900:
 992 // end-sanitize-r5900
 993 *r3900:
 994 // start-sanitize-tx19
 995 *tx19:
 996 // end-sanitize-tx19
 997 {
 998   int s = MASKED64 (GPR[RS], 5, 0);
 999   GPR[RD] = (unsigned64) GPR[RT] >> s;
1000 }
1001
1002
1003 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1004 "dsub r<RD>, r<RS>, r<RT>"
1005 *mipsIII:
1006 *mipsIV:
1007 // start-sanitize-r5900
1008 *r5900:
1009 // end-sanitize-r5900
1010 *r3900:
1011 // start-sanitize-tx19
1012 *tx19:
1013 // end-sanitize-tx19
1014 {
1015   ALU64_BEGIN (GPR[RS]);
1016   ALU64_SUB (GPR[RT]);
1017   ALU64_END (GPR[RD]);
1018 }
1019
1020
1021 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1022 "dsubu r<RD>, r<RS>, r<RT>"
1023 *mipsIII:
1024 *mipsIV:
1025 // start-sanitize-r5900
1026 *r5900:
1027 // end-sanitize-r5900
1028 *r3900:
1029 // start-sanitize-tx19
1030 *tx19:
1031 // end-sanitize-tx19
1032 {
1033   GPR[RD] = GPR[RS] - GPR[RT];
1034 }
1035
1036
1037 000010,26.INSTR_INDEX:NORMAL:32::J
1038 "j <INSTR_INDEX>"
1039 *mipsI:
1040 *mipsII:
1041 *mipsIII:
1042 *mipsIV:
1043 // start-sanitize-r5900
1044 *r5900:
1045 // end-sanitize-r5900
1046 *r3900:
1047 // start-sanitize-tx19
1048 *tx19:
1049 // end-sanitize-tx19
1050 {
1051   /* NOTE: The region used is that of the delay slot NIA and NOT the
1052      current instruction */
1053   address_word region = (NIA & MASK (63, 28));
1054   DELAY_SLOT (region | (INSTR_INDEX << 2));
1055 }
1056
1057
1058 000011,26.INSTR_INDEX:NORMAL:32::JAL
1059 "jal <INSTR_INDEX>"
1060 *mipsI:
1061 *mipsII:
1062 *mipsIII:
1063 *mipsIV:
1064 // start-sanitize-r5900
1065 *r5900:
1066 // end-sanitize-r5900
1067 *r3900:
1068 // start-sanitize-tx19
1069 *tx19:
1070 // end-sanitize-tx19
1071 {
1072   /* NOTE: The region used is that of the delay slot and NOT the
1073      current instruction */
1074   address_word region = (NIA & MASK (63, 28));
1075   GPR[31] = CIA + 8;
1076   DELAY_SLOT (region | (INSTR_INDEX << 2));
1077 }
1078
1079
1080 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1081 "jalr r<RS>":RD == 31
1082 "jalr r<RD>, r<RS>"
1083 *mipsI:
1084 *mipsII:
1085 *mipsIII:
1086 *mipsIV:
1087 // start-sanitize-r5900
1088 *r5900:
1089 // end-sanitize-r5900
1090 *r3900:
1091 // start-sanitize-tx19
1092 *tx19:
1093 // end-sanitize-tx19
1094 {
1095   address_word temp = GPR[RS];
1096   GPR[RD] = CIA + 8;
1097   DELAY_SLOT (temp);
1098 }
1099
1100
1101 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1102 "jr r<RS>"
1103 *mipsI:
1104 *mipsII:
1105 *mipsIII:
1106 *mipsIV:
1107 // start-sanitize-r5900
1108 *r5900:
1109 // end-sanitize-r5900
1110 *r3900:
1111 // start-sanitize-tx19
1112 *tx19:
1113 // end-sanitize-tx19
1114 {
1115   DELAY_SLOT (GPR[RS]);
1116 }
1117
1118
1119 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1120 "lb r<RT>, <OFFSET>(r<BASE>)"
1121 *mipsI:
1122 *mipsII:
1123 *mipsIII:
1124 *mipsIV:
1125 // start-sanitize-r5900
1126 *r5900:
1127 // end-sanitize-r5900
1128 *r3900:
1129 // start-sanitize-tx19
1130 *tx19:
1131 // end-sanitize-tx19
1132 {
1133   unsigned32 instruction = instruction_0;
1134   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1135   int destreg = ((instruction >> 16) & 0x0000001F);
1136   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1137   {
1138     address_word vaddr = ((uword64)op1 + offset);
1139     address_word paddr;
1140     int uncached;
1141     {
1142       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1143         {
1144           uword64 memval = 0;
1145           uword64 memval1 = 0;
1146           uword64 mask = 0x7;
1147           unsigned int shift = 0;
1148           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1149           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1150           unsigned int byte;
1151           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1152           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1153           byte = ((vaddr & mask) ^ (bigend << shift));
1154           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1155         }
1156     }
1157   }
1158 }
1159
1160
1161 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1162 "lbu r<RT>, <OFFSET>(r<BASE>)"
1163 *mipsI:
1164 *mipsII:
1165 *mipsIII:
1166 *mipsIV:
1167 // start-sanitize-r5900
1168 *r5900:
1169 // end-sanitize-r5900
1170 *r3900:
1171 // start-sanitize-tx19
1172 *tx19:
1173 // end-sanitize-tx19
1174 {
1175   unsigned32 instruction = instruction_0;
1176   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1177   int destreg = ((instruction >> 16) & 0x0000001F);
1178   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1179   {
1180     address_word vaddr = ((unsigned64)op1 + offset);
1181     address_word paddr;
1182     int uncached;
1183     {
1184       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1185         {
1186           unsigned64 memval = 0;
1187           unsigned64 memval1 = 0;
1188           unsigned64 mask = 0x7;
1189           unsigned int shift = 0;
1190           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1191           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1192           unsigned int byte;
1193           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1194           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1195           byte = ((vaddr & mask) ^ (bigend << shift));
1196           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1197         }
1198     }
1199   }
1200 }
1201
1202
1203 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1204 "ld r<RT>, <OFFSET>(r<BASE>)"
1205 *mipsIII:
1206 *mipsIV:
1207 // start-sanitize-r5900
1208 *r5900:
1209 // end-sanitize-r5900
1210 *r3900:
1211 // start-sanitize-tx19
1212 *tx19:
1213 // end-sanitize-tx19
1214 {
1215   unsigned32 instruction = instruction_0;
1216   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1217   int destreg = ((instruction >> 16) & 0x0000001F);
1218   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1219   {
1220     address_word vaddr = ((unsigned64)op1 + offset);
1221     address_word paddr;
1222     int uncached;
1223     if ((vaddr & 7) != 0)
1224       SignalExceptionAddressLoad();
1225     else
1226       {
1227         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1228           {
1229             unsigned64 memval = 0;
1230             unsigned64 memval1 = 0;
1231             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1232             GPR[destreg] = memval;
1233           }
1234       }
1235   }
1236 }
1237
1238
1239 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1240 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1241 *mipsII:
1242 *mipsIII:
1243 *mipsIV:
1244 // start-sanitize-r5900
1245 *r5900:
1246 // end-sanitize-r5900
1247 *r3900:
1248 // start-sanitize-tx19
1249 *tx19:
1250 // end-sanitize-tx19
1251 {
1252   unsigned32 instruction = instruction_0;
1253   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1254   int destreg = ((instruction >> 16) & 0x0000001F);
1255   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1256   {
1257     address_word vaddr = ((unsigned64)op1 + offset);
1258     address_word paddr;
1259     int uncached;
1260     if ((vaddr & 7) != 0)
1261       SignalExceptionAddressLoad();
1262     else
1263       {
1264         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1265           {
1266             unsigned64 memval = 0;
1267             unsigned64 memval1 = 0;
1268             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1269             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1270           }
1271       }
1272   }
1273 }
1274
1275
1276 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1277 "ldl r<RT>, <OFFSET>(r<BASE>)"
1278 *mipsIII:
1279 *mipsIV:
1280 // start-sanitize-r5900
1281 *r5900:
1282 // end-sanitize-r5900
1283 *r3900:
1284 // start-sanitize-tx19
1285 *tx19:
1286 // end-sanitize-tx19
1287 {
1288   unsigned32 instruction = instruction_0;
1289   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1290   int destreg = ((instruction >> 16) & 0x0000001F);
1291   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1292   {
1293     address_word vaddr = ((unsigned64)op1 + offset);
1294     address_word paddr;
1295     int uncached;
1296     {
1297       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1298         {
1299           unsigned64 memval = 0;
1300           unsigned64 memval1 = 0;
1301           unsigned64 mask = 7;
1302           unsigned int reverse = (ReverseEndian ? mask : 0);
1303           unsigned int bigend = (BigEndianCPU ? mask : 0);
1304           int byte;
1305           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1306           byte = ((vaddr & mask) ^ bigend);
1307           if (!!ByteSwapMem)
1308             paddr &= ~mask;
1309           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1310           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1311         }
1312     }
1313   }
1314 }
1315
1316
1317 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1318 "ldr r<RT>, <OFFSET>(r<BASE>)"
1319 *mipsIII:
1320 *mipsIV:
1321 // start-sanitize-r5900
1322 *r5900:
1323 // end-sanitize-r5900
1324 *r3900:
1325 // start-sanitize-tx19
1326 *tx19:
1327 // end-sanitize-tx19
1328 {
1329   unsigned32 instruction = instruction_0;
1330   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1331   int destreg = ((instruction >> 16) & 0x0000001F);
1332   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1333   {
1334     address_word vaddr = ((unsigned64)op1 + offset);
1335     address_word paddr;
1336     int uncached;
1337     {
1338       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1339         {
1340           unsigned64 memval = 0;
1341           unsigned64 memval1 = 0;
1342           unsigned64 mask = 7;
1343           unsigned int reverse = (ReverseEndian ? mask : 0);
1344           unsigned int bigend = (BigEndianCPU ? mask : 0);
1345           int byte;
1346           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1347           byte = ((vaddr & mask) ^ bigend);
1348           if (!ByteSwapMem)
1349             paddr &= ~mask;
1350           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1351           {
1352             unsigned64 srcmask;
1353             if (byte == 0)
1354               srcmask = 0;
1355             else
1356               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1357             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1358           }
1359         }
1360     }
1361   }
1362 }
1363
1364
1365 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1366 "lh r<RT>, <OFFSET>(r<BASE>)"
1367 *mipsI:
1368 *mipsII:
1369 *mipsIII:
1370 *mipsIV:
1371 // start-sanitize-r5900
1372 *r5900:
1373 // end-sanitize-r5900
1374 *r3900:
1375 // start-sanitize-tx19
1376 *tx19:
1377 // end-sanitize-tx19
1378 {
1379   unsigned32 instruction = instruction_0;
1380   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1381   int destreg = ((instruction >> 16) & 0x0000001F);
1382   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1383   {
1384     address_word vaddr = ((unsigned64)op1 + offset);
1385     address_word paddr;
1386     int uncached;
1387     if ((vaddr & 1) != 0)
1388       SignalExceptionAddressLoad();
1389     else
1390       {
1391         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1392           {
1393             unsigned64 memval = 0;
1394             unsigned64 memval1 = 0;
1395             unsigned64 mask = 0x7;
1396             unsigned int shift = 1;
1397             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1398             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1399             unsigned int byte;
1400             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1401             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1402             byte = ((vaddr & mask) ^ (bigend << shift));
1403             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1404           }
1405       }
1406   }
1407 }
1408
1409
1410 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1411 "lhu r<RT>, <OFFSET>(r<BASE>)"
1412 *mipsI:
1413 *mipsII:
1414 *mipsIII:
1415 *mipsIV:
1416 // start-sanitize-r5900
1417 *r5900:
1418 // end-sanitize-r5900
1419 *r3900:
1420 // start-sanitize-tx19
1421 *tx19:
1422 // end-sanitize-tx19
1423 {
1424   unsigned32 instruction = instruction_0;
1425   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1426   int destreg = ((instruction >> 16) & 0x0000001F);
1427   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1428   {
1429     address_word vaddr = ((unsigned64)op1 + offset);
1430     address_word paddr;
1431     int uncached;
1432     if ((vaddr & 1) != 0)
1433       SignalExceptionAddressLoad();
1434     else
1435       {
1436         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1437           {
1438             unsigned64 memval = 0;
1439             unsigned64 memval1 = 0;
1440             unsigned64 mask = 0x7;
1441             unsigned int shift = 1;
1442             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1443             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1444             unsigned int byte;
1445             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1446             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1447             byte = ((vaddr & mask) ^ (bigend << shift));
1448             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1449           }
1450       }
1451   }
1452 }
1453
1454
1455 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1456 "ll r<RT>, <OFFSET>(r<BASE>)"
1457 *mipsII:
1458 *mipsIII:
1459 *mipsIV:
1460 // start-sanitize-r5900
1461 *r5900:
1462 // end-sanitize-r5900
1463 *r3900:
1464 // start-sanitize-tx19
1465 *tx19:
1466 // end-sanitize-tx19
1467 {
1468   unsigned32 instruction = instruction_0;
1469   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1470   int destreg = ((instruction >> 16) & 0x0000001F);
1471   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1472   {
1473     address_word vaddr = ((unsigned64)op1 + offset);
1474     address_word paddr;
1475     int uncached;
1476     if ((vaddr & 3) != 0)
1477       SignalExceptionAddressLoad();
1478     else
1479       {
1480         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1481           {
1482             unsigned64 memval = 0;
1483             unsigned64 memval1 = 0;
1484             unsigned64 mask = 0x7;
1485             unsigned int shift = 2;
1486             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1487             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1488             unsigned int byte;
1489             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1490             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1491             byte = ((vaddr & mask) ^ (bigend << shift));
1492             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1493             LLBIT = 1;
1494           }
1495       }
1496   }
1497 }
1498
1499
1500 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1501 "lld r<RT>, <OFFSET>(r<BASE>)"
1502 *mipsIII:
1503 *mipsIV:
1504 // start-sanitize-r5900
1505 *r5900:
1506 // end-sanitize-r5900
1507 *r3900:
1508 // start-sanitize-tx19
1509 *tx19:
1510 // end-sanitize-tx19
1511 {
1512   unsigned32 instruction = instruction_0;
1513   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1514   int destreg = ((instruction >> 16) & 0x0000001F);
1515   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1516   {
1517     address_word vaddr = ((unsigned64)op1 + offset);
1518     address_word paddr;
1519     int uncached;
1520     if ((vaddr & 7) != 0)
1521       SignalExceptionAddressLoad();
1522     else
1523       {
1524         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1525           {
1526             unsigned64 memval = 0;
1527             unsigned64 memval1 = 0;
1528             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1529             GPR[destreg] = memval;
1530             LLBIT = 1;
1531           }
1532       }
1533   }
1534 }
1535
1536
1537 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1538 "lui r<RT>, <IMMEDIATE>"
1539 *mipsI:
1540 *mipsII:
1541 *mipsIII:
1542 *mipsIV:
1543 // start-sanitize-r5900
1544 *r5900:
1545 // end-sanitize-r5900
1546 *r3900:
1547 // start-sanitize-tx19
1548 *tx19:
1549 // end-sanitize-tx19
1550 {
1551   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1552 }
1553
1554
1555 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1556 "lw r<RT>, <OFFSET>(r<BASE>)"
1557 *mipsI:
1558 *mipsII:
1559 *mipsIII:
1560 *mipsIV:
1561 // start-sanitize-r5900
1562 *r5900:
1563 // end-sanitize-r5900
1564 *r3900:
1565 // start-sanitize-tx19
1566 *tx19:
1567 // end-sanitize-tx19
1568 {
1569   unsigned32 instruction = instruction_0;
1570   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1571   int destreg = ((instruction >> 16) & 0x0000001F);
1572   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1573   {
1574     address_word vaddr = ((unsigned64)op1 + offset);
1575     address_word paddr;
1576     int uncached;
1577     if ((vaddr & 3) != 0)
1578       SignalExceptionAddressLoad();
1579     else
1580       {
1581         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1582           {
1583             unsigned64 memval = 0;
1584             unsigned64 memval1 = 0;
1585             unsigned64 mask = 0x7;
1586             unsigned int shift = 2;
1587             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1588             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1589             unsigned int byte;
1590             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1591             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1592             byte = ((vaddr & mask) ^ (bigend << shift));
1593             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1594           }
1595       }
1596   }
1597 }
1598
1599
1600 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1601 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1602 *mipsI:
1603 *mipsII:
1604 *mipsIII:
1605 *mipsIV:
1606 // start-sanitize-r5900
1607 *r5900:
1608 // end-sanitize-r5900
1609 *r3900:
1610 // start-sanitize-tx19
1611 *tx19:
1612 // end-sanitize-tx19
1613 {
1614   unsigned32 instruction = instruction_0;
1615   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1616   int destreg = ((instruction >> 16) & 0x0000001F);
1617   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1618   {
1619     address_word vaddr = ((unsigned64)op1 + offset);
1620     address_word paddr;
1621     int uncached;
1622     if ((vaddr & 3) != 0)
1623       SignalExceptionAddressLoad();
1624     else
1625       {
1626         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1627           {
1628             unsigned64 memval = 0;
1629             unsigned64 memval1 = 0;
1630             unsigned64 mask = 0x7;
1631             unsigned int shift = 2;
1632             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1633             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1634             unsigned int byte;
1635             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1636             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1637             byte = ((vaddr & mask) ^ (bigend << shift));
1638             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1639           }
1640       }
1641   }
1642 }
1643
1644
1645 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1646 "lwl r<RT>, <OFFSET>(r<BASE>)"
1647 *mipsI:
1648 *mipsII:
1649 *mipsIII:
1650 *mipsIV:
1651 // start-sanitize-r5900
1652 *r5900:
1653 // end-sanitize-r5900
1654 *r3900:
1655 // start-sanitize-tx19
1656 *tx19:
1657 // end-sanitize-tx19
1658 {
1659   unsigned32 instruction = instruction_0;
1660   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1661   int destreg = ((instruction >> 16) & 0x0000001F);
1662   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1663   {
1664     address_word vaddr = ((unsigned64)op1 + offset);
1665     address_word paddr;
1666     int uncached;
1667     {
1668       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1669         {
1670           unsigned64 memval = 0;
1671           unsigned64 memval1 = 0;
1672           unsigned64 mask = 3;
1673           unsigned int reverse = (ReverseEndian ? mask : 0);
1674           unsigned int bigend = (BigEndianCPU ? mask : 0);
1675           int byte;
1676           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1677           byte = ((vaddr & mask) ^ bigend);
1678           if (!!ByteSwapMem)
1679             paddr &= ~mask;
1680           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1681           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1682             memval >>= 32;
1683           }
1684           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1685           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1686         }
1687     }
1688   }
1689 }
1690
1691
1692 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1693 "lwr r<RT>, <OFFSET>(r<BASE>)"
1694 *mipsI:
1695 *mipsII:
1696 *mipsIII:
1697 *mipsIV:
1698 // start-sanitize-r5900
1699 *r5900:
1700 // end-sanitize-r5900
1701 *r3900:
1702 // start-sanitize-tx19
1703 *tx19:
1704 // end-sanitize-tx19
1705 {
1706   unsigned32 instruction = instruction_0;
1707   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1708   int destreg = ((instruction >> 16) & 0x0000001F);
1709   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1710   {
1711     address_word vaddr = ((unsigned64)op1 + offset);
1712     address_word paddr;
1713     int uncached;
1714     {
1715       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1716         {
1717           unsigned64 memval = 0;
1718           unsigned64 memval1 = 0;
1719           unsigned64 mask = 3;
1720           unsigned int reverse = (ReverseEndian ? mask : 0);
1721           unsigned int bigend = (BigEndianCPU ? mask : 0);
1722           int byte;
1723           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1724           byte = ((vaddr & mask) ^ bigend);
1725           if (!ByteSwapMem)
1726             paddr &= ~mask;
1727           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1728           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1729             memval >>= 32;
1730           }
1731           {
1732             unsigned64 srcmask;
1733             if (byte == 0)
1734               srcmask = 0;
1735             else
1736               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1737             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1738           }
1739           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1740         }
1741     }
1742   }
1743 }
1744
1745
1746 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1747 "lwu r<RT>, <OFFSET>(r<BASE>)"
1748 *mipsIII:
1749 *mipsIV:
1750 // start-sanitize-r5900
1751 *r5900:
1752 // end-sanitize-r5900
1753 *r3900:
1754 // start-sanitize-tx19
1755 *tx19:
1756 // end-sanitize-tx19
1757 {
1758   unsigned32 instruction = instruction_0;
1759   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760   int destreg = ((instruction >> 16) & 0x0000001F);
1761   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1762   {
1763     address_word vaddr = ((unsigned64)op1 + offset);
1764     address_word paddr;
1765     int uncached;
1766     if ((vaddr & 3) != 0)
1767       SignalExceptionAddressLoad();
1768     else
1769       {
1770         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1771           {
1772             unsigned64 memval = 0;
1773             unsigned64 memval1 = 0;
1774             unsigned64 mask = 0x7;
1775             unsigned int shift = 2;
1776             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1778             unsigned int byte;
1779             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781             byte = ((vaddr & mask) ^ (bigend << shift));
1782             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1783           }
1784       }
1785   }
1786 }
1787
1788
1789 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1790 "mfhi r<RD>"
1791 *mipsI:
1792 *mipsII:
1793 *mipsIII:
1794 *mipsIV:
1795 // start-sanitize-r5900
1796 *r5900:
1797 // end-sanitize-r5900
1798 *r3900:
1799 // start-sanitize-tx19
1800 *tx19:
1801 // end-sanitize-tx19
1802 {
1803   GPR[RD] = HI;
1804   HIACCESS = 3;
1805 }
1806
1807
1808 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1809 "mflo r<RD>"
1810 *mipsI:
1811 *mipsII:
1812 *mipsIII:
1813 *mipsIV:
1814 // start-sanitize-r5900
1815 *r5900:
1816 // end-sanitize-r5900
1817 *r3900:
1818 // start-sanitize-tx19
1819 *tx19:
1820 // end-sanitize-tx19
1821 {
1822   GPR[RD] = LO;
1823   LOACCESS = 3; /* 3rd instruction will be safe */
1824 }
1825
1826
1827 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1828 "movn r<RD>, r<RS>, r<RT>"
1829 *mipsIV:
1830 // start-sanitize-r5900
1831 *r5900:
1832 // end-sanitize-r5900
1833 {
1834   if (GPR[RT] != 0)
1835     GPR[RD] = GPR[RS];
1836 }
1837
1838
1839 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1840 "movz r<RD>, r<RS>, r<RT>"
1841 *mipsIV:
1842 // start-sanitize-r5900
1843 *r5900:
1844 // end-sanitize-r5900
1845 {
1846   if (GPR[RT] == 0)
1847     GPR[RD] = GPR[RS];
1848 }
1849
1850
1851 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1852 "mthi r<RS>"
1853 *mipsI:
1854 *mipsII:
1855 *mipsIII:
1856 *mipsIV:
1857 // start-sanitize-r5900
1858 *r5900:
1859 // end-sanitize-r5900
1860 *r3900:
1861 // start-sanitize-tx19
1862 *tx19:
1863 // end-sanitize-tx19
1864 {
1865   if (HIACCESS != 0)
1866     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
1867   HI = GPR[RS];
1868   HIACCESS = 3; /* 3rd instruction will be safe */
1869 }
1870
1871
1872 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1873 "mtlo r<RS>"
1874 *mipsI:
1875 *mipsII:
1876 *mipsIII:
1877 *mipsIV:
1878 // start-sanitize-r5900
1879 *r5900:
1880 // end-sanitize-r5900
1881 *r3900:
1882 // start-sanitize-tx19
1883 *tx19:
1884 // end-sanitize-tx19
1885 {
1886   if (LOACCESS != 0)
1887     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
1888   LO = GPR[RS];
1889   LOACCESS = 3; /* 3rd instruction will be safe */
1890 }
1891
1892
1893 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
1894 "mult r<RS>, r<RT>"
1895 *mipsI:
1896 *mipsII:
1897 *mipsIII:
1898 *mipsIV:
1899 // start-sanitize-r5900
1900 *r5900:
1901 // end-sanitize-r5900
1902 *r3900:
1903 // start-sanitize-tx19
1904 *tx19:
1905 // end-sanitize-tx19
1906 {
1907   signed64 prod;
1908   CHECKHILO ("Multiplication");
1909   prod = (((signed64)(signed32) GPR[RS])
1910           * ((signed64)(signed32) GPR[RT]));
1911   LO = EXTEND32 (VL4_8 (prod));
1912   HI = EXTEND32 (VH4_8 (prod));
1913 }
1914
1915
1916 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
1917 "multu r<RS>, r<RT>"
1918 *mipsI:
1919 *mipsII:
1920 *mipsIII:
1921 *mipsIV:
1922 // start-sanitize-r5900
1923 *r5900:
1924 // end-sanitize-r5900
1925 *r3900:
1926 // start-sanitize-tx19
1927 *tx19:
1928 // end-sanitize-tx19
1929 {
1930   unsigned64 prod;
1931   CHECKHILO ("Multiplication");
1932   prod = (((unsigned64)(unsigned32) GPR[RS])
1933           * ((unsigned64)(unsigned32) GPR[RT]));
1934   LO = EXTEND32 (VL4_8 (prod));
1935   HI = EXTEND32 (VH4_8 (prod));
1936 }
1937
1938
1939 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1940 "nor r<RD>, r<RS>, r<RT>"
1941 *mipsI:
1942 *mipsII:
1943 *mipsIII:
1944 *mipsIV:
1945 // start-sanitize-r5900
1946 *r5900:
1947 // end-sanitize-r5900
1948 *r3900:
1949 // start-sanitize-tx19
1950 *tx19:
1951 // end-sanitize-tx19
1952 {
1953   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
1954 }
1955
1956
1957 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1958 "or r<RD>, r<RS>, r<RT>"
1959 *mipsI:
1960 *mipsII:
1961 *mipsIII:
1962 *mipsIV:
1963 // start-sanitize-r5900
1964 *r5900:
1965 // end-sanitize-r5900
1966 *r3900:
1967 // start-sanitize-tx19
1968 *tx19:
1969 // end-sanitize-tx19
1970 {
1971   GPR[RD] = (GPR[RS] | GPR[RT]);
1972 }
1973
1974
1975 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
1976 "ori r<RT>, r<RS>, <IMMEDIATE>"
1977 *mipsI:
1978 *mipsII:
1979 *mipsIII:
1980 *mipsIV:
1981 // start-sanitize-r5900
1982 *r5900:
1983 // end-sanitize-r5900
1984 *r3900:
1985 // start-sanitize-tx19
1986 *tx19:
1987 // end-sanitize-tx19
1988 {
1989   GPR[RT] = (GPR[RS] | IMMEDIATE);
1990 }
1991
1992
1993 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1994 *mipsIV:
1995 // start-sanitize-r5900
1996 *r5900:
1997 // end-sanitize-r5900
1998 {
1999   unsigned32 instruction = instruction_0;
2000   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2001   int hint = ((instruction >> 16) & 0x0000001F);
2002   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2003   {
2004     address_word vaddr = ((unsigned64)op1 + offset);
2005     address_word paddr;
2006     int uncached;
2007     {
2008       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2009         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2010     }
2011   }
2012 }
2013
2014 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2015 "sb r<RT>, <OFFSET>(r<BASE>)"
2016 *mipsI:
2017 *mipsII:
2018 *mipsIII:
2019 *mipsIV:
2020 // start-sanitize-r5900
2021 *r5900:
2022 // end-sanitize-r5900
2023 *r3900:
2024 // start-sanitize-tx19
2025 *tx19:
2026 // end-sanitize-tx19
2027 {
2028   unsigned32 instruction = instruction_0;
2029   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2030   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2031   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2032   {
2033     address_word vaddr = ((unsigned64)op1 + offset);
2034     address_word paddr;
2035     int uncached;
2036     {
2037       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2038         {
2039           unsigned64 memval = 0;
2040           unsigned64 memval1 = 0;
2041           unsigned64 mask = 0x7;
2042           unsigned int shift = 0;
2043           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2044           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2045           unsigned int byte;
2046           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2047           byte = ((vaddr & mask) ^ (bigend << shift));
2048           memval = ((unsigned64) op2 << (8 * byte));
2049           {
2050             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2051           }
2052         }
2053     }
2054   }
2055 }
2056
2057
2058 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2059 "sc r<RT>, <OFFSET>(r<BASE>)"
2060 *mipsII:
2061 *mipsIII:
2062 *mipsIV:
2063 // start-sanitize-r5900
2064 *r5900:
2065 // end-sanitize-r5900
2066 *r3900:
2067 // start-sanitize-tx19
2068 *tx19:
2069 // end-sanitize-tx19
2070 {
2071   unsigned32 instruction = instruction_0;
2072   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2073   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2074   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2075   {
2076     address_word vaddr = ((unsigned64)op1 + offset);
2077     address_word paddr;
2078     int uncached;
2079     if ((vaddr & 3) != 0)
2080       SignalExceptionAddressStore();
2081     else
2082       {
2083         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2084           {
2085             unsigned64 memval = 0;
2086             unsigned64 memval1 = 0;
2087             unsigned64 mask = 0x7;
2088             unsigned int byte;
2089             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2090             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2091             memval = ((unsigned64) op2 << (8 * byte));
2092             if (LLBIT)
2093               {
2094                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2095               }
2096             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2097           }
2098       }
2099   }
2100 }
2101
2102
2103 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2104 "scd r<RT>, <OFFSET>(r<BASE>)"
2105 *mipsIII:
2106 *mipsIV:
2107 // start-sanitize-r5900
2108 *r5900:
2109 // end-sanitize-r5900
2110 *r3900:
2111 // start-sanitize-tx19
2112 *tx19:
2113 // end-sanitize-tx19
2114 {
2115   unsigned32 instruction = instruction_0;
2116   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2117   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2118   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2119   {
2120     address_word vaddr = ((unsigned64)op1 + offset);
2121     address_word paddr;
2122     int uncached;
2123     if ((vaddr & 7) != 0)
2124       SignalExceptionAddressStore();
2125     else
2126       {
2127         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2128           {
2129             unsigned64 memval = 0;
2130             unsigned64 memval1 = 0;
2131             memval = op2;
2132             if (LLBIT)
2133               {
2134                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2135               }
2136             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2137           }
2138       }
2139   }
2140 }
2141
2142
2143 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2144 "sd r<RT>, <OFFSET>(r<BASE>)"
2145 *mipsIII:
2146 *mipsIV:
2147 // start-sanitize-r5900
2148 *r5900:
2149 // end-sanitize-r5900
2150 *r3900:
2151 // start-sanitize-tx19
2152 *tx19:
2153 // end-sanitize-tx19
2154 {
2155   unsigned32 instruction = instruction_0;
2156   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2157   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2158   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2159   {
2160     address_word vaddr = ((unsigned64)op1 + offset);
2161     address_word paddr;
2162     int uncached;
2163     if ((vaddr & 7) != 0)
2164       SignalExceptionAddressStore();
2165     else
2166       {
2167         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2168           {
2169             unsigned64 memval = 0;
2170             unsigned64 memval1 = 0;
2171             memval = op2;
2172             {
2173               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2174             }
2175           }
2176       }
2177   }
2178 }
2179
2180
2181 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2182 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2183 *mipsII:
2184 *mipsIII:
2185 *mipsIV:
2186 // start-sanitize-r5900
2187 *r5900:
2188 // end-sanitize-r5900
2189 *r3900:
2190 // start-sanitize-tx19
2191 *tx19:
2192 // end-sanitize-tx19
2193 {
2194   unsigned32 instruction = instruction_0;
2195   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2196   int destreg = ((instruction >> 16) & 0x0000001F);
2197   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2198   {
2199     address_word vaddr = ((unsigned64)op1 + offset);
2200     address_word paddr;
2201     int uncached;
2202     if ((vaddr & 7) != 0)
2203       SignalExceptionAddressStore();
2204     else
2205       {
2206         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2207           {
2208             unsigned64 memval = 0;
2209             unsigned64 memval1 = 0;
2210             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2211             {
2212               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2213             }
2214           }
2215       }
2216   }
2217 }
2218
2219
2220 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2221 "sdl r<RT>, <OFFSET>(r<BASE>)"
2222 *mipsIII:
2223 *mipsIV:
2224 // start-sanitize-r5900
2225 *r5900:
2226 // end-sanitize-r5900
2227 *r3900:
2228 // start-sanitize-tx19
2229 *tx19:
2230 // end-sanitize-tx19
2231 {
2232   unsigned32 instruction = instruction_0;
2233   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2234   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2235   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2236   {
2237     address_word vaddr = ((unsigned64)op1 + offset);
2238     address_word paddr;
2239     int uncached;
2240     {
2241       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2242         {
2243           unsigned64 memval = 0;
2244           unsigned64 memval1 = 0;
2245           unsigned64 mask = 7;
2246           unsigned int reverse = (ReverseEndian ? mask : 0);
2247           unsigned int bigend = (BigEndianCPU ? mask : 0);
2248           int byte;
2249           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2250           byte = ((vaddr & mask) ^ bigend);
2251           if (!!ByteSwapMem)
2252             paddr &= ~mask;
2253           memval = (op2 >> (8 * (7 - byte)));
2254           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2255         }
2256     }
2257   }
2258 }
2259
2260
2261 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2262 "sdr r<RT>, <OFFSET>(r<BASE>)"
2263 *mipsIII:
2264 *mipsIV:
2265 // start-sanitize-r5900
2266 *r5900:
2267 // end-sanitize-r5900
2268 *r3900:
2269 // start-sanitize-tx19
2270 *tx19:
2271 // end-sanitize-tx19
2272 {
2273   unsigned32 instruction = instruction_0;
2274   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2275   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2276   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2277   {
2278     address_word vaddr = ((unsigned64)op1 + offset);
2279     address_word paddr;
2280     int uncached;
2281     {
2282       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2283         {
2284           unsigned64 memval = 0;
2285           unsigned64 memval1 = 0;
2286           unsigned64 mask = 7;
2287           unsigned int reverse = (ReverseEndian ? mask : 0);
2288           unsigned int bigend = (BigEndianCPU ? mask : 0);
2289           int byte;
2290           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2291           byte = ((vaddr & mask) ^ bigend);
2292           if (!ByteSwapMem)
2293             paddr &= ~mask;
2294           memval = ((unsigned64) op2 << (byte * 8));
2295           StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2296         }
2297     }
2298   }
2299 }
2300
2301
2302 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2303 "sh r<RT>, <OFFSET>(r<BASE>)"
2304 *mipsI:
2305 *mipsII:
2306 *mipsIII:
2307 *mipsIV:
2308 // start-sanitize-r5900
2309 *r5900:
2310 // end-sanitize-r5900
2311 *r3900:
2312 // start-sanitize-tx19
2313 *tx19:
2314 // end-sanitize-tx19
2315 {
2316   unsigned32 instruction = instruction_0;
2317   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2318   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2319   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2320   {
2321     address_word vaddr = ((unsigned64)op1 + offset);
2322     address_word paddr;
2323     int uncached;
2324     if ((vaddr & 1) != 0)
2325       SignalExceptionAddressStore();
2326     else
2327       {
2328         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2329           {
2330             unsigned64 memval = 0;
2331             unsigned64 memval1 = 0;
2332             unsigned64 mask = 0x7;
2333             unsigned int shift = 1;
2334             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2335             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2336             unsigned int byte;
2337             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2338             byte = ((vaddr & mask) ^ (bigend << shift));
2339             memval = ((unsigned64) op2 << (8 * byte));
2340             {
2341               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2342             }
2343           }
2344       }
2345   }
2346 }
2347
2348
2349 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2350 "sll r<RD>, r<RT>, <SHIFT>"
2351 *mipsI:
2352 *mipsII:
2353 *mipsIII:
2354 *mipsIV:
2355 // start-sanitize-r5900
2356 *r5900:
2357 // end-sanitize-r5900
2358 *r3900:
2359 // start-sanitize-tx19
2360 *tx19:
2361 // end-sanitize-tx19
2362 {
2363   int s = SHIFT;
2364   unsigned32 temp = (GPR[RT] << s);
2365   GPR[RD] = EXTEND32 (temp);
2366 }
2367
2368
2369 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2370 "sllv r<RD>, r<RT>, r<RS>"
2371 *mipsI:
2372 *mipsII:
2373 *mipsIII:
2374 *mipsIV:
2375 // start-sanitize-r5900
2376 *r5900:
2377 // end-sanitize-r5900
2378 *r3900:
2379 // start-sanitize-tx19
2380 *tx19:
2381 // end-sanitize-tx19
2382 {
2383   int s = MASKED (GPR[RS], 4, 0);
2384   unsigned32 temp = (GPR[RT] << s);
2385   GPR[RD] = EXTEND32 (temp);
2386 }
2387
2388
2389 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2390 "slt r<RD>, r<RS>, r<RT>"
2391 *mipsI:
2392 *mipsII:
2393 *mipsIII:
2394 *mipsIV:
2395 // start-sanitize-r5900
2396 *r5900:
2397 // end-sanitize-r5900
2398 *r3900:
2399 // start-sanitize-tx19
2400 *tx19:
2401 // end-sanitize-tx19
2402 {
2403   GPR[RD] = (GPR[RS] < GPR[RT]);
2404 }
2405
2406
2407 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2408 "slti r<RT>, r<RS>, <IMMEDIATE>"
2409 *mipsI:
2410 *mipsII:
2411 *mipsIII:
2412 *mipsIV:
2413 // start-sanitize-r5900
2414 *r5900:
2415 // end-sanitize-r5900
2416 *r3900:
2417 // start-sanitize-tx19
2418 *tx19:
2419 // end-sanitize-tx19
2420 {
2421   GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
2422 }
2423
2424
2425 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2426 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2427 *mipsI:
2428 *mipsII:
2429 *mipsIII:
2430 *mipsIV:
2431 // start-sanitize-r5900
2432 *r5900:
2433 // end-sanitize-r5900
2434 *r3900:
2435 // start-sanitize-tx19
2436 *tx19:
2437 // end-sanitize-tx19
2438 {
2439   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2440 }
2441
2442 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2443 "sltu r<RD>, r<RS>, r<RT>"
2444 *mipsI:
2445 *mipsII:
2446 *mipsIII:
2447 *mipsIV:
2448 // start-sanitize-r5900
2449 *r5900:
2450 // end-sanitize-r5900
2451 *r3900:
2452 // start-sanitize-tx19
2453 *tx19:
2454 // end-sanitize-tx19
2455 {
2456   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2457 }
2458
2459
2460 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2461 "sra r<RD>, r<RT>, <SHIFT>"
2462 *mipsI:
2463 *mipsII:
2464 *mipsIII:
2465 *mipsIV:
2466 // start-sanitize-r5900
2467 *r5900:
2468 // end-sanitize-r5900
2469 *r3900:
2470 // start-sanitize-tx19
2471 *tx19:
2472 // end-sanitize-tx19
2473 {
2474   int s = SHIFT;
2475   signed32 temp = (signed32) GPR[RT] >> s;
2476   GPR[RD] = EXTEND32 (temp);
2477 }
2478
2479
2480 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2481 "srav r<RD>, r<RT>, r<RS>"
2482 *mipsI:
2483 *mipsII:
2484 *mipsIII:
2485 *mipsIV:
2486 // start-sanitize-r5900
2487 *r5900:
2488 // end-sanitize-r5900
2489 *r3900:
2490 // start-sanitize-tx19
2491 *tx19:
2492 // end-sanitize-tx19
2493 {
2494   int s = MASKED (GPR[RS], 4, 0);
2495   signed32 temp = (signed32) GPR[RT] >> s;
2496   GPR[RD] = EXTEND32 (temp);
2497 }
2498
2499
2500 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2501 "srl r<RD>, r<RT>, <SHIFT>"
2502 *mipsI:
2503 *mipsII:
2504 *mipsIII:
2505 *mipsIV:
2506 // start-sanitize-r5900
2507 *r5900:
2508 // end-sanitize-r5900
2509 *r3900:
2510 // start-sanitize-tx19
2511 *tx19:
2512 // end-sanitize-tx19
2513 {
2514   int s = SHIFT;
2515   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2516   GPR[RD] = EXTEND32 (temp);
2517 }
2518
2519
2520 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2521 "srlv r<RD>, r<RT>, r<RS>"
2522 *mipsI:
2523 *mipsII:
2524 *mipsIII:
2525 *mipsIV:
2526 // start-sanitize-r5900
2527 *r5900:
2528 // end-sanitize-r5900
2529 *r3900:
2530 // start-sanitize-tx19
2531 *tx19:
2532 // end-sanitize-tx19
2533 {
2534   int s = MASKED (GPR[RS], 4, 0);
2535   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2536   GPR[RD] = EXTEND32 (temp);
2537 }
2538
2539
2540 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2541 "sub r<RD>, r<RS>, r<RT>"
2542 *mipsI:
2543 *mipsII:
2544 *mipsIII:
2545 *mipsIV:
2546 // start-sanitize-r5900
2547 *r5900:
2548 // end-sanitize-r5900
2549 *r3900:
2550 // start-sanitize-tx19
2551 *tx19:
2552 // end-sanitize-tx19
2553 {
2554   ALU32_BEGIN (GPR[RS]);
2555   ALU32_SUB (GPR[RT]);
2556   ALU32_END (GPR[RD]);
2557 }
2558
2559
2560 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2561 "subu r<RD>, r<RS>, r<RT>"
2562 *mipsI:
2563 *mipsII:
2564 *mipsIII:
2565 *mipsIV:
2566 // start-sanitize-r5900
2567 *r5900:
2568 // end-sanitize-r5900
2569 *r3900:
2570 // start-sanitize-tx19
2571 *tx19:
2572 // end-sanitize-tx19
2573 {
2574   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2575 }
2576
2577
2578 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2579 "sw r<RT>, <OFFSET>(r<BASE>)"
2580 *mipsI:
2581 *mipsII:
2582 *mipsIII:
2583 *mipsIV:
2584 // start-sanitize-r5900
2585 *r5900:
2586 // end-sanitize-r5900
2587 *r3900:
2588 // start-sanitize-tx19
2589 *tx19:
2590 // end-sanitize-tx19
2591 {
2592   unsigned32 instruction = instruction_0;
2593   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2594   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2595   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2596   {
2597     address_word vaddr = ((unsigned64)op1 + offset);
2598     address_word paddr;
2599     int uncached;
2600     if ((vaddr & 3) != 0)
2601       SignalExceptionAddressStore();
2602     else
2603       {
2604         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2605           {
2606             unsigned64 memval = 0;
2607             unsigned64 memval1 = 0;
2608             unsigned64 mask = 0x7;
2609             unsigned int byte;
2610             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2611             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2612             memval = ((unsigned64) op2 << (8 * byte));
2613             {
2614               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2615             }
2616           }
2617       }
2618   }
2619 }
2620
2621
2622 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2623 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2624 *mipsI:
2625 *mipsII:
2626 *mipsIII:
2627 *mipsIV:
2628 // start-sanitize-r5900
2629 *r5900:
2630 // end-sanitize-r5900
2631 *r3900:
2632 // start-sanitize-tx19
2633 *tx19:
2634 // end-sanitize-tx19
2635 {
2636   unsigned32 instruction = instruction_0;
2637   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2638   int destreg = ((instruction >> 16) & 0x0000001F);
2639   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2640   {
2641     address_word vaddr = ((unsigned64)op1 + offset);
2642     address_word paddr;
2643     int uncached;
2644     if ((vaddr & 3) != 0)
2645       SignalExceptionAddressStore();
2646     else
2647       {
2648         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2649           {
2650             unsigned64 memval = 0;
2651             unsigned64 memval1 = 0;
2652             unsigned64 mask = 0x7;
2653             unsigned int byte;
2654             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2655             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2656             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2657             {
2658               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2659             }
2660           }
2661       }
2662   }
2663 }
2664
2665
2666 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2667 "swl r<RT>, <OFFSET>(r<BASE>)"
2668 *mipsI:
2669 *mipsII:
2670 *mipsIII:
2671 *mipsIV:
2672 // start-sanitize-r5900
2673 *r5900:
2674 // end-sanitize-r5900
2675 *r3900:
2676 // start-sanitize-tx19
2677 *tx19:
2678 // end-sanitize-tx19
2679 {
2680   unsigned32 instruction = instruction_0;
2681   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2682   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2683   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2684   {
2685     address_word vaddr = ((unsigned64)op1 + offset);
2686     address_word paddr;
2687     int uncached;
2688     {
2689       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2690         {
2691           unsigned64 memval = 0;
2692           unsigned64 memval1 = 0;
2693           unsigned64 mask = 3;
2694           unsigned int reverse = (ReverseEndian ? mask : 0);
2695           unsigned int bigend = (BigEndianCPU ? mask : 0);
2696           int byte;
2697           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2698           byte = ((vaddr & mask) ^ bigend);
2699           if (!!ByteSwapMem)
2700             paddr &= ~mask;
2701           memval = (op2 >> (8 * (3 - byte)));
2702           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2703             memval <<= 32;
2704           }
2705           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2706         }
2707     }
2708   }
2709 }
2710
2711
2712 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2713 "swr r<RT>, <OFFSET>(r<BASE>)"
2714 *mipsI:
2715 *mipsII:
2716 *mipsIII:
2717 *mipsIV:
2718 // start-sanitize-r5900
2719 *r5900:
2720 // end-sanitize-r5900
2721 *r3900:
2722 // start-sanitize-tx19
2723 *tx19:
2724 // end-sanitize-tx19
2725 {
2726   unsigned32 instruction = instruction_0;
2727   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2728   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2729   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2730   {
2731     address_word vaddr = ((unsigned64)op1 + offset);
2732     address_word paddr;
2733     int uncached;
2734     {
2735       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2736         {
2737           unsigned64 memval = 0;
2738           unsigned64 memval1 = 0;
2739           unsigned64 mask = 3;
2740           unsigned int reverse = (ReverseEndian ? mask : 0);
2741           unsigned int bigend = (BigEndianCPU ? mask : 0);
2742           int byte;
2743           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2744           byte = ((vaddr & mask) ^ bigend);
2745           if (!ByteSwapMem)
2746             paddr &= ~mask;
2747           memval = ((unsigned64) op2 << (byte * 8));
2748           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2749             memval <<= 32;
2750           }
2751           StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
2752         }
2753     }
2754   }
2755 }
2756
2757
2758 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2759 "sync":STYPE == 0
2760 "sync <STYPE>"
2761 *mipsII:
2762 *mipsIII:
2763 *mipsIV:
2764 // start-sanitize-r5900
2765 *r5900:
2766 // end-sanitize-r5900
2767 *r3900:
2768 // start-sanitize-tx19
2769 *tx19:
2770 // end-sanitize-tx19
2771 {
2772   SyncOperation (STYPE);
2773 }
2774
2775
2776 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2777 "syscall <CODE>"
2778 *mipsI:
2779 *mipsII:
2780 *mipsIII:
2781 *mipsIV:
2782 // start-sanitize-r5900
2783 *r5900:
2784 // end-sanitize-r5900
2785 *r3900:
2786 // start-sanitize-tx19
2787 *tx19:
2788 // end-sanitize-tx19
2789 {
2790   SignalException(SystemCall, instruction_0);
2791 }
2792
2793
2794 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2795 "teq r<RS>, r<RT>"
2796 *mipsII:
2797 *mipsIII:
2798 *mipsIV:
2799 // start-sanitize-r5900
2800 *r5900:
2801 // end-sanitize-r5900
2802 *r3900:
2803 // start-sanitize-tx19
2804 *tx19:
2805 // end-sanitize-tx19
2806 {
2807   if (GPR[RS] == GPR[RT])
2808     SignalException(Trap, instruction_0);
2809 }
2810
2811
2812 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2813 "teqi r<RS>, <IMMEDIATE>"
2814 *mipsII:
2815 *mipsIII:
2816 *mipsIV:
2817 // start-sanitize-r5900
2818 *r5900:
2819 // end-sanitize-r5900
2820 *r3900:
2821 // start-sanitize-tx19
2822 *tx19:
2823 // end-sanitize-tx19
2824 {
2825   if (GPR[RS] == EXTEND16 (IMMEDIATE))
2826     SignalException(Trap, instruction_0);
2827 }
2828
2829
2830 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2831 "tge r<RS>, r<RT>"
2832 *mipsII:
2833 *mipsIII:
2834 *mipsIV:
2835 // start-sanitize-r5900
2836 *r5900:
2837 // end-sanitize-r5900
2838 *r3900:
2839 // start-sanitize-tx19
2840 *tx19:
2841 // end-sanitize-tx19
2842 {
2843   if (GPR[RS] >= GPR[RT])
2844     SignalException(Trap, instruction_0);
2845 }
2846
2847
2848 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2849 "tgei r<RS>, <IMMEDIATE>"
2850 *mipsII:
2851 *mipsIII:
2852 *mipsIV:
2853 // start-sanitize-r5900
2854 *r5900:
2855 // end-sanitize-r5900
2856 *r3900:
2857 // start-sanitize-tx19
2858 *tx19:
2859 // end-sanitize-tx19
2860 {
2861   if (GPR[RS] >= EXTEND16 (IMMEDIATE))
2862     SignalException(Trap, instruction_0);
2863 }
2864
2865
2866 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2867 "tgeiu r<RS>, <IMMEDIATE>"
2868 *mipsII:
2869 *mipsIII:
2870 *mipsIV:
2871 // start-sanitize-r5900
2872 *r5900:
2873 // end-sanitize-r5900
2874 *r3900:
2875 // start-sanitize-tx19
2876 *tx19:
2877 // end-sanitize-tx19
2878 {
2879   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2880     SignalException(Trap, instruction_0);
2881 }
2882
2883
2884 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2885 "tgeu r<RS>, r<RT>"
2886 *mipsII:
2887 *mipsIII:
2888 *mipsIV:
2889 // start-sanitize-r5900
2890 *r5900:
2891 // end-sanitize-r5900
2892 *r3900:
2893 // start-sanitize-tx19
2894 *tx19:
2895 // end-sanitize-tx19
2896 {
2897   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2898     SignalException(Trap, instruction_0);
2899 }
2900
2901
2902 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2903 "tlt r<RS>, r<RT>"
2904 *mipsII:
2905 *mipsIII:
2906 *mipsIV:
2907 // start-sanitize-r5900
2908 *r5900:
2909 // end-sanitize-r5900
2910 *r3900:
2911 // start-sanitize-tx19
2912 *tx19:
2913 // end-sanitize-tx19
2914 {
2915   if (GPR[RS] < GPR[RT])
2916     SignalException(Trap, instruction_0);
2917 }
2918
2919
2920 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2921 "tlti r<RS>, <IMMEDIATE>"
2922 *mipsII:
2923 *mipsIII:
2924 *mipsIV:
2925 // start-sanitize-r5900
2926 *r5900:
2927 // end-sanitize-r5900
2928 *r3900:
2929 // start-sanitize-tx19
2930 *tx19:
2931 // end-sanitize-tx19
2932 {
2933   if (GPR[RS] < EXTEND16 (IMMEDIATE))
2934     SignalException(Trap, instruction_0);
2935 }
2936
2937
2938 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2939 "tltiu r<RS>, <IMMEDIATE>"
2940 *mipsII:
2941 *mipsIII:
2942 *mipsIV:
2943 // start-sanitize-r5900
2944 *r5900:
2945 // end-sanitize-r5900
2946 *r3900:
2947 // start-sanitize-tx19
2948 *tx19:
2949 // end-sanitize-tx19
2950 {
2951   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2952     SignalException(Trap, instruction_0);
2953 }
2954
2955
2956 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2957 "tltu r<RS>, r<RT>"
2958 *mipsII:
2959 *mipsIII:
2960 *mipsIV:
2961 // start-sanitize-r5900
2962 *r5900:
2963 // end-sanitize-r5900
2964 *r3900:
2965 // start-sanitize-tx19
2966 *tx19:
2967 // end-sanitize-tx19
2968 {
2969   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2970     SignalException(Trap, instruction_0);
2971 }
2972
2973
2974 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2975 "tne r<RS>, r<RT>"
2976 *mipsII:
2977 *mipsIII:
2978 *mipsIV:
2979 // start-sanitize-r5900
2980 *r5900:
2981 // end-sanitize-r5900
2982 *r3900:
2983 // start-sanitize-tx19
2984 *tx19:
2985 // end-sanitize-tx19
2986 {
2987   if (GPR[RS] != GPR[RT])
2988     SignalException(Trap, instruction_0);
2989 }
2990
2991
2992 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2993 "tne r<RS>, <IMMEDIATE>"
2994 *mipsII:
2995 *mipsIII:
2996 *mipsIV:
2997 // start-sanitize-r5900
2998 *r5900:
2999 // end-sanitize-r5900
3000 *r3900:
3001 // start-sanitize-tx19
3002 *tx19:
3003 // end-sanitize-tx19
3004 {
3005   if (GPR[RS] != EXTEND16 (IMMEDIATE))
3006     SignalException(Trap, instruction_0);
3007 }
3008
3009
3010 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3011 "xor r<RD>, r<RS>, r<RT>"
3012 *mipsI:
3013 *mipsII:
3014 *mipsIII:
3015 *mipsIV:
3016 // start-sanitize-r5900
3017 *r5900:
3018 // end-sanitize-r5900
3019 *r3900:
3020 // start-sanitize-tx19
3021 *tx19:
3022 // end-sanitize-tx19
3023 {
3024   GPR[RD] = GPR[RS] ^ GPR[RT];
3025 }
3026
3027
3028 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3029 "xori r<RT>, r<RS>, <IMMEDIATE>"
3030 *mipsI:
3031 *mipsII:
3032 *mipsIII:
3033 *mipsIV:
3034 // start-sanitize-r5900
3035 *r5900:
3036 // end-sanitize-r5900
3037 *r3900:
3038 // start-sanitize-tx19
3039 *tx19:
3040 // end-sanitize-tx19
3041 {
3042   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3043 }
3044
3045 \f
3046 //
3047 // MIPS Architecture:
3048 //
3049 //        FPU Instruction Set (COP1 & COP1X)
3050 //
3051
3052
3053 :%s:::FMT:int fmt
3054 {
3055   switch (fmt)
3056     {
3057     case fmt_single: return "s";
3058     case fmt_double: return "d";
3059     case fmt_word: return "w";
3060     case fmt_long: return "l";
3061     default: return "?";
3062     }
3063 }
3064
3065 :%s:::TF:int tf
3066 {
3067   if (tf)
3068     return "t";
3069   else
3070     return "f";
3071 }
3072
3073 :%s:::ND:int nd
3074 {
3075   if (nd)
3076     return "l";
3077   else
3078     return "";
3079 }
3080
3081 :%s:::COND:int cond
3082 {
3083   switch (cond)
3084     {
3085     case 00: return "f";
3086     case 01: return "un";
3087     case 02: return "eq";
3088     case 03: return "ueq";
3089     case 04: return "olt";
3090     case 05: return "ult";
3091     case 06: return "ole";
3092     case 07: return "ule";
3093     case 010: return "sf";
3094     case 011: return "ngle";
3095     case 012: return "seq";
3096     case 013: return "ngl";
3097     case 014: return "lt";
3098     case 015: return "nge";
3099     case 016: return "le";
3100     case 017: return "ngt";
3101     default: return "?";
3102     }
3103 }
3104
3105
3106 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3107 "abs.%s<FMT> f<FD>, f<FS>"
3108 *mipsI:
3109 *mipsII:
3110 *mipsIII:
3111 *mipsIV:
3112 // start-sanitize-r5900
3113 *r5900:
3114 // end-sanitize-r5900
3115 *r3900:
3116 // start-sanitize-tx19
3117 *tx19:
3118 // end-sanitize-tx19
3119 {
3120   unsigned32 instruction = instruction_0;
3121   int destreg = ((instruction >> 6) & 0x0000001F);
3122   int fs = ((instruction >> 11) & 0x0000001F);
3123   int format = ((instruction >> 21) & 0x00000007);
3124   {
3125     if ((format != fmt_single) && (format != fmt_double))
3126       SignalException(ReservedInstruction,instruction);
3127     else
3128       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3129   }
3130 }
3131
3132
3133
3134
3135 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3136 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3137 *mipsI:
3138 *mipsII:
3139 *mipsIII:
3140 *mipsIV:
3141 // start-sanitize-r5900
3142 *r5900:
3143 // end-sanitize-r5900
3144 *r3900:
3145 // start-sanitize-tx19
3146 *tx19:
3147 // end-sanitize-tx19
3148 {
3149   unsigned32 instruction = instruction_0;
3150   int destreg = ((instruction >> 6) & 0x0000001F);
3151   int fs = ((instruction >> 11) & 0x0000001F);
3152   int ft = ((instruction >> 16) & 0x0000001F);
3153   int format = ((instruction >> 21) & 0x00000007);
3154   {
3155     if ((format != fmt_single) && (format != fmt_double))
3156       SignalException(ReservedInstruction, instruction);
3157     else
3158       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3159   }
3160 }
3161
3162
3163 //
3164 // FIXME: This does not correctly resolve mipsI-mipsIV differences.
3165 //
3166 // BC1F
3167 // BC1FL
3168 // BC1T
3169 // BC1TL
3170 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3171 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3172 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3173 *mipsI:
3174 *mipsII:
3175 *mipsIII:
3176 *mipsIV:
3177 // start-sanitize-r5900
3178 *r5900:
3179 // end-sanitize-r5900
3180 *r3900:
3181 // start-sanitize-tx19
3182 *tx19:
3183 // end-sanitize-tx19
3184 {
3185   unsigned32 instruction = instruction_0;
3186   signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3187   int boolean = ((instruction >> 16) & 0x00000001);
3188   int likely = ((instruction >> 17) & 0x00000001);
3189   int condition_code = ((instruction >> 18) & 0x00000007);
3190   {
3191     if (condition_code != 0)
3192       SignalException(ReservedInstruction,instruction);
3193     else {
3194       int condition = (PREVCOC1() == boolean);
3195       /* NOTE: The branch occurs AFTER the next instruction has been executed */
3196       if (condition) {
3197         DELAY_SLOT (PC + offset);
3198       }
3199       else if (likely) {
3200         NULLIFY_NEXT_INSTRUCTION ();
3201       }
3202     }
3203   }
3204 }
3205
3206
3207 //
3208 // FIXME: This does not correctly differentiate between mips*
3209 //
3210 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3211 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3212 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3213 *mipsI:
3214 *mipsII:
3215 *mipsIII:
3216 *mipsIV:
3217 // start-sanitize-r5900
3218 *r5900:
3219 // end-sanitize-r5900
3220 *r3900:
3221 // start-sanitize-tx19
3222 *tx19:
3223 // end-sanitize-tx19
3224 {
3225   unsigned32 instruction = instruction_0;
3226   int cmpflags = ((instruction >> 0) & 0x0000000F);
3227   int condition_code = ((instruction >> 8) & 0x00000007);
3228   int fs = ((instruction >> 11) & 0x0000001F);
3229   int ft = ((instruction >> 16) & 0x0000001F);
3230   int format = ((instruction >> 21) & 0x00000007);
3231   if (condition_code != 0)
3232     {
3233       SignalException(ReservedInstruction,instruction);
3234     }
3235   else
3236     {
3237       if ((format != fmt_single) && (format != fmt_double))
3238         SignalException(ReservedInstruction,instruction);
3239       else {
3240         if (condition_code != 0)
3241           SignalException(ReservedInstruction,instruction);
3242         else
3243           {
3244             int ignore = 0;
3245             int less = 0;
3246             int equal = 0;
3247             int unordered = 1;
3248             unsigned64 ofs = ValueFPR(fs,format);
3249             unsigned64 oft = ValueFPR(ft,format);
3250             if (NaN(ofs,format) || NaN(oft,format)) {
3251               if (FCSR & FP_ENABLE(IO)) {
3252                 FCSR |= FP_CAUSE(IO);
3253                 SignalExceptionFPE();
3254                 ignore = 1;
3255               }
3256             } else {
3257               less = Less(ofs,oft,format);
3258               equal = Equal(ofs,oft,format);
3259               unordered = 0;
3260             }
3261             if (!ignore) {
3262               int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3263               SETFCC(condition_code,condition);
3264             }
3265           }
3266       }
3267     }
3268 }
3269
3270
3271 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3272 "ceil.l.%s<FMT> f<FD>, f<FS>"
3273 *mipsIII:
3274 *mipsIV:
3275 // start-sanitize-r5900
3276 *r5900:
3277 // end-sanitize-r5900
3278 *r3900:
3279 // start-sanitize-tx19
3280 *tx19:
3281 // end-sanitize-tx19
3282 {
3283   unsigned32 instruction = instruction_0;
3284   int destreg = ((instruction >> 6) & 0x0000001F);
3285   int fs = ((instruction >> 11) & 0x0000001F);
3286   int format = ((instruction >> 21) & 0x00000007);
3287   {
3288     if ((format != fmt_single) && (format != fmt_double))
3289       SignalException(ReservedInstruction,instruction);
3290     else
3291       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3292   }
3293 }
3294
3295
3296 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3297 *mipsII:
3298 *mipsIII:
3299 *mipsIV:
3300 // start-sanitize-r5900
3301 *r5900:
3302 // end-sanitize-r5900
3303 *r3900:
3304 // start-sanitize-tx19
3305 *tx19:
3306 // end-sanitize-tx19
3307 {
3308   unsigned32 instruction = instruction_0;
3309   int destreg = ((instruction >> 6) & 0x0000001F);
3310   int fs = ((instruction >> 11) & 0x0000001F);
3311   int format = ((instruction >> 21) & 0x00000007);
3312   {
3313   if ((format != fmt_single) && (format != fmt_double))
3314    SignalException(ReservedInstruction,instruction);
3315   else
3316    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3317   }
3318 }
3319
3320
3321 // CFC1
3322 // CTC1
3323 01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
3324 *mipsI:
3325 *mipsII:
3326 *mipsIII:
3327 *mipsIV:
3328 // start-sanitize-r5900
3329 *r5900:
3330 // end-sanitize-r5900
3331 *r3900:
3332 // start-sanitize-tx19
3333 *tx19:
3334 // end-sanitize-tx19
3335 {
3336   unsigned32 instruction = instruction_0;
3337   int fs = ((instruction >> 11) & 0x0000001F);
3338   int ft = ((instruction >> 16) & 0x0000001F);
3339   int to = ((instruction >> 23) & 0x00000001);
3340   {
3341     if (to) {
3342       if (fs == 0) {
3343         PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
3344       } else if (fs == 31) {
3345         PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
3346       } /* else NOP */
3347       PENDING_FILL(COCIDX,0); /* special case */
3348     } else { /* control from */
3349       if (fs == 0) {
3350         PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
3351       } else if (fs == 31) {
3352         PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
3353       } /* else NOP */
3354     }
3355   }
3356 }
3357
3358
3359 //
3360 // FIXME: Does not correctly differentiate between mips*
3361 //
3362 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3363 "cvt.d.%s<FMT> f<FD>, f<FS>"
3364 *mipsI:
3365 *mipsII:
3366 *mipsIII:
3367 *mipsIV:
3368 // start-sanitize-r5900
3369 *r5900:
3370 // end-sanitize-r5900
3371 *r3900:
3372 // start-sanitize-tx19
3373 *tx19:
3374 // end-sanitize-tx19
3375 {
3376   unsigned32 instruction = instruction_0;
3377   int destreg = ((instruction >> 6) & 0x0000001F);
3378   int fs = ((instruction >> 11) & 0x0000001F);
3379   int format = ((instruction >> 21) & 0x00000007);
3380   {
3381     if ((format == fmt_double) | 0)
3382       SignalException(ReservedInstruction,instruction);
3383     else
3384       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3385   }
3386 }
3387
3388
3389 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3390 "cvt.l.%s<FMT> f<FD>, f<FS>"
3391 *mipsIII:
3392 *mipsIV:
3393 // start-sanitize-r5900
3394 *r5900:
3395 // end-sanitize-r5900
3396 *r3900:
3397 // start-sanitize-tx19
3398 *tx19:
3399 // end-sanitize-tx19
3400 {
3401   unsigned32 instruction = instruction_0;
3402   int destreg = ((instruction >> 6) & 0x0000001F);
3403   int fs = ((instruction >> 11) & 0x0000001F);
3404   int format = ((instruction >> 21) & 0x00000007);
3405   {
3406     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3407       SignalException(ReservedInstruction,instruction);
3408     else
3409       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3410   }
3411 }
3412
3413
3414 //
3415 // FIXME: Does not correctly differentiate between mips*
3416 //
3417 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3418 "cvt.s.%s<FMT> f<FD>, f<FS>"
3419 *mipsI:
3420 *mipsII:
3421 *mipsIII:
3422 *mipsIV:
3423 // start-sanitize-r5900
3424 *r5900:
3425 // end-sanitize-r5900
3426 *r3900:
3427 // start-sanitize-tx19
3428 *tx19:
3429 // end-sanitize-tx19
3430 {
3431   unsigned32 instruction = instruction_0;
3432   int destreg = ((instruction >> 6) & 0x0000001F);
3433   int fs = ((instruction >> 11) & 0x0000001F);
3434   int format = ((instruction >> 21) & 0x00000007);
3435   {
3436     if ((format == fmt_single) | 0)
3437       SignalException(ReservedInstruction,instruction);
3438     else
3439       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3440   }
3441 }
3442
3443
3444 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3445 "cvt.w.%s<FMT> f<FD>, f<FS>"
3446 *mipsI:
3447 *mipsII:
3448 *mipsIII:
3449 *mipsIV:
3450 // start-sanitize-r5900
3451 *r5900:
3452 // end-sanitize-r5900
3453 *r3900:
3454 // start-sanitize-tx19
3455 *tx19:
3456 // end-sanitize-tx19
3457 {
3458   unsigned32 instruction = instruction_0;
3459   int destreg = ((instruction >> 6) & 0x0000001F);
3460   int fs = ((instruction >> 11) & 0x0000001F);
3461   int format = ((instruction >> 21) & 0x00000007);
3462   {
3463     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3464       SignalException(ReservedInstruction,instruction);
3465     else
3466       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3467   }
3468 }
3469
3470
3471 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3472 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3473 *mipsI:
3474 *mipsII:
3475 *mipsIII:
3476 *mipsIV:
3477 // start-sanitize-r5900
3478 *r5900:
3479 // end-sanitize-r5900
3480 *r3900:
3481 // start-sanitize-tx19
3482 *tx19:
3483 // end-sanitize-tx19
3484 {
3485   unsigned32 instruction = instruction_0;
3486   int destreg = ((instruction >> 6) & 0x0000001F);
3487   int fs = ((instruction >> 11) & 0x0000001F);
3488   int ft = ((instruction >> 16) & 0x0000001F);
3489   int format = ((instruction >> 21) & 0x00000007);
3490   {
3491     if ((format != fmt_single) && (format != fmt_double))
3492       SignalException(ReservedInstruction,instruction);
3493     else
3494       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3495   }
3496 }
3497
3498
3499 // DMFC1
3500 // DMTC1
3501 01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
3502 *mipsIII:
3503 *mipsIV:
3504 // start-sanitize-r5900
3505 *r5900:
3506 // end-sanitize-r5900
3507 *r3900:
3508 // start-sanitize-tx19
3509 *tx19:
3510 // end-sanitize-tx19
3511 {
3512   unsigned32 instruction = instruction_0;
3513   int fs = ((instruction >> 11) & 0x0000001F);
3514   int ft = ((instruction >> 16) & 0x0000001F);
3515   int to = ((instruction >> 23) & 0x00000001);
3516   {
3517     if (to) {
3518       if (SizeFGR() == 64) {
3519         PENDING_FILL((fs + FGRIDX),GPR[ft]);
3520       } else
3521         if ((fs & 0x1) == 0)
3522           {
3523             PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
3524             PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
3525           }
3526     } else {
3527       if (SizeFGR() == 64) {
3528         PENDING_FILL(ft,FGR[fs]);
3529       } else
3530         if ((fs & 0x1) == 0) {
3531           PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
3532         } else {
3533           PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3534         }
3535     }
3536   }
3537 }
3538
3539
3540 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3541 "floor.l.%s<FMT> f<FD>, f<FS>"
3542 *mipsIII:
3543 *mipsIV:
3544 // start-sanitize-r5900
3545 *r5900:
3546 // end-sanitize-r5900
3547 *r3900:
3548 // start-sanitize-tx19
3549 *tx19:
3550 // end-sanitize-tx19
3551 {
3552   unsigned32 instruction = instruction_0;
3553   int destreg = ((instruction >> 6) & 0x0000001F);
3554   int fs = ((instruction >> 11) & 0x0000001F);
3555   int format = ((instruction >> 21) & 0x00000007);
3556   {
3557     if ((format != fmt_single) && (format != fmt_double))
3558       SignalException(ReservedInstruction,instruction);
3559     else
3560       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3561   }
3562 }
3563
3564
3565 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3566 "floor.w.%s<FMT> f<FD>, f<FS>"
3567 *mipsII:
3568 *mipsIII:
3569 *mipsIV:
3570 // start-sanitize-r5900
3571 *r5900:
3572 // end-sanitize-r5900
3573 *r3900:
3574 // start-sanitize-tx19
3575 *tx19:
3576 // end-sanitize-tx19
3577 {
3578   unsigned32 instruction = instruction_0;
3579   int destreg = ((instruction >> 6) & 0x0000001F);
3580   int fs = ((instruction >> 11) & 0x0000001F);
3581   int format = ((instruction >> 21) & 0x00000007);
3582   {
3583     if ((format != fmt_single) && (format != fmt_double))
3584       SignalException(ReservedInstruction,instruction);
3585     else
3586       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3587   }
3588 }
3589
3590
3591 // LDC1
3592 110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
3593
3594
3595 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3596 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3597 *mipsIV:
3598 // start-sanitize-r5900
3599 *r5900:
3600 // end-sanitize-r5900
3601 {
3602   unsigned32 instruction = instruction_0;
3603   int destreg = ((instruction >> 6) & 0x0000001F);
3604   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3605   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3606   {
3607     address_word vaddr = ((unsigned64)op1 + op2);
3608     address_word paddr;
3609     int uncached;
3610     if ((vaddr & 7) != 0)
3611       SignalExceptionAddressLoad();
3612     else
3613       {
3614         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3615           {
3616             unsigned64 memval = 0;
3617             unsigned64 memval1 = 0;
3618             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
3619             COP_LD(1,destreg,memval);;
3620           }
3621       }
3622   }
3623 }
3624
3625
3626 // LWC1
3627 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3628
3629
3630 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3631 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3632 *mipsIV:
3633 // start-sanitize-r5900
3634 *r5900:
3635 // end-sanitize-r5900
3636 {
3637   unsigned32 instruction = instruction_0;
3638   int destreg = ((instruction >> 6) & 0x0000001F);
3639   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3640   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3641   {
3642    address_word vaddr = ((unsigned64)op1 + op2);
3643    address_word paddr;
3644    int uncached;
3645    if ((vaddr & 3) != 0)
3646     SignalExceptionAddressLoad();
3647    else
3648    {
3649     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3650     {
3651      unsigned64 memval = 0;
3652      unsigned64 memval1 = 0;
3653      unsigned64 mask = 0x7;
3654      unsigned int shift = 2;
3655      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
3656      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
3657      unsigned int byte;
3658      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
3659      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
3660      byte = ((vaddr & mask) ^ (bigend << shift));
3661      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
3662     }
3663    }
3664   }
3665 }
3666
3667
3668
3669 //
3670 // FIXME: Not correct for mips*
3671 //
3672 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
3673 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3674 *mipsIV:
3675 // start-sanitize-r5900
3676 *r5900:
3677 // end-sanitize-r5900
3678 {
3679   unsigned32 instruction = instruction_0;
3680   int destreg = ((instruction >> 6) & 0x0000001F);
3681   int fs = ((instruction >> 11) & 0x0000001F);
3682   int ft = ((instruction >> 16) & 0x0000001F);
3683   int fr = ((instruction >> 21) & 0x0000001F);
3684   {
3685     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3686   }
3687 }
3688
3689
3690 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
3691 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3692 *mipsIV:
3693 // start-sanitize-r5900
3694 *r5900:
3695 // end-sanitize-r5900
3696 {
3697   unsigned32 instruction = instruction_0;
3698   int destreg = ((instruction >> 6) & 0x0000001F);
3699   int fs = ((instruction >> 11) & 0x0000001F);
3700   int ft = ((instruction >> 16) & 0x0000001F);
3701   int fr = ((instruction >> 21) & 0x0000001F);
3702   {
3703     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3704   }
3705 }
3706
3707
3708 // MFC1
3709 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
3710 "m<X>c1 r<RT>, f<FS>"
3711 *mipsI:
3712 *mipsII:
3713 *mipsIII:
3714 *mipsIV:
3715 // start-sanitize-r5900
3716 *r5900:
3717 // end-sanitize-r5900
3718 *r3900:
3719 // start-sanitize-tx19
3720 *tx19:
3721 // end-sanitize-tx19
3722 {
3723   unsigned32 instruction = instruction_0;
3724   int fs = ((instruction >> 11) & 0x0000001F);
3725   int ft = ((instruction >> 16) & 0x0000001F);
3726   int to = ((instruction >> 23) & 0x00000001);
3727   {
3728     if (to) {
3729       if (SizeFGR() == 64) {
3730         PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
3731       } else {
3732         PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
3733       }
3734     } else {
3735       PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
3736     }
3737   }
3738 }
3739
3740
3741 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3742 "mov.%s<FMT> f<FD>, f<FS>"
3743 *mipsI:
3744 *mipsII:
3745 *mipsIII:
3746 *mipsIV:
3747 // start-sanitize-r5900
3748 *r5900:
3749 // end-sanitize-r5900
3750 *r3900:
3751 // start-sanitize-tx19
3752 *tx19:
3753 // end-sanitize-tx19
3754 {
3755   unsigned32 instruction = instruction_0;
3756   int destreg = ((instruction >> 6) & 0x0000001F);
3757   int fs = ((instruction >> 11) & 0x0000001F);
3758   int format = ((instruction >> 21) & 0x00000007);
3759   {
3760     StoreFPR(destreg,format,ValueFPR(fs,format));
3761   }
3762 }
3763
3764
3765 // MOVF
3766 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
3767 "mov%s<TF> r<RD>, r<RS>, <CC>"
3768 *mipsIV:
3769 // start-sanitize-r5900
3770 *r5900:
3771 // end-sanitize-r5900
3772 {
3773   if (GETFCC(CC) == TF)
3774     GPR[RD] = GPR[RS];
3775 }
3776
3777
3778 // MOVF.fmt
3779 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3780 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3781 *mipsIV:
3782 // start-sanitize-r5900
3783 *r5900:
3784 // end-sanitize-r5900
3785 {
3786   unsigned32 instruction = instruction_0;
3787   int format = ((instruction >> 21) & 0x00000007);
3788   {
3789    if (GETFCC(CC) == TF)
3790      StoreFPR (FD, format, ValueFPR (FS, format));
3791    else
3792      StoreFPR (FD, format, ValueFPR (FD, format));
3793   }
3794 }
3795
3796
3797 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3798 *mipsIV:
3799 // start-sanitize-r5900
3800 *r5900:
3801 // end-sanitize-r5900
3802 {
3803   unsigned32 instruction = instruction_0;
3804   int destreg = ((instruction >> 6) & 0x0000001F);
3805   int fs = ((instruction >> 11) & 0x0000001F);
3806   int format = ((instruction >> 21) & 0x00000007);
3807   {
3808     StoreFPR(destreg,format,ValueFPR(fs,format));
3809   }
3810 }
3811
3812
3813 // MOVT see MOVtf
3814
3815
3816 // MOVT.fmt see MOVtf.fmt
3817
3818
3819
3820 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3821 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3822 *mipsIV:
3823 // start-sanitize-r5900
3824 *r5900:
3825 // end-sanitize-r5900
3826 {
3827   unsigned32 instruction = instruction_0;
3828   int destreg = ((instruction >> 6) & 0x0000001F);
3829   int fs = ((instruction >> 11) & 0x0000001F);
3830   int format = ((instruction >> 21) & 0x00000007);
3831   {
3832    StoreFPR(destreg,format,ValueFPR(fs,format));
3833   }
3834 }
3835
3836
3837 // MSUB.fmt
3838 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3839 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3840 *mipsIV:
3841 // start-sanitize-r5900
3842 *r5900:
3843 // end-sanitize-r5900
3844 {
3845   unsigned32 instruction = instruction_0;
3846   int destreg = ((instruction >> 6) & 0x0000001F);
3847   int fs = ((instruction >> 11) & 0x0000001F);
3848   int ft = ((instruction >> 16) & 0x0000001F);
3849   int fr = ((instruction >> 21) & 0x0000001F);
3850   {
3851     StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3852   }
3853 }
3854
3855
3856 // MSUB.fmt
3857 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3858 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3859 *mipsIV:
3860 // start-sanitize-r5900
3861 *r5900:
3862 // end-sanitize-r5900
3863 {
3864   unsigned32 instruction = instruction_0;
3865   int destreg = ((instruction >> 6) & 0x0000001F);
3866   int fs = ((instruction >> 11) & 0x0000001F);
3867   int ft = ((instruction >> 16) & 0x0000001F);
3868   int fr = ((instruction >> 21) & 0x0000001F);
3869   {
3870    StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3871   }
3872 }
3873
3874
3875 // MTC1 see MxC1
3876
3877
3878 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3879 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3880 *mipsI:
3881 *mipsII:
3882 *mipsIII:
3883 *mipsIV:
3884 // start-sanitize-r5900
3885 *r5900:
3886 // end-sanitize-r5900
3887 *r3900:
3888 // start-sanitize-tx19
3889 *tx19:
3890 // end-sanitize-tx19
3891 {
3892   unsigned32 instruction = instruction_0;
3893   int destreg = ((instruction >> 6) & 0x0000001F);
3894   int fs = ((instruction >> 11) & 0x0000001F);
3895   int ft = ((instruction >> 16) & 0x0000001F);
3896   int format = ((instruction >> 21) & 0x00000007);
3897   {
3898     if ((format != fmt_single) && (format != fmt_double))
3899       SignalException(ReservedInstruction,instruction);
3900     else
3901       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3902   }
3903 }
3904
3905
3906 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3907 "neg.%s<FMT> f<FD>, f<FS>"
3908 *mipsI:
3909 *mipsII:
3910 *mipsIII:
3911 *mipsIV:
3912 // start-sanitize-r5900
3913 *r5900:
3914 // end-sanitize-r5900
3915 *r3900:
3916 // start-sanitize-tx19
3917 *tx19:
3918 // end-sanitize-tx19
3919 {
3920   unsigned32 instruction = instruction_0;
3921   int destreg = ((instruction >> 6) & 0x0000001F);
3922   int fs = ((instruction >> 11) & 0x0000001F);
3923   int format = ((instruction >> 21) & 0x00000007);
3924   {
3925     if ((format != fmt_single) && (format != fmt_double))
3926       SignalException(ReservedInstruction,instruction);
3927     else
3928       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3929   }
3930 }
3931
3932
3933 // NMADD.fmt
3934 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3935 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3936 *mipsIV:
3937 {
3938   unsigned32 instruction = instruction_0;
3939   int destreg = ((instruction >> 6) & 0x0000001F);
3940   int fs = ((instruction >> 11) & 0x0000001F);
3941   int ft = ((instruction >> 16) & 0x0000001F);
3942   int fr = ((instruction >> 21) & 0x0000001F);
3943   {
3944    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3945   }
3946 }
3947
3948
3949 // NMADD.fmt
3950 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3951 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3952 *mipsIV:
3953 {
3954   unsigned32 instruction = instruction_0;
3955   int destreg = ((instruction >> 6) & 0x0000001F);
3956   int fs = ((instruction >> 11) & 0x0000001F);
3957   int ft = ((instruction >> 16) & 0x0000001F);
3958   int fr = ((instruction >> 21) & 0x0000001F);
3959   {
3960    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3961   }
3962 }
3963
3964
3965 // NMSUB.fmt
3966 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3967 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3968 *mipsIV:
3969 {
3970   unsigned32 instruction = instruction_0;
3971   int destreg = ((instruction >> 6) & 0x0000001F);
3972   int fs = ((instruction >> 11) & 0x0000001F);
3973   int ft = ((instruction >> 16) & 0x0000001F);
3974   int fr = ((instruction >> 21) & 0x0000001F);
3975   {
3976    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3977   }
3978 }
3979
3980
3981 // NMSUB.fmt
3982 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
3983 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3984 *mipsIV:
3985 {
3986   unsigned32 instruction = instruction_0;
3987   int destreg = ((instruction >> 6) & 0x0000001F);
3988   int fs = ((instruction >> 11) & 0x0000001F);
3989   int ft = ((instruction >> 16) & 0x0000001F);
3990   int fr = ((instruction >> 21) & 0x0000001F);
3991   {
3992     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3993   }
3994 }
3995
3996
3997 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
3998 "prefx <HINT>, r<INDEX>(r<BASE>)"
3999 *mipsIV:
4000 {
4001   unsigned32 instruction = instruction_0;
4002   int fs = ((instruction >> 11) & 0x0000001F);
4003   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4004   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4005   {
4006     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4007     address_word paddr;
4008     int uncached;
4009     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4010       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4011   }
4012 }
4013
4014 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4015 *mipsIV:
4016 "recip.%s<FMT> f<FD>, f<FS>"
4017 {
4018   unsigned32 instruction = instruction_0;
4019   int destreg = ((instruction >> 6) & 0x0000001F);
4020   int fs = ((instruction >> 11) & 0x0000001F);
4021   int format = ((instruction >> 21) & 0x00000007);
4022   {
4023   if ((format != fmt_single) && (format != fmt_double))
4024    SignalException(ReservedInstruction,instruction);
4025   else
4026    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4027   }
4028 }
4029
4030
4031 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4032 "round.l.%s<FMT> f<FD>, f<FS>"
4033 *mipsIII:
4034 *mipsIV:
4035 // start-sanitize-r5900
4036 *r5900:
4037 // end-sanitize-r5900
4038 *r3900:
4039 // start-sanitize-tx19
4040 *tx19:
4041 // end-sanitize-tx19
4042 {
4043   unsigned32 instruction = instruction_0;
4044   int destreg = ((instruction >> 6) & 0x0000001F);
4045   int fs = ((instruction >> 11) & 0x0000001F);
4046   int format = ((instruction >> 21) & 0x00000007);
4047   {
4048     if ((format != fmt_single) && (format != fmt_double))
4049       SignalException(ReservedInstruction,instruction);
4050     else
4051       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4052   }
4053 }
4054
4055
4056 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4057 "round.w.%s<FMT> f<FD>, f<FS>"
4058 *mipsII:
4059 *mipsIII:
4060 *mipsIV:
4061 // start-sanitize-r5900
4062 *r5900:
4063 // end-sanitize-r5900
4064 *r3900:
4065 // start-sanitize-tx19
4066 *tx19:
4067 // end-sanitize-tx19
4068 {
4069   unsigned32 instruction = instruction_0;
4070   int destreg = ((instruction >> 6) & 0x0000001F);
4071   int fs = ((instruction >> 11) & 0x0000001F);
4072   int format = ((instruction >> 21) & 0x00000007);
4073   {
4074   if ((format != fmt_single) && (format != fmt_double))
4075    SignalException(ReservedInstruction,instruction);
4076   else
4077    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4078   }
4079 }
4080
4081
4082 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4083 *mipsIV:
4084 "rsqrt.%s<FMT> f<FD>, f<FS>"
4085 {
4086   unsigned32 instruction = instruction_0;
4087   int destreg = ((instruction >> 6) & 0x0000001F);
4088   int fs = ((instruction >> 11) & 0x0000001F);
4089   int format = ((instruction >> 21) & 0x00000007);
4090   {
4091   if ((format != fmt_single) && (format != fmt_double))
4092    SignalException(ReservedInstruction,instruction);
4093   else
4094    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4095   }
4096 }
4097
4098
4099 // SDC1
4100
4101
4102 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4103 *mipsIV:
4104 // start-sanitize-r5900
4105 *r5900:
4106 // end-sanitize-r5900
4107 {
4108   unsigned32 instruction = instruction_0;
4109   int fs = ((instruction >> 11) & 0x0000001F);
4110   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4111   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4112   {
4113     address_word vaddr = ((unsigned64)op1 + op2);
4114     address_word paddr;
4115     int uncached;
4116     if ((vaddr & 7) != 0)
4117       SignalExceptionAddressStore();
4118     else
4119       {
4120         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4121           {
4122             unsigned64 memval = 0;
4123             unsigned64 memval1 = 0;
4124             memval = (unsigned64)COP_SD(1,fs);
4125             {
4126               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4127             }
4128           }
4129       }
4130   }
4131 }
4132
4133
4134 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4135 "sqrt.%s<FMT> f<FD>, f<FS>"
4136 *mipsII:
4137 *mipsIII:
4138 *mipsIV:
4139 // start-sanitize-r5900
4140 *r5900:
4141 // end-sanitize-r5900
4142 *r3900:
4143 // start-sanitize-tx19
4144 *tx19:
4145 // end-sanitize-tx19
4146 {
4147   unsigned32 instruction = instruction_0;
4148   int destreg = ((instruction >> 6) & 0x0000001F);
4149   int fs = ((instruction >> 11) & 0x0000001F);
4150   int format = ((instruction >> 21) & 0x00000007);
4151   {
4152     if ((format != fmt_single) && (format != fmt_double))
4153       SignalException(ReservedInstruction,instruction);
4154     else
4155       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4156   }
4157 }
4158
4159
4160 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4161 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4162 *mipsI:
4163 *mipsII:
4164 *mipsIII:
4165 *mipsIV:
4166 // start-sanitize-r5900
4167 *r5900:
4168 // end-sanitize-r5900
4169 *r3900:
4170 // start-sanitize-tx19
4171 *tx19:
4172 // end-sanitize-tx19
4173 {
4174   unsigned32 instruction = instruction_0;
4175   int destreg = ((instruction >> 6) & 0x0000001F);
4176   int fs = ((instruction >> 11) & 0x0000001F);
4177   int ft = ((instruction >> 16) & 0x0000001F);
4178   int format = ((instruction >> 21) & 0x00000007);
4179   {
4180     if ((format != fmt_single) && (format != fmt_double))
4181       SignalException(ReservedInstruction,instruction);
4182     else
4183       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4184   }
4185 }
4186
4187
4188 // SWC1
4189
4190
4191 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4192 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4193 *mipsIV:
4194 // start-sanitize-r5900
4195 *r5900:
4196 // end-sanitize-r5900
4197 {
4198   unsigned32 instruction = instruction_0;
4199   int fs = ((instruction >> 11) & 0x0000001F);
4200   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4201   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4202   {
4203    address_word vaddr = ((unsigned64)op1 + op2);
4204    address_word paddr;
4205    int uncached;
4206    if ((vaddr & 3) != 0)
4207     SignalExceptionAddressStore();
4208    else
4209    {
4210     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4211     {
4212      unsigned64 memval = 0;
4213      unsigned64 memval1 = 0;
4214      unsigned64 mask = 0x7;
4215      unsigned int byte;
4216      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4217      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4218      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4219       {
4220        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4221       }
4222     }
4223    }
4224   }
4225 }
4226
4227
4228 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4229 "trunc.l.%s<FMT> f<FD>, f<FS>"
4230 *mipsIII:
4231 *mipsIV:
4232 // start-sanitize-r5900
4233 *r5900:
4234 // end-sanitize-r5900
4235 *r3900:
4236 // start-sanitize-tx19
4237 *tx19:
4238 // end-sanitize-tx19
4239 {
4240   unsigned32 instruction = instruction_0;
4241   int destreg = ((instruction >> 6) & 0x0000001F);
4242   int fs = ((instruction >> 11) & 0x0000001F);
4243   int format = ((instruction >> 21) & 0x00000007);
4244   {
4245   if ((format != fmt_single) && (format != fmt_double))
4246    SignalException(ReservedInstruction,instruction);
4247   else
4248    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4249   }
4250 }
4251
4252
4253 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4254 "trunc.w.%s<FMT> f<FD>, f<FS>"
4255 *mipsII:
4256 *mipsIII:
4257 *mipsIV:
4258 // start-sanitize-r5900
4259 *r5900:
4260 // end-sanitize-r5900
4261 *r3900:
4262 // start-sanitize-tx19
4263 *tx19:
4264 // end-sanitize-tx19
4265 {
4266   unsigned32 instruction = instruction_0;
4267   int destreg = ((instruction >> 6) & 0x0000001F);
4268   int fs = ((instruction >> 11) & 0x0000001F);
4269   int format = ((instruction >> 21) & 0x00000007);
4270   {
4271   if ((format != fmt_single) && (format != fmt_double))
4272    SignalException(ReservedInstruction,instruction);
4273   else
4274    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4275   }
4276 }
4277
4278 \f
4279 //
4280 // MIPS Architecture:
4281 //
4282 //        System Control Instruction Set (COP0)
4283 //
4284
4285
4286 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4287 "bc0f <OFFSET>"
4288 *mipsI:
4289 *mipsII:
4290 *mipsIII:
4291 *mipsIV:
4292 // start-sanitize-r5900
4293 *r5900:
4294 // end-sanitize-r5900
4295
4296
4297 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4298 "bc0fl <OFFSET>"
4299 *mipsI:
4300 *mipsII:
4301 *mipsIII:
4302 *mipsIV:
4303 // start-sanitize-r5900
4304 *r5900:
4305 // end-sanitize-r5900
4306
4307
4308 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4309 "bc0t <OFFSET>"
4310 *mipsI:
4311 *mipsII:
4312 *mipsIII:
4313 *mipsIV:
4314 // start-sanitize-r5900
4315 *r5900:
4316 // end-sanitize-r5900
4317
4318
4319
4320 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4321 "bc0tl <OFFSET>"
4322 *mipsI:
4323 *mipsII:
4324 *mipsIII:
4325 *mipsIV:
4326 // start-sanitize-r5900
4327 *r5900:
4328 // end-sanitize-r5900
4329
4330
4331 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4332 *mipsIII:
4333 *mipsIV:
4334 // start-sanitize-r5900
4335 *r5900:
4336 // end-sanitize-r5900
4337 *r3900:
4338 // start-sanitize-tx19
4339 *tx19:
4340 // end-sanitize-tx19
4341 {
4342   unsigned32 instruction = instruction_0;
4343   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4344   int hint = ((instruction >> 16) & 0x0000001F);
4345   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4346   {
4347     address_word vaddr = (op1 + offset);
4348     address_word paddr;
4349     int uncached;
4350     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4351       CacheOp(hint,vaddr,paddr,instruction);
4352   }
4353 }
4354
4355
4356 010000,10000,000000000000000,111001:COP0:32::DI
4357 "di"
4358 *mipsI:
4359 *mipsII:
4360 *mipsIII:
4361 *mipsIV:
4362 // start-sanitize-r5900
4363 *r5900:
4364 // end-sanitize-r5900
4365
4366
4367 010000,10000,000000000000000,111000:COP0:32::EI
4368 "ei"
4369 *mipsI:
4370 *mipsII:
4371 *mipsIII:
4372 *mipsIV:
4373 // start-sanitize-r5900
4374 *r5900:
4375 // end-sanitize-r5900
4376
4377
4378 010000,10000,000000000000000,011000:COP0:32::ERET
4379 "eret"
4380 *mipsIII:
4381 *mipsIV:
4382 // start-sanitize-r5900
4383 *r5900:
4384 // end-sanitize-r5900
4385
4386
4387 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4388 "mfc0 r<RT>, r<RD> # <REGX>"
4389 *mipsI:
4390 *mipsII:
4391 *mipsIII:
4392 *mipsIV:
4393 // start-sanitize-r5900
4394 *r5900:
4395 // end-sanitize-r5900
4396
4397
4398 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4399 "mtc0 r<RT>, r<RD> # <REGX>"
4400 *mipsI:
4401 *mipsII:
4402 *mipsIII:
4403 *mipsIV:
4404 // start-sanitize-r5900
4405 *r5900:
4406 // end-sanitize-r5900
4407
4408
4409 010000,10000,000000000000000,001000:COP0:32::TLBP
4410 "tlbp"
4411 *mipsI:
4412 *mipsII:
4413 *mipsIII:
4414 *mipsIV:
4415 // start-sanitize-r5900
4416 *r5900:
4417 // end-sanitize-r5900
4418
4419
4420 010000,10000,000000000000000,000001:COP0:32::TLBR
4421 "tlbr"
4422 *mipsI:
4423 *mipsII:
4424 *mipsIII:
4425 *mipsIV:
4426 // start-sanitize-r5900
4427 *r5900:
4428 // end-sanitize-r5900
4429
4430
4431 010000,10000,000000000000000,000010:COP0:32::TLBWI
4432 "tlbwi"
4433 *mipsI:
4434 *mipsII:
4435 *mipsIII:
4436 *mipsIV:
4437 // start-sanitize-r5900
4438 *r5900:
4439 // end-sanitize-r5900
4440
4441
4442 010000,10000,000000000000000,000110:COP0:32::TLBWR
4443 "tlbwr"
4444 *mipsI:
4445 *mipsII:
4446 *mipsIII:
4447 *mipsIV:
4448 // start-sanitize-r5900
4449 *r5900:
4450 // end-sanitize-r5900
4451
4452 \f
4453 //
4454 // MIPS Architecture:
4455 //
4456 //        CPU Instruction Set (mips16)
4457 //
4458
4459 // The instructions in this section are ordered according
4460 // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
4461
4462
4463 // FIXME: Instead of having the code for mips16 instructions here.
4464 // these instructions should instead call the corresponding 32bit
4465 // instruction (or a function implementing that instructions code).
4466
4467
4468 // Load and Store Instructions
4469
4470
4471 10000,xxx,ddd,55555:RRI:16::LB
4472 *mips16:
4473 {
4474   unsigned32 instruction = instruction_0;
4475   signed_word op1 = (instruction >> 8) & 0x7;
4476   int destreg = (instruction >> 5) & 0x7;
4477   int offset = (instruction >> 0) & 0x1f;
4478   if (op1 < 2)
4479     op1 += 16;
4480   op1 = GPR[op1];
4481   if (destreg < 2)
4482     destreg += 16;
4483   if (have_extendval)
4484     {
4485       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4486       if (offset >= 0x8000)
4487         offset -= 0x10000;
4488       have_extendval = 0;
4489     }
4490   else
4491     {
4492     }
4493   if (have_extendval)
4494     SignalException (ReservedInstruction, instruction);
4495   {
4496     address_word vaddr = ((unsigned64)op1 + offset);
4497     address_word paddr;
4498     int uncached;
4499     {
4500       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4501         {
4502           unsigned64 memval = 0;
4503           unsigned64 memval1 = 0;
4504           unsigned64 mask = 0x7;
4505           unsigned int shift = 0;
4506           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4507           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4508           unsigned int byte;
4509           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4510           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
4511           byte = ((vaddr & mask) ^ (bigend << shift));
4512           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
4513         }
4514     }
4515   }
4516 }
4517
4518
4519 10100,xxx,ddd,55555:RRI:16::LBU
4520 *mips16:
4521 {
4522   unsigned32 instruction = instruction_0;
4523   signed_word op1 = (instruction >> 8) & 0x7;
4524   int destreg = (instruction >> 5) & 0x7;
4525   int offset = (instruction >> 0) & 0x1f;
4526   if (op1 < 2)
4527     op1 += 16;
4528   op1 = GPR[op1];
4529   if (destreg < 2)
4530     destreg += 16;
4531   if (have_extendval)
4532     {
4533       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4534       if (offset >= 0x8000)
4535         offset -= 0x10000;
4536       have_extendval = 0;
4537     }
4538   else
4539     {
4540     }
4541   if (have_extendval)
4542     SignalException (ReservedInstruction, instruction);
4543   {
4544     address_word vaddr = ((unsigned64)op1 + offset);
4545     address_word paddr;
4546     int uncached;
4547     {
4548       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4549         {
4550           unsigned64 memval = 0;
4551           unsigned64 memval1 = 0;
4552           unsigned64 mask = 0x7;
4553           unsigned int shift = 0;
4554           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4555           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4556           unsigned int byte;
4557           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4558           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
4559           byte = ((vaddr & mask) ^ (bigend << shift));
4560           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
4561         }
4562     }
4563   }
4564 }
4565
4566
4567 10001,xxx,ddd,HHHHH:RRI:16::LH
4568 *mips16:
4569 {
4570   unsigned32 instruction = instruction_0;
4571   signed_word op1 = (instruction >> 8) & 0x7;
4572   int destreg = (instruction >> 5) & 0x7;
4573   int offset = (instruction >> 0) & 0x1f;
4574   if (op1 < 2)
4575     op1 += 16;
4576   op1 = GPR[op1];
4577   if (destreg < 2)
4578     destreg += 16;
4579   if (have_extendval)
4580     {
4581       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4582       if (offset >= 0x8000)
4583         offset -= 0x10000;
4584       have_extendval = 0;
4585     }
4586   else
4587     {
4588       offset <<= 1;
4589     }
4590   if (have_extendval)
4591     SignalException (ReservedInstruction, instruction);
4592   {
4593     address_word vaddr = ((unsigned64)op1 + offset);
4594     address_word paddr;
4595     int uncached;
4596     if ((vaddr & 1) != 0)
4597       SignalExceptionAddressLoad();
4598     else
4599       {
4600         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4601           {
4602             unsigned64 memval = 0;
4603             unsigned64 memval1 = 0;
4604             unsigned64 mask = 0x7;
4605             unsigned int shift = 1;
4606             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4607             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4608             unsigned int byte;
4609             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4610             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
4611             byte = ((vaddr & mask) ^ (bigend << shift));
4612             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
4613           }
4614       }
4615   }
4616 }
4617
4618
4619 10101,xxx,ddd,HHHHH:RRI:16::LHU
4620 *mips16:
4621 {
4622   unsigned32 instruction = instruction_0;
4623   signed_word op1 = (instruction >> 8) & 0x7;
4624   int destreg = (instruction >> 5) & 0x7;
4625   int offset = (instruction >> 0) & 0x1f;
4626   if (op1 < 2)
4627     op1 += 16;
4628   op1 = GPR[op1];
4629   if (destreg < 2)
4630     destreg += 16;
4631   if (have_extendval)
4632     {
4633       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4634       if (offset >= 0x8000)
4635         offset -= 0x10000;
4636       have_extendval = 0;
4637     }
4638   else
4639     {
4640       offset <<= 1;
4641     }
4642   if (have_extendval)
4643     SignalException (ReservedInstruction, instruction);
4644   {
4645     address_word vaddr = ((unsigned64)op1 + offset);
4646     address_word paddr;
4647     int uncached;
4648     if ((vaddr & 1) != 0)
4649       SignalExceptionAddressLoad();
4650     else
4651       {
4652         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4653           {
4654             unsigned64 memval = 0;
4655             unsigned64 memval1 = 0;
4656             unsigned64 mask = 0x7;
4657             unsigned int shift = 1;
4658             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4659             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4660             unsigned int byte;
4661             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4662             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
4663             byte = ((vaddr & mask) ^ (bigend << shift));
4664             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
4665           }
4666       }
4667   }
4668 }
4669
4670
4671 10011,xxx,ddd,WWWWW:RRI:16::LW
4672 *mips16:
4673 {
4674   unsigned32 instruction = instruction_0;
4675   signed_word op1 = (instruction >> 8) & 0x7;
4676   int destreg = (instruction >> 5) & 0x7;
4677   int offset = (instruction >> 0) & 0x1f;
4678   if (op1 < 2)
4679     op1 += 16;
4680   op1 = GPR[op1];
4681   if (destreg < 2)
4682     destreg += 16;
4683   if (have_extendval)
4684     {
4685       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4686       if (offset >= 0x8000)
4687         offset -= 0x10000;
4688       have_extendval = 0;
4689     }
4690   else
4691     {
4692       offset <<= 2;
4693     }
4694   if (have_extendval)
4695     SignalException (ReservedInstruction, instruction);
4696   {
4697     address_word vaddr = ((unsigned64)op1 + offset);
4698     address_word paddr;
4699     int uncached;
4700     if ((vaddr & 3) != 0)
4701       SignalExceptionAddressLoad();
4702     else
4703       {
4704         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4705           {
4706             unsigned64 memval = 0;
4707             unsigned64 memval1 = 0;
4708             unsigned64 mask = 0x7;
4709             unsigned int shift = 2;
4710             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4711             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4712             unsigned int byte;
4713             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4714             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4715             byte = ((vaddr & mask) ^ (bigend << shift));
4716             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4717           }
4718       }
4719   }
4720 }
4721
4722
4723 10110,ddd,VVVVVVVV,P:RI:16::LWPC
4724 *mips16:
4725 {
4726   unsigned32 instruction = instruction_0;
4727   int destreg = (instruction >> 8) & 0x7;
4728   int offset = (instruction >> 0) & 0xff;
4729   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
4730   if (destreg < 2)
4731     destreg += 16;
4732   if (have_extendval)
4733     {
4734       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4735       if (offset >= 0x8000)
4736         offset -= 0x10000;
4737       have_extendval = 0;
4738     }
4739   else
4740     {
4741       offset <<= 2;
4742     }
4743   if (have_extendval)
4744     SignalException (ReservedInstruction, instruction);
4745   {
4746     address_word vaddr = ((unsigned64)op1 + offset);
4747     address_word paddr;
4748     int uncached;
4749     if ((vaddr & 3) != 0)
4750       SignalExceptionAddressLoad();
4751     else
4752       {
4753         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4754           {
4755             unsigned64 memval = 0;
4756             unsigned64 memval1 = 0;
4757             unsigned64 mask = 0x7;
4758             unsigned int shift = 2;
4759             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4760             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4761             unsigned int byte;
4762             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4763             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4764             byte = ((vaddr & mask) ^ (bigend << shift));
4765             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4766           }
4767       }
4768   }
4769 }
4770
4771
4772 10010,ddd,VVVVVVVV,s:RI:16::LWSP
4773 *mips16:
4774 {
4775   unsigned32 instruction = instruction_0;
4776   int destreg = (instruction >> 8) & 0x7;
4777   int offset = (instruction >> 0) & 0xff;
4778   signed_word op1 = 29;
4779   if (destreg < 2)
4780     destreg += 16;
4781   if (have_extendval)
4782     {
4783       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4784       if (offset >= 0x8000)
4785         offset -= 0x10000;
4786       have_extendval = 0;
4787     }
4788   else
4789     {
4790       offset <<= 2;
4791     }
4792   op1 = GPR[op1];
4793   if (have_extendval)
4794     SignalException (ReservedInstruction, instruction);
4795   {
4796     address_word vaddr = ((unsigned64)op1 + offset);
4797     address_word paddr;
4798     int uncached;
4799     if ((vaddr & 3) != 0)
4800       SignalExceptionAddressLoad();
4801     else
4802       {
4803         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4804           {
4805             unsigned64 memval = 0;
4806             unsigned64 memval1 = 0;
4807             unsigned64 mask = 0x7;
4808             unsigned int shift = 2;
4809             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4810             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4811             unsigned int byte;
4812             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4813             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4814             byte = ((vaddr & mask) ^ (bigend << shift));
4815             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4816           }
4817       }
4818   }
4819 }
4820
4821
4822 10111,xxx,ddd,WWWWW:RRI:16::LWU
4823 *mips16:
4824 {
4825   unsigned32 instruction = instruction_0;
4826   signed_word op1 = (instruction >> 8) & 0x7;
4827   int destreg = (instruction >> 5) & 0x7;
4828   int offset = (instruction >> 0) & 0x1f;
4829   if (op1 < 2)
4830     op1 += 16;
4831   op1 = GPR[op1];
4832   if (destreg < 2)
4833     destreg += 16;
4834   if (have_extendval)
4835     {
4836       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4837       if (offset >= 0x8000)
4838         offset -= 0x10000;
4839       have_extendval = 0;
4840     }
4841   else
4842     {
4843       offset <<= 2;
4844     }
4845   if (have_extendval)
4846     SignalException (ReservedInstruction, instruction);
4847   {
4848     address_word vaddr = ((unsigned64)op1 + offset);
4849     address_word paddr;
4850     int uncached;
4851     if ((vaddr & 3) != 0)
4852       SignalExceptionAddressLoad();
4853     else
4854       {
4855         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4856           {
4857             unsigned64 memval = 0;
4858             unsigned64 memval1 = 0;
4859             unsigned64 mask = 0x7;
4860             unsigned int shift = 2;
4861             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4862             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4863             unsigned int byte;
4864             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4865             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4866             byte = ((vaddr & mask) ^ (bigend << shift));
4867             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
4868           }
4869       }
4870   }
4871 }
4872
4873
4874 00111,xxx,ddd,DDDDD:RRI:16::LD
4875 *mips16:
4876 {
4877   unsigned32 instruction = instruction_0;
4878   signed_word op1 = (instruction >> 8) & 0x7;
4879   int destreg = (instruction >> 5) & 0x7;
4880   int offset = (instruction >> 0) & 0x1f;
4881   if (op1 < 2)
4882     op1 += 16;
4883   op1 = GPR[op1];
4884   if (destreg < 2)
4885     destreg += 16;
4886   if (have_extendval)
4887     {
4888       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4889       if (offset >= 0x8000)
4890         offset -= 0x10000;
4891       have_extendval = 0;
4892     }
4893   else
4894     {
4895       offset <<= 3;
4896     }
4897   if (have_extendval)
4898     SignalException (ReservedInstruction, instruction);
4899   {
4900     address_word vaddr = ((unsigned64)op1 + offset);
4901     address_word paddr;
4902     int uncached;
4903     if ((vaddr & 7) != 0)
4904       SignalExceptionAddressLoad();
4905     else
4906       {
4907         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4908           {
4909             unsigned64 memval = 0;
4910             unsigned64 memval1 = 0;
4911             unsigned64 mask = 0x7;
4912             unsigned int shift = 4;
4913             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4914             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4915             unsigned int byte;
4916             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4917             GPR[destreg] = memval;
4918           }
4919       }
4920   }
4921 }
4922
4923
4924 11111100,ddd,5.RD,P:RI64:16::LDPC
4925 *mips16:
4926 {
4927   unsigned32 instruction = instruction_0;
4928   int destreg = (instruction >> 5) & 0x7;
4929   int offset = (instruction >> 0) & 0x1f;
4930   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7;
4931   if (destreg < 2)
4932     destreg += 16;
4933   if (have_extendval)
4934     {
4935       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4936       if (offset >= 0x8000)
4937         offset -= 0x10000;
4938       have_extendval = 0;
4939     }
4940   else
4941     {
4942       offset <<= 3;
4943     }
4944   if (have_extendval)
4945     SignalException (ReservedInstruction, instruction);
4946   {
4947     address_word vaddr = ((unsigned64)op1 + offset);
4948     address_word paddr;
4949     int uncached;
4950     if ((vaddr & 7) != 0)
4951       SignalExceptionAddressLoad();
4952     else
4953       {
4954         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4955           {
4956             unsigned64 memval = 0;
4957             unsigned64 memval1 = 0;
4958             unsigned64 mask = 0x7;
4959             unsigned int shift = 4;
4960             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4961             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4962             unsigned int byte;
4963             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4964             GPR[destreg] = memval;
4965           }
4966       }
4967   }
4968 }
4969
4970
4971 11111000,ddd,5.RD,s:RI64:16::LDSP
4972 *mips16:
4973 {
4974   unsigned32 instruction = instruction_0;
4975   int destreg = (instruction >> 5) & 0x7;
4976   int offset = (instruction >> 0) & 0x1f;
4977   signed_word op1 = 29;
4978   if (destreg < 2)
4979     destreg += 16;
4980   if (have_extendval)
4981     {
4982       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4983       if (offset >= 0x8000)
4984         offset -= 0x10000;
4985       have_extendval = 0;
4986     }
4987   else
4988     {
4989       offset <<= 3;
4990     }
4991   op1 = GPR[op1];
4992   if (have_extendval)
4993     SignalException (ReservedInstruction, instruction);
4994   {
4995     address_word vaddr = ((unsigned64)op1 + offset);
4996     address_word paddr;
4997     int uncached;
4998     if ((vaddr & 7) != 0)
4999       SignalExceptionAddressLoad();
5000     else
5001       {
5002         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5003           {
5004             unsigned64 memval = 0;
5005             unsigned64 memval1 = 0;
5006             unsigned64 mask = 0x7;
5007             unsigned int shift = 4;
5008             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5009             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5010             unsigned int byte;
5011             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
5012             GPR[destreg] = memval;
5013           }
5014       }
5015   }
5016 }
5017
5018
5019 11000,xxx,yyy,55555:RRI:16::SB
5020 *mips16:
5021 {
5022   unsigned32 instruction = instruction_0;
5023   signed_word op1 = (instruction >> 8) & 0x7;
5024   signed_word op2 = (instruction >> 5) & 0x7;
5025   int offset = (instruction >> 0) & 0x1f;
5026   if (op1 < 2)
5027     op1 += 16;
5028   op1 = GPR[op1];
5029   if (op2 < 2)
5030     op2 += 16;
5031   op2 = GPR[op2];
5032   if (have_extendval)
5033     {
5034       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5035       if (offset >= 0x8000)
5036         offset -= 0x10000;
5037       have_extendval = 0;
5038     }
5039   else
5040     {
5041     }
5042   if (have_extendval)
5043     SignalException (ReservedInstruction, instruction);
5044   {
5045     address_word vaddr = ((unsigned64)op1 + offset);
5046     address_word paddr;
5047     int uncached;
5048     {
5049       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5050         {
5051           unsigned64 memval = 0;
5052           unsigned64 memval1 = 0;
5053           unsigned64 mask = 0x7;
5054           unsigned int shift = 0;
5055           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5056           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5057           unsigned int byte;
5058           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5059           byte = ((vaddr & mask) ^ (bigend << shift));
5060           memval = ((unsigned64) op2 << (8 * byte));
5061           {
5062             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
5063           }
5064         }
5065     }
5066   }
5067 }
5068
5069
5070 11001,xxx,yyy,HHHHH:RRI:16::SH
5071 *mips16:
5072 {
5073   unsigned32 instruction = instruction_0;
5074   signed_word op1 = (instruction >> 8) & 0x7;
5075   signed_word op2 = (instruction >> 5) & 0x7;
5076   int offset = (instruction >> 0) & 0x1f;
5077   if (op1 < 2)
5078     op1 += 16;
5079   op1 = GPR[op1];
5080   if (op2 < 2)
5081     op2 += 16;
5082   op2 = GPR[op2];
5083   if (have_extendval)
5084     {
5085       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5086       if (offset >= 0x8000)
5087         offset -= 0x10000;
5088       have_extendval = 0;
5089     }
5090   else
5091     {
5092       offset <<= 1;
5093     }
5094   if (have_extendval)
5095     SignalException (ReservedInstruction, instruction);
5096   {
5097     address_word vaddr = ((unsigned64)op1 + offset);
5098     address_word paddr;
5099     int uncached;
5100     if ((vaddr & 1) != 0)
5101       SignalExceptionAddressStore();
5102     else
5103       {
5104         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5105           {
5106             unsigned64 memval = 0;
5107             unsigned64 memval1 = 0;
5108             unsigned64 mask = 0x7;
5109             unsigned int shift = 1;
5110             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5111             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5112             unsigned int byte;
5113             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5114             byte = ((vaddr & mask) ^ (bigend << shift));
5115             memval = ((unsigned64) op2 << (8 * byte));
5116             {
5117               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
5118             }
5119           }
5120       }
5121   }
5122 }
5123
5124
5125 11011,xxx,yyy,WWWWW:RRI:16::SW
5126 *mips16:
5127 {
5128   unsigned32 instruction = instruction_0;
5129   signed_word op1 = (instruction >> 8) & 0x7;
5130   signed_word op2 = (instruction >> 5) & 0x7;
5131   int offset = (instruction >> 0) & 0x1f;
5132   if (op1 < 2)
5133     op1 += 16;
5134   op1 = GPR[op1];
5135   if (op2 < 2)
5136     op2 += 16;
5137   op2 = GPR[op2];
5138   if (have_extendval)
5139     {
5140       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5141       if (offset >= 0x8000)
5142         offset -= 0x10000;
5143       have_extendval = 0;
5144     }
5145   else
5146     {
5147       offset <<= 2;
5148     }
5149   if (have_extendval)
5150     SignalException (ReservedInstruction, instruction);
5151   {
5152     address_word vaddr = ((unsigned64)op1 + offset);
5153     address_word paddr;
5154     int uncached;
5155     if ((vaddr & 3) != 0)
5156       SignalExceptionAddressStore();
5157     else
5158       {
5159         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5160           {
5161             unsigned64 memval = 0;
5162             unsigned64 memval1 = 0;
5163             unsigned64 mask = 0x7;
5164             unsigned int byte;
5165             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5166             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5167             memval = ((unsigned64) op2 << (8 * byte));
5168             {
5169               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5170             }
5171           }
5172       }
5173   }
5174 }
5175
5176
5177 11010,yyy,VVVVVVVV,s:RI:16::SWSP
5178 *mips16:
5179 {
5180   unsigned32 instruction = instruction_0;
5181   signed_word op2 = (instruction >> 8) & 0x7;
5182   int offset = (instruction >> 0) & 0xff;
5183   signed_word op1 = 29;
5184   if (op2 < 2)
5185     op2 += 16;
5186   op2 = GPR[op2];
5187   if (have_extendval)
5188     {
5189       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5190       if (offset >= 0x8000)
5191         offset -= 0x10000;
5192       have_extendval = 0;
5193     }
5194   else
5195     {
5196       offset <<= 2;
5197     }
5198   op1 = GPR[op1];
5199   if (have_extendval)
5200     SignalException (ReservedInstruction, instruction);
5201   {
5202     address_word vaddr = ((unsigned64)op1 + offset);
5203     address_word paddr;
5204     int uncached;
5205     if ((vaddr & 3) != 0)
5206       SignalExceptionAddressStore();
5207     else
5208       {
5209         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5210           {
5211             unsigned64 memval = 0;
5212             unsigned64 memval1 = 0;
5213             unsigned64 mask = 0x7;
5214             unsigned int byte;
5215             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5216             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5217             memval = ((unsigned64) op2 << (8 * byte));
5218             {
5219               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5220             }
5221           }
5222       }
5223   }
5224 }
5225
5226
5227 01100010,VVVVVVVV,Q,s:I8:16::SWRASP
5228 *mips16:
5229 {
5230   unsigned32 instruction = instruction_0;
5231   int offset = (instruction >> 0) & 0xff;
5232   signed_word op2 = 31;
5233   signed_word op1 = 29;
5234   if (have_extendval)
5235     {
5236       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5237       if (offset >= 0x8000)
5238         offset -= 0x10000;
5239       have_extendval = 0;
5240     }
5241   else
5242     {
5243       offset <<= 2;
5244     }
5245   op2 = GPR[op2];
5246   op1 = GPR[op1];
5247   if (have_extendval)
5248     SignalException (ReservedInstruction, instruction);
5249   {
5250     address_word vaddr = ((unsigned64)op1 + offset);
5251     address_word paddr;
5252     int uncached;
5253     if ((vaddr & 3) != 0)
5254       SignalExceptionAddressStore();
5255     else
5256       {
5257         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5258           {
5259             unsigned64 memval = 0;
5260             unsigned64 memval1 = 0;
5261             unsigned64 mask = 0x7;
5262             unsigned int byte;
5263             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5264             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5265             memval = ((unsigned64) op2 << (8 * byte));
5266             {
5267               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5268             }
5269           }
5270       }
5271   }
5272 }
5273
5274
5275 01111,xxx,yyy,DDDDD:RRI:16::SD
5276 *mips16:
5277 {
5278   unsigned32 instruction = instruction_0;
5279   signed_word op1 = (instruction >> 8) & 0x7;
5280   signed_word op2 = (instruction >> 5) & 0x7;
5281   int offset = (instruction >> 0) & 0x1f;
5282   if (op1 < 2)
5283     op1 += 16;
5284   op1 = GPR[op1];
5285   if (op2 < 2)
5286     op2 += 16;
5287   op2 = GPR[op2];
5288   if (have_extendval)
5289     {
5290       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5291       if (offset >= 0x8000)
5292         offset -= 0x10000;
5293       have_extendval = 0;
5294     }
5295   else
5296     {
5297       offset <<= 3;
5298     }
5299   if (have_extendval)
5300     SignalException (ReservedInstruction, instruction);
5301   {
5302     address_word vaddr = ((unsigned64)op1 + offset);
5303     address_word paddr;
5304     int uncached;
5305     if ((vaddr & 7) != 0)
5306       SignalExceptionAddressStore();
5307     else
5308       {
5309         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5310           {
5311             unsigned64 memval = 0;
5312             unsigned64 memval1 = 0;
5313             memval = op2;
5314             {
5315               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5316             }
5317           }
5318       }
5319   }
5320 }
5321
5322
5323 11111001,yyy,5.RD,s:RI64:16::SDSP
5324 *mips16:
5325 {
5326   unsigned32 instruction = instruction_0;
5327   signed_word op2 = (instruction >> 5) & 0x7;
5328   int offset = (instruction >> 0) & 0x1f;
5329   signed_word op1 = 29;
5330   if (op2 < 2)
5331     op2 += 16;
5332   op2 = GPR[op2];
5333   if (have_extendval)
5334     {
5335       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5336       if (offset >= 0x8000)
5337         offset -= 0x10000;
5338       have_extendval = 0;
5339     }
5340   else
5341     {
5342       offset <<= 3;
5343     }
5344   op1 = GPR[op1];
5345   if (have_extendval)
5346     SignalException (ReservedInstruction, instruction);
5347   {
5348     address_word vaddr = ((unsigned64)op1 + offset);
5349     address_word paddr;
5350     int uncached;
5351     if ((vaddr & 7) != 0)
5352       SignalExceptionAddressStore();
5353     else
5354       {
5355         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5356           {
5357             unsigned64 memval = 0;
5358             unsigned64 memval1 = 0;
5359             memval = op2;
5360             {
5361               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5362             }
5363           }
5364       }
5365   }
5366 }
5367
5368
5369 11111010,CCCCCCCC,s,Q:I64:16::SDRASP
5370 *mips16:
5371 {
5372   unsigned32 instruction = instruction_0;
5373   int offset = (instruction >> 0) & 0xff;
5374   signed_word op1 = 29;
5375   signed_word op2 = 31;
5376   if (have_extendval)
5377     {
5378       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5379       if (offset >= 0x8000)
5380         offset -= 0x10000;
5381       have_extendval = 0;
5382     }
5383   else
5384     {
5385       offset <<= 3;
5386     }
5387   op1 = GPR[op1];
5388   op2 = GPR[op2];
5389   if (have_extendval)
5390     SignalException (ReservedInstruction, instruction);
5391   {
5392     address_word vaddr = ((unsigned64)op1 + offset);
5393     address_word paddr;
5394     int uncached;
5395     if ((vaddr & 7) != 0)
5396       SignalExceptionAddressStore();
5397     else
5398       {
5399         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5400           {
5401             unsigned64 memval = 0;
5402             unsigned64 memval1 = 0;
5403             memval = op2;
5404             {
5405               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5406             }
5407           }
5408       }
5409   }
5410 }
5411
5412
5413 // ALU Immediate Instructions
5414
5415
5416 01101,ddd,UUUUUUUU,Z:RI:16::LI
5417 *mips16:
5418 {
5419   unsigned32 instruction = instruction_0;
5420   int destreg = (instruction >> 8) & 0x7;
5421   int op2 = (instruction >> 0) & 0xff;
5422   signed_word op1 = 0;
5423   if (destreg < 2)
5424     destreg += 16;
5425   if (have_extendval)
5426     {
5427       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5428       have_extendval = 0;
5429     }
5430   else
5431     {
5432     }
5433   if (have_extendval)
5434     SignalException (ReservedInstruction, instruction);
5435   {
5436     if (destreg != 0)
5437       GPR[destreg] = (op1 | op2);
5438   }
5439 }
5440
5441
5442 01000,xxx,ddd,04444:RRI_A:16::ADDIU
5443 *mips16:
5444 {
5445   unsigned32 instruction = instruction_0;
5446   signed_word op1 = (instruction >> 8) & 0x7;
5447   int destreg = (instruction >> 5) & 0x7;
5448   int op2 = (instruction >> 0) & 0xf;
5449   if (op1 < 2)
5450     op1 += 16;
5451   op1 = GPR[op1];
5452   if (destreg < 2)
5453     destreg += 16;
5454   if (have_extendval)
5455     {
5456       op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5457       if (op2 >= 0x4000)
5458         op2 -= 0x8000;
5459       have_extendval = 0;
5460     }
5461   else
5462     {
5463       if (op2 >= 0x8)
5464         op2 -= 0x10;
5465     }
5466   if (have_extendval)
5467     SignalException (ReservedInstruction, instruction);
5468   {
5469     unsigned int temp = (unsigned int)(op1 + op2);
5470     signed int tempS = (signed int)temp;
5471     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5472   }
5473 }
5474
5475
5476 01001,www,kkkkkkkk:RI:16::ADDIU8
5477 *mips16:
5478 {
5479   unsigned32 instruction = instruction_0;
5480   signed_word op1 = (instruction >> 8) & 0x7;
5481   int destreg;
5482   int op2 = (instruction >> 0) & 0xff;
5483   if (op1 < 2)
5484     op1 += 16;
5485   destreg = op1;
5486   op1 = GPR[op1];
5487   if (have_extendval)
5488     {
5489       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5490       if (op2 >= 0x8000)
5491         op2 -= 0x10000;
5492       have_extendval = 0;
5493     }
5494   else
5495     {
5496       if (op2 >= 0x80)
5497         op2 -= 0x100;
5498     }
5499   if (have_extendval)
5500     SignalException (ReservedInstruction, instruction);
5501   {
5502     unsigned int temp = (unsigned int)(op1 + op2);
5503     signed int tempS = (signed int)temp;
5504     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5505   }
5506 }
5507
5508
5509 01100011,KKKKKKKK,S:I8:16::ADJSP
5510 *mips16:
5511 {
5512   unsigned32 instruction = instruction_0;
5513   int op2 = (instruction >> 0) & 0xff;
5514   signed_word op1 = 29;
5515   int destreg;
5516   if (have_extendval)
5517     {
5518       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5519       if (op2 >= 0x8000)
5520         op2 -= 0x10000;
5521       have_extendval = 0;
5522     }
5523   else
5524     {
5525       if (op2 >= 0x80)
5526         op2 -= 0x100;
5527       op2 <<= 3;
5528     }
5529   destreg = op1;
5530   op1 = GPR[op1];
5531   if (have_extendval)
5532     SignalException (ReservedInstruction, instruction);
5533   {
5534     unsigned int temp = (unsigned int)(op1 + op2);
5535     signed int tempS = (signed int)temp;
5536     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5537   }
5538 }
5539
5540
5541 00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC
5542 *mips16:
5543 {
5544   unsigned32 instruction = instruction_0;
5545   int destreg = (instruction >> 8) & 0x7;
5546   int op2 = (instruction >> 0) & 0xff;
5547   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
5548   if (destreg < 2)
5549     destreg += 16;
5550   if (have_extendval)
5551     {
5552       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5553       if (op2 >= 0x8000)
5554         op2 -= 0x10000;
5555       have_extendval = 0;
5556     }
5557   else
5558     {
5559       op2 <<= 2;
5560     }
5561   if (have_extendval)
5562     SignalException (ReservedInstruction, instruction);
5563   {
5564     unsigned int temp = (unsigned int)(op1 + op2);
5565     signed int tempS = (signed int)temp;
5566     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5567   }
5568 }
5569
5570
5571 00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP
5572 *mips16:
5573 {
5574   unsigned32 instruction = instruction_0;
5575   int destreg = (instruction >> 8) & 0x7;
5576   int op2 = (instruction >> 0) & 0xff;
5577   signed_word op1 = 29;
5578   if (destreg < 2)
5579     destreg += 16;
5580   if (have_extendval)
5581     {
5582       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5583       if (op2 >= 0x8000)
5584         op2 -= 0x10000;
5585       have_extendval = 0;
5586     }
5587   else
5588     {
5589       op2 <<= 2;
5590     }
5591   op1 = GPR[op1];
5592   if (have_extendval)
5593     SignalException (ReservedInstruction, instruction);
5594   {
5595     unsigned int temp = (unsigned int)(op1 + op2);
5596     signed int tempS = (signed int)temp;
5597     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5598   }
5599 }
5600
5601
5602 01000,xxx,ddd,14444:RRI_A:16::DADDIU
5603 *mips16:
5604 {
5605   unsigned32 instruction = instruction_0;
5606   signed_word op1 = (instruction >> 8) & 0x7;
5607   int destreg = (instruction >> 5) & 0x7;
5608   int op2 = (instruction >> 0) & 0xf;
5609   if (op1 < 2)
5610     op1 += 16;
5611   op1 = GPR[op1];
5612   if (destreg < 2)
5613     destreg += 16;
5614   if (have_extendval)
5615     {
5616       op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5617       if (op2 >= 0x4000)
5618         op2 -= 0x8000;
5619       have_extendval = 0;
5620     }
5621   else
5622     {
5623       if (op2 >= 0x8)
5624         op2 -= 0x10;
5625     }
5626   if (have_extendval)
5627     SignalException (ReservedInstruction, instruction);
5628   {
5629     unsigned64 temp = (unsigned64)(op1 + op2);
5630     word64 tempS = (word64)temp;
5631     GPR[destreg] = (unsigned64)temp;
5632   }
5633 }
5634
5635
5636 11111101,www,jjjjj:RI64:16::DADDIU5
5637 *mips16:
5638 {
5639   unsigned32 instruction = instruction_0;
5640   signed_word op1 = (instruction >> 5) & 0x7;
5641   int destreg;
5642   int op2 = (instruction >> 0) & 0x1f;
5643   if (op1 < 2)
5644     op1 += 16;
5645   destreg = op1;
5646   op1 = GPR[op1];
5647   if (have_extendval)
5648     {
5649       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5650       if (op2 >= 0x8000)
5651         op2 -= 0x10000;
5652       have_extendval = 0;
5653     }
5654   else
5655     {
5656       if (op2 >= 0x10)
5657         op2 -= 0x20;
5658     }
5659   if (have_extendval)
5660     SignalException (ReservedInstruction, instruction);
5661   {
5662     unsigned64 temp = (unsigned64)(op1 + op2);
5663     word64 tempS = (word64)temp;
5664     GPR[destreg] = (unsigned64)temp;
5665   }
5666 }
5667
5668
5669 11111011,KKKKKKKK,S:I64:16::DADJSP
5670 *mips16:
5671 {
5672   unsigned32 instruction = instruction_0;
5673   int op2 = (instruction >> 0) & 0xff;
5674   signed_word op1 = 29;
5675   int destreg;
5676   if (have_extendval)
5677     {
5678       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5679       if (op2 >= 0x8000)
5680         op2 -= 0x10000;
5681       have_extendval = 0;
5682     }
5683   else
5684     {
5685       if (op2 >= 0x80)
5686         op2 -= 0x100;
5687       op2 <<= 3;
5688     }
5689   destreg = op1;
5690   op1 = GPR[op1];
5691   if (have_extendval)
5692     SignalException (ReservedInstruction, instruction);
5693   {
5694     unsigned64 temp = (unsigned64)(op1 + op2);
5695     word64 tempS = (word64)temp;
5696     GPR[destreg] = (unsigned64)temp;
5697   }
5698 }
5699
5700
5701 11111110,ddd,EEEEE,P:RI64:16::DADDIUPC
5702 *mips16:
5703 {
5704   unsigned32 instruction = instruction_0;
5705   int destreg = (instruction >> 5) & 0x7;
5706   int op2 = (instruction >> 0) & 0x1f;
5707   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
5708   if (destreg < 2)
5709     destreg += 16;
5710   if (have_extendval)
5711     {
5712       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5713       if (op2 >= 0x8000)
5714         op2 -= 0x10000;
5715       have_extendval = 0;
5716     }
5717   else
5718     {
5719       op2 <<= 2;
5720     }
5721   if (have_extendval)
5722     SignalException (ReservedInstruction, instruction);
5723   {
5724     unsigned64 temp = (unsigned64)(op1 + op2);
5725     word64 tempS = (word64)temp;
5726     GPR[destreg] = (unsigned64)temp;
5727   }
5728 }
5729
5730
5731 11111111,ddd,EEEEE,s:RI64:16::DADDIUSP
5732 *mips16:
5733 {
5734   unsigned32 instruction = instruction_0;
5735   int destreg = (instruction >> 5) & 0x7;
5736   int op2 = (instruction >> 0) & 0x1f;
5737   signed_word op1 = 29;
5738   if (destreg < 2)
5739     destreg += 16;
5740   if (have_extendval)
5741     {
5742       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5743       if (op2 >= 0x8000)
5744         op2 -= 0x10000;
5745       have_extendval = 0;
5746     }
5747   else
5748     {
5749       op2 <<= 2;
5750     }
5751   op1 = GPR[op1];
5752   if (have_extendval)
5753     SignalException (ReservedInstruction, instruction);
5754   {
5755     unsigned64 temp = (unsigned64)(op1 + op2);
5756     word64 tempS = (word64)temp;
5757     GPR[destreg] = (unsigned64)temp;
5758   }
5759 }
5760
5761
5762 01010,xxx,88888888,T:RI:16::SLTI
5763 *mips16:
5764 {
5765   unsigned32 instruction = instruction_0;
5766   signed_word op1 = (instruction >> 8) & 0x7;
5767   int op2 = (instruction >> 0) & 0xff;
5768   int destreg = 24;
5769   if (op1 < 2)
5770     op1 += 16;
5771   op1 = GPR[op1];
5772   if (have_extendval)
5773     {
5774       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5775       if (op2 >= 0x8000)
5776         op2 -= 0x10000;
5777       have_extendval = 0;
5778     }
5779   else
5780     {
5781     }
5782   if (have_extendval)
5783     SignalException (ReservedInstruction, instruction);
5784   {
5785     if ((word64)op1 < (word64)op2)
5786       GPR[destreg] = 1;
5787     else
5788       GPR[destreg] = 0;
5789   }
5790 }
5791
5792
5793 01011,xxx,88888888,T:RI:16::SLTIU
5794 *mips16:
5795 {
5796   unsigned32 instruction = instruction_0;
5797   signed_word op1 = (instruction >> 8) & 0x7;
5798   int op2 = (instruction >> 0) & 0xff;
5799   int destreg = 24;
5800   if (op1 < 2)
5801     op1 += 16;
5802   op1 = GPR[op1];
5803   if (have_extendval)
5804     {
5805       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5806       if (op2 >= 0x8000)
5807         op2 -= 0x10000;
5808       have_extendval = 0;
5809     }
5810   else
5811     {
5812     }
5813   if (have_extendval)
5814     SignalException (ReservedInstruction, instruction);
5815   {
5816     if ((unsigned64)op1 < (unsigned64)op2)
5817       GPR[destreg] = 1;
5818     else
5819       GPR[destreg] = 0;
5820   }
5821 }
5822
5823
5824 11101,xxx,yyy,01010,T:RR:16::CMP
5825 *mips16:
5826 {
5827   unsigned32 instruction = instruction_0;
5828   signed_word op1 = (instruction >> 8) & 0x7;
5829   signed_word op2 = (instruction >> 5) & 0x7;
5830   int destreg = 24;
5831   if (op1 < 2)
5832     op1 += 16;
5833   op1 = GPR[op1];
5834   if (op2 < 2)
5835     op2 += 16;
5836   op2 = GPR[op2];
5837   if (have_extendval)
5838     SignalException (ReservedInstruction, instruction);
5839   {
5840     GPR[destreg] = (op1 ^ op2);
5841   }
5842 }
5843
5844
5845 01110,xxx,UUUUUUUU,T:RI:16::CMPI
5846 *mips16:
5847 {
5848   unsigned32 instruction = instruction_0;
5849   signed_word op1 = (instruction >> 8) & 0x7;
5850   int op2 = (instruction >> 0) & 0xff;
5851   int destreg = 24;
5852   if (op1 < 2)
5853     op1 += 16;
5854   op1 = GPR[op1];
5855   if (have_extendval)
5856     {
5857       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5858       have_extendval = 0;
5859     }
5860   else
5861     {
5862     }
5863   if (have_extendval)
5864     SignalException (ReservedInstruction, instruction);
5865   {
5866     GPR[destreg] = (op1 ^ op2);
5867   }
5868 }
5869
5870
5871 // Two/Three Operand, Register-Type
5872
5873
5874 11100,xxx,yyy,ddd,01:RRR:16::ADDU
5875 *mips16:
5876 {
5877   unsigned32 instruction = instruction_0;
5878   signed_word op1 = (instruction >> 8) & 0x7;
5879   signed_word op2 = (instruction >> 5) & 0x7;
5880   int destreg = (instruction >> 2) & 0x7;
5881   if (op1 < 2)
5882     op1 += 16;
5883   op1 = GPR[op1];
5884   if (op2 < 2)
5885     op2 += 16;
5886   op2 = GPR[op2];
5887   if (destreg < 2)
5888     destreg += 16;
5889   if (have_extendval)
5890     SignalException (ReservedInstruction, instruction);
5891   {
5892     unsigned int temp = (unsigned int)(op1 + op2);
5893     signed int tempS = (signed int)temp;
5894     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5895   }
5896 }
5897
5898
5899 11100,xxx,yyy,ddd,11:RRR:16::SUBU
5900 *mips16:
5901 {
5902   unsigned32 instruction = instruction_0;
5903   signed_word op1 = (instruction >> 8) & 0x7;
5904   signed_word op2 = (instruction >> 5) & 0x7;
5905   int destreg = (instruction >> 2) & 0x7;
5906   if (op1 < 2)
5907     op1 += 16;
5908   op1 = GPR[op1];
5909   if (op2 < 2)
5910     op2 += 16;
5911   op2 = GPR[op2];
5912   if (destreg < 2)
5913     destreg += 16;
5914   if (have_extendval)
5915     SignalException (ReservedInstruction, instruction);
5916   {
5917     unsigned int temp = (unsigned int)(op1 - op2);
5918     signed int tempS = (signed int)temp;
5919     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5920   }
5921 }
5922
5923
5924 11100,xxx,yyy,ddd,00:RRR:16::DADDU
5925 *mips16:
5926 {
5927   unsigned32 instruction = instruction_0;
5928   signed_word op1 = (instruction >> 8) & 0x7;
5929   signed_word op2 = (instruction >> 5) & 0x7;
5930   int destreg = (instruction >> 2) & 0x7;
5931   if (op1 < 2)
5932     op1 += 16;
5933   op1 = GPR[op1];
5934   if (op2 < 2)
5935     op2 += 16;
5936   op2 = GPR[op2];
5937   if (destreg < 2)
5938     destreg += 16;
5939   if (have_extendval)
5940     SignalException (ReservedInstruction, instruction);
5941   {
5942     unsigned64 temp = (unsigned64)(op1 + op2);
5943     word64 tempS = (word64)temp;
5944     GPR[destreg] = (unsigned64)temp;
5945   }
5946 }
5947
5948
5949 11100,xxx,yyy,ddd,10:RRR:16::DSUBU
5950 *mips16:
5951 {
5952   unsigned32 instruction = instruction_0;
5953   signed_word op1 = (instruction >> 8) & 0x7;
5954   signed_word op2 = (instruction >> 5) & 0x7;
5955   int destreg = (instruction >> 2) & 0x7;
5956   if (op1 < 2)
5957     op1 += 16;
5958   op1 = GPR[op1];
5959   if (op2 < 2)
5960     op2 += 16;
5961   op2 = GPR[op2];
5962   if (destreg < 2)
5963     destreg += 16;
5964   if (have_extendval)
5965     SignalException (ReservedInstruction, instruction);
5966   {
5967     unsigned64 temp = (unsigned64)(op1 - op2);
5968     word64 tempS = (word64)temp;
5969     GPR[destreg] = (unsigned64)temp;
5970   }
5971 }
5972
5973
5974 11101,xxx,yyy,00010,T:RR:16::SLT
5975 *mips16:
5976 {
5977   unsigned32 instruction = instruction_0;
5978   signed_word op1 = (instruction >> 8) & 0x7;
5979   signed_word op2 = (instruction >> 5) & 0x7;
5980   int destreg = 24;
5981   if (op1 < 2)
5982     op1 += 16;
5983   op1 = GPR[op1];
5984   if (op2 < 2)
5985     op2 += 16;
5986   op2 = GPR[op2];
5987   if (have_extendval)
5988     SignalException (ReservedInstruction, instruction);
5989   {
5990     if ((word64)op1 < (word64)op2)
5991       GPR[destreg] = 1;
5992     else
5993       GPR[destreg] = 0;
5994   }
5995 }
5996
5997
5998 11101,xxx,yyy,00011,T:RR:16::SLTU
5999 *mips16:
6000 {
6001   unsigned32 instruction = instruction_0;
6002   signed_word op1 = (instruction >> 8) & 0x7;
6003   signed_word op2 = (instruction >> 5) & 0x7;
6004   int destreg = 24;
6005   if (op1 < 2)
6006     op1 += 16;
6007   op1 = GPR[op1];
6008   if (op2 < 2)
6009     op2 += 16;
6010   op2 = GPR[op2];
6011   if (have_extendval)
6012     SignalException (ReservedInstruction, instruction);
6013   {
6014     if ((unsigned64)op1 < (unsigned64)op2)
6015       GPR[destreg] = 1;
6016     else
6017       GPR[destreg] = 0;
6018   }
6019 }
6020
6021
6022 11101,ddd,yyy,01011,Z:RR:16::NEG
6023 *mips16:
6024 {
6025   unsigned32 instruction = instruction_0;
6026   int destreg = (instruction >> 8) & 0x7;
6027   signed_word op2 = (instruction >> 5) & 0x7;
6028   signed_word op1 = 0;
6029   if (destreg < 2)
6030     destreg += 16;
6031   if (op2 < 2)
6032     op2 += 16;
6033   op2 = GPR[op2];
6034   if (have_extendval)
6035     SignalException (ReservedInstruction, instruction);
6036   {
6037     unsigned int temp = (unsigned int)(op1 - op2);
6038     signed int tempS = (signed int)temp;
6039     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6040   }
6041 }
6042
6043
6044 11101,www,yyy,01100:RR:16::AND
6045 *mips16:
6046 {
6047   unsigned32 instruction = instruction_0;
6048   signed_word op1 = (instruction >> 8) & 0x7;
6049   int destreg;
6050   signed_word op2 = (instruction >> 5) & 0x7;
6051   if (op1 < 2)
6052     op1 += 16;
6053   destreg = op1;
6054   op1 = GPR[op1];
6055   if (op2 < 2)
6056     op2 += 16;
6057   op2 = GPR[op2];
6058   if (have_extendval)
6059     SignalException (ReservedInstruction, instruction);
6060   {
6061     GPR[destreg] = (op1 & op2);
6062   }
6063 }
6064
6065
6066 11101,www,yyy,01101:RR:16::OR
6067 *mips16:
6068 {
6069   unsigned32 instruction = instruction_0;
6070   signed_word op1 = (instruction >> 8) & 0x7;
6071   int destreg;
6072   signed_word op2 = (instruction >> 5) & 0x7;
6073   if (op1 < 2)
6074     op1 += 16;
6075   destreg = op1;
6076   op1 = GPR[op1];
6077   if (op2 < 2)
6078     op2 += 16;
6079   op2 = GPR[op2];
6080   if (have_extendval)
6081     SignalException (ReservedInstruction, instruction);
6082   {
6083     if (destreg != 0)
6084       GPR[destreg] = (op1 | op2);
6085   }
6086 }
6087
6088
6089 11101,www,yyy,01110:RR:16::XOR
6090 *mips16:
6091 {
6092   unsigned32 instruction = instruction_0;
6093   signed_word op1 = (instruction >> 8) & 0x7;
6094   int destreg;
6095   signed_word op2 = (instruction >> 5) & 0x7;
6096   if (op1 < 2)
6097     op1 += 16;
6098   destreg = op1;
6099   op1 = GPR[op1];
6100   if (op2 < 2)
6101     op2 += 16;
6102   op2 = GPR[op2];
6103   if (have_extendval)
6104     SignalException (ReservedInstruction, instruction);
6105   {
6106     GPR[destreg] = (op1 ^ op2);
6107   }
6108 }
6109
6110
6111 11101,ddd,yyy,01111,Z:RR:16::NOT
6112 *mips16:
6113 {
6114   unsigned32 instruction = instruction_0;
6115   int destreg = (instruction >> 8) & 0x7;
6116   signed_word op2 = (instruction >> 5) & 0x7;
6117   signed_word op1 = 0;
6118   if (destreg < 2)
6119     destreg += 16;
6120   if (op2 < 2)
6121     op2 += 16;
6122   op2 = GPR[op2];
6123   if (have_extendval)
6124     SignalException (ReservedInstruction, instruction);
6125   {
6126     if (destreg != 0)
6127       GPR[destreg] = ~(op1 | op2);
6128   }
6129 }
6130
6131
6132 01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32
6133 *mips16:
6134 {
6135   unsigned32 instruction = instruction_0;
6136   int destreg = (instruction >> 5) & 0x7;
6137   signed_word op1 = (instruction >> 0) & 0x1f;
6138   signed_word op2 = 0;
6139   if (destreg < 2)
6140     destreg += 16;
6141   op1 = GPR[op1];
6142   if (have_extendval)
6143     SignalException (ReservedInstruction, instruction);
6144   {
6145     if (destreg != 0)
6146       GPR[destreg] = (op1 | op2);
6147   }
6148 }
6149
6150
6151 01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R
6152 *mips16:
6153 {
6154   unsigned32 instruction = instruction_0;
6155   int destreg = (instruction >> 3) & 0x1f;
6156   signed_word op1 = (instruction >> 0) & 0x7;
6157   signed_word op2 = 0;
6158   destreg = (destreg >> 2) | ((destreg & 3) << 3);
6159   if (op1 < 2)
6160     op1 += 16;
6161   op1 = GPR[op1];
6162   if (have_extendval)
6163     SignalException (ReservedInstruction, instruction);
6164   {
6165     if (destreg != 0)
6166       GPR[destreg] = (op1 | op2);
6167   }
6168 }
6169
6170
6171 00110,ddd,yyy,sss,00:ISHIFT:16::SLL
6172 *mips16:
6173 {
6174   unsigned32 instruction = instruction_0;
6175   int destreg = (instruction >> 8) & 0x7;
6176   signed_word op2 = (instruction >> 5) & 0x7;
6177   int op1 = (instruction >> 2) & 0x7;
6178   if (destreg < 2)
6179     destreg += 16;
6180   if (op2 < 2)
6181     op2 += 16;
6182   op2 = GPR[op2];
6183   if (have_extendval)
6184     {
6185       op1 = (extendval >> 6) & 0x1f;
6186       have_extendval = 0;
6187     }
6188   else
6189     {
6190       if (op1 == 0)
6191         op1 = 8;
6192     }
6193   if (have_extendval)
6194     SignalException (ReservedInstruction, instruction);
6195   {
6196     GPR[destreg] = ((unsigned64)op2 << op1);
6197     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6198   }
6199 }
6200
6201
6202 00110,ddd,yyy,sss,10:ISHIFT:16::SRL
6203 *mips16:
6204 {
6205   unsigned32 instruction = instruction_0;
6206   int destreg = (instruction >> 8) & 0x7;
6207   signed_word op2 = (instruction >> 5) & 0x7;
6208   int op1 = (instruction >> 2) & 0x7;
6209   if (destreg < 2)
6210     destreg += 16;
6211   if (op2 < 2)
6212     op2 += 16;
6213   op2 = GPR[op2];
6214   if (have_extendval)
6215     {
6216       op1 = (extendval >> 6) & 0x1f;
6217       have_extendval = 0;
6218     }
6219   else
6220     {
6221       if (op1 == 0)
6222         op1 = 8;
6223     }
6224   if (have_extendval)
6225     SignalException (ReservedInstruction, instruction);
6226   {
6227     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6228     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6229   }
6230 }
6231
6232
6233 00110,ddd,yyy,sss,11:ISHIFT:16::SRA
6234 *mips16:
6235 {
6236   unsigned32 instruction = instruction_0;
6237   int destreg = (instruction >> 8) & 0x7;
6238   signed_word op2 = (instruction >> 5) & 0x7;
6239   int op1 = (instruction >> 2) & 0x7;
6240   if (destreg < 2)
6241     destreg += 16;
6242   if (op2 < 2)
6243     op2 += 16;
6244   op2 = GPR[op2];
6245   if (have_extendval)
6246     {
6247       op1 = (extendval >> 6) & 0x1f;
6248       have_extendval = 0;
6249     }
6250   else
6251     {
6252       if (op1 == 0)
6253         op1 = 8;
6254     }
6255   if (have_extendval)
6256     SignalException (ReservedInstruction, instruction);
6257   {
6258     unsigned int highbit = (unsigned int)1 << 31;
6259     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6260     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6261     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6262   }
6263 }
6264
6265
6266 11101,xxx,vvv,00100:RR:16::SLLV
6267 *mips16:
6268 {
6269   unsigned32 instruction = instruction_0;
6270   signed_word op1 = (instruction >> 8) & 0x7;
6271   signed_word op2 = (instruction >> 5) & 0x7;
6272   int destreg;
6273   if (op1 < 2)
6274     op1 += 16;
6275   op1 = GPR[op1];
6276   if (op2 < 2)
6277     op2 += 16;
6278   destreg = op2;
6279   op2 = GPR[op2];
6280   if (have_extendval)
6281     SignalException (ReservedInstruction, instruction);
6282   {
6283     op1 &= 0x1F;
6284     GPR[destreg] = ((unsigned64)op2 << op1);
6285     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6286   }
6287 }
6288
6289
6290 11101,xxx,vvv,00110:RR:16::SRLV
6291 *mips16:
6292 {
6293   unsigned32 instruction = instruction_0;
6294   signed_word op1 = (instruction >> 8) & 0x7;
6295   signed_word op2 = (instruction >> 5) & 0x7;
6296   int destreg;
6297   if (op1 < 2)
6298     op1 += 16;
6299   op1 = GPR[op1];
6300   if (op2 < 2)
6301     op2 += 16;
6302   destreg = op2;
6303   op2 = GPR[op2];
6304   if (have_extendval)
6305     SignalException (ReservedInstruction, instruction);
6306   {
6307     op1 &= 0x1F;
6308     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6309     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6310   }
6311 }
6312
6313
6314 11101,xxx,vvv,00111:RR:16::SRAV
6315 *mips16:
6316 {
6317   unsigned32 instruction = instruction_0;
6318   signed_word op1 = (instruction >> 8) & 0x7;
6319   signed_word op2 = (instruction >> 5) & 0x7;
6320   int destreg;
6321   if (op1 < 2)
6322     op1 += 16;
6323   op1 = GPR[op1];
6324   if (op2 < 2)
6325     op2 += 16;
6326   destreg = op2;
6327   op2 = GPR[op2];
6328   if (have_extendval)
6329     SignalException (ReservedInstruction, instruction);
6330   {
6331     unsigned int highbit = (unsigned int)1 << 31;
6332     op1 &= 0x1F;
6333     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6334     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6335     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6336   }
6337 }
6338
6339
6340 00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL
6341 *mips16:
6342 {
6343   unsigned32 instruction = instruction_0;
6344   int destreg = (instruction >> 8) & 0x7;
6345   signed_word op2 = (instruction >> 5) & 0x7;
6346   int op1 = (instruction >> 2) & 0x7;
6347   if (destreg < 2)
6348     destreg += 16;
6349   if (op2 < 2)
6350     op2 += 16;
6351   op2 = GPR[op2];
6352   if (have_extendval)
6353     {
6354       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6355       have_extendval = 0;
6356     }
6357   else
6358     {
6359       if (op1 == 0)
6360         op1 = 8;
6361     }
6362   if (have_extendval)
6363     SignalException (ReservedInstruction, instruction);
6364   {
6365     GPR[destreg] = ((unsigned64)op2 << op1);
6366   }
6367 }
6368
6369
6370 11101,XXX,vvv,01000:RR:16::DSRL
6371 *mips16:
6372 {
6373   unsigned32 instruction = instruction_0;
6374   int op1 = (instruction >> 8) & 0x7;
6375   signed_word op2 = (instruction >> 5) & 0x7;
6376   int destreg;
6377   if (have_extendval)
6378     {
6379       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6380       have_extendval = 0;
6381     }
6382   else
6383     {
6384       if (op1 == 0)
6385         op1 = 8;
6386     }
6387   if (op2 < 2)
6388     op2 += 16;
6389   destreg = op2;
6390   op2 = GPR[op2];
6391   if (have_extendval)
6392     SignalException (ReservedInstruction, instruction);
6393   {
6394     GPR[destreg] = ((unsigned64)(op2) >> op1);
6395   }
6396 }
6397
6398
6399 11101,xxx,vvv,10011:RR:16::DSRA
6400 *mips16:
6401 {
6402   unsigned32 instruction = instruction_0;
6403   int op1 = (instruction >> 8) & 0x7;
6404   signed_word op2 = (instruction >> 5) & 0x7;
6405   int destreg;
6406   if (have_extendval)
6407     {
6408       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6409       have_extendval = 0;
6410     }
6411   else
6412     {
6413       if (op1 == 0)
6414         op1 = 8;
6415     }
6416   if (op2 < 2)
6417     op2 += 16;
6418   destreg = op2;
6419   op2 = GPR[op2];
6420   if (have_extendval)
6421     SignalException (ReservedInstruction, instruction);
6422   {
6423     unsigned64 highbit = (unsigned64)1 << 63;
6424     GPR[destreg] = ((unsigned64)(op2) >> op1);
6425     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6426   }
6427 }
6428
6429
6430 11101,xxx,vvv,10100:RR:16::DSLLV
6431 *mips16:
6432 {
6433   unsigned32 instruction = instruction_0;
6434   signed_word op1 = (instruction >> 8) & 0x7;
6435   signed_word op2 = (instruction >> 5) & 0x7;
6436   int destreg;
6437   if (op1 < 2)
6438     op1 += 16;
6439   op1 = GPR[op1];
6440   if (op2 < 2)
6441     op2 += 16;
6442   destreg = op2;
6443   op2 = GPR[op2];
6444   if (have_extendval)
6445     SignalException (ReservedInstruction, instruction);
6446   {
6447     op1 &= 0x3F;
6448     GPR[destreg] = ((unsigned64)op2 << op1);
6449   }
6450 }
6451
6452
6453 11101,xxx,vvv,10110:RR:16::DSRLV
6454 *mips16:
6455 {
6456   unsigned32 instruction = instruction_0;
6457   signed_word op1 = (instruction >> 8) & 0x7;
6458   signed_word op2 = (instruction >> 5) & 0x7;
6459   int destreg;
6460   if (op1 < 2)
6461     op1 += 16;
6462   op1 = GPR[op1];
6463   if (op2 < 2)
6464     op2 += 16;
6465   destreg = op2;
6466   op2 = GPR[op2];
6467   if (have_extendval)
6468     SignalException (ReservedInstruction, instruction);
6469   {
6470     op1 &= 0x3F;
6471     GPR[destreg] = ((unsigned64)(op2) >> op1);
6472   }
6473 }
6474
6475
6476 11101,xxx,vvv,10111:RR:16::DSRAV
6477 *mips16:
6478 {
6479   unsigned32 instruction = instruction_0;
6480   signed_word op1 = (instruction >> 8) & 0x7;
6481   signed_word op2 = (instruction >> 5) & 0x7;
6482   int destreg;
6483   if (op1 < 2)
6484     op1 += 16;
6485   op1 = GPR[op1];
6486   if (op2 < 2)
6487     op2 += 16;
6488   destreg = op2;
6489   op2 = GPR[op2];
6490   if (have_extendval)
6491     SignalException (ReservedInstruction, instruction);
6492   {
6493     unsigned64 highbit = (unsigned64)1 << 63;
6494     op1 &= 0x3F;
6495     GPR[destreg] = ((unsigned64)(op2) >> op1);
6496     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6497   }
6498 }
6499
6500
6501 // Multiply /Divide Instructions
6502
6503
6504 11101,xxx,yyy,11000:RR:16::MULT
6505 *mips16:
6506 {
6507   unsigned32 instruction = instruction_0;
6508   signed_word op1 = (instruction >> 8) & 0x7;
6509   signed_word op2 = (instruction >> 5) & 0x7;
6510   if (op1 < 2)
6511     op1 += 16;
6512   op1 = GPR[op1];
6513   if (op2 < 2)
6514     op2 += 16;
6515   op2 = GPR[op2];
6516   if (have_extendval)
6517     SignalException (ReservedInstruction, instruction);
6518   {
6519     CHECKHILO("Multiplication");
6520     {
6521       unsigned64 temp = ((word64) op1 * (word64) op2);
6522       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
6523       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
6524     }
6525   }
6526 }
6527
6528
6529 11101,xxx,yyy,11001:RR:16::MULTU
6530 *mips16:
6531 {
6532   unsigned32 instruction = instruction_0;
6533   signed_word op1 = (instruction >> 8) & 0x7;
6534   signed_word op2 = (instruction >> 5) & 0x7;
6535   if (op1 < 2)
6536     op1 += 16;
6537   op1 = GPR[op1];
6538   if (op2 < 2)
6539     op2 += 16;
6540   op2 = GPR[op2];
6541   if (have_extendval)
6542     SignalException (ReservedInstruction, instruction);
6543   {
6544     CHECKHILO("Multiplication");
6545     {
6546       unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
6547       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
6548       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
6549     }
6550   }
6551 }
6552
6553
6554 11101,xxx,yyy,11010:RR:16::DIV
6555 *mips16:
6556 {
6557   unsigned32 instruction = instruction_0;
6558   signed_word op1 = (instruction >> 8) & 0x7;
6559   signed_word op2 = (instruction >> 5) & 0x7;
6560   if (op1 < 2)
6561     op1 += 16;
6562   op1 = GPR[op1];
6563   if (op2 < 2)
6564     op2 += 16;
6565   op2 = GPR[op2];
6566   if (have_extendval)
6567     SignalException (ReservedInstruction, instruction);
6568   {
6569     CHECKHILO("Division");
6570     {
6571       int d1 = op1;
6572       int d2 = op2;
6573       if (d2 == 0)
6574         {
6575           LO = SIGNEXTEND(0x80000000,32);
6576           HI = SIGNEXTEND(0,32);
6577         }
6578       else if (d2 == -1 && d1 == 0x80000000)
6579         {
6580           LO = SIGNEXTEND(0x80000000,32);
6581           HI = SIGNEXTEND(0,32);
6582         }
6583       else
6584         {
6585           LO = SIGNEXTEND((d1 / d2),32);
6586           HI = SIGNEXTEND((d1 % d2),32);
6587         }
6588     }
6589   }
6590 }
6591
6592
6593 11101,xxx,yyy,11011:RR:16::DIVU
6594 *mips16:
6595 {
6596   unsigned32 instruction = instruction_0;
6597   signed_word op1 = (instruction >> 8) & 0x7;
6598   signed_word op2 = (instruction >> 5) & 0x7;
6599   if (op1 < 2)
6600     op1 += 16;
6601   op1 = GPR[op1];
6602   if (op2 < 2)
6603     op2 += 16;
6604   op2 = GPR[op2];
6605   if (have_extendval)
6606     SignalException (ReservedInstruction, instruction);
6607   {
6608     CHECKHILO("Division");
6609     {
6610       unsigned int d1 = op1;
6611       unsigned int d2 = op2;
6612       if (d2 == 0)
6613         {
6614           LO = SIGNEXTEND(0x80000000,32);
6615           HI = SIGNEXTEND(0,32);
6616         }
6617       else if (d2 == -1 && d1 == 0x80000000)
6618         {
6619           LO = SIGNEXTEND(0x80000000,32);
6620           HI = SIGNEXTEND(0,32);
6621         }
6622       else
6623         {
6624           LO = SIGNEXTEND((d1 / d2),32);
6625           HI = SIGNEXTEND((d1 % d2),32);
6626         }
6627     }
6628   }
6629 }
6630
6631
6632 11101,ddd,00010000:RR:16::MFHI
6633 *mips16:
6634 {
6635   unsigned32 instruction = instruction_0;
6636   int destreg = (instruction >> 8) & 0x7;
6637   if (destreg < 2)
6638     destreg += 16;
6639   if (have_extendval)
6640     SignalException (ReservedInstruction, instruction);
6641   {
6642     GPR[destreg] = HI;
6643     HIACCESS = 3; /* 3rd instruction will be safe */
6644   }
6645 }
6646
6647
6648 11101,ddd,00010010:RR:16::MFLO
6649 *mips16:
6650 {
6651   unsigned32 instruction = instruction_0;
6652   int destreg = (instruction >> 8) & 0x7;
6653   if (destreg < 2)
6654     destreg += 16;
6655   if (have_extendval)
6656     SignalException (ReservedInstruction, instruction);
6657   {
6658     GPR[destreg] = LO;
6659     LOACCESS = 3; /* 3rd instruction will be safe */
6660   }
6661 }
6662
6663
6664 11101,xxx,yyy,11100:RR:16::DMULT
6665 *mips16:
6666 {
6667   unsigned32 instruction = instruction_0;
6668   signed_word op1 = (instruction >> 8) & 0x7;
6669   signed_word op2 = (instruction >> 5) & 0x7;
6670   if (op1 < 2)
6671     op1 += 16;
6672   op1 = GPR[op1];
6673   if (op2 < 2)
6674     op2 += 16;
6675   op2 = GPR[op2];
6676   if (have_extendval)
6677     SignalException (ReservedInstruction, instruction);
6678   {
6679     CHECKHILO("Multiplication");
6680     {
6681       unsigned64 mid;
6682       unsigned64 midhi;
6683       unsigned64 temp;
6684       int sign = 0;
6685       if (op1 < 0) { op1 = - op1; ++sign; }
6686       if (op2 < 0) { op2 = - op2; ++sign; }
6687       LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
6688       HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
6689       mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
6690       midhi = SET64HI(VL4_8(mid));
6691       temp = (LO + midhi);
6692       if ((temp == midhi) ? (LO != 0) : (temp < midhi))
6693         HI += 1;
6694       HI += VH4_8(mid);
6695       mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
6696       midhi = SET64HI(VL4_8(mid));
6697       LO = (temp + midhi);
6698       if ((LO == midhi) ? (temp != 0) : (LO < midhi))
6699         HI += 1;
6700       HI += VH4_8(mid);
6701       if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; }
6702     }
6703   }
6704 }
6705
6706
6707 11101,xxx,yyy,11101:RR:16::DMULTU
6708 *mips16:
6709 {
6710   unsigned32 instruction = instruction_0;
6711   signed_word op1 = (instruction >> 8) & 0x7;
6712   signed_word op2 = (instruction >> 5) & 0x7;
6713   if (op1 < 2)
6714     op1 += 16;
6715   op1 = GPR[op1];
6716   if (op2 < 2)
6717     op2 += 16;
6718   op2 = GPR[op2];
6719   if (have_extendval)
6720     SignalException (ReservedInstruction, instruction);
6721   {
6722     CHECKHILO("Multiplication");
6723     {
6724       unsigned64 mid;
6725       unsigned64 midhi;
6726       unsigned64 temp;
6727       LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
6728       HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
6729       mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
6730       midhi = SET64HI(VL4_8(mid));
6731       temp = (LO + midhi);
6732       if ((temp == midhi) ? (LO != 0) : (temp < midhi))
6733         HI += 1;
6734       HI += VH4_8(mid);
6735       mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
6736       midhi = SET64HI(VL4_8(mid));
6737       LO = (temp + midhi);
6738       if ((LO == midhi) ? (temp != 0) : (LO < midhi))
6739         HI += 1;
6740       HI += VH4_8(mid);
6741     }
6742   }
6743 }
6744
6745
6746 11101,xxx,yyy,11110:RR:16::DDIV
6747 *mips16:
6748 {
6749   unsigned32 instruction = instruction_0;
6750   signed_word op1 = (instruction >> 8) & 0x7;
6751   signed_word op2 = (instruction >> 5) & 0x7;
6752   if (op1 < 2)
6753     op1 += 16;
6754   op1 = GPR[op1];
6755   if (op2 < 2)
6756     op2 += 16;
6757   op2 = GPR[op2];
6758   if (have_extendval)
6759     SignalException (ReservedInstruction, instruction);
6760   {
6761     CHECKHILO("Division");
6762     {
6763       word64 d1 = op1;
6764       word64 d2 = op2;
6765       if (d2 == 0)
6766         {
6767           LO = SIGNED64 (0x8000000000000000);
6768           HI = 0;
6769         }
6770       else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
6771         {
6772           LO = SIGNED64 (0x8000000000000000);
6773           HI = 0;
6774         }
6775       else
6776         {
6777           LO = (d1 / d2);
6778           HI = (d1 % d2);
6779         }
6780     }
6781   }
6782 }
6783
6784
6785 11101,xxx,yyy,11111:RR:16::DDIVU
6786 *mips16:
6787 {
6788   unsigned32 instruction = instruction_0;
6789   signed_word op1 = (instruction >> 8) & 0x7;
6790   signed_word op2 = (instruction >> 5) & 0x7;
6791   if (op1 < 2)
6792     op1 += 16;
6793   op1 = GPR[op1];
6794   if (op2 < 2)
6795     op2 += 16;
6796   op2 = GPR[op2];
6797   if (have_extendval)
6798     SignalException (ReservedInstruction, instruction);
6799   {
6800     CHECKHILO("Division");
6801     {
6802       unsigned64 d1 = op1;
6803       unsigned64 d2 = op2;
6804       if (d2 == 0)
6805         {
6806           LO = SIGNED64 (0x8000000000000000);
6807           HI = 0;
6808         }
6809       else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
6810         {
6811           LO = SIGNED64 (0x8000000000000000);
6812           HI = 0;
6813         }
6814       else
6815         {
6816           LO = (d1 / d2);
6817           HI = (d1 % d2);
6818         }
6819     }
6820   }
6821 }
6822
6823
6824 // Jump and Branch Instructions
6825
6826
6827 // JALX
6828 // JAL
6829 00011,aaaaaaaaaaa:I:16::JAL
6830 *mips16:
6831 {
6832   unsigned32 instruction = instruction_0;
6833   unsigned_word op1 = (instruction >> 0) & 0x7ff;
6834   {
6835     address_word paddr;
6836     int uncached;
6837     if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))
6838       {
6839         unsigned64 memval;
6840         unsigned int reverse = (ReverseEndian ? 3 : 0);
6841         unsigned int bigend = (BigEndianCPU ? 3 : 0);
6842         unsigned int byte;
6843         paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1)));
6844         LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL);
6845         byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1));
6846         memval = (memval >> (8 * byte)) & 0xffff;
6847         op1 = (((op1 & 0x1f) << 23)
6848                | ((op1 & 0x3e0) << 13)
6849                | (memval << 2));
6850         if ((instruction & 0x400) == 0)
6851           op1 |= 1;
6852         PC += 2;
6853       }
6854   }
6855   op1 |= PC & ~ (unsigned64) 0x0fffffff;
6856   if (have_extendval)
6857     SignalException (ReservedInstruction, instruction);
6858   {
6859     int destreg = 31;
6860     GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
6861     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6862        so we just truncate it to 32 bits here.  */
6863     op1 = VL4_8(op1);
6864     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6865     DELAY_SLOT op1;
6866     JALDELAYSLOT();
6867   }
6868 }
6869
6870
6871 11101,xxx,00000000:RR:16::JR
6872 *mips16:
6873 {
6874   unsigned32 instruction = instruction_0;
6875   signed_word op1 = (instruction >> 8) & 0x7;
6876   if (op1 < 2)
6877     op1 += 16;
6878   op1 = GPR[op1];
6879   if (have_extendval)
6880     SignalException (ReservedInstruction, instruction);
6881   {
6882     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6883        so we just truncate it to 32 bits here.  */
6884     op1 = VL4_8(op1);
6885     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6886     DELAY_SLOT op1;
6887     DELAYSLOT();
6888   }
6889 }
6890
6891
6892 1110100000100000,r:RR:16::JRRA
6893 *mips16:
6894 {
6895   unsigned32 instruction = instruction_0;
6896   signed_word op1 = 31;
6897   op1 = GPR[op1];
6898   if (have_extendval)
6899     SignalException (ReservedInstruction, instruction);
6900   {
6901     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6902        so we just truncate it to 32 bits here.  */
6903     op1 = VL4_8(op1);
6904     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6905     DELAY_SLOT op1;
6906     DELAYSLOT();
6907   }
6908 }
6909
6910
6911 11101,xxx,01000000,R:RR:16::JALR
6912 *mips16:
6913 {
6914   unsigned32 instruction = instruction_0;
6915   signed_word op1 = (instruction >> 8) & 0x7;
6916   int destreg = 31;
6917   if (op1 < 2)
6918     op1 += 16;
6919   op1 = GPR[op1];
6920   if (have_extendval)
6921     SignalException (ReservedInstruction, instruction);
6922   {
6923     GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
6924     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6925        so we just truncate it to 32 bits here.  */
6926     op1 = VL4_8(op1);
6927     /* NOTE: The jump occurs AFTER the next instruction has been executed */
6928     DELAY_SLOT op1;
6929     DELAYSLOT();
6930   }
6931 }
6932
6933
6934 00100,xxx,pppppppp,z:RI:16::BEQZ
6935 *mips16:
6936 {
6937   unsigned32 instruction = instruction_0;
6938   signed_word op1 = (instruction >> 8) & 0x7;
6939   int offset = (instruction >> 0) & 0xff;
6940   signed_word op2 = 0;
6941   if (op1 < 2)
6942     op1 += 16;
6943   op1 = GPR[op1];
6944   if (have_extendval)
6945     {
6946       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6947       if (offset >= 0x8000)
6948         offset -= 0x10000;
6949       have_extendval = 0;
6950     }
6951   else
6952     {
6953       if (offset >= 0x80)
6954         offset -= 0x100;
6955     }
6956   offset *= 2;
6957   if (have_extendval)
6958     SignalException (ReservedInstruction, instruction);
6959   {
6960     int condition = (op1 == op2);
6961     if (condition)
6962       PC = PC + offset;
6963   }
6964 }
6965
6966
6967 00101,xxx,pppppppp,z:RI:16::BNEZ
6968 *mips16:
6969 {
6970   unsigned32 instruction = instruction_0;
6971   signed_word op1 = (instruction >> 8) & 0x7;
6972   int offset = (instruction >> 0) & 0xff;
6973   signed_word op2 = 0;
6974   if (op1 < 2)
6975     op1 += 16;
6976   op1 = GPR[op1];
6977   if (have_extendval)
6978     {
6979       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6980       if (offset >= 0x8000)
6981         offset -= 0x10000;
6982       have_extendval = 0;
6983     }
6984   else
6985     {
6986       if (offset >= 0x80)
6987         offset -= 0x100;
6988     }
6989   offset *= 2;
6990   if (have_extendval)
6991     SignalException (ReservedInstruction, instruction);
6992   {
6993     int condition = (op1 != op2);
6994     if (condition)
6995       PC = PC + offset;
6996   }
6997 }
6998
6999
7000 01100000,pppppppp,t,z:I8:16::BTEQZ
7001 *mips16:
7002 {
7003   unsigned32 instruction = instruction_0;
7004   int offset = (instruction >> 0) & 0xff;
7005   signed_word op1 = 24;
7006   signed_word op2 = 0;
7007   if (have_extendval)
7008     {
7009       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7010       if (offset >= 0x8000)
7011         offset -= 0x10000;
7012       have_extendval = 0;
7013     }
7014   else
7015     {
7016       if (offset >= 0x80)
7017         offset -= 0x100;
7018     }
7019   offset *= 2;
7020   op1 = GPR[op1];
7021   if (have_extendval)
7022     SignalException (ReservedInstruction, instruction);
7023   {
7024     int condition = (op1 == op2);
7025     if (condition)
7026       PC = PC + offset;
7027   }
7028 }
7029
7030
7031 01100001,pppppppp,t,z:I8:16::BTNEZ
7032 *mips16:
7033 {
7034   unsigned32 instruction = instruction_0;
7035   int offset = (instruction >> 0) & 0xff;
7036   signed_word op1 = 24;
7037   signed_word op2 = 0;
7038   if (have_extendval)
7039     {
7040       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7041       if (offset >= 0x8000)
7042         offset -= 0x10000;
7043       have_extendval = 0;
7044     }
7045   else
7046     {
7047       if (offset >= 0x80)
7048         offset -= 0x100;
7049     }
7050   offset *= 2;
7051   op1 = GPR[op1];
7052   if (have_extendval)
7053     SignalException (ReservedInstruction, instruction);
7054   {
7055     int condition = (op1 != op2);
7056     if (condition)
7057       PC = PC + offset;
7058   }
7059 }
7060
7061
7062 00010,qqqqqqqqqqq,z,Z:I:16::B
7063 *mips16:
7064 {
7065   unsigned32 instruction = instruction_0;
7066   int offset = (instruction >> 0) & 0x7ff;
7067   signed_word op2 = 0;
7068   signed_word op1 = 0;
7069   if (have_extendval)
7070     {
7071       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7072       if (offset >= 0x8000)
7073         offset -= 0x10000;
7074       have_extendval = 0;
7075     }
7076   else
7077     {
7078       if (offset >= 0x400)
7079         offset -= 0x800;
7080     }
7081   offset *= 2;
7082   if (have_extendval)
7083     SignalException (ReservedInstruction, instruction);
7084   {
7085     int condition = (op1 == op2);
7086     if (condition)
7087       PC = PC + offset;
7088   }
7089 }
7090
7091
7092 // Special Instructions
7093
7094
7095 // See the front of the mips16 doc
7096 11110,eeeeeeeeeee:I:16::EXTEND
7097 *mips16:
7098 {
7099   unsigned32 instruction = instruction_0;
7100   int ext = (instruction >> 0) & 0x7ff;
7101   if (have_extendval)
7102     SignalException (ReservedInstruction, instruction);
7103   {
7104     extendval = ext;
7105     have_extendval = 1;
7106   }
7107 }
7108
7109
7110 01100,******,00101:RR:16::BREAK
7111 *mips16:
7112 {
7113   unsigned32 instruction = instruction_0;
7114   if (have_extendval)
7115     SignalException (ReservedInstruction, instruction);
7116   {
7117     SignalException(BreakPoint,instruction);
7118   }
7119 }
7120
7121 \f
7122 // start-sanitize-r5900
7123
7124 // FIXME: The instructions below which are typically r5900 specific
7125 //        need to be merged back into the above.
7126
7127 // end-sanitize-r5900
7128 // start-sanitize-r5900
7129
7130 011100,5.RS,5.RT,0000000000011010:MMINORM:32::DIV1
7131 *r5900:
7132 {
7133   unsigned32 instruction = instruction_0;
7134   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7135   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7136   {
7137     CHECKHILO("Division");
7138     {
7139       int d1 = op1;
7140       int d2 = op2;
7141       if (d2 == 0)
7142         {
7143           LO1 = SIGNEXTEND(0x80000000,32);
7144           HI1 = SIGNEXTEND(0,32);
7145         }
7146       else if (d2 == -1 && d1 == 0x80000000)
7147         {
7148           LO1 = SIGNEXTEND(0x80000000,32);
7149           HI1 = SIGNEXTEND(0,32);
7150         }
7151       else
7152         {
7153           LO1 = SIGNEXTEND((d1 / d2),32);
7154           HI1 = SIGNEXTEND((d1 % d2),32);
7155         }
7156     }
7157   }
7158 }
7159
7160 // end-sanitize-r5900
7161 // start-sanitize-r5900
7162
7163 011100,5.RS,5.RT,0000000000011011:MMINORM:32::DIVU1
7164 *r5900:
7165 {
7166   unsigned32 instruction = instruction_0;
7167   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7168   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7169   {
7170     CHECKHILO("Division");
7171     {
7172       unsigned int d1 = op1;
7173       unsigned int d2 = op2;
7174       if (d2 == 0)
7175         {
7176           LO1 = SIGNEXTEND(0x80000000,32);
7177           HI1 = SIGNEXTEND(0,32);
7178         }
7179       else if (d2 == -1 && d1 == 0x80000000)
7180         {
7181           LO1 = SIGNEXTEND(0x80000000,32);
7182           HI1 = SIGNEXTEND(0,32);
7183         }
7184       else
7185         {
7186           LO1 = SIGNEXTEND((d1 / d2),32);
7187           HI1 = SIGNEXTEND((d1 % d2),32);
7188         }
7189     }
7190   }
7191 }
7192
7193 // end-sanitize-r5900
7194
7195 011101,26.INSTR_INDEX:NORMAL:32::JALX
7196 // start-sanitize-r5900
7197 *r5900:
7198 // end-sanitize-r5900
7199 *r3900:
7200 // start-sanitize-tx19
7201 *tx19:
7202 // end-sanitize-tx19
7203 {
7204   unsigned32 instruction = instruction_0;
7205   unsigned_word op1 = (((instruction >> 0) & 0x03FFFFFF) << 2);
7206   op1 |= (PC & ~0x0FFFFFFF); /* address of instruction in delay slot for the jump */
7207   {
7208     int destreg = 31;
7209     GPR[destreg] = (PC + 4); /* NOTE: The PC is already 4 ahead within the simulator */
7210     op1 ^= 1;
7211     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7212        so we just truncate it to 32 bits here.  */
7213     op1 = VL4_8(op1);
7214     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7215     DELAY_SLOT op1;
7216     /* JALDELAYSLOT(); FIXME */
7217   }
7218 }
7219
7220 // start-sanitize-r5900
7221
7222 011110,5.RS,5.RT,16.OFFSET:NORMAL:128::LQ
7223 *r5900:
7224 {
7225   unsigned32 instruction = instruction_0;
7226   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
7227   int destreg = ((instruction >> 16) & 0x0000001F);
7228   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7229   {
7230     address_word vaddr = ((unsigned64)op1 + offset);
7231     address_word paddr;
7232     int uncached;
7233     if ((vaddr & 15) != 0)
7234       SignalExceptionAddressLoad();
7235     else
7236       {
7237         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
7238           {
7239             unsigned64 memval = 0;
7240             unsigned64 memval1 = 0;
7241             unsigned64 mask = 0x7;
7242             unsigned int shift = 8;
7243             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
7244             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
7245             unsigned int byte;
7246             LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
7247             GPR[destreg] = memval;
7248             GPR1[destreg] = memval1;
7249           }
7250       }
7251   }
7252 }
7253
7254 // end-sanitize-r5900
7255 // start-sanitize-r5900
7256
7257 011100,5.RS,5.RT,5.RD,00000000000:MMINORM:32::MADD
7258 *r5900:
7259 *r3900:
7260 {
7261   unsigned32 instruction = instruction_0;
7262   int destreg = ((instruction >> 11) & 0x0000001F);
7263   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7264   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7265   {
7266     word64 prod = (word64)WORD64(VL4_8(HI),VL4_8(LO)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7267     LO = SIGNEXTEND(prod,32);
7268     HI = SIGNEXTEND( VH4_8(prod), 32);
7269     if( destreg != 0 ) GPR[destreg] = LO;
7270   }
7271 }
7272
7273 // end-sanitize-r5900
7274 // start-sanitize-r5900
7275
7276 011100,5.RS,5.RT,5.RD,00000000001:MMINORM:32::MADDU
7277 *r5900:
7278 *r3900:
7279 {
7280   unsigned32 instruction = instruction_0;
7281   int destreg = ((instruction >> 11) & 0x0000001F);
7282   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7283   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7284   {
7285     unsigned64 prod = (unsigned64)WORD64(VL4_8(HI),VL4_8(LO)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7286     LO = SIGNEXTEND(prod,32);
7287     HI = SIGNEXTEND( VH4_8(prod), 32);
7288     if( destreg != 0 ) GPR[destreg] = LO;
7289   }
7290 }
7291
7292 // end-sanitize-r5900
7293 // start-sanitize-r5900
7294
7295 011100,5.RS,5.RT,5.RD,00000100000:MMINORM:32::MADD1
7296 *r5900:
7297 {
7298   unsigned32 instruction = instruction_0;
7299   int destreg = ((instruction >> 11) & 0x0000001F);
7300   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7301   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7302   {
7303     word64 prod = (word64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7304     LO1 = SIGNEXTEND(prod,32);
7305     HI1 = SIGNEXTEND( VH4_8(prod), 32);
7306     if( destreg != 0 ) GPR[destreg] = LO1;
7307   }
7308 }
7309
7310 // end-sanitize-r5900
7311 // start-sanitize-r5900
7312
7313 011100,5.RS,5.RT,5.RD,00000100001:MMINORM:32::MADDU1
7314 *r5900:
7315 {
7316   unsigned32 instruction = instruction_0;
7317   int destreg = ((instruction >> 11) & 0x0000001F);
7318   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7319   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7320   {
7321     unsigned64 prod = (unsigned64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7322     LO1 = SIGNEXTEND(prod,32);
7323     HI1 = SIGNEXTEND( VH4_8(prod), 32);
7324     if( destreg != 0 ) GPR[destreg] = LO1;
7325   }
7326 }
7327
7328 // end-sanitize-r5900
7329 // start-sanitize-r5900
7330
7331 0111000000000000,5.RD,00000010000:MMINORM:32::MFHI1
7332 *r5900:
7333 {
7334   unsigned32 instruction = instruction_0;
7335   int destreg = ((instruction >> 11) & 0x0000001F);
7336   {
7337     GPR[destreg] = HI1;
7338     HI1ACCESS = 3; /* 3rd instruction will be safe */
7339   }
7340 }
7341
7342 // end-sanitize-r5900
7343 // start-sanitize-r5900
7344
7345 0111000000000000,5.RD,00000010010:MMINORM:32::MFLO1
7346 *r5900:
7347 {
7348   unsigned32 instruction = instruction_0;
7349   int destreg = ((instruction >> 11) & 0x0000001F);
7350   {
7351     GPR[destreg] = LO1;
7352     LO1ACCESS = 3; /* 3rd instruction will be safe */
7353   }
7354 }
7355
7356 // end-sanitize-r5900
7357 // start-sanitize-r5900
7358
7359 0000000000000000,5.RD,00000101000:SPECIAL:32::MFSA
7360 *r5900:
7361 {
7362   unsigned32 instruction = instruction_0;
7363   int destreg = ((instruction >> 11) & 0x0000001F);
7364   {
7365     GPR[destreg] = SA;
7366   }
7367 }
7368
7369 // end-sanitize-r5900
7370 // start-sanitize-r5900
7371
7372 011100,5.RS,000000000000000010001:MMINORM:32::MTHI1
7373 *r5900:
7374 {
7375   unsigned32 instruction = instruction_0;
7376   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7377   {
7378     if (HI1ACCESS != 0)
7379       sim_io_error(sd,"MT (move-to) over-writing HI register value\n");
7380     HI1 = op1;
7381     HI1ACCESS = 3; /* 3rd instruction will be safe */
7382   }
7383 }
7384
7385 // end-sanitize-r5900
7386 // start-sanitize-r5900
7387
7388 011100,5.RS,000000000000000010011:MMINORM:32::MTLO1
7389 *r5900:
7390 {
7391   unsigned32 instruction = instruction_0;
7392   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7393   {
7394     if (LO1ACCESS != 0)
7395       sim_io_error(sd,"MT (move-to) over-writing LO register value");
7396     LO1 = op1;
7397     LO1ACCESS = 3; /* 3rd instruction will be safe */
7398   }
7399 }
7400
7401 // end-sanitize-r5900
7402 // start-sanitize-r5900
7403
7404 000000,5.RS,000000000000000101001:SPECIAL:32::MTSA
7405 *r5900:
7406 {
7407   unsigned32 instruction = instruction_0;
7408   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7409   {
7410     SA = op1;
7411   }
7412 }
7413
7414 // end-sanitize-r5900
7415 // start-sanitize-r5900
7416
7417 000001,5.RS,11000,16.IMMEDIATE:REGIMM:32::MTSAB
7418 *r5900:
7419 {
7420   SA = ((GPR[RA] & 0xF) ^ (IMMEDIATE & 0xF)) * 8;
7421 }
7422
7423 // end-sanitize-r5900
7424 // start-sanitize-r5900
7425
7426 000001,5.RS,11001,16.IMMEDIATE:REGIMM:32::MTSAH
7427 *r5900:
7428 {
7429   SA = ((GPR[RS] & 0x7) ^ (IMMEDIATE & 0x7)) * 16;
7430 }
7431
7432 // end-sanitize-r5900
7433 // start-sanitize-r5900
7434
7435 011100,5.RS,5.RT,5.RD,00000011000:MMINORM:32::MULT1
7436 *r5900:
7437 {
7438   unsigned32 instruction = instruction_0;
7439   int destreg = ((instruction >> 11) & 0x0000001F);
7440   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7441   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7442   {
7443     CHECKHILO("Multiplication");
7444     {
7445       unsigned64 temp = ((word64) op1 * (word64) op2);
7446       LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7447       HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7448       if ( destreg != 0 )
7449         GPR[destreg] = LO1;
7450     }
7451   }
7452 }
7453
7454 // end-sanitize-r5900
7455 // start-sanitize-r5900
7456
7457 011100,5.RS,5.RT,5.RD,00000011001:MMINORM:32::MULTU1
7458 *r5900:
7459 {
7460   unsigned32 instruction = instruction_0;
7461   int destreg = ((instruction >> 11) & 0x0000001F);
7462   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7463   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7464   {
7465     CHECKHILO("Multiplication");
7466     {
7467       unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
7468       LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7469       HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7470       if ( destreg != 0 )
7471         GPR[destreg] = LO1;
7472     }
7473   }
7474 }
7475
7476 // end-sanitize-r5900
7477 // start-sanitize-r5900
7478
7479 01110000000,5.RT,5.RD,00101101000:MMI1:32::PABSH
7480 *r5900:
7481 {
7482   unsigned32 instruction = instruction_0;
7483   int destreg = ((instruction >> 11) & 0x0000001F);
7484   signed_word rt_reg = GPR[RT];
7485   signed_word rt_reg1 = GPR1[RT];
7486   {
7487     int i;
7488     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7489       {
7490         if (RT_SH(i) >= 0)
7491           GPR_SH(destreg,i) =  RT_SH(i);
7492         else if (RT_SH(i) == -32768)
7493           GPR_SH(destreg,i) = 32767;
7494         else
7495           GPR_SH(destreg,i) = -RT_SH(i);
7496       }
7497   }
7498 }
7499
7500 // end-sanitize-r5900
7501 // start-sanitize-r5900
7502
7503 01110000000,5.RT,5.RD,00001101000:MMI1:32::PABSW
7504 *r5900:
7505 {
7506   unsigned32 instruction = instruction_0;
7507   int destreg = ((instruction >> 11) & 0x0000001F);
7508   signed_word rt_reg = GPR[RT];
7509   signed_word rt_reg1 = GPR1[RT];
7510   {
7511     int i;
7512     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7513       {
7514         if (RT_SW(i) >= 0)
7515           GPR_SW(destreg,i) =  RT_SW(i);
7516         else if (RT_SW(i) == (int)0x80000000)
7517           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
7518         else
7519           GPR_SW(destreg,i) = -RT_SW(i);
7520       }
7521   }
7522 }
7523
7524 // end-sanitize-r5900
7525 // start-sanitize-r5900
7526
7527 011100,5.RS,5.RT,5.RD,01000001000:MMI0:32::PADDB
7528 *r5900:
7529 {
7530   unsigned32 instruction = instruction_0;
7531   int destreg = ((instruction >> 11) & 0x0000001F);
7532   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7533   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7534   signed_word rt_reg = GPR[RT];
7535   signed_word rt_reg1 = GPR1[RT];
7536   {
7537     int i;
7538     for (i=0; i < BYTES_IN_MMI_REGS; i++)
7539       {
7540         int s = RS_SB(i);
7541         int t = RT_SB(i);
7542         int r = s + t;
7543         GPR_SB(destreg,i) = r;
7544       }
7545   }
7546 }
7547
7548 // end-sanitize-r5900
7549 // start-sanitize-r5900
7550
7551 011100,5.RS,5.RT,5.RD,00100001000:MMI0:32::PADDH
7552 *r5900:
7553 {
7554   unsigned32 instruction = instruction_0;
7555   int destreg = ((instruction >> 11) & 0x0000001F);
7556   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7557   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
7558   signed_word rt_reg = GPR[RT];
7559   signed_word rt_reg1 = GPR1[RT];
7560   {
7561     int i;
7562     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7563       {
7564         int s = RS_SH(i);
7565         int t = RT_SH(i);
7566         int r = s + t;
7567         GPR_SH(destreg,i) = r;
7568       }
7569   }
7570 }
7571
7572 // end-sanitize-r5900
7573 // start-sanitize-r5900
7574
7575 011100,5.RS,5.RT,5.RD,00000001000:MMI0:32::PADDW
7576 *r5900:
7577 {
7578   unsigned32 instruction = instruction_0;
7579   int destreg = ((instruction >> 11) & 0x0000001F);
7580   signed_word rs_reg = GPR[RS];
7581   signed_word rs_reg1 = GPR1[RS];
7582   signed_word rt_reg = GPR[RT];
7583   signed_word rt_reg1 = GPR1[RT];
7584   {
7585     int i;
7586     for (i=0; i < WORDS_IN_MMI_REGS; i++)
7587       {
7588         signed64 s = RS_SW(i);
7589         signed64 t = RT_SW(i);
7590         signed64 r = s + t;
7591         GPR_SW(destreg,i) = r;
7592       }
7593   }
7594 }
7595
7596 // end-sanitize-r5900
7597 // start-sanitize-r5900
7598
7599 011100,5.RS,5.RT,5.RD,11000001000:MMI0:32::PADDSB
7600 *r5900:
7601 {
7602   unsigned32 instruction = instruction_0;
7603   int destreg = ((instruction >> 11) & 0x0000001F);
7604   signed_word rs_reg = GPR[RS];
7605   signed_word rs_reg1 = GPR1[RS];
7606   signed_word rt_reg = GPR[RT];
7607   signed_word rt_reg1 = GPR1[RT];
7608   {
7609     int i;
7610     for (i=0; i < BYTES_IN_MMI_REGS; i++)
7611       {
7612         int s = RS_SB(i);
7613         int t = RT_SB(i);
7614         int r = s + t;
7615         if (r > 127)
7616           GPR_SB(destreg,i) = 127;
7617         else if (r < -128)
7618           GPR_SB(destreg,i) = -128;
7619         else
7620           GPR_SB(destreg,i) = r;
7621       }
7622   }
7623 }
7624
7625 // end-sanitize-r5900
7626 // start-sanitize-r5900
7627
7628 011100,5.RS,5.RT,5.RD,10100001000:MMI0:32::PADDSH
7629 *r5900:
7630 {
7631   unsigned32 instruction = instruction_0;
7632   int destreg = ((instruction >> 11) & 0x0000001F);
7633   signed_word rs_reg = GPR[RS];
7634   signed_word rs_reg1 = GPR1[RS];
7635   signed_word rt_reg = GPR[RT];
7636   signed_word rt_reg1 = GPR1[RT];
7637   {
7638     int i;
7639     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7640       {
7641         int s = RS_SH(i);
7642         int t = RT_SH(i);
7643         int r = s + t;
7644         if (r > 32767)
7645           GPR_SH(destreg,i) = 32767;
7646         else if (r < -32768)
7647           GPR_SH(destreg,i) = -32768;
7648         else
7649           GPR_SH(destreg,i) = r;
7650       }
7651   }
7652 }
7653
7654 // end-sanitize-r5900
7655 // start-sanitize-r5900
7656
7657 011100,5.RS,5.RT,5.RD,10000001000:MMI0:32::PADDSW
7658 *r5900:
7659 {
7660   unsigned32 instruction = instruction_0;
7661   int destreg = ((instruction >> 11) & 0x0000001F);
7662   signed_word rs_reg = GPR[RS];
7663   signed_word rs_reg1 = GPR1[RS];
7664   signed_word rt_reg = GPR[RT];
7665   signed_word rt_reg1 = GPR1[RT];
7666   {
7667     int i;
7668     for (i=0; i < WORDS_IN_MMI_REGS; i++)
7669       {
7670         signed64 s = RS_SW(i);
7671         signed64 t = RT_SW(i);
7672         signed64 r = s + t;
7673         if (r > (int)0x7FFFFFFF)
7674           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
7675         else if (r < (int)0x80000000)
7676           GPR_SW(destreg,i) = (int)0x80000000;
7677         else
7678           GPR_SW(destreg,i) = r;
7679       }
7680   }
7681 }
7682
7683 // end-sanitize-r5900
7684 // start-sanitize-r5900
7685
7686 011100,5.RS,5.RT,5.RD,11000101000:MMI1:32::PADDUB
7687 *r5900:
7688 {
7689   unsigned32 instruction = instruction_0;
7690   int destreg = ((instruction >> 11) & 0x0000001F);
7691   signed_word rs_reg = GPR[RS];
7692   signed_word rs_reg1 = GPR1[RS];
7693   signed_word rt_reg = GPR[RT];
7694   signed_word rt_reg1 = GPR1[RT];
7695   {
7696     int i;
7697     for (i=0; i < BYTES_IN_MMI_REGS; i++)
7698       {
7699         unsigned int s = RS_UB(i);
7700         unsigned int t = RT_UB(i);
7701         unsigned int r = s + t;
7702         if (r > 0xFF)
7703           GPR_UB(destreg,i) = 0xFF;
7704         else
7705           GPR_UB(destreg,i) = r;
7706       }
7707   }
7708 }
7709
7710 // end-sanitize-r5900
7711 // start-sanitize-r5900
7712
7713 011100,5.RS,5.RT,5.RD,10100101000:MMI1:32::PADDUH
7714 *r5900:
7715 {
7716   unsigned32 instruction = instruction_0;
7717   int destreg = ((instruction >> 11) & 0x0000001F);
7718   signed_word rs_reg = GPR[RS];
7719   signed_word rs_reg1 = GPR1[RS];
7720   signed_word rt_reg = GPR[RT];
7721   signed_word rt_reg1 = GPR1[RT];
7722   {
7723     int i;
7724     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7725       {
7726         unsigned int s = RS_UH(i);
7727         unsigned int t = RT_UH(i);
7728         unsigned int r = s + t;
7729         if (r > 0xFFFF)
7730           GPR_UH(destreg,i) = 0xFFFF;
7731         else
7732           GPR_UH(destreg,i) = r;
7733       }
7734   }
7735 }
7736
7737 // end-sanitize-r5900
7738 // start-sanitize-r5900
7739
7740 011100,5.RS,5.RT,5.RD,10000101000:MMI1:32::PADDUW
7741 *r5900:
7742 {
7743   unsigned32 instruction = instruction_0;
7744   int destreg = ((instruction >> 11) & 0x0000001F);
7745   signed_word rs_reg = GPR[RS];
7746   signed_word rs_reg1 = GPR1[RS];
7747   signed_word rt_reg = GPR[RT];
7748   signed_word rt_reg1 = GPR1[RT];
7749   {
7750     int i;
7751     for (i=0; i < WORDS_IN_MMI_REGS; i++)
7752       {
7753         unsigned64 s = RS_UW(i);
7754         unsigned64 t = RT_UW(i);
7755         unsigned64 r = s + t;
7756         if (r > 0xFFFFFFFF)
7757           GPR_UW(destreg,i) = 0xFFFFFFFF;
7758         else
7759           GPR_UW(destreg,i) = r;
7760       }
7761   }
7762 }
7763
7764 // end-sanitize-r5900
7765 // start-sanitize-r5900
7766
7767 011100,5.RS,5.RT,5.RD,00100101000:MMI1:32::PADSBH
7768 *r5900:
7769 {
7770   unsigned32 instruction = instruction_0;
7771   int destreg = ((instruction >> 11) & 0x0000001F);
7772   signed_word rs_reg = GPR[RS];
7773   signed_word rs_reg1 = GPR1[RS];
7774   signed_word rt_reg = GPR[RT];
7775   signed_word rt_reg1 = GPR1[RT];
7776   {
7777     int i;
7778     for(i=0;i<HALFWORDS_IN_MMI_REGS/2;i++)
7779       GPR_SH(destreg,i) = RS_SH(i) - RT_SH(i);
7780     for(;i<HALFWORDS_IN_MMI_REGS;i++)
7781       GPR_SH(destreg,i) = RS_SH(i) + RT_SH(i);
7782   }
7783 }
7784
7785 // end-sanitize-r5900
7786 // start-sanitize-r5900
7787
7788 011100,5.RS,5.RT,5.RD,10010001001:MMI2:32::PAND
7789 *r5900:
7790 {
7791   unsigned32 instruction = instruction_0;
7792   int destreg = ((instruction >> 11) & 0x0000001F);
7793   signed_word rs_reg = GPR[RS];
7794   signed_word rs_reg1 = GPR1[RS];
7795   signed_word rt_reg = GPR[RT];
7796   signed_word rt_reg1 = GPR1[RT];
7797   {
7798     int i;
7799     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7800       GPR_UW(destreg,i) = (RS_UW(i) & RT_UW(i));
7801   }
7802 }
7803
7804 // end-sanitize-r5900
7805 // start-sanitize-r5900
7806
7807 011100,5.RS,5.RT,5.RD,01010101000:MMI1:32::PCEQB
7808 *r5900:
7809 {
7810   unsigned32 instruction = instruction_0;
7811   int destreg = ((instruction >> 11) & 0x0000001F);
7812   signed_word rs_reg = GPR[RS];
7813   signed_word rs_reg1 = GPR1[RS];
7814   signed_word rt_reg = GPR[RT];
7815   signed_word rt_reg1 = GPR1[RT];
7816   {
7817     int i;
7818     for(i=0;i<BYTES_IN_MMI_REGS;i++)
7819       {
7820         if (RS_SB(i) == RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
7821         else                        GPR_SB(destreg,i) = 0;
7822       }
7823   }
7824 }
7825
7826 // end-sanitize-r5900
7827 // start-sanitize-r5900
7828
7829 011100,5.RS,5.RT,5.RD,00110101000:MMI1:32::PCEQH
7830 *r5900:
7831 {
7832   unsigned32 instruction = instruction_0;
7833   int destreg = ((instruction >> 11) & 0x0000001F);
7834   signed_word rs_reg = GPR[RS];
7835   signed_word rs_reg1 = GPR1[RS];
7836   signed_word rt_reg = GPR[RT];
7837   signed_word rt_reg1 = GPR1[RT];
7838   {
7839     int i;
7840     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7841       {
7842         if (RS_SH(i) == RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
7843         else                        GPR_SH(destreg,i) = 0;
7844       }
7845   }
7846 }
7847
7848 // end-sanitize-r5900
7849 // start-sanitize-r5900
7850
7851 011100,5.RS,5.RT,5.RD,00010101000:MMI1:32::PCEQW
7852 *r5900:
7853 {
7854   unsigned32 instruction = instruction_0;
7855   int destreg = ((instruction >> 11) & 0x0000001F);
7856   signed_word rs_reg = GPR[RS];
7857   signed_word rs_reg1 = GPR1[RS];
7858   signed_word rt_reg = GPR[RT];
7859   signed_word rt_reg1 = GPR1[RT];
7860   {
7861     int i;
7862     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7863       {
7864         if (RS_SW(i) == RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
7865         else                        GPR_SW(destreg,i) = 0;
7866       }
7867   }
7868 }
7869
7870 // end-sanitize-r5900
7871 // start-sanitize-r5900
7872
7873 011100,5.RS,5.RT,5.RD,01010001000:MMI0:32::PCGTB
7874 *r5900:
7875 {
7876   unsigned32 instruction = instruction_0;
7877   int destreg = ((instruction >> 11) & 0x0000001F);
7878   signed_word rs_reg = GPR[RS];
7879   signed_word rs_reg1 = GPR1[RS];
7880   signed_word rt_reg = GPR[RT];
7881   signed_word rt_reg1 = GPR1[RT];
7882   {
7883     int i;
7884     for(i=0;i<BYTES_IN_MMI_REGS;i++)
7885       {
7886         if (RS_SB(i) > RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
7887         else                        GPR_SB(destreg,i) = 0;
7888       }
7889   }
7890 }
7891
7892 // end-sanitize-r5900
7893 // start-sanitize-r5900
7894
7895 011100,5.RS,5.RT,5.RD,00110001000:MMI0:32::PCGTH
7896 *r5900:
7897 {
7898   unsigned32 instruction = instruction_0;
7899   int destreg = ((instruction >> 11) & 0x0000001F);
7900   signed_word rs_reg = GPR[RS];
7901   signed_word rs_reg1 = GPR1[RS];
7902   signed_word rt_reg = GPR[RT];
7903   signed_word rt_reg1 = GPR1[RT];
7904   {
7905     int i;
7906     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7907       {
7908         if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
7909         else                        GPR_SH(destreg,i) = 0;
7910       }
7911   }
7912 }
7913
7914 // end-sanitize-r5900
7915 // start-sanitize-r5900
7916
7917 011100,5.RS,5.RT,5.RD,00010001000:MMI0:32::PCGTW
7918 *r5900:
7919 {
7920   unsigned32 instruction = instruction_0;
7921   int destreg = ((instruction >> 11) & 0x0000001F);
7922   signed_word rs_reg = GPR[RS];
7923   signed_word rs_reg1 = GPR1[RS];
7924   signed_word rt_reg = GPR[RT];
7925   signed_word rt_reg1 = GPR1[RT];
7926   {
7927     int i;
7928     for(i=0;i<WORDS_IN_MMI_REGS;i++)
7929       {
7930         if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
7931         else                        GPR_SW(destreg,i) = 0;
7932       }
7933   }
7934 }
7935
7936 // end-sanitize-r5900
7937 // start-sanitize-r5900
7938
7939 01110000000,5.RT,5.RD,11011101001:MMI3:32::PCPYH
7940 *r5900:
7941 {
7942   unsigned32 instruction = instruction_0;
7943   int destreg = ((instruction >> 11) & 0x0000001F);
7944   signed_word rt_reg = GPR[RT];
7945   signed_word rt_reg1 = GPR1[RT];
7946   {
7947     GPR_UH(destreg,7) = GPR_UH(destreg,6) = GPR_UH(destreg,5) = GPR_UH(destreg,4) = RT_UH(4);
7948     GPR_UH(destreg,3) = GPR_UH(destreg,2) = GPR_UH(destreg,1) = GPR_UH(destreg,0) = RT_UH(0);
7949   }
7950 }
7951
7952 // end-sanitize-r5900
7953 // start-sanitize-r5900
7954
7955 011100,5.RS,5.RT,5.RD,01110001001:MMI2:32::PCPYLD
7956 *r5900:
7957 {
7958   unsigned32 instruction = instruction_0;
7959   int destreg = ((instruction >> 11) & 0x0000001F);
7960   signed_word rs_reg = GPR[RS];
7961   signed_word rs_reg1 = GPR1[RS];
7962   signed_word rt_reg = GPR[RT];
7963   signed_word rt_reg1 = GPR1[RT];
7964   {
7965     GPR_UD(destreg,0) = RT_UD(0);
7966     GPR_UD(destreg,1) = RS_UD(0);
7967   }
7968 }
7969
7970 // end-sanitize-r5900
7971 // start-sanitize-r5900
7972
7973 011100,5.RS,5.RT,5.RD,01110101001:MMI3:32::PCPYUD
7974 *r5900:
7975 {
7976   unsigned32 instruction = instruction_0;
7977   int destreg = ((instruction >> 11) & 0x0000001F);
7978   signed_word rs_reg = GPR[RS];
7979   signed_word rs_reg1 = GPR1[RS];
7980   signed_word rt_reg = GPR[RT];
7981   signed_word rt_reg1 = GPR1[RT];
7982   {
7983     GPR_UD(destreg,0) = RS_UD(1);
7984     GPR_UD(destreg,1) = RT_UD(1);
7985   }
7986 }
7987
7988 // end-sanitize-r5900
7989 // start-sanitize-r5900
7990
7991 011100,5.RS,5.RT,0000011101001001:MMI2:32::PDIVBW
7992 *r5900:
7993 {
7994   signed_word rs_reg = GPR[RS];
7995   signed_word rs_reg1 = GPR1[RS];
7996   signed_word rt_reg = GPR[RT];
7997   signed_word rt_reg1 = GPR1[RT];
7998   {
7999     signed32 devisor = RT_SH(0);
8000     if (devisor == -1)
8001       {
8002         LO_SW(0) = -RS_SW(0);
8003         HI_SW(0) = 0;
8004         LO_SW(1) = -RS_SW(1);
8005         HI_SW(1) = 0;
8006         LO_SW(2) = -RS_SW(2);
8007         HI_SW(2) = 0;
8008         LO_SW(3) = -RS_SW(3);
8009         HI_SW(3) = 0;
8010       }
8011     else if (devisor != 0)
8012       {
8013         LO_SW(0) = RS_SW(0) / devisor;
8014         HI_SW(0) = SIGNEXTEND( (RS_SW(0) % devisor), 16 );
8015         LO_SW(1) = RS_SW(1) / devisor;
8016         HI_SW(1) = SIGNEXTEND( (RS_SW(1) % devisor), 16 );
8017         LO_SW(2) = RS_SW(2) / devisor;
8018         HI_SW(2) = SIGNEXTEND( (RS_SW(2) % devisor), 16 );
8019         LO_SW(3) = RS_SW(3) / devisor;
8020         HI_SW(3) = SIGNEXTEND( (RS_SW(3) % devisor), 16 );
8021       }
8022   }
8023 }
8024
8025 // end-sanitize-r5900
8026 // start-sanitize-r5900
8027
8028 011100,5.RS,5.RT,0000001101101001:MMI3:32::PDIVUW
8029 *r5900:
8030 {
8031   signed_word rs_reg = GPR[RS];
8032   signed_word rs_reg1 = GPR1[RS];
8033   signed_word rt_reg = GPR[RT];
8034   signed_word rt_reg1 = GPR1[RT];
8035   {
8036     if (RT_UW(0) != 0)
8037       {
8038         LO  = (signed32)(RS_UW(0) / RT_UW(0));
8039         HI  = (signed32)(RS_UW(0) % RT_UW(0));
8040       }
8041     if (RT_UW(2) != 0)
8042       {
8043         LO1 = (signed32)(RS_UW(2) / RT_UW(2));
8044         HI1 = (signed32)(RS_UW(2) % RT_UW(2));
8045       }
8046   }
8047 }
8048
8049 // end-sanitize-r5900
8050 // start-sanitize-r5900
8051
8052 011100,5.RS,5.RT,0000001101001001:MMI2:32::PDIVW
8053 *r5900:
8054 {
8055   signed_word rs_reg = GPR[RS];
8056   signed_word rs_reg1 = GPR1[RS];
8057   signed_word rt_reg = GPR[RT];
8058   signed_word rt_reg1 = GPR1[RT];
8059   {
8060     if (RT_SW(0) == -1)
8061       {
8062         LO  = -RS_SW(0);
8063         HI  = 0;
8064       }
8065     else if (RT_UW(0) != 0)
8066       {
8067         LO  = (signed32)(RS_SW(0) / RT_SW(0));
8068         HI  = (signed32)(RS_SW(0) % RT_SW(0));
8069       }
8070     if (RT_SW(2) == -1)
8071       {
8072         LO1 = -RS_SW(2);
8073         HI1 = 0;
8074       }
8075     else if (RT_UW(2) != 0)
8076       {
8077         LO1 = (signed32)(RS_SW(2) / RT_SW(2));
8078         HI1 = (signed32)(RS_SW(2) % RT_SW(2));
8079       }
8080   }
8081 }
8082
8083 // end-sanitize-r5900
8084 // start-sanitize-r5900
8085
8086 01110000000,5.RT,5.RD,11010101001:MMI3:32::PEXCH
8087 *r5900:
8088 {
8089   unsigned32 instruction = instruction_0;
8090   int destreg = ((instruction >> 11) & 0x0000001F);
8091   signed_word rt_reg = GPR[RT];
8092   signed_word rt_reg1 = GPR1[RT];
8093   {
8094     GPR_UH(destreg,0) = RT_UH(0);
8095     GPR_UH(destreg,1) = RT_UH(2);
8096     GPR_UH(destreg,2) = RT_UH(1);
8097     GPR_UH(destreg,3) = RT_UH(3);
8098     GPR_UH(destreg,4) = RT_UH(4);
8099     GPR_UH(destreg,5) = RT_UH(6);
8100     GPR_UH(destreg,6) = RT_UH(5);
8101     GPR_UH(destreg,7) = RT_UH(7);
8102   }
8103 }
8104
8105 // end-sanitize-r5900
8106 // start-sanitize-r5900
8107
8108 01110000000,5.RT,5.RD,11110101001:MMI3:32::PEXCW
8109 *r5900:
8110 {
8111   unsigned32 instruction = instruction_0;
8112   int destreg = ((instruction >> 11) & 0x0000001F);
8113   signed_word rt_reg = GPR[RT];
8114   signed_word rt_reg1 = GPR1[RT];
8115   {
8116     GPR_UW(destreg,0) = RT_UW(0);
8117     GPR_UW(destreg,1) = RT_UW(2);
8118     GPR_UW(destreg,2) = RT_UW(1);
8119     GPR_UW(destreg,3) = RT_UW(3);
8120   }
8121 }
8122
8123 // end-sanitize-r5900
8124 // start-sanitize-r5900
8125
8126 01110000000,5.RT,5.RD,11010001001:MMI2:32::PEXOH
8127 *r5900:
8128 {
8129   unsigned32 instruction = instruction_0;
8130   int destreg = ((instruction >> 11) & 0x0000001F);
8131   signed_word rt_reg = GPR[RT];
8132   signed_word rt_reg1 = GPR1[RT];
8133   {
8134     GPR_UH(destreg,0) = RT_UH(2);
8135     GPR_UH(destreg,1) = RT_UH(1);
8136     GPR_UH(destreg,2) = RT_UH(0);
8137     GPR_UH(destreg,3) = RT_UH(3);
8138     GPR_UH(destreg,4) = RT_UH(6);
8139     GPR_UH(destreg,5) = RT_UH(5);
8140     GPR_UH(destreg,6) = RT_UH(4);
8141     GPR_UH(destreg,7) = RT_UH(7);
8142   }
8143 }
8144
8145 // end-sanitize-r5900
8146 // start-sanitize-r5900
8147
8148 01110000000,5.RT,5.RD,11110001001:MMI2:32::PEXOW
8149 *r5900:
8150 {
8151   unsigned32 instruction = instruction_0;
8152   int destreg = ((instruction >> 11) & 0x0000001F);
8153   signed_word rt_reg = GPR[RT];
8154   signed_word rt_reg1 = GPR1[RT];
8155   {
8156     GPR_UW(destreg,0) = RT_UW(2);
8157     GPR_UW(destreg,1) = RT_UW(1);
8158     GPR_UW(destreg,2) = RT_UW(0);
8159     GPR_UW(destreg,3) = RT_UW(3);
8160   }
8161 }
8162
8163 // end-sanitize-r5900
8164 // start-sanitize-r5900
8165
8166 01110000000,5.RT,5.RD,11110001000:MMI0:32::PEXT5
8167 *r5900:
8168 {
8169   unsigned32 instruction = instruction_0;
8170   int destreg = ((instruction >> 11) & 0x0000001F);
8171   signed_word rt_reg = GPR[RT];
8172   signed_word rt_reg1 = GPR1[RT];
8173   {
8174     int i;
8175     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8176       {
8177         unsigned32 x = RT_UW(i);
8178         GPR_UW(destreg,i) = ((x & (1  << 15)) << (31 - 15))
8179           | ((x & (31 << 10)) << (19 - 10))
8180           | ((x & (31 << 5))  << (11 - 5))
8181           | ((x & (31 << 0))  << (3  - 0));
8182       }
8183   }
8184 }
8185
8186 // end-sanitize-r5900
8187 // start-sanitize-r5900
8188
8189 011100,5.RS,5.RT,5.RD,11010001000:MMI0:32::PEXTLB
8190 *r5900:
8191 {
8192   unsigned32 instruction = instruction_0;
8193   int destreg = ((instruction >> 11) & 0x0000001F);
8194   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8195   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8196   signed_word rt_reg = GPR[RT];
8197   signed_word rt_reg1 = GPR1[RT];
8198   {
8199     GPR_UB(destreg,0)  = RT_UB(0);
8200     GPR_UB(destreg,1)  = RS_UB(0);
8201     GPR_UB(destreg,2)  = RT_UB(1);
8202     GPR_UB(destreg,3)  = RS_UB(1);
8203     GPR_UB(destreg,4)  = RT_UB(2);
8204     GPR_UB(destreg,5)  = RS_UB(2);
8205     GPR_UB(destreg,6)  = RT_UB(3);
8206     GPR_UB(destreg,7)  = RS_UB(3);
8207     GPR_UB(destreg,8)  = RT_UB(4);
8208     GPR_UB(destreg,9)  = RS_UB(4);
8209     GPR_UB(destreg,10) = RT_UB(5);
8210     GPR_UB(destreg,11) = RS_UB(5);
8211     GPR_UB(destreg,12) = RT_UB(6);
8212     GPR_UB(destreg,13) = RS_UB(6);
8213     GPR_UB(destreg,14) = RT_UB(7);
8214     GPR_UB(destreg,15) = RS_UB(7);
8215   }
8216 }
8217
8218 // end-sanitize-r5900
8219 // start-sanitize-r5900
8220
8221 011100,5.RS,5.RT,5.RD,10110001000:MMI0:32::PEXTLH
8222 *r5900:
8223 {
8224   unsigned32 instruction = instruction_0;
8225   int destreg = ((instruction >> 11) & 0x0000001F);
8226   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8227   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8228   signed_word rt_reg = GPR[RT];
8229   signed_word rt_reg1 = GPR1[RT];
8230   {
8231     GPR_UH(destreg,0)  = RT_UH(0);
8232     GPR_UH(destreg,1)  = RS_UH(0);
8233     GPR_UH(destreg,2)  = RT_UH(1);
8234     GPR_UH(destreg,3)  = RS_UH(1);
8235     GPR_UH(destreg,4)  = RT_UH(2);
8236     GPR_UH(destreg,5)  = RS_UH(2);
8237     GPR_UH(destreg,6)  = RT_UH(3);
8238     GPR_UH(destreg,7)  = RS_UH(3);
8239   }
8240 }
8241
8242 // end-sanitize-r5900
8243 // start-sanitize-r5900
8244
8245 011100,5.RS,5.RT,5.RD,10010001000:MMI0:32::PEXTLW
8246 *r5900:
8247 {
8248   unsigned32 instruction = instruction_0;
8249   int destreg = ((instruction >> 11) & 0x0000001F);
8250   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8251   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8252   signed_word rt_reg = GPR[RT];
8253   signed_word rt_reg1 = GPR1[RT];
8254   {
8255     GPR_UW(destreg,0)  = RT_UW(0);
8256     GPR_UW(destreg,1)  = RS_UW(0);
8257     GPR_UW(destreg,2)  = RT_UW(1);
8258     GPR_UW(destreg,3)  = RS_UW(1);
8259   }
8260 }
8261
8262 // end-sanitize-r5900
8263 // start-sanitize-r5900
8264
8265 011100,5.RS,5.RT,5.RD,11010101000:MMI1:32::PEXTUB
8266 *r5900:
8267 {
8268   unsigned32 instruction = instruction_0;
8269   int destreg = ((instruction >> 11) & 0x0000001F);
8270   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8271   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8272   signed_word rt_reg = GPR[RT];
8273   signed_word rt_reg1 = GPR1[RT];
8274   {
8275     GPR_UB(destreg,0)  = RT_UB(8);
8276     GPR_UB(destreg,1)  = RS_UB(8);
8277     GPR_UB(destreg,2)  = RT_UB(9);
8278     GPR_UB(destreg,3)  = RS_UB(9);
8279     GPR_UB(destreg,4)  = RT_UB(10);
8280     GPR_UB(destreg,5)  = RS_UB(10);
8281     GPR_UB(destreg,6)  = RT_UB(11);
8282     GPR_UB(destreg,7)  = RS_UB(11);
8283     GPR_UB(destreg,8)  = RT_UB(12);
8284     GPR_UB(destreg,9)  = RS_UB(12);
8285     GPR_UB(destreg,10) = RT_UB(13);
8286     GPR_UB(destreg,11) = RS_UB(13);
8287     GPR_UB(destreg,12) = RT_UB(14);
8288     GPR_UB(destreg,13) = RS_UB(14);
8289     GPR_UB(destreg,14) = RT_UB(15);
8290     GPR_UB(destreg,15) = RS_UB(15);
8291   }
8292 }
8293
8294 // end-sanitize-r5900
8295 // start-sanitize-r5900
8296
8297 011100,5.RS,5.RT,5.RD,10110101000:MMI1:32::PEXTUH
8298 *r5900:
8299 {
8300   unsigned32 instruction = instruction_0;
8301   int destreg = ((instruction >> 11) & 0x0000001F);
8302   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8303   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8304   signed_word rt_reg = GPR[RT];
8305   signed_word rt_reg1 = GPR1[RT];
8306   {
8307     GPR_UH(destreg,0)  = RT_UH(4);
8308     GPR_UH(destreg,1)  = RS_UH(4);
8309     GPR_UH(destreg,2)  = RT_UH(5);
8310     GPR_UH(destreg,3)  = RS_UH(5);
8311     GPR_UH(destreg,4)  = RT_UH(6);
8312     GPR_UH(destreg,5)  = RS_UH(6);
8313     GPR_UH(destreg,6)  = RT_UH(7);
8314     GPR_UH(destreg,7)  = RS_UH(7);
8315   }
8316 }
8317
8318 // end-sanitize-r5900
8319 // start-sanitize-r5900
8320
8321 011100,5.RS,5.RT,5.RD,10010101000:MMI1:32::PEXTUW
8322 *r5900:
8323 {
8324   unsigned32 instruction = instruction_0;
8325   int destreg = ((instruction >> 11) & 0x0000001F);
8326   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8327   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8328   signed_word rt_reg = GPR[RT];
8329   signed_word rt_reg1 = GPR1[RT];
8330   {
8331     GPR_UW(destreg,0)  = RT_UW(2);
8332     GPR_UW(destreg,1)  = RS_UW(2);
8333     GPR_UW(destreg,2)  = RT_UW(3);
8334     GPR_UW(destreg,3)  = RS_UW(3);
8335   }
8336 }
8337
8338 // end-sanitize-r5900
8339 // start-sanitize-r5900
8340
8341 011100,5.RS,5.RT,5.RD,10001001001:MMI2:32::PHMADDH
8342 *r5900:
8343 {
8344   unsigned32 instruction = instruction_0;
8345   int destreg = ((instruction >> 11) & 0x0000001F);
8346   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8347   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8348   signed_word rt_reg = GPR[RT];
8349   signed_word rt_reg1 = GPR1[RT];
8350   {
8351     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) + (RS_SH(0) * RT_SH(0));
8352     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) + (RS_SH(2) * RT_SH(2));
8353     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) + (RS_SH(4) * RT_SH(4));
8354     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) + (RS_SH(6) * RT_SH(6));
8355   }
8356 }
8357
8358 // end-sanitize-r5900
8359 // start-sanitize-r5900
8360
8361 011100,5.RS,5.RT,5.RD,10101001001:MMI2:32::PHMSUBH
8362 *r5900:
8363 {
8364   unsigned32 instruction = instruction_0;
8365   int destreg = ((instruction >> 11) & 0x0000001F);
8366   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8367   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8368   signed_word rt_reg = GPR[RT];
8369   signed_word rt_reg1 = GPR1[RT];
8370   {
8371     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) - (RS_SH(0) * RT_SH(0));
8372     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) - (RS_SH(2) * RT_SH(2));
8373     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) - (RS_SH(4) * RT_SH(4));
8374     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) - (RS_SH(6) * RT_SH(6));
8375   }
8376 }
8377
8378 // end-sanitize-r5900
8379 // start-sanitize-r5900
8380
8381 011100,5.RS,5.RT,5.RD,01010001001:MMI2:32::PINTH
8382 *r5900:
8383 {
8384   unsigned32 instruction = instruction_0;
8385   int destreg = ((instruction >> 11) & 0x0000001F);
8386   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8387   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8388   signed_word rt_reg = GPR[RT];
8389   signed_word rt_reg1 = GPR1[RT];
8390   {
8391     GPR_UH(destreg,0)  = RT_UH(0);
8392     GPR_UH(destreg,1)  = RS_UH(4);
8393     GPR_UH(destreg,2)  = RT_UH(1);
8394     GPR_UH(destreg,3)  = RS_UH(5);
8395     GPR_UH(destreg,4)  = RT_UH(2);
8396     GPR_UH(destreg,5)  = RS_UH(6);
8397     GPR_UH(destreg,6)  = RT_UH(3);
8398     GPR_UH(destreg,7)  = RS_UH(7);
8399   }
8400 }
8401
8402 // end-sanitize-r5900
8403 // start-sanitize-r5900
8404
8405 011100,5.RS,5.RT,5.RD,01010101001:MMI3:32::PINTOH
8406 *r5900:
8407 {
8408   unsigned32 instruction = instruction_0;
8409   int destreg = ((instruction >> 11) & 0x0000001F);
8410   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8411   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8412   signed_word rt_reg = GPR[RT];
8413   signed_word rt_reg1 = GPR1[RT];
8414   {
8415     GPR_UH(destreg,0) = RT_UH(0);
8416     GPR_UH(destreg,1) = RS_UH(0);
8417     GPR_UH(destreg,2) = RT_UH(2);
8418     GPR_UH(destreg,3) = RS_UH(2);
8419     GPR_UH(destreg,4) = RT_UH(4);
8420     GPR_UH(destreg,5) = RS_UH(4);
8421     GPR_UH(destreg,6) = RT_UH(6);
8422     GPR_UH(destreg,7) = RS_UH(6);
8423   }
8424 }
8425
8426 // end-sanitize-r5900
8427 // start-sanitize-r5900
8428
8429 011100,5.RS,00000,5.RD,00000000100:MMINORM:32::PLZCW
8430 *r5900:
8431 {
8432   unsigned32 instruction = instruction_0;
8433   int destreg = ((instruction >> 11) & 0x0000001F);
8434   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8435   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8436   {
8437     unsigned long value;
8438     int test;
8439     int count;
8440     int i;
8441     value = RS_UW(0);
8442     count = 0;
8443     test = !!(value & (1 << 31));
8444     for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8445       count++;
8446     GPR_UW(destreg,0) = count;
8447     value = RS_UW(1);
8448     count = 0;
8449     test = !!(value & (1 << 31));
8450     for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8451       count++;
8452     GPR_UW(destreg,1) = count;
8453   }
8454 }
8455
8456 // end-sanitize-r5900
8457 // start-sanitize-r5900
8458
8459 011100,5.RS,5.RT,5.RD,10000001001:MMI2:32::PMADDH
8460 *r5900:
8461 {
8462   unsigned32 instruction = instruction_0;
8463   int destreg = ((instruction >> 11) & 0x0000001F);
8464   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8465   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8466   signed_word rt_reg = GPR[RT];
8467   signed_word rt_reg1 = GPR1[RT];
8468   {
8469     GPR_SW(destreg,0) = LO_SW(0) += (RS_SH(0) * RT_SH(0));
8470     LO_SW(1) += (RS_SH(1) * RT_SH(1));
8471     GPR_SW(destreg,1) = HI_SW(0) += (RS_SH(2) * RT_SH(2));
8472     HI_SW(1) += (RS_SH(3) * RT_SH(3));
8473     GPR_SW(destreg,2) = LO_SW(2) += (RS_SH(4) * RT_SH(4));
8474     LO_SW(3) += (RS_SH(5) * RT_SH(5));
8475     GPR_SW(destreg,3) = HI_SW(2) += (RS_SH(6) * RT_SH(6));
8476     HI_SW(3) += (RS_SH(7) * RT_SH(7));
8477   }
8478 }
8479
8480 // end-sanitize-r5900
8481 // start-sanitize-r5900
8482
8483 011100,5.RS,5.RT,5.RD,00000101001:MMI3:32::PMADDUW
8484 *r5900:
8485 {
8486   unsigned32 instruction = instruction_0;
8487   int destreg = ((instruction >> 11) & 0x0000001F);
8488   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8489   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8490   signed_word rt_reg = GPR[RT];
8491   signed_word rt_reg1 = GPR1[RT];
8492   {
8493     unsigned64 sum0 = U8_4 (HI_SW(0), LO_SW(0));
8494     unsigned64 sum1 = U8_4 (HI_SW(2), LO_SW(2));
8495     unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
8496     unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
8497     sum0 += prod0;
8498     sum1 += prod1;
8499     GPR_UD(destreg,0) = sum0;
8500     GPR_UD(destreg,1) = sum1;
8501     LO  = SIGNEXTEND( sum0, 32 );
8502     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8503     LO1 = SIGNEXTEND( sum1, 32 );
8504     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8505   }
8506 }
8507
8508 // end-sanitize-r5900
8509 // start-sanitize-r5900
8510
8511 011100,5.RS,5.RT,5.RD,00000001001:MMI2:32::PMADDW
8512 *r5900:
8513 {
8514   unsigned32 instruction = instruction_0;
8515   int destreg = ((instruction >> 11) & 0x0000001F);
8516   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8517   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8518   signed_word rt_reg = GPR[RT];
8519   signed_word rt_reg1 = GPR1[RT];
8520   {
8521     signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
8522     signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
8523     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8524     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8525     sum0 += prod0;
8526     sum1 += prod1;
8527     GPR_SD(destreg,0) = sum0;
8528     GPR_SD(destreg,1) = sum1;
8529     LO  = SIGNEXTEND( sum0, 32 );
8530     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8531     LO1 = SIGNEXTEND( sum1, 32 );
8532     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8533   }
8534 }
8535
8536 // end-sanitize-r5900
8537 // start-sanitize-r5900
8538
8539 011100,5.RS,5.RT,5.RD,00111001000:MMI0:32::PMAXH
8540 *r5900:
8541 {
8542   unsigned32 instruction = instruction_0;
8543   int destreg = ((instruction >> 11) & 0x0000001F);
8544   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8545   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8546   signed_word rt_reg = GPR[RT];
8547   signed_word rt_reg1 = GPR1[RT];
8548   {
8549     int i;
8550     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8551       {
8552         if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
8553         else                        GPR_SH(destreg,i) = RT_SH(i);
8554       }
8555   }
8556 }
8557
8558 // end-sanitize-r5900
8559 // start-sanitize-r5900
8560
8561 011100,5.RS,5.RT,5.RD,00011001000:MMI0:32::PMAXW
8562 *r5900:
8563 {
8564   unsigned32 instruction = instruction_0;
8565   int destreg = ((instruction >> 11) & 0x0000001F);
8566   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8567   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8568   signed_word rt_reg = GPR[RT];
8569   signed_word rt_reg1 = GPR1[RT];
8570   {
8571     int i;
8572     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8573       {
8574         if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
8575         else                        GPR_SW(destreg,i) = RT_SW(i);
8576       }
8577   }
8578 }
8579
8580 // end-sanitize-r5900
8581 // start-sanitize-r5900
8582
8583 0111000000000000,5.RD,01000001001:MMI2:32::PMFHI
8584 *r5900:
8585 {
8586   unsigned32 instruction = instruction_0;
8587   int destreg = ((instruction >> 11) & 0x0000001F);
8588   {
8589     GPR_SD(destreg,0) = HI;
8590     GPR_SD(destreg,1) = HI1;
8591   }
8592 }
8593
8594 // end-sanitize-r5900
8595 // start-sanitize-r5900
8596
8597 0111000000000000,5.RD,01001001001:MMI2:32::PMFLO
8598 *r5900:
8599 {
8600   unsigned32 instruction = instruction_0;
8601   int destreg = ((instruction >> 11) & 0x0000001F);
8602   {
8603     GPR_SD(destreg,0) = LO;
8604     GPR_SD(destreg,1) = LO1;
8605   }
8606 }
8607
8608 // end-sanitize-r5900
8609 // start-sanitize-r5900
8610
8611 0111000000000000,5.RD,5.SHIFT,110000:MMINORM:32::PMFHL
8612 *r5900:
8613 {
8614   unsigned32 instruction = instruction_0;
8615   int op1 = ((instruction >> 6) & 0x0000001F);
8616   int destreg = ((instruction >> 11) & 0x0000001F);
8617   {
8618     if (op1 == 0)
8619       {
8620         GPR_UW(destreg,0) = LO_UW(0);
8621         GPR_UW(destreg,1) = HI_UW(0);
8622         GPR_UW(destreg,2) = LO_UW(2);
8623         GPR_UW(destreg,3) = HI_UW(2);
8624       }
8625     else if (op1 == 1)
8626       {
8627         GPR_UW(destreg,0) = LO_UW(1);
8628         GPR_UW(destreg,1) = HI_UW(1);
8629         GPR_UW(destreg,2) = LO_UW(3);
8630         GPR_UW(destreg,3) = HI_UW(3);
8631       }
8632     else if (op1 == 2)
8633       {
8634         /* NOTE: This code implements a saturate according to the
8635            figure on page B-115 and not according to the
8636            definition on page B-113 */
8637         signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0);
8638         signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2);
8639         if ( t > SIGNED64 (0x000000007FFFFFFF) )
8640           GPR_SD(destreg,0) = SIGNED64 (0x000000007FFFFFFF);
8641         else if ( t < - SIGNED64 (0x0000000080000000) )
8642           GPR_SD(destreg,0) = - SIGNED64 (0x0000000080000000);
8643         else
8644           GPR_SD(destreg,0) = t;
8645         if ( u > SIGNED64 (0x000000007FFFFFFF) )
8646           GPR_SD(destreg,1) = SIGNED64 (0x000000007FFFFFFF);
8647         else if ( u < - SIGNED64 (0x0000000080000000) )
8648           GPR_SD(destreg,1) = - SIGNED64 (0x0000000080000000);
8649         else
8650           GPR_SD(destreg,1) = u;
8651       }
8652     else if (op1 == 3)
8653       {
8654         GPR_UH(destreg,0) = LO_UH(0);
8655         GPR_UH(destreg,1) = LO_UH(2);
8656         GPR_UH(destreg,2) = HI_UH(0);
8657         GPR_UH(destreg,3) = HI_UH(2);
8658         GPR_UH(destreg,4) = LO_UH(4);
8659         GPR_UH(destreg,5) = LO_UH(6);
8660         GPR_UH(destreg,6) = HI_UH(4);
8661         GPR_UH(destreg,7) = HI_UH(6);
8662       }
8663     else if (op1 == 4)
8664       {
8665         if (LO_SW(0) > 0x7FFF)
8666           GPR_UH(destreg,0) = 0x7FFF;
8667         else if (LO_SW(0) < -0x8000)
8668           GPR_UH(destreg,0) = 0x8000;
8669         else
8670           GPR_UH(destreg,0) = LO_UH(0);
8671         if (LO_SW(1) > 0x7FFF)
8672           GPR_UH(destreg,1) = 0x7FFF;
8673         else if (LO_SW(1) < -0x8000)
8674           GPR_UH(destreg,1) = 0x8000;
8675         else
8676           GPR_UH(destreg,1) = LO_UH(2);
8677         if (HI_SW(0) > 0x7FFF)
8678           GPR_UH(destreg,2) = 0x7FFF;
8679         else if (HI_SW(0) < -0x8000)
8680           GPR_UH(destreg,2) = 0x8000;
8681         else
8682           GPR_UH(destreg,2) = HI_UH(0);
8683         if (HI_SW(1) > 0x7FFF)
8684           GPR_UH(destreg,3) = 0x7FFF;
8685         else if (HI_SW(1) < -0x8000)
8686           GPR_UH(destreg,3) = 0x8000;
8687         else
8688           GPR_UH(destreg,3) = HI_UH(2);
8689         if (LO_SW(2) > 0x7FFF)
8690           GPR_UH(destreg,4) = 0x7FFF;
8691         else if (LO_SW(2) < -0x8000)
8692           GPR_UH(destreg,4) = 0x8000;
8693         else
8694           GPR_UH(destreg,4) = LO_UH(4);
8695         if (LO_SW(3) > 0x7FFF)
8696           GPR_UH(destreg,5) = 0x7FFF;
8697         else if (LO_SW(3) < -0x8000)
8698           GPR_UH(destreg,5) = 0x8000;
8699         else
8700           GPR_UH(destreg,5) = LO_UH(6);
8701         if (HI_SW(2) > 0x7FFF)
8702           GPR_UH(destreg,6) = 0x7FFF;
8703         else if (HI_SW(2) < -0x8000)
8704           GPR_UH(destreg,6) = 0x8000;
8705         else
8706           GPR_UH(destreg,6) = HI_UH(4);
8707         if (HI_SW(3) > 0x7FFF)
8708           GPR_UH(destreg,7) = 0x7FFF;
8709         else if (HI_SW(3) < -0x8000)
8710           GPR_UH(destreg,7) = 0x8000;
8711         else
8712           GPR_UH(destreg,7) = HI_UH(6);
8713       }
8714   }
8715 }
8716
8717 // end-sanitize-r5900
8718 // start-sanitize-r5900
8719
8720 011100,5.RS,5.RT,5.RD,00111101000:MMI1:32::PMINH
8721 *r5900:
8722 {
8723   unsigned32 instruction = instruction_0;
8724   int destreg = ((instruction >> 11) & 0x0000001F);
8725   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8726   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8727   signed_word rt_reg = GPR[RT];
8728   signed_word rt_reg1 = GPR1[RT];
8729   {
8730     int i;
8731     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8732       {
8733         if (RS_SH(i) < RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
8734         else                        GPR_SH(destreg,i) = RT_SH(i);
8735       }
8736   }
8737 }
8738
8739 // end-sanitize-r5900
8740 // start-sanitize-r5900
8741
8742 011100,5.RS,5.RT,5.RD,00011101000:MMI1:32::PMINW
8743 *r5900:
8744 {
8745   unsigned32 instruction = instruction_0;
8746   int destreg = ((instruction >> 11) & 0x0000001F);
8747   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8748   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8749   signed_word rt_reg = GPR[RT];
8750   signed_word rt_reg1 = GPR1[RT];
8751   {
8752     int i;
8753     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8754       {
8755         if (RS_SW(i) < RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
8756         else                        GPR_SW(destreg,i) = RT_SW(i);
8757       }
8758   }
8759 }
8760
8761 // end-sanitize-r5900
8762 // start-sanitize-r5900
8763
8764 011100,5.RS,5.RT,5.RD,10100001001:MMI2:32::PMSUBH
8765 *r5900:
8766 {
8767   unsigned32 instruction = instruction_0;
8768   int destreg = ((instruction >> 11) & 0x0000001F);
8769   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8770   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8771   signed_word rt_reg = GPR[RT];
8772   signed_word rt_reg1 = GPR1[RT];
8773   {
8774     GPR_SW(destreg,0) = LO_SW(0) -= (RS_SH(0) * RT_SH(0));
8775     LO_SW(1) -= (RS_SH(1) * RT_SH(1));
8776     GPR_SW(destreg,1) = HI_SW(0) -= (RS_SH(2) * RT_SH(2));
8777     HI_SW(1) -= (RS_SH(3) * RT_SH(3));
8778     GPR_SW(destreg,2) = LO_SW(2) -= (RS_SH(4) * RT_SH(4));
8779     LO_SW(3) -= (RS_SH(5) * RT_SH(5));
8780     GPR_SW(destreg,3) = HI_SW(2) -= (RS_SH(6) * RT_SH(6));
8781     HI_SW(3) -= (RS_SH(7) * RT_SH(7));
8782   }
8783 }
8784
8785 // end-sanitize-r5900
8786 // start-sanitize-r5900
8787
8788 011100,5.RS,5.RT,5.RD,00100001001:MMI2:32::PMSUBW
8789 *r5900:
8790 {
8791   unsigned32 instruction = instruction_0;
8792   int destreg = ((instruction >> 11) & 0x0000001F);
8793   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8794   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8795   signed_word rt_reg = GPR[RT];
8796   signed_word rt_reg1 = GPR1[RT];
8797   {
8798     signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
8799     signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
8800     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8801     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8802     sum0 -= prod0;
8803     sum1 -= prod1;
8804     GPR_SD(destreg,0) = sum0;
8805     GPR_SD(destreg,1) = sum1;
8806     LO  = SIGNEXTEND( sum0, 32 );
8807     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8808     LO1 = SIGNEXTEND( sum1, 32 );
8809     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8810   }
8811 }
8812
8813 // end-sanitize-r5900
8814 // start-sanitize-r5900
8815
8816 011100,5.RS,000000000001000101001:MMI3:32::PMTHI
8817 *r5900:
8818 {
8819   unsigned32 instruction = instruction_0;
8820   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8821   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8822   {
8823     HI  = RS_SD(0);
8824     HI1 = RS_SD(1);
8825   }
8826 }
8827
8828 // end-sanitize-r5900
8829 // start-sanitize-r5900
8830
8831 011100,5.RS,000000000001001101001:MMI3:32::PMTLO
8832 *r5900:
8833 {
8834   unsigned32 instruction = instruction_0;
8835   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8836   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8837   {
8838     LO  = RS_SD(0);
8839     LO1 = RS_SD(1);
8840   }
8841 }
8842
8843 // end-sanitize-r5900
8844 // start-sanitize-r5900
8845
8846 011100,5.RS,000000000000000110001:MMINORM:32::PMTHL.LW
8847 *r5900:
8848 {
8849   unsigned32 instruction = instruction_0;
8850   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8851   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8852   {
8853     LO_UW(0) = RS_UW(0);
8854     HI_UW(0) = RS_UW(1);
8855     LO_UW(2) = RS_UW(2);
8856     HI_UW(2) = RS_UW(3);
8857   }
8858 }
8859
8860 // end-sanitize-r5900
8861 // start-sanitize-r5900
8862
8863 011100,5.RS,5.RT,5.RD,11100001001:MMI2:32::PMULTH
8864 *r5900:
8865 {
8866   unsigned32 instruction = instruction_0;
8867   int destreg = ((instruction >> 11) & 0x0000001F);
8868   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8869   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8870   signed_word rt_reg = GPR[RT];
8871   signed_word rt_reg1 = GPR1[RT];
8872   {
8873     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(0) * RT_SH(0));
8874     LO_SW(1) = (RS_SH(1) * RT_SH(1));
8875     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(2) * RT_SH(2));
8876     HI_SW(1) = (RS_SH(3) * RT_SH(3));
8877     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(4) * RT_SH(4));
8878     LO_SW(3) = (RS_SH(5) * RT_SH(5));
8879     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(6) * RT_SH(6));
8880     HI_SW(3) = (RS_SH(7) * RT_SH(7));
8881   }
8882 }
8883
8884 // end-sanitize-r5900
8885 // start-sanitize-r5900
8886
8887 011100,5.RS,5.RT,5.RD,01100101001:MMI3:32::PMULTUW
8888 *r5900:
8889 {
8890   unsigned32 instruction = instruction_0;
8891   int destreg = ((instruction >> 11) & 0x0000001F);
8892   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8893   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8894   signed_word rt_reg = GPR[RT];
8895   signed_word rt_reg1 = GPR1[RT];
8896   {
8897     unsigned64 sum0 = 0;
8898     unsigned64 sum1 = 0;
8899     unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
8900     unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
8901     sum0 = prod0;
8902     sum1 = prod1;
8903     GPR_UD(destreg,0) = sum0;
8904     GPR_UD(destreg,1) = sum1;
8905     LO  = SIGNEXTEND( sum0, 32 );
8906     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8907     LO1 = SIGNEXTEND( sum1, 32 );
8908     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8909   }
8910 }
8911
8912 // end-sanitize-r5900
8913 // start-sanitize-r5900
8914
8915 011100,5.RS,5.RT,5.RD,01100001001:MMI2:32::PMULTW
8916 *r5900:
8917 {
8918   unsigned32 instruction = instruction_0;
8919   int destreg = ((instruction >> 11) & 0x0000001F);
8920   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8921   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8922   signed_word rt_reg = GPR[RT];
8923   signed_word rt_reg1 = GPR1[RT];
8924   {
8925     signed64 sum0 = 0;
8926     signed64 sum1 = 0;
8927     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8928     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8929     sum0 = prod0;
8930     sum1 = prod1;
8931     GPR_SD(destreg,0) = sum0;
8932     GPR_SD(destreg,1) = sum1;
8933     LO  = SIGNEXTEND( sum0, 32 );
8934     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
8935     LO1 = SIGNEXTEND( sum1, 32 );
8936     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8937   }
8938 }
8939
8940 // end-sanitize-r5900
8941 // start-sanitize-r5900
8942
8943 011100,5.RS,5.RT,5.RD,10011101001:MMI3:32::PNOR
8944 *r5900:
8945 {
8946   unsigned32 instruction = instruction_0;
8947   int destreg = ((instruction >> 11) & 0x0000001F);
8948   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8949   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8950   signed_word rt_reg = GPR[RT];
8951   signed_word rt_reg1 = GPR1[RT];
8952   {
8953     int i;
8954     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8955       GPR_UW(destreg,i) = ~(RS_UW(i) | RT_UW(i));
8956   }
8957 }
8958
8959 // end-sanitize-r5900
8960 // start-sanitize-r5900
8961
8962 011100,5.RS,5.RT,5.RD,10010101001:MMI3:32::POR
8963 *r5900:
8964 {
8965   unsigned32 instruction = instruction_0;
8966   int destreg = ((instruction >> 11) & 0x0000001F);
8967   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8968   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8969   signed_word rt_reg = GPR[RT];
8970   signed_word rt_reg1 = GPR1[RT];
8971   {
8972     int i;
8973     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8974       GPR_UW(destreg,i) = (RS_UW(i) | RT_UW(i));
8975   }
8976 }
8977
8978 // end-sanitize-r5900
8979 // start-sanitize-r5900
8980
8981 01110000000,5.RT,5.RD,11111001000:MMI0:32::PPAC5
8982 *r5900:
8983 {
8984   unsigned32 instruction = instruction_0;
8985   int destreg = ((instruction >> 11) & 0x0000001F);
8986   signed_word rt_reg = GPR[RT];
8987   signed_word rt_reg1 = GPR1[RT];
8988   {
8989     int i;
8990     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8991       {
8992         unsigned32 x = RT_UW(i);
8993         GPR_UW(destreg,i) = ((x & (1  << 31)) >> (31 - 15))
8994           | ((x & (31 << 19)) >> (19 - 10))
8995           | ((x & (31 << 11)) >> (11 - 5))
8996           | ((x & (31 <<  3)) >> (3  - 0));
8997       }
8998   }
8999 }
9000
9001 // end-sanitize-r5900
9002 // start-sanitize-r5900
9003
9004 011100,5.RS,5.RT,5.RD,11011001000:MMI0:32::PPACB
9005 *r5900:
9006 {
9007   unsigned32 instruction = instruction_0;
9008   int destreg = ((instruction >> 11) & 0x0000001F);
9009   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9010   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9011   signed_word rt_reg = GPR[RT];
9012   signed_word rt_reg1 = GPR1[RT];
9013   {
9014     GPR_UB(destreg,0)  = RT_UB(0);
9015     GPR_UB(destreg,1)  = RT_UB(2);
9016     GPR_UB(destreg,2)  = RT_UB(4);
9017     GPR_UB(destreg,3)  = RT_UB(6);
9018     GPR_UB(destreg,4)  = RT_UB(8);
9019     GPR_UB(destreg,5)  = RT_UB(10);
9020     GPR_UB(destreg,6)  = RT_UB(12);
9021     GPR_UB(destreg,7)  = RT_UB(14);
9022     GPR_UB(destreg,8)  = RS_UB(0);
9023     GPR_UB(destreg,9)  = RS_UB(2);
9024     GPR_UB(destreg,10) = RS_UB(4);
9025     GPR_UB(destreg,11) = RS_UB(6);
9026     GPR_UB(destreg,12) = RS_UB(8);
9027     GPR_UB(destreg,13) = RS_UB(10);
9028     GPR_UB(destreg,14) = RS_UB(12);
9029     GPR_UB(destreg,15) = RS_UB(14);
9030   }
9031 }
9032
9033 // end-sanitize-r5900
9034 // start-sanitize-r5900
9035
9036 011100,5.RS,5.RT,5.RD,10111001000:MMI0:32::PPACH
9037 *r5900:
9038 {
9039   unsigned32 instruction = instruction_0;
9040   int destreg = ((instruction >> 11) & 0x0000001F);
9041   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9042   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9043   signed_word rt_reg = GPR[RT];
9044   signed_word rt_reg1 = GPR1[RT];
9045   {
9046     GPR_UH(destreg,0)  = RT_UH(0);
9047     GPR_UH(destreg,1)  = RT_UH(2);
9048     GPR_UH(destreg,2)  = RT_UH(4);
9049     GPR_UH(destreg,3)  = RT_UH(6);
9050     GPR_UH(destreg,4)  = RS_UH(0);
9051     GPR_UH(destreg,5)  = RS_UH(2);
9052     GPR_UH(destreg,6)  = RS_UH(4);
9053     GPR_UH(destreg,7)  = RS_UH(6);
9054   }
9055 }
9056
9057 // end-sanitize-r5900
9058 // start-sanitize-r5900
9059
9060 011100,5.RS,5.RT,5.RD,10011001000:MMI0:32::PPACW
9061 *r5900:
9062 {
9063   unsigned32 instruction = instruction_0;
9064   int destreg = ((instruction >> 11) & 0x0000001F);
9065   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9066   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9067   signed_word rt_reg = GPR[RT];
9068   signed_word rt_reg1 = GPR1[RT];
9069   {
9070     GPR_UW(destreg,0)  = RT_UW(0);
9071     GPR_UW(destreg,1)  = RT_UW(2);
9072     GPR_UW(destreg,2)  = RS_UW(0);
9073     GPR_UW(destreg,3)  = RS_UW(2);
9074   }
9075 }
9076
9077 // end-sanitize-r5900
9078 // start-sanitize-r5900
9079
9080 01110000000,5.RT,5.RD,11011001001:MMI2:32::PREVH
9081 *r5900:
9082 {
9083   unsigned32 instruction = instruction_0;
9084   int destreg = ((instruction >> 11) & 0x0000001F);
9085   signed_word rt_reg = GPR[RT];
9086   signed_word rt_reg1 = GPR1[RT];
9087   {
9088     GPR_UH(destreg,0)  = RT_UH(3);
9089     GPR_UH(destreg,1)  = RT_UH(2);
9090     GPR_UH(destreg,2)  = RT_UH(1);
9091     GPR_UH(destreg,3)  = RT_UH(0);
9092     GPR_UH(destreg,4)  = RT_UH(7);
9093     GPR_UH(destreg,5)  = RT_UH(6);
9094     GPR_UH(destreg,6)  = RT_UH(5);
9095     GPR_UH(destreg,7)  = RT_UH(4);
9096   }
9097 }
9098
9099 // end-sanitize-r5900
9100 // start-sanitize-r5900
9101
9102 01110000000,5.RT,5.RD,11111001001:MMI2:32::PROT3W
9103 *r5900:
9104 {
9105   unsigned32 instruction = instruction_0;
9106   int destreg = ((instruction >> 11) & 0x0000001F);
9107   signed_word rt_reg = GPR[RT];
9108   signed_word rt_reg1 = GPR1[RT];
9109   {
9110     GPR_UW(destreg,0)  = RT_UW(0);
9111     GPR_UW(destreg,1)  = RT_UW(3);
9112     GPR_UW(destreg,2)  = RT_UW(1);
9113     GPR_UW(destreg,3)  = RT_UW(2);
9114   }
9115 }
9116
9117 // end-sanitize-r5900
9118 // start-sanitize-r5900
9119
9120 01110000000,5.RT,5.RD,5.SHIFT,110100:MMINORM:32::PSLLH
9121 *r5900:
9122 {
9123   unsigned32 instruction = instruction_0;
9124   int op1 = ((instruction >> 6) & 0x0000001F);
9125   int destreg = ((instruction >> 11) & 0x0000001F);
9126   signed_word rt_reg = GPR[RT];
9127   signed_word rt_reg1 = GPR1[RT];
9128   {
9129     int shift_by = op1 & (16-1);
9130     int i;
9131     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9132       GPR_UH(destreg,i) = (RT_UH(i) << shift_by);
9133   }
9134 }
9135
9136 // end-sanitize-r5900
9137 // start-sanitize-r5900
9138
9139 011100,5.RS,5.RT,5.RD,00010001001:MMI2:32::PSLLVW
9140 *r5900:
9141 {
9142   unsigned32 instruction = instruction_0;
9143   int destreg = ((instruction >> 11) & 0x0000001F);
9144   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9145   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9146   signed_word rt_reg = GPR[RT];
9147   signed_word rt_reg1 = GPR1[RT];
9148   {
9149     int s0 = (RS_UB(0) & 0x1F);
9150     int s1 = (RS_UB(8) & 0x1F);
9151     signed32 temp0 = RT_UW(0) << s0;
9152     signed32 temp1 = RT_UW(2) << s1;
9153     GPR_SD(destreg,0) = (signed64)temp0;
9154     GPR_SD(destreg,1) = (signed64)temp1;
9155   }
9156 }
9157
9158 // end-sanitize-r5900
9159 // start-sanitize-r5900
9160
9161 01110000000,5.RT,5.RD,5.SHIFT,111100:MMINORM:32::PSLLW
9162 *r5900:
9163 {
9164   unsigned32 instruction = instruction_0;
9165   int op1 = ((instruction >> 6) & 0x0000001F);
9166   int destreg = ((instruction >> 11) & 0x0000001F);
9167   signed_word rt_reg = GPR[RT];
9168   signed_word rt_reg1 = GPR1[RT];
9169   {
9170     int shift_by = op1 & (32-1);
9171     int i;
9172     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9173       GPR_UW(destreg,i) = (RT_UW(i) << shift_by);
9174   }
9175 }
9176
9177 // end-sanitize-r5900
9178 // start-sanitize-r5900
9179
9180 01110000000,5.RT,5.RD,5.SHIFT,110111:MMINORM:32::PSRAH
9181 *r5900:
9182 {
9183   unsigned32 instruction = instruction_0;
9184   int op1 = ((instruction >> 6) & 0x0000001F);
9185   int destreg = ((instruction >> 11) & 0x0000001F);
9186   signed_word rt_reg = GPR[RT];
9187   signed_word rt_reg1 = GPR1[RT];
9188   {
9189     int shift_by = op1 & (16-1);
9190     int i;
9191     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9192       GPR_SH(destreg,i) = SIGNEXTEND( (RT_SH(i) >> shift_by), (16-shift_by) );
9193   }
9194 }
9195
9196 // end-sanitize-r5900
9197 // start-sanitize-r5900
9198
9199 011100,5.RS,5.RT,5.RD,00011101001:MMI3:32::PSRAVW
9200 *r5900:
9201 {
9202   unsigned32 instruction = instruction_0;
9203   int destreg = ((instruction >> 11) & 0x0000001F);
9204   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9205   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9206   signed_word rt_reg = GPR[RT];
9207   signed_word rt_reg1 = GPR1[RT];
9208   {
9209     GPR_SD(destreg,0) = SIGNEXTEND( (RT_SW (0) >> (RS_UB(0) & 0x1F)), 32-(RS_UB(0) & 0x1F) );
9210     GPR_SD(destreg,1) = SIGNEXTEND( (RT_SW (2) >> (RS_UB(8) & 0x1F)), 32-(RS_UB(8) & 0x1F) );
9211   }
9212 }
9213
9214 // end-sanitize-r5900
9215 // start-sanitize-r5900
9216
9217 01110000000,5.RT,5.RD,5.SHIFT,111111:MMINORM:32::PSRAW
9218 *r5900:
9219 {
9220   unsigned32 instruction = instruction_0;
9221   int op1 = ((instruction >> 6) & 0x0000001F);
9222   int destreg = ((instruction >> 11) & 0x0000001F);
9223   signed_word rt_reg = GPR[RT];
9224   signed_word rt_reg1 = GPR1[RT];
9225   {
9226     int shift_by = op1 & (32-1);
9227     int i;
9228     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9229       GPR_SW(destreg,i) = SIGNEXTEND( (RT_SW(i) >> shift_by), (32-shift_by) );
9230   }
9231 }
9232
9233 // end-sanitize-r5900
9234 // start-sanitize-r5900
9235
9236 01110000000,5.RT,5.RD,5.SHIFT,110110:MMINORM:32::PSRLH
9237 *r5900:
9238 {
9239   unsigned32 instruction = instruction_0;
9240   int op1 = ((instruction >> 6) & 0x0000001F);
9241   int destreg = ((instruction >> 11) & 0x0000001F);
9242   signed_word rt_reg = GPR[RT];
9243   signed_word rt_reg1 = GPR1[RT];
9244   {
9245     int shift_by = op1 & (16-1);
9246     int i;
9247     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9248       GPR_UH(destreg,i) = (RT_UH(i) >> shift_by);
9249   }
9250 }
9251
9252 // end-sanitize-r5900
9253 // start-sanitize-r5900
9254
9255 011100,5.RS,5.RT,5.RD,00011001001:MMI2:32::PSRLVW
9256 *r5900:
9257 {
9258   unsigned32 instruction = instruction_0;
9259   int destreg = ((instruction >> 11) & 0x0000001F);
9260   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9261   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9262   signed_word rt_reg = GPR[RT];
9263   signed_word rt_reg1 = GPR1[RT];
9264   {
9265     GPR_UD(destreg,0) = SIGNEXTEND ( RT_UW(0) >> (RS_UB(0) & 0x1F), 31);
9266     GPR_UD(destreg,1) = SIGNEXTEND ( RT_UW(2) >> (RS_UB(8) & 0x1F), 31);
9267   }
9268 }
9269
9270 // end-sanitize-r5900
9271 // start-sanitize-r5900
9272
9273 01110000000,5.RT,5.RD,5.SHIFT,111110:MMINORM:32::PSRLW
9274 *r5900:
9275 {
9276   unsigned32 instruction = instruction_0;
9277   int op1 = ((instruction >> 6) & 0x0000001F);
9278   int destreg = ((instruction >> 11) & 0x0000001F);
9279   signed_word rt_reg = GPR[RT];
9280   signed_word rt_reg1 = GPR1[RT];
9281   {
9282     int shift_by = op1 & (32-1);
9283     int i;
9284     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9285       GPR_UW(destreg,i) = (RT_UW(i) >> shift_by);
9286   }
9287 }
9288
9289 // end-sanitize-r5900
9290 // start-sanitize-r5900
9291
9292 011100,5.RS,5.RT,5.RD,01001001000:MMI0:32::PSUBB
9293 *r5900:
9294 {
9295   unsigned32 instruction = instruction_0;
9296   int destreg = ((instruction >> 11) & 0x0000001F);
9297   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9298   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9299   signed_word rt_reg = GPR[RT];
9300   signed_word rt_reg1 = GPR1[RT];
9301   {
9302     int i;
9303     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9304       {
9305         int s = RS_SB(i);
9306         int t = RT_SB(i);
9307         int r = s - t;
9308         GPR_SB(destreg,i) = r;
9309       }
9310   }
9311 }
9312
9313 // end-sanitize-r5900
9314 // start-sanitize-r5900
9315
9316 011100,5.RS,5.RT,5.RD,00101001000:MMI0:32::PSUBH
9317 *r5900:
9318 {
9319   unsigned32 instruction = instruction_0;
9320   int destreg = ((instruction >> 11) & 0x0000001F);
9321   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9322   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9323   signed_word rt_reg = GPR[RT];
9324   signed_word rt_reg1 = GPR1[RT];
9325   {
9326     int i;
9327     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9328       {
9329         int s = RS_SH(i);
9330         int t = RT_SH(i);
9331         int r = s - t;
9332         GPR_SH(destreg,i) = r;
9333       }
9334   }
9335 }
9336
9337 // end-sanitize-r5900
9338 // start-sanitize-r5900
9339
9340 011100,5.RS,5.RT,5.RD,11001001000:MMI0:32::PSUBSB
9341 *r5900:
9342 {
9343   unsigned32 instruction = instruction_0;
9344   int destreg = ((instruction >> 11) & 0x0000001F);
9345   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9346   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9347   signed_word rt_reg = GPR[RT];
9348   signed_word rt_reg1 = GPR1[RT];
9349   {
9350     int i;
9351     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9352       {
9353         int s = RS_SB(i);
9354         int t = RT_SB(i);
9355         int r = s - t;
9356         if (r > 127)
9357           GPR_SB(destreg,i) = 127;
9358         else if (r < -128)
9359           GPR_SB(destreg,i) = -128;
9360         else
9361           GPR_SB(destreg,i) = r;
9362       }
9363   }
9364 }
9365
9366 // end-sanitize-r5900
9367 // start-sanitize-r5900
9368
9369 011100,5.RS,5.RT,5.RD,10101001000:MMI0:32::PSUBSH
9370 *r5900:
9371 {
9372   unsigned32 instruction = instruction_0;
9373   int destreg = ((instruction >> 11) & 0x0000001F);
9374   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9375   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9376   signed_word rt_reg = GPR[RT];
9377   signed_word rt_reg1 = GPR1[RT];
9378   {
9379     int i;
9380     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9381       {
9382         int s = RS_SH(i);
9383         int t = RT_SH(i);
9384         int r = s - t;
9385         if (r > 32767)
9386           GPR_SH(destreg,i) = 32767;
9387         else if (r < -32768)
9388           GPR_SH(destreg,i) = -32768;
9389         else
9390           GPR_SH(destreg,i) = r;
9391       }
9392   }
9393 }
9394
9395 // end-sanitize-r5900
9396 // start-sanitize-r5900
9397
9398 011100,5.RS,5.RT,5.RD,10001001000:MMI0:32::PSUBSW
9399 *r5900:
9400 {
9401   unsigned32 instruction = instruction_0;
9402   int destreg = ((instruction >> 11) & 0x0000001F);
9403   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9404   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9405   signed_word rt_reg = GPR[RT];
9406   signed_word rt_reg1 = GPR1[RT];
9407   {
9408     int i;
9409     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9410       {
9411         signed64 s = RS_SW(i);
9412         signed64 t = RT_SW(i);
9413         signed64 r = s - t;
9414         if (r > (int)0x7FFFFFFF)
9415           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
9416         else if (r < (int)0x80000000)
9417           GPR_SW(destreg,i) = (int)0x80000000;
9418         else
9419           GPR_SW(destreg,i) = r;
9420       }
9421   }
9422 }
9423
9424 // end-sanitize-r5900
9425 // start-sanitize-r5900
9426
9427 011100,5.RS,5.RT,5.RD,11001101000:MMI1:32::PSUBUB
9428 *r5900:
9429 {
9430   unsigned32 instruction = instruction_0;
9431   int destreg = ((instruction >> 11) & 0x0000001F);
9432   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9433   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9434   signed_word rt_reg = GPR[RT];
9435   signed_word rt_reg1 = GPR1[RT];
9436   {
9437     int i;
9438     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9439       {
9440         unsigned int s = RS_UB(i);
9441         unsigned int t = RT_UB(i);
9442         unsigned int r = s - t;
9443         if (r > 0xFF)
9444           GPR_UB(destreg,i) = 0;
9445         else
9446           GPR_UB(destreg,i) = r;
9447       }
9448   }
9449 }
9450
9451 // end-sanitize-r5900
9452 // start-sanitize-r5900
9453
9454 011100,5.RS,5.RT,5.RD,10101101000:MMI1:32::PSUBUH
9455 *r5900:
9456 {
9457   unsigned32 instruction = instruction_0;
9458   int destreg = ((instruction >> 11) & 0x0000001F);
9459   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9460   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9461   signed_word rt_reg = GPR[RT];
9462   signed_word rt_reg1 = GPR1[RT];
9463   {
9464     int i;
9465     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9466       {
9467         unsigned int s = RS_UH(i);
9468         unsigned int t = RT_UH(i);
9469         unsigned int r = s - t;
9470         if (r > 0xFFFF)
9471           GPR_UH(destreg,i) = 0;
9472         else
9473           GPR_UH(destreg,i) = r;
9474       }
9475   }
9476 }
9477
9478 // end-sanitize-r5900
9479 // start-sanitize-r5900
9480
9481 011100,5.RS,5.RT,5.RD,10001101000:MMI1:32::PSUBUW
9482 *r5900:
9483 {
9484   unsigned32 instruction = instruction_0;
9485   int destreg = ((instruction >> 11) & 0x0000001F);
9486   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9487   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9488   signed_word rt_reg = GPR[RT];
9489   signed_word rt_reg1 = GPR1[RT];
9490   {
9491     int i;
9492     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9493       {
9494         unsigned64 s = RS_UW(i);
9495         unsigned64 t = RT_UW(i);
9496         unsigned64 r = s - t;
9497         if (r > 0xFFFFFFFF)
9498           GPR_UW(destreg,i) = 0;
9499         else
9500           GPR_UW(destreg,i) = r;
9501       }
9502   }
9503 }
9504
9505 // end-sanitize-r5900
9506 // start-sanitize-r5900
9507
9508 011100,5.RS,5.RT,5.RD,00001001000:MMI0:32::PSUBW
9509 *r5900:
9510 {
9511   unsigned32 instruction = instruction_0;
9512   int destreg = ((instruction >> 11) & 0x0000001F);
9513   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9514   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9515   signed_word rt_reg = GPR[RT];
9516   signed_word rt_reg1 = GPR1[RT];
9517   {
9518     int i;
9519     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9520       {
9521         signed64 s = RS_SW(i);
9522         signed64 t = RT_SW(i);
9523         signed64 r = s - t;
9524         GPR_SW(destreg,i) = r;
9525       }
9526   }
9527 }
9528
9529 // end-sanitize-r5900
9530 // start-sanitize-r5900
9531
9532 011100,5.RS,5.RT,5.RD,10011001001:MMI2:32::PXOR
9533 *r5900:
9534 {
9535   unsigned32 instruction = instruction_0;
9536   int destreg = ((instruction >> 11) & 0x0000001F);
9537   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9538   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9539   signed_word rt_reg = GPR[RT];
9540   signed_word rt_reg1 = GPR1[RT];
9541   {
9542     int i;
9543     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9544       GPR_UW(destreg,i) = (RS_UW(i) ^ RT_UW(i));
9545   }
9546 }
9547
9548 // end-sanitize-r5900
9549 // start-sanitize-r5900
9550
9551 011100,5.RS,5.RT,5.RD,11011101000:MMI1:32::QFSRV
9552 *r5900:
9553 {
9554   unsigned32 instruction = instruction_0;
9555   int destreg = ((instruction >> 11) & 0x0000001F);
9556   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9557   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9558   signed_word rt_reg = GPR[RT];
9559   signed_word rt_reg1 = GPR1[RT];
9560   {
9561     int bytes = (SA / 8) % 16;
9562     if (SA % 8)
9563       SignalException(ReservedInstruction,instruction);
9564     else
9565       {
9566         int i;
9567         for(i=0;i<(16-bytes);i++)
9568           GPR_SB(destreg,i) = RT_SB(bytes+i);
9569         for(;i<16;i++)
9570           GPR_SB(destreg,i) = RS_SB(i-(16-bytes));
9571       }
9572   }
9573 }
9574
9575 // end-sanitize-r5900
9576 // start-sanitize-r5900
9577
9578 011111,5.RS,5.RT,16.OFFSET:NORMAL:128::SQ
9579 *r5900:
9580 {
9581   unsigned32 instruction = instruction_0;
9582   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
9583   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9584   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9585   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9586   signed_word rt_reg = GPR[RT];
9587   signed_word rt_reg1 = GPR1[RT];
9588   {
9589     address_word vaddr = ((unsigned64)op1 + offset);
9590     address_word paddr;
9591     int uncached;
9592     if ((vaddr & 15) != 0)
9593       SignalExceptionAddressStore();
9594     else
9595       {
9596         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
9597           {
9598             unsigned64 memval = 0;
9599             unsigned64 memval1 = 0;
9600             memval  = rsigned_word;
9601             memval1 = rsigned_word1;
9602             {
9603               StoreMemory(uncached,AccessLength_QUADWORD,memval,memval1,paddr,vaddr,isREAL);
9604             }
9605           }
9606       }
9607   }
9608 }
9609
9610 // end-sanitize-r5900
9611 \f
9612 // start-sanitize-cygnus-never
9613
9614 // // FIXME FIXME FIXME What is this instruction?
9615 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
9616 // *mipsI:
9617 // *mipsII:
9618 // *mipsIII:
9619 // *mipsIV:
9620 // // start-sanitize-r5900
9621 // *r5900:
9622 // // end-sanitize-r5900
9623 // *r3900:
9624 // // start-sanitize-tx19
9625 // *tx19:
9626 // // end-sanitize-tx19
9627 // {
9628 //   unsigned32 instruction = instruction_0;
9629 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
9630 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9631 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9632 //   {
9633 //     if (CoProcPresent(3))
9634 //       SignalException(CoProcessorUnusable);
9635 //     else
9636 //       SignalException(ReservedInstruction,instruction);
9637 //   }
9638 // }
9639
9640 // end-sanitize-cygnus-never
9641 // start-sanitize-cygnus-never
9642
9643 // // FIXME FIXME FIXME What is this?
9644 // 11100,******,00001:RR:16::SDBBP
9645 // *mips16:
9646 // {
9647 //   unsigned32 instruction = instruction_0;
9648 //   if (have_extendval)
9649 //     SignalException (ReservedInstruction, instruction);
9650 //   {
9651 //     SignalException(DebugBreakPoint,instruction);
9652 //   }
9653 // }
9654
9655 // end-sanitize-cygnus-never
9656 // start-sanitize-cygnus-never
9657
9658 // // FIXME FIXME FIXME What is this?
9659 // 000000,********************,001110:SPECIAL:32::SDBBP
9660 // *r3900:
9661 // {
9662 //   unsigned32 instruction = instruction_0;
9663 //   {
9664 //     SignalException(DebugBreakPoint,instruction);
9665 //   }
9666 // }
9667
9668 // end-sanitize-cygnus-never
9669 // start-sanitize-cygnus-never
9670
9671 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
9672 // // isn't yet reconized by this simulator.
9673 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
9674 // *vr4100:
9675 // {
9676 //   unsigned32 instruction = instruction_0;
9677 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9678 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9679 //   {
9680 //     CHECKHILO("Multiply-Add");
9681 //     {
9682 //       unsigned64 temp = (op1 * op2);
9683 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
9684 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
9685 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
9686 //     }
9687 //   }
9688 // }
9689
9690 // end-sanitize-cygnus-never
9691 // start-sanitize-cygnus-never
9692
9693 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
9694 // // isn't yet reconized by this simulator.
9695 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
9696 // *vr4100:
9697 // {
9698 //   unsigned32 instruction = instruction_0;
9699 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9700 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
9701 //   {
9702 //     CHECKHILO("Multiply-Add");
9703 //     {
9704 //       unsigned64 temp = (op1 * op2);
9705 //       LO = LO + temp;
9706 //     }
9707 //   }
9708 // }
9709
9710 // start-sanitize-cygnus-never