sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 :model:::vr4100:mips4100:
  47 // start-sanitize-vr4320
  48 :model:::vr4320:mips4320:
  49 // end-sanitize-vr4320
  50 // start-sanitize-cygnus
  51 :model:::vr5400:mips5400:
  52 :model:::mdmx:mdmx:
  53 // end-sanitize-cygnus
  54 :model:::vr5000:mips5000:
  55
  56
  57
  58 // Pseudo instructions known by IGEN
  59 :internal::::illegal:
  60 {
  61   SignalException (ReservedInstruction, 0);
  62 }
  63
  64
  65 // Pseudo instructions known by interp.c
  66 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  67 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  68 "rsvd <OP>"
  69 {
  70   SignalException (ReservedInstruction, instruction_0);
  71 }
  72
  73
  74
  75 // Helper:
  76 //
  77 // Simulate a 32 bit delayslot instruction
  78 //
  79
  80 :function:::address_word:delayslot32:address_word target
  81 {
  82   instruction_word delay_insn;
  83   sim_events_slip (SD, 1);
  84   DSPC = CIA;
  85   CIA = CIA + 4; /* NOTE not mips16 */
  86   STATE |= simDELAYSLOT;
  87   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  88   idecode_issue (CPU_, delay_insn, (CIA));
  89   STATE &= ~simDELAYSLOT;
  90   return target;
  91 }
  92
  93 :function:::address_word:nullify_next_insn32:
  94 {
  95   sim_events_slip (SD, 1);
  96   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  97   return CIA + 8;
  98 }
  99
 100 // start-sanitize-branchbug4011
 101 :function:::void:check_4011_branch_bug:
 102 {
 103   if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
 104     sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
 105                       itable[MY_INDEX].name,
 106                       (long) CIA,
 107                       (long) BRANCHBUG4011_LAST_CIA);
 108 }
 109
 110 :function:::void:mark_4011_branch_bug:address_word target
 111 {
 112   if (BRANCHBUG4011_OPTION)
 113     {
 114       BRANCHBUG4011_OPTION = 2;
 115       BRANCHBUG4011_LAST_TARGET = target;
 116       BRANCHBUG4011_LAST_CIA = CIA;
 117     }
 118 }
 119
 120 // end-sanitize-branchbug4011
 121 // Helper:
 122 //
 123 // Check that an access to a HI/LO register meets timing requirements
 124 //
 125 // The following requirements exist:
 126 //
 127 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 128 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 129 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 130 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 131 //
 132
 133 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 134 {
 135   if (history->mf.timestamp + 3 > time)
 136     {
 137       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 138                         itable[MY_INDEX].name,
 139                         new, (long) CIA,
 140                         (long) history->mf.cia);
 141       return 0;
 142     }
 143   return 1;
 144 }
 145
 146 :function:::int:check_mt_hilo:hilo_history *history
 147 *mipsI,mipsII,mipsIII,mipsIV:
 148 *vr5000:
 149 // start-sanitize-vr4320
 150 *vr4320:
 151 // end-sanitize-vr4320
 152 // start-sanitize-cygnus
 153 *vr5400:
 154 // end-sanitize-cygnus
 155 {
 156   signed64 time = sim_events_time (SD);
 157   int ok = check_mf_cycles (SD_, history, time, "MT");
 158   history->mt.timestamp = time;
 159   history->mt.cia = CIA;
 160   return ok;
 161 }
 162
 163 :function:::int:check_mt_hilo:hilo_history *history
 164 *r3900:
 165 // start-sanitize-tx19
 166 *tx19:
 167 // end-sanitize-tx19
 168 // start-sanitize-r5900
 169 *r5900:
 170 // end-sanitize-r5900
 171 {
 172   signed64 time = sim_events_time (SD);
 173   history->mt.timestamp = time;
 174   history->mt.cia = CIA;
 175   return 1;
 176 }
 177
 178
 179 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 180 *mipsI,mipsII,mipsIII,mipsIV:
 181 *vr4100:
 182 *vr5000:
 183 // start-sanitize-vr4320
 184 *vr4320:
 185 // end-sanitize-vr4320
 186 // start-sanitize-cygnus
 187 *vr5400:
 188 // end-sanitize-cygnus
 189 *r3900:
 190 // start-sanitize-tx19
 191 *tx19:
 192 // end-sanitize-tx19
 193 {
 194   signed64 time = sim_events_time (SD);
 195   int ok = 1;
 196   if (peer != NULL
 197       && peer->mt.timestamp > history->op.timestamp
 198       && history->mt.timestamp < history->op.timestamp
 199       && ! (history->mf.timestamp > history->op.timestamp
 200             && history->mf.timestamp < peer->mt.timestamp)
 201       && ! (peer->mf.timestamp > history->op.timestamp
 202             && peer->mf.timestamp < peer->mt.timestamp))
 203     {
 204       /* The peer has been written to since the last OP yet we have
 205          not */
 206       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 207                         itable[MY_INDEX].name,
 208                         (long) CIA,
 209                         (long) history->op.cia,
 210                         (long) peer->mt.cia);
 211       ok = 0;
 212     }
 213   history->mf.timestamp = time;
 214   history->mf.cia = CIA;
 215   return ok;
 216 }
 217
 218 // start-sanitize-r5900
 219 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 220 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 221 // end-sanitize-r5900
 222 // start-sanitize-r5900
 223 *r5900:
 224 // end-sanitize-r5900
 225 // start-sanitize-r5900
 226 {
 227   /* FIXME: could record the fact that a stall occured if we want */
 228   signed64 time = sim_events_time (SD);
 229   history->mf.timestamp = time;
 230   history->mf.cia = CIA;
 231   return 1;
 232 }
 233 // end-sanitize-r5900
 234
 235
 236 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 237 *mipsI,mipsII,mipsIII,mipsIV:
 238 *vr4100:
 239 *vr5000:
 240 // start-sanitize-vr4320
 241 *vr4320:
 242 // end-sanitize-vr4320
 243 // start-sanitize-cygnus
 244 *vr5400:
 245 // end-sanitize-cygnus
 246 {
 247   signed64 time = sim_events_time (SD);
 248   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 249             && check_mf_cycles (SD_, lo, time, "OP"));
 250   hi->op.timestamp = time;
 251   lo->op.timestamp = time;
 252   hi->op.cia = CIA;
 253   lo->op.cia = CIA;
 254   return ok;
 255 }
 256
 257 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 258 // a mf{hi,lo}
 259 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 260 *r3900:
 261 // start-sanitize-tx19
 262 *tx19:
 263 // end-sanitize-tx19
 264 // start-sanitize-r5900
 265 *r5900:
 266 // end-sanitize-r5900
 267 {
 268   /* FIXME: could record the fact that a stall occured if we want */
 269   signed64 time = sim_events_time (SD);
 270   hi->op.timestamp = time;
 271   lo->op.timestamp = time;
 272   hi->op.cia = CIA;
 273   lo->op.cia = CIA;
 274   return 1;
 275 }
 276
 277
 278 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 279 *mipsI,mipsII,mipsIII,mipsIV:
 280 *vr4100:
 281 *vr5000:
 282 // start-sanitize-vr4320
 283 *vr4320:
 284 // end-sanitize-vr4320
 285 // start-sanitize-cygnus
 286 *vr5400:
 287 // end-sanitize-cygnus
 288 *r3900:
 289 // start-sanitize-tx19
 290 *tx19:
 291 // end-sanitize-tx19
 292 {
 293   signed64 time = sim_events_time (SD);
 294   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 295             && check_mf_cycles (SD_, lo, time, "OP"));
 296   hi->op.timestamp = time;
 297   lo->op.timestamp = time;
 298   hi->op.cia = CIA;
 299   lo->op.cia = CIA;
 300   return ok;
 301 }
 302
 303
 304 // start-sanitize-r5900
 305 // The r5900 div et.al insns _can_ be exectuted immediatly after
 306 // a mf{hi,lo}
 307 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 308 // end-sanitize-r5900
 309 // start-sanitize-r5900
 310 *r5900:
 311 // end-sanitize-r5900
 312 // start-sanitize-r5900
 313 {
 314   /* FIXME: could record the fact that a stall occured if we want */
 315   signed64 time = sim_events_time (SD);
 316   hi->op.timestamp = time;
 317   lo->op.timestamp = time;
 318   hi->op.cia = CIA;
 319   lo->op.cia = CIA;
 320   return 1;
 321 }
 322 // end-sanitize-r5900
 323
 324
 325
 326 //
 327 // Mips Architecture:
 328 //
 329 //        CPU Instruction Set (mipsI - mipsIV)
 330 //
 331
 332
 333
 334 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 335 "add r<RD>, r<RS>, r<RT>"
 336 *mipsI,mipsII,mipsIII,mipsIV:
 337 *vr5000:
 338 // start-sanitize-vr4320
 339 *vr4320:
 340 // end-sanitize-vr4320
 341 // start-sanitize-cygnus
 342 *vr5400:
 343 // end-sanitize-cygnus
 344 // start-sanitize-r5900
 345 *r5900:
 346 // end-sanitize-r5900
 347 *r3900:
 348 // start-sanitize-tx19
 349 *tx19:
 350 // end-sanitize-tx19
 351 {
 352   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 353   {
 354     ALU32_BEGIN (GPR[RS]);
 355     ALU32_ADD (GPR[RT]);
 356     ALU32_END (GPR[RD]);
 357   }
 358   TRACE_ALU_RESULT (GPR[RD]);
 359 }
 360
 361
 362
 363 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 364 "addi r<RT>, r<RS>, IMMEDIATE"
 365 *mipsI,mipsII,mipsIII,mipsIV:
 366 *vr5000:
 367 // start-sanitize-vr4320
 368 *vr4320:
 369 // end-sanitize-vr4320
 370 // start-sanitize-cygnus
 371 *vr5400:
 372 // end-sanitize-cygnus
 373 // start-sanitize-r5900
 374 *r5900:
 375 // end-sanitize-r5900
 376 *r3900:
 377 // start-sanitize-tx19
 378 *tx19:
 379 // end-sanitize-tx19
 380 {
 381   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 382   {
 383     ALU32_BEGIN (GPR[RS]);
 384     ALU32_ADD (EXTEND16 (IMMEDIATE));
 385     ALU32_END (GPR[RT]);
 386   }
 387   TRACE_ALU_RESULT (GPR[RT]);
 388 }
 389
 390
 391
 392 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 393 {
 394   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 395   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 396   TRACE_ALU_RESULT (GPR[rt]);
 397 }
 398
 399 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 400 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 401 *mipsI,mipsII,mipsIII,mipsIV:
 402 *vr5000:
 403 // start-sanitize-vr4320
 404 *vr4320:
 405 // end-sanitize-vr4320
 406 // start-sanitize-cygnus
 407 *vr5400:
 408 // end-sanitize-cygnus
 409 // start-sanitize-r5900
 410 *r5900:
 411 // end-sanitize-r5900
 412 *r3900:
 413 // start-sanitize-tx19
 414 *tx19:
 415 // end-sanitize-tx19
 416 {
 417   do_addiu (SD_, RS, RT, IMMEDIATE);
 418 }
 419
 420
 421
 422 :function:::void:do_addu:int rs, int rt, int rd
 423 {
 424   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 425   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 426   TRACE_ALU_RESULT (GPR[rd]);
 427 }
 428
 429 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 430 "addu r<RD>, r<RS>, r<RT>"
 431 *mipsI,mipsII,mipsIII,mipsIV:
 432 *vr5000:
 433 // start-sanitize-vr4320
 434 *vr4320:
 435 // end-sanitize-vr4320
 436 // start-sanitize-cygnus
 437 *vr5400:
 438 // end-sanitize-cygnus
 439 // start-sanitize-r5900
 440 *r5900:
 441 // end-sanitize-r5900
 442 *r3900:
 443 // start-sanitize-tx19
 444 *tx19:
 445 // end-sanitize-tx19
 446 {
 447   do_addu (SD_, RS, RT, RD);
 448 }
 449
 450
 451
 452 :function:::void:do_and:int rs, int rt, int rd
 453 {
 454   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 455   GPR[rd] = GPR[rs] & GPR[rt];
 456   TRACE_ALU_RESULT (GPR[rd]);
 457 }
 458
 459 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 460 "and r<RD>, r<RS>, r<RT>"
 461 *mipsI,mipsII,mipsIII,mipsIV:
 462 *vr5000:
 463 // start-sanitize-vr4320
 464 *vr4320:
 465 // end-sanitize-vr4320
 466 // start-sanitize-cygnus
 467 *vr5400:
 468 // end-sanitize-cygnus
 469 // start-sanitize-r5900
 470 *r5900:
 471 // end-sanitize-r5900
 472 *r3900:
 473 // start-sanitize-tx19
 474 *tx19:
 475 // end-sanitize-tx19
 476 {
 477   do_and (SD_, RS, RT, RD);
 478 }
 479
 480
 481
 482 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 483 "and r<RT>, r<RS>, <IMMEDIATE>"
 484 *mipsI,mipsII,mipsIII,mipsIV:
 485 *vr5000:
 486 // start-sanitize-vr4320
 487 *vr4320:
 488 // end-sanitize-vr4320
 489 // start-sanitize-cygnus
 490 *vr5400:
 491 // end-sanitize-cygnus
 492 // start-sanitize-r5900
 493 *r5900:
 494 // end-sanitize-r5900
 495 *r3900:
 496 // start-sanitize-tx19
 497 *tx19:
 498 // end-sanitize-tx19
 499 {
 500   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 501   GPR[RT] = GPR[RS] & IMMEDIATE;
 502   TRACE_ALU_RESULT (GPR[RT]);
 503 }
 504
 505
 506
 507 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 508 "beq r<RS>, r<RT>, <OFFSET>"
 509 *mipsI,mipsII,mipsIII,mipsIV:
 510 *vr5000:
 511 // start-sanitize-vr4320
 512 *vr4320:
 513 // end-sanitize-vr4320
 514 // start-sanitize-cygnus
 515 *vr5400:
 516 // end-sanitize-cygnus
 517 // start-sanitize-r5900
 518 *r5900:
 519 // end-sanitize-r5900
 520 *r3900:
 521 // start-sanitize-tx19
 522 *tx19:
 523 // end-sanitize-tx19
 524 {
 525   address_word offset = EXTEND16 (OFFSET) << 2;
 526   check_branch_bug ();
 527   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 528     {
 529       mark_branch_bug (NIA+offset);
 530       DELAY_SLOT (NIA + offset);
 531     }
 532 }
 533
 534
 535
 536 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 537 "beql r<RS>, r<RT>, <OFFSET>"
 538 *mipsII:
 539 *mipsIII:
 540 *mipsIV:
 541 *vr5000:
 542 // start-sanitize-vr4320
 543 *vr4320:
 544 // end-sanitize-vr4320
 545 // start-sanitize-cygnus
 546 *vr5400:
 547 // end-sanitize-cygnus
 548 // start-sanitize-r5900
 549 *r5900:
 550 // end-sanitize-r5900
 551 *r3900:
 552 // start-sanitize-tx19
 553 *tx19:
 554 // end-sanitize-tx19
 555 {
 556   address_word offset = EXTEND16 (OFFSET) << 2;
 557   check_branch_bug ();
 558   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 559     {
 560       mark_branch_bug (NIA+offset);
 561       DELAY_SLOT (NIA + offset);
 562     }
 563   else
 564     NULLIFY_NEXT_INSTRUCTION ();
 565 }
 566
 567
 568
 569 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 570 "bgez r<RS>, <OFFSET>"
 571 *mipsI,mipsII,mipsIII,mipsIV:
 572 *vr5000:
 573 // start-sanitize-vr4320
 574 *vr4320:
 575 // end-sanitize-vr4320
 576 // start-sanitize-cygnus
 577 *vr5400:
 578 // end-sanitize-cygnus
 579 // start-sanitize-r5900
 580 *r5900:
 581 // end-sanitize-r5900
 582 *r3900:
 583 // start-sanitize-tx19
 584 *tx19:
 585 // end-sanitize-tx19
 586 {
 587   address_word offset = EXTEND16 (OFFSET) << 2;
 588   check_branch_bug ();
 589   if ((signed_word) GPR[RS] >= 0)
 590     {
 591       mark_branch_bug (NIA+offset);
 592       DELAY_SLOT (NIA + offset);
 593     }
 594 }
 595
 596
 597
 598 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 599 "bgezal r<RS>, <OFFSET>"
 600 *mipsI,mipsII,mipsIII,mipsIV:
 601 *vr5000:
 602 // start-sanitize-vr4320
 603 *vr4320:
 604 // end-sanitize-vr4320
 605 // start-sanitize-cygnus
 606 *vr5400:
 607 // end-sanitize-cygnus
 608 // start-sanitize-r5900
 609 *r5900:
 610 // end-sanitize-r5900
 611 *r3900:
 612 // start-sanitize-tx19
 613 *tx19:
 614 // end-sanitize-tx19
 615 {
 616   address_word offset = EXTEND16 (OFFSET) << 2;
 617   check_branch_bug ();
 618   RA = (CIA + 8);
 619   if ((signed_word) GPR[RS] >= 0)
 620     {
 621       mark_branch_bug (NIA+offset);
 622       DELAY_SLOT (NIA + offset);
 623     }
 624 }
 625
 626
 627
 628 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 629 "bgezall r<RS>, <OFFSET>"
 630 *mipsII:
 631 *mipsIII:
 632 *mipsIV:
 633 *vr5000:
 634 // start-sanitize-vr4320
 635 *vr4320:
 636 // end-sanitize-vr4320
 637 // start-sanitize-cygnus
 638 *vr5400:
 639 // end-sanitize-cygnus
 640 // start-sanitize-r5900
 641 *r5900:
 642 // end-sanitize-r5900
 643 *r3900:
 644 // start-sanitize-tx19
 645 *tx19:
 646 // end-sanitize-tx19
 647 {
 648   address_word offset = EXTEND16 (OFFSET) << 2;
 649   check_branch_bug ();
 650   RA = (CIA + 8);
 651   /* NOTE: The branch occurs AFTER the next instruction has been
 652      executed */
 653   if ((signed_word) GPR[RS] >= 0)
 654     {
 655       mark_branch_bug (NIA+offset);
 656       DELAY_SLOT (NIA + offset);
 657     }
 658   else
 659     NULLIFY_NEXT_INSTRUCTION ();
 660 }
 661
 662
 663
 664 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 665 "bgezl r<RS>, <OFFSET>"
 666 *mipsII:
 667 *mipsIII:
 668 *mipsIV:
 669 *vr5000:
 670 // start-sanitize-vr4320
 671 *vr4320:
 672 // end-sanitize-vr4320
 673 // start-sanitize-cygnus
 674 *vr5400:
 675 // end-sanitize-cygnus
 676 // start-sanitize-r5900
 677 *r5900:
 678 // end-sanitize-r5900
 679 *r3900:
 680 // start-sanitize-tx19
 681 *tx19:
 682 // end-sanitize-tx19
 683 {
 684   address_word offset = EXTEND16 (OFFSET) << 2;
 685   check_branch_bug ();
 686   if ((signed_word) GPR[RS] >= 0)
 687     {
 688       mark_branch_bug (NIA+offset);
 689       DELAY_SLOT (NIA + offset);
 690     }
 691   else
 692     NULLIFY_NEXT_INSTRUCTION ();
 693 }
 694
 695
 696
 697 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 698 "bgtz r<RS>, <OFFSET>"
 699 *mipsI,mipsII,mipsIII,mipsIV:
 700 *vr5000:
 701 // start-sanitize-vr4320
 702 *vr4320:
 703 // end-sanitize-vr4320
 704 // start-sanitize-cygnus
 705 *vr5400:
 706 // end-sanitize-cygnus
 707 // start-sanitize-r5900
 708 *r5900:
 709 // end-sanitize-r5900
 710 *r3900:
 711 // start-sanitize-tx19
 712 *tx19:
 713 // end-sanitize-tx19
 714 {
 715   address_word offset = EXTEND16 (OFFSET) << 2;
 716   check_branch_bug ();
 717   if ((signed_word) GPR[RS] > 0)
 718     {
 719       mark_branch_bug (NIA+offset);
 720       DELAY_SLOT (NIA + offset);
 721     }
 722 }
 723
 724
 725
 726 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 727 "bgtzl r<RS>, <OFFSET>"
 728 *mipsII:
 729 *mipsIII:
 730 *mipsIV:
 731 *vr5000:
 732 // start-sanitize-vr4320
 733 *vr4320:
 734 // end-sanitize-vr4320
 735 // start-sanitize-cygnus
 736 *vr5400:
 737 // end-sanitize-cygnus
 738 // start-sanitize-r5900
 739 *r5900:
 740 // end-sanitize-r5900
 741 *r3900:
 742 // start-sanitize-tx19
 743 *tx19:
 744 // end-sanitize-tx19
 745 {
 746   address_word offset = EXTEND16 (OFFSET) << 2;
 747   check_branch_bug ();
 748   /* NOTE: The branch occurs AFTER the next instruction has been
 749      executed */
 750   if ((signed_word) GPR[RS] > 0)
 751     {
 752       mark_branch_bug (NIA+offset);
 753       DELAY_SLOT (NIA + offset);
 754     }
 755   else
 756     NULLIFY_NEXT_INSTRUCTION ();
 757 }
 758
 759
 760
 761 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 762 "blez r<RS>, <OFFSET>"
 763 *mipsI,mipsII,mipsIII,mipsIV:
 764 *vr5000:
 765 // start-sanitize-vr4320
 766 *vr4320:
 767 // end-sanitize-vr4320
 768 // start-sanitize-cygnus
 769 *vr5400:
 770 // end-sanitize-cygnus
 771 // start-sanitize-r5900
 772 *r5900:
 773 // end-sanitize-r5900
 774 *r3900:
 775 // start-sanitize-tx19
 776 *tx19:
 777 // end-sanitize-tx19
 778 {
 779   address_word offset = EXTEND16 (OFFSET) << 2;
 780   check_branch_bug ();
 781   /* NOTE: The branch occurs AFTER the next instruction has been
 782      executed */
 783   if ((signed_word) GPR[RS] <= 0)
 784     {
 785       mark_branch_bug (NIA+offset);
 786       DELAY_SLOT (NIA + offset);
 787     }
 788 }
 789
 790
 791
 792 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 793 "bgezl r<RS>, <OFFSET>"
 794 *mipsII:
 795 *mipsIII:
 796 *mipsIV:
 797 *vr5000:
 798 // start-sanitize-vr4320
 799 *vr4320:
 800 // end-sanitize-vr4320
 801 // start-sanitize-cygnus
 802 *vr5400:
 803 // end-sanitize-cygnus
 804 // start-sanitize-r5900
 805 *r5900:
 806 // end-sanitize-r5900
 807 *r3900:
 808 // start-sanitize-tx19
 809 *tx19:
 810 // end-sanitize-tx19
 811 {
 812   address_word offset = EXTEND16 (OFFSET) << 2;
 813   check_branch_bug ();
 814   if ((signed_word) GPR[RS] <= 0)
 815     {
 816       mark_branch_bug (NIA+offset);
 817       DELAY_SLOT (NIA + offset);
 818     }
 819   else
 820     NULLIFY_NEXT_INSTRUCTION ();
 821 }
 822
 823
 824
 825 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 826 "bltz r<RS>, <OFFSET>"
 827 *mipsI,mipsII,mipsIII,mipsIV:
 828 *vr5000:
 829 // start-sanitize-vr4320
 830 *vr4320:
 831 // end-sanitize-vr4320
 832 // start-sanitize-cygnus
 833 *vr5400:
 834 // end-sanitize-cygnus
 835 // start-sanitize-r5900
 836 *r5900:
 837 // end-sanitize-r5900
 838 *r3900:
 839 // start-sanitize-tx19
 840 *tx19:
 841 // end-sanitize-tx19
 842 {
 843   address_word offset = EXTEND16 (OFFSET) << 2;
 844   check_branch_bug ();
 845   if ((signed_word) GPR[RS] < 0)
 846     {
 847       mark_branch_bug (NIA+offset);
 848       DELAY_SLOT (NIA + offset);
 849     }
 850 }
 851
 852
 853
 854 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 855 "bltzal r<RS>, <OFFSET>"
 856 *mipsI,mipsII,mipsIII,mipsIV:
 857 *vr5000:
 858 // start-sanitize-vr4320
 859 *vr4320:
 860 // end-sanitize-vr4320
 861 // start-sanitize-cygnus
 862 *vr5400:
 863 // end-sanitize-cygnus
 864 // start-sanitize-r5900
 865 *r5900:
 866 // end-sanitize-r5900
 867 *r3900:
 868 // start-sanitize-tx19
 869 *tx19:
 870 // end-sanitize-tx19
 871 {
 872   address_word offset = EXTEND16 (OFFSET) << 2;
 873   check_branch_bug ();
 874   RA = (CIA + 8);
 875   /* NOTE: The branch occurs AFTER the next instruction has been
 876      executed */
 877   if ((signed_word) GPR[RS] < 0)
 878     {
 879       mark_branch_bug (NIA+offset);
 880       DELAY_SLOT (NIA + offset);
 881     }
 882 }
 883
 884
 885
 886 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 887 "bltzall r<RS>, <OFFSET>"
 888 *mipsII:
 889 *mipsIII:
 890 *mipsIV:
 891 *vr5000:
 892 // start-sanitize-vr4320
 893 *vr4320:
 894 // end-sanitize-vr4320
 895 // start-sanitize-cygnus
 896 *vr5400:
 897 // end-sanitize-cygnus
 898 // start-sanitize-r5900
 899 *r5900:
 900 // end-sanitize-r5900
 901 *r3900:
 902 // start-sanitize-tx19
 903 *tx19:
 904 // end-sanitize-tx19
 905 {
 906   address_word offset = EXTEND16 (OFFSET) << 2;
 907   check_branch_bug ();
 908   RA = (CIA + 8);
 909   if ((signed_word) GPR[RS] < 0)
 910     {
 911       mark_branch_bug (NIA+offset);
 912       DELAY_SLOT (NIA + offset);
 913     }
 914   else
 915     NULLIFY_NEXT_INSTRUCTION ();
 916 }
 917
 918
 919
 920 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 921 "bltzl r<RS>, <OFFSET>"
 922 *mipsII:
 923 *mipsIII:
 924 *mipsIV:
 925 *vr5000:
 926 // start-sanitize-vr4320
 927 *vr4320:
 928 // end-sanitize-vr4320
 929 // start-sanitize-cygnus
 930 *vr5400:
 931 // end-sanitize-cygnus
 932 // start-sanitize-r5900
 933 *r5900:
 934 // end-sanitize-r5900
 935 *r3900:
 936 // start-sanitize-tx19
 937 *tx19:
 938 // end-sanitize-tx19
 939 {
 940   address_word offset = EXTEND16 (OFFSET) << 2;
 941   check_branch_bug ();
 942   /* NOTE: The branch occurs AFTER the next instruction has been
 943      executed */
 944   if ((signed_word) GPR[RS] < 0)
 945     {
 946       mark_branch_bug (NIA+offset);
 947       DELAY_SLOT (NIA + offset);
 948     }
 949   else
 950     NULLIFY_NEXT_INSTRUCTION ();
 951 }
 952
 953
 954
 955 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 956 "bne r<RS>, r<RT>, <OFFSET>"
 957 *mipsI,mipsII,mipsIII,mipsIV:
 958 *vr5000:
 959 // start-sanitize-vr4320
 960 *vr4320:
 961 // end-sanitize-vr4320
 962 // start-sanitize-cygnus
 963 *vr5400:
 964 // end-sanitize-cygnus
 965 // start-sanitize-r5900
 966 *r5900:
 967 // end-sanitize-r5900
 968 *r3900:
 969 // start-sanitize-tx19
 970 *tx19:
 971 // end-sanitize-tx19
 972 {
 973   address_word offset = EXTEND16 (OFFSET) << 2;
 974   check_branch_bug ();
 975   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 976     {
 977       mark_branch_bug (NIA+offset);
 978       DELAY_SLOT (NIA + offset);
 979     }
 980 }
 981
 982
 983
 984 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 985 "bnel r<RS>, r<RT>, <OFFSET>"
 986 *mipsII:
 987 *mipsIII:
 988 *mipsIV:
 989 *vr5000:
 990 // start-sanitize-vr4320
 991 *vr4320:
 992 // end-sanitize-vr4320
 993 // start-sanitize-cygnus
 994 *vr5400:
 995 // end-sanitize-cygnus
 996 // start-sanitize-r5900
 997 *r5900:
 998 // end-sanitize-r5900
 999 *r3900:
1000 // start-sanitize-tx19
1001 *tx19:
1002 // end-sanitize-tx19
1003 {
1004   address_word offset = EXTEND16 (OFFSET) << 2;
1005   check_branch_bug ();
1006   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1007     {
1008       mark_branch_bug (NIA+offset);
1009       DELAY_SLOT (NIA + offset);
1010     }
1011   else
1012     NULLIFY_NEXT_INSTRUCTION ();
1013 }
1014
1015
1016
1017 000000,20.CODE,001101:SPECIAL:32::BREAK
1018 "break"
1019 *mipsI,mipsII,mipsIII,mipsIV:
1020 *vr5000:
1021 // start-sanitize-vr4320
1022 *vr4320:
1023 // end-sanitize-vr4320
1024 // start-sanitize-cygnus
1025 *vr5400:
1026 // end-sanitize-cygnus
1027 // start-sanitize-r5900
1028 *r5900:
1029 // end-sanitize-r5900
1030 *r3900:
1031 // start-sanitize-tx19
1032 *tx19:
1033 // end-sanitize-tx19
1034 {
1035   /* Check for some break instruction which are reserved for use by the simulator.  */
1036   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1037   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1038       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1039     {
1040       sim_engine_halt (SD, CPU, NULL, cia,
1041                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1042     }
1043   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1044            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1045     {
1046       if (STATE & simDELAYSLOT)
1047         PC = cia - 4; /* reference the branch instruction */
1048       else
1049         PC = cia;
1050       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1051     }
1052 // start-sanitize-sky
1053   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1054     {
1055       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1056     }
1057   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1058     {
1059       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1060     }
1061 // end-sanitize-sky
1062
1063   /* If we get this far, we're not an instruction reserved by the sim.  Raise
1064      the exception. */
1065   SignalException(BreakPoint, instruction_0);
1066 }
1067
1068
1069
1070
1071
1072
1073 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1074 "dadd r<RD>, r<RS>, r<RT>"
1075 *mipsIII:
1076 *mipsIV:
1077 *vr5000:
1078 // start-sanitize-vr4320
1079 *vr4320:
1080 // end-sanitize-vr4320
1081 // start-sanitize-cygnus
1082 *vr5400:
1083 // end-sanitize-cygnus
1084 // start-sanitize-r5900
1085 *r5900:
1086 // end-sanitize-r5900
1087 // start-sanitize-tx19
1088 *tx19:
1089 // end-sanitize-tx19
1090 {
1091   /* this check's for overflow */
1092   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1093   {
1094     ALU64_BEGIN (GPR[RS]);
1095     ALU64_ADD (GPR[RT]);
1096     ALU64_END (GPR[RD]);
1097   }
1098   TRACE_ALU_RESULT (GPR[RD]);
1099 }
1100
1101
1102
1103 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1104 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1105 *mipsIII:
1106 *mipsIV:
1107 *vr5000:
1108 // start-sanitize-vr4320
1109 *vr4320:
1110 // end-sanitize-vr4320
1111 // start-sanitize-cygnus
1112 *vr5400:
1113 // end-sanitize-cygnus
1114 // start-sanitize-r5900
1115 *r5900:
1116 // end-sanitize-r5900
1117 // start-sanitize-tx19
1118 *tx19:
1119 // end-sanitize-tx19
1120 {
1121   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1122   {
1123     ALU64_BEGIN (GPR[RS]);
1124     ALU64_ADD (EXTEND16 (IMMEDIATE));
1125     ALU64_END (GPR[RT]);
1126   }
1127   TRACE_ALU_RESULT (GPR[RT]);
1128 }
1129
1130
1131
1132 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1133 {
1134   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1135   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1136   TRACE_ALU_RESULT (GPR[rt]);
1137 }
1138
1139 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1140 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1141 *mipsIII:
1142 *mipsIV:
1143 *vr5000:
1144 // start-sanitize-vr4320
1145 *vr4320:
1146 // end-sanitize-vr4320
1147 // start-sanitize-cygnus
1148 *vr5400:
1149 // end-sanitize-cygnus
1150 // start-sanitize-r5900
1151 *r5900:
1152 // end-sanitize-r5900
1153 // start-sanitize-tx19
1154 *tx19:
1155 // end-sanitize-tx19
1156 {
1157   do_daddiu (SD_, RS, RT, IMMEDIATE);
1158 }
1159
1160
1161
1162 :function:::void:do_daddu:int rs, int rt, int rd
1163 {
1164   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1165   GPR[rd] = GPR[rs] + GPR[rt];
1166   TRACE_ALU_RESULT (GPR[rd]);
1167 }
1168
1169 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1170 "daddu r<RD>, r<RS>, r<RT>"
1171 *mipsIII:
1172 *mipsIV:
1173 *vr5000:
1174 // start-sanitize-vr4320
1175 *vr4320:
1176 // end-sanitize-vr4320
1177 // start-sanitize-cygnus
1178 *vr5400:
1179 // end-sanitize-cygnus
1180 // start-sanitize-r5900
1181 *r5900:
1182 // end-sanitize-r5900
1183 // start-sanitize-tx19
1184 *tx19:
1185 // end-sanitize-tx19
1186 {
1187   do_daddu (SD_, RS, RT, RD);
1188 }
1189
1190
1191
1192 :function:64::void:do_ddiv:int rs, int rt
1193 {
1194   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1195   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1196   {
1197     signed64 n = GPR[rs];
1198     signed64 d = GPR[rt];
1199     if (d == 0)
1200       {
1201         LO = SIGNED64 (0x8000000000000000);
1202         HI = 0;
1203       }
1204     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1205       {
1206         LO = SIGNED64 (0x8000000000000000);
1207         HI = 0;
1208       }
1209     else
1210       {
1211         LO = (n / d);
1212         HI = (n % d);
1213       }
1214   }
1215   TRACE_ALU_RESULT2 (HI, LO);
1216 }
1217
1218 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1219 "ddiv r<RS>, r<RT>"
1220 *mipsIII:
1221 *mipsIV:
1222 *vr5000:
1223 // start-sanitize-vr4320
1224 *vr4320:
1225 // end-sanitize-vr4320
1226 // start-sanitize-cygnus
1227 *vr5400:
1228 // end-sanitize-cygnus
1229 // start-sanitize-r5900
1230 *r5900:
1231 // end-sanitize-r5900
1232 // start-sanitize-tx19
1233 *tx19:
1234 // end-sanitize-tx19
1235 {
1236   do_ddiv (SD_, RS, RT);
1237 }
1238
1239
1240
1241 :function:64::void:do_ddivu:int rs, int rt
1242 {
1243   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1244   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1245   {
1246     unsigned64 n = GPR[rs];
1247     unsigned64 d = GPR[rt];
1248     if (d == 0)
1249       {
1250         LO = SIGNED64 (0x8000000000000000);
1251         HI = 0;
1252       }
1253     else
1254       {
1255         LO = (n / d);
1256         HI = (n % d);
1257       }
1258   }
1259   TRACE_ALU_RESULT2 (HI, LO);
1260 }
1261
1262 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1263 "ddivu r<RS>, r<RT>"
1264 *mipsIII:
1265 *mipsIV:
1266 *vr5000:
1267 // start-sanitize-vr4320
1268 *vr4320:
1269 // end-sanitize-vr4320
1270 // start-sanitize-cygnus
1271 *vr5400:
1272 // end-sanitize-cygnus
1273 // start-sanitize-tx19
1274 *tx19:
1275 // end-sanitize-tx19
1276 {
1277   do_ddivu (SD_, RS, RT);
1278 }
1279
1280
1281
1282 :function:::void:do_div:int rs, int rt
1283 {
1284   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1285   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1286   {
1287     signed32 n = GPR[rs];
1288     signed32 d = GPR[rt];
1289     if (d == 0)
1290       {
1291         LO = EXTEND32 (0x80000000);
1292         HI = EXTEND32 (0);
1293       }
1294     else if (n == SIGNED32 (0x80000000) && d == -1)
1295       {
1296         LO = EXTEND32 (0x80000000);
1297         HI = EXTEND32 (0);
1298       }
1299     else
1300       {
1301         LO = EXTEND32 (n / d);
1302         HI = EXTEND32 (n % d);
1303       }
1304   }
1305   TRACE_ALU_RESULT2 (HI, LO);
1306 }
1307
1308 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1309 "div r<RS>, r<RT>"
1310 *mipsI,mipsII,mipsIII,mipsIV:
1311 *vr5000:
1312 // start-sanitize-vr4320
1313 *vr4320:
1314 // end-sanitize-vr4320
1315 // start-sanitize-cygnus
1316 *vr5400:
1317 // end-sanitize-cygnus
1318 // start-sanitize-r5900
1319 *r5900:
1320 // end-sanitize-r5900
1321 *r3900:
1322 // start-sanitize-tx19
1323 *tx19:
1324 // end-sanitize-tx19
1325 {
1326   do_div (SD_, RS, RT);
1327 }
1328
1329
1330
1331 :function:::void:do_divu:int rs, int rt
1332 {
1333   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1334   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1335   {
1336     unsigned32 n = GPR[rs];
1337     unsigned32 d = GPR[rt];
1338     if (d == 0)
1339       {
1340         LO = EXTEND32 (0x80000000);
1341         HI = EXTEND32 (0);
1342       }
1343    else
1344      {
1345        LO = EXTEND32 (n / d);
1346        HI = EXTEND32 (n % d);
1347      }
1348   }
1349   TRACE_ALU_RESULT2 (HI, LO);
1350 }
1351
1352 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1353 "divu r<RS>, r<RT>"
1354 *mipsI,mipsII,mipsIII,mipsIV:
1355 *vr5000:
1356 // start-sanitize-vr4320
1357 *vr4320:
1358 // end-sanitize-vr4320
1359 // start-sanitize-cygnus
1360 *vr5400:
1361 // end-sanitize-cygnus
1362 // start-sanitize-r5900
1363 *r5900:
1364 // end-sanitize-r5900
1365 *r3900:
1366 // start-sanitize-tx19
1367 *tx19:
1368 // end-sanitize-tx19
1369 {
1370   do_divu (SD_, RS, RT);
1371 }
1372
1373
1374
1375 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1376 {
1377   unsigned64 lo;
1378   unsigned64 hi;
1379   unsigned64 m00;
1380   unsigned64 m01;
1381   unsigned64 m10;
1382   unsigned64 m11;
1383   unsigned64 mid;
1384   int sign;
1385   unsigned64 op1 = GPR[rs];
1386   unsigned64 op2 = GPR[rt];
1387   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1388   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1389   /* make signed multiply unsigned */
1390   sign = 0;
1391   if (signed_p)
1392     {
1393       if (op1 < 0)
1394         {
1395           op1 = - op1;
1396           ++sign;
1397         }
1398       if (op2 < 0)
1399         {
1400           op2 = - op2;
1401           ++sign;
1402         }
1403     }
1404   /* multuply out the 4 sub products */
1405   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1406   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1407   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1408   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1409   /* add the products */
1410   mid = ((unsigned64) VH4_8 (m00)
1411          + (unsigned64) VL4_8 (m10)
1412          + (unsigned64) VL4_8 (m01));
1413   lo = U8_4 (mid, m00);
1414   hi = (m11
1415         + (unsigned64) VH4_8 (mid)
1416         + (unsigned64) VH4_8 (m01)
1417         + (unsigned64) VH4_8 (m10));
1418   /* fix the sign */
1419   if (sign & 1)
1420     {
1421       lo = -lo;
1422       if (lo == 0)
1423         hi = -hi;
1424       else
1425         hi = -hi - 1;
1426     }
1427   /* save the result HI/LO (and a gpr) */
1428   LO = lo;
1429   HI = hi;
1430   if (rd != 0)
1431     GPR[rd] = lo;
1432   TRACE_ALU_RESULT2 (HI, LO);
1433 }
1434
1435 :function:::void:do_dmult:int rs, int rt, int rd
1436 {
1437   do_dmultx (SD_, rs, rt, rd, 1);
1438 }
1439
1440 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1441 "dmult r<RS>, r<RT>"
1442 *mipsIII,mipsIV:
1443 // start-sanitize-tx19
1444 *tx19:
1445 // end-sanitize-tx19
1446 // start-sanitize-vr4320
1447 *vr4320:
1448 // end-sanitize-vr4320
1449 {
1450   do_dmult (SD_, RS, RT, 0);
1451 }
1452
1453 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1454 "dmult r<RS>, r<RT>":RD == 0
1455 "dmult r<RD>, r<RS>, r<RT>"
1456 *vr5000:
1457 // start-sanitize-cygnus
1458 *vr5400:
1459 // end-sanitize-cygnus
1460 {
1461   do_dmult (SD_, RS, RT, RD);
1462 }
1463
1464
1465
1466 :function:::void:do_dmultu:int rs, int rt, int rd
1467 {
1468   do_dmultx (SD_, rs, rt, rd, 0);
1469 }
1470
1471 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1472 "dmultu r<RS>, r<RT>"
1473 *mipsIII,mipsIV:
1474 // start-sanitize-tx19
1475 *tx19:
1476 // end-sanitize-tx19
1477 // start-sanitize-vr4320
1478 *vr4320:
1479 // end-sanitize-vr4320
1480 {
1481   do_dmultu (SD_, RS, RT, 0);
1482 }
1483
1484 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1485 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1486 "dmultu r<RS>, r<RT>"
1487 *vr5000:
1488 // start-sanitize-cygnus
1489 *vr5400:
1490 // end-sanitize-cygnus
1491 {
1492   do_dmultu (SD_, RS, RT, RD);
1493 }
1494
1495
1496
1497 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1498 "dsll r<RD>, r<RT>, <SHIFT>"
1499 *mipsIII:
1500 *mipsIV:
1501 *vr5000:
1502 // start-sanitize-vr4320
1503 *vr4320:
1504 // end-sanitize-vr4320
1505 // start-sanitize-cygnus
1506 *vr5400:
1507 // end-sanitize-cygnus
1508 // start-sanitize-r5900
1509 *r5900:
1510 // end-sanitize-r5900
1511 // start-sanitize-tx19
1512 *tx19:
1513 // end-sanitize-tx19
1514 {
1515   int s = SHIFT;
1516   GPR[RD] = GPR[RT] << s;
1517 }
1518
1519
1520 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1521 "dsll32 r<RD>, r<RT>, <SHIFT>"
1522 *mipsIII:
1523 *mipsIV:
1524 *vr5000:
1525 // start-sanitize-vr4320
1526 *vr4320:
1527 // end-sanitize-vr4320
1528 // start-sanitize-cygnus
1529 *vr5400:
1530 // end-sanitize-cygnus
1531 // start-sanitize-r5900
1532 *r5900:
1533 // end-sanitize-r5900
1534 // start-sanitize-tx19
1535 *tx19:
1536 // end-sanitize-tx19
1537 {
1538   int s = 32 + SHIFT;
1539   GPR[RD] = GPR[RT] << s;
1540 }
1541
1542
1543
1544 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1545 "dsllv r<RD>, r<RT>, r<RS>"
1546 *mipsIII:
1547 *mipsIV:
1548 *vr5000:
1549 // start-sanitize-vr4320
1550 *vr4320:
1551 // end-sanitize-vr4320
1552 // start-sanitize-cygnus
1553 *vr5400:
1554 // end-sanitize-cygnus
1555 // start-sanitize-r5900
1556 *r5900:
1557 // end-sanitize-r5900
1558 // start-sanitize-tx19
1559 *tx19:
1560 // end-sanitize-tx19
1561 {
1562   int s = MASKED64 (GPR[RS], 5, 0);
1563   GPR[RD] = GPR[RT] << s;
1564 }
1565
1566
1567
1568 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1569 "dsra r<RD>, r<RT>, <SHIFT>"
1570 *mipsIII:
1571 *mipsIV:
1572 *vr5000:
1573 // start-sanitize-vr4320
1574 *vr4320:
1575 // end-sanitize-vr4320
1576 // start-sanitize-cygnus
1577 *vr5400:
1578 // end-sanitize-cygnus
1579 // start-sanitize-r5900
1580 *r5900:
1581 // end-sanitize-r5900
1582 // start-sanitize-tx19
1583 *tx19:
1584 // end-sanitize-tx19
1585 {
1586   int s = SHIFT;
1587   GPR[RD] = ((signed64) GPR[RT]) >> s;
1588 }
1589
1590
1591 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1592 "dsra32 r<RT>, r<RD>, <SHIFT>"
1593 *mipsIII:
1594 *mipsIV:
1595 *vr5000:
1596 // start-sanitize-vr4320
1597 *vr4320:
1598 // end-sanitize-vr4320
1599 // start-sanitize-cygnus
1600 *vr5400:
1601 // end-sanitize-cygnus
1602 // start-sanitize-r5900
1603 *r5900:
1604 // end-sanitize-r5900
1605 // start-sanitize-tx19
1606 *tx19:
1607 // end-sanitize-tx19
1608 {
1609   int s = 32 + SHIFT;
1610   GPR[RD] = ((signed64) GPR[RT]) >> s;
1611 }
1612
1613
1614 :function:::void:do_dsrav:int rs, int rt, int rd
1615 {
1616   int s = MASKED64 (GPR[rs], 5, 0);
1617   TRACE_ALU_INPUT2 (GPR[rt], s);
1618   GPR[rd] = ((signed64) GPR[rt]) >> s;
1619   TRACE_ALU_RESULT (GPR[rd]);
1620 }
1621
1622 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1623 "dsra32 r<RT>, r<RD>, r<RS>"
1624 *mipsIII:
1625 *mipsIV:
1626 *vr5000:
1627 // start-sanitize-vr4320
1628 *vr4320:
1629 // end-sanitize-vr4320
1630 // start-sanitize-cygnus
1631 *vr5400:
1632 // end-sanitize-cygnus
1633 // start-sanitize-r5900
1634 *r5900:
1635 // end-sanitize-r5900
1636 // start-sanitize-tx19
1637 *tx19:
1638 // end-sanitize-tx19
1639 {
1640   do_dsrav (SD_, RS, RT, RD);
1641 }
1642
1643
1644 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1645 "dsrl r<RD>, r<RT>, <SHIFT>"
1646 *mipsIII:
1647 *mipsIV:
1648 *vr5000:
1649 // start-sanitize-vr4320
1650 *vr4320:
1651 // end-sanitize-vr4320
1652 // start-sanitize-cygnus
1653 *vr5400:
1654 // end-sanitize-cygnus
1655 // start-sanitize-r5900
1656 *r5900:
1657 // end-sanitize-r5900
1658 // start-sanitize-tx19
1659 *tx19:
1660 // end-sanitize-tx19
1661 {
1662   int s = SHIFT;
1663   GPR[RD] = (unsigned64) GPR[RT] >> s;
1664 }
1665
1666
1667 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1668 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1669 *mipsIII:
1670 *mipsIV:
1671 *vr5000:
1672 // start-sanitize-vr4320
1673 *vr4320:
1674 // end-sanitize-vr4320
1675 // start-sanitize-cygnus
1676 *vr5400:
1677 // end-sanitize-cygnus
1678 // start-sanitize-r5900
1679 *r5900:
1680 // end-sanitize-r5900
1681 // start-sanitize-tx19
1682 *tx19:
1683 // end-sanitize-tx19
1684 {
1685   int s = 32 + SHIFT;
1686   GPR[RD] = (unsigned64) GPR[RT] >> s;
1687 }
1688
1689
1690 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1691 "dsrl32 r<RD>, r<RT>, r<RS>"
1692 *mipsIII:
1693 *mipsIV:
1694 *vr5000:
1695 // start-sanitize-vr4320
1696 *vr4320:
1697 // end-sanitize-vr4320
1698 // start-sanitize-cygnus
1699 *vr5400:
1700 // end-sanitize-cygnus
1701 // start-sanitize-r5900
1702 *r5900:
1703 // end-sanitize-r5900
1704 // start-sanitize-tx19
1705 *tx19:
1706 // end-sanitize-tx19
1707 {
1708   int s = MASKED64 (GPR[RS], 5, 0);
1709   GPR[RD] = (unsigned64) GPR[RT] >> s;
1710 }
1711
1712
1713 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1714 "dsub r<RD>, r<RS>, r<RT>"
1715 *mipsIII:
1716 *mipsIV:
1717 *vr5000:
1718 // start-sanitize-vr4320
1719 *vr4320:
1720 // end-sanitize-vr4320
1721 // start-sanitize-cygnus
1722 *vr5400:
1723 // end-sanitize-cygnus
1724 // start-sanitize-r5900
1725 *r5900:
1726 // end-sanitize-r5900
1727 // start-sanitize-tx19
1728 *tx19:
1729 // end-sanitize-tx19
1730 {
1731   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1732   {
1733     ALU64_BEGIN (GPR[RS]);
1734     ALU64_SUB (GPR[RT]);
1735     ALU64_END (GPR[RD]);
1736   }
1737   TRACE_ALU_RESULT (GPR[RD]);
1738 }
1739
1740
1741 :function:::void:do_dsubu:int rs, int rt, int rd
1742 {
1743   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1744   GPR[rd] = GPR[rs] - GPR[rt];
1745   TRACE_ALU_RESULT (GPR[rd]);
1746 }
1747
1748 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1749 "dsubu r<RD>, r<RS>, r<RT>"
1750 *mipsIII:
1751 *mipsIV:
1752 *vr5000:
1753 // start-sanitize-vr4320
1754 *vr4320:
1755 // end-sanitize-vr4320
1756 // start-sanitize-cygnus
1757 *vr5400:
1758 // end-sanitize-cygnus
1759 // start-sanitize-r5900
1760 *r5900:
1761 // end-sanitize-r5900
1762 // start-sanitize-tx19
1763 *tx19:
1764 // end-sanitize-tx19
1765 {
1766   do_dsubu (SD_, RS, RT, RD);
1767 }
1768
1769
1770 000010,26.INSTR_INDEX:NORMAL:32::J
1771 "j <INSTR_INDEX>"
1772 *mipsI,mipsII,mipsIII,mipsIV:
1773 *vr5000:
1774 // start-sanitize-vr4320
1775 *vr4320:
1776 // end-sanitize-vr4320
1777 // start-sanitize-cygnus
1778 *vr5400:
1779 // end-sanitize-cygnus
1780 // start-sanitize-r5900
1781 *r5900:
1782 // end-sanitize-r5900
1783 *r3900:
1784 // start-sanitize-tx19
1785 *tx19:
1786 // end-sanitize-tx19
1787 {
1788   /* NOTE: The region used is that of the delay slot NIA and NOT the
1789      current instruction */
1790   address_word region = (NIA & MASK (63, 28));
1791   DELAY_SLOT (region | (INSTR_INDEX << 2));
1792 }
1793
1794
1795 000011,26.INSTR_INDEX:NORMAL:32::JAL
1796 "jal <INSTR_INDEX>"
1797 *mipsI,mipsII,mipsIII,mipsIV:
1798 *vr5000:
1799 // start-sanitize-vr4320
1800 *vr4320:
1801 // end-sanitize-vr4320
1802 // start-sanitize-cygnus
1803 *vr5400:
1804 // end-sanitize-cygnus
1805 // start-sanitize-r5900
1806 *r5900:
1807 // end-sanitize-r5900
1808 *r3900:
1809 // start-sanitize-tx19
1810 *tx19:
1811 // end-sanitize-tx19
1812 {
1813   /* NOTE: The region used is that of the delay slot and NOT the
1814      current instruction */
1815   address_word region = (NIA & MASK (63, 28));
1816   GPR[31] = CIA + 8;
1817   DELAY_SLOT (region | (INSTR_INDEX << 2));
1818 }
1819
1820
1821 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1822 "jalr r<RS>":RD == 31
1823 "jalr r<RD>, r<RS>"
1824 *mipsI,mipsII,mipsIII,mipsIV:
1825 *vr5000:
1826 // start-sanitize-vr4320
1827 *vr4320:
1828 // end-sanitize-vr4320
1829 // start-sanitize-cygnus
1830 *vr5400:
1831 // end-sanitize-cygnus
1832 // start-sanitize-r5900
1833 *r5900:
1834 // end-sanitize-r5900
1835 *r3900:
1836 // start-sanitize-tx19
1837 *tx19:
1838 // end-sanitize-tx19
1839 {
1840   address_word temp = GPR[RS];
1841   GPR[RD] = CIA + 8;
1842   DELAY_SLOT (temp);
1843 }
1844
1845
1846 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1847 "jr r<RS>"
1848 *mipsI,mipsII,mipsIII,mipsIV:
1849 *vr5000:
1850 // start-sanitize-vr4320
1851 *vr4320:
1852 // end-sanitize-vr4320
1853 // start-sanitize-cygnus
1854 *vr5400:
1855 // end-sanitize-cygnus
1856 // start-sanitize-r5900
1857 *r5900:
1858 // end-sanitize-r5900
1859 *r3900:
1860 // start-sanitize-tx19
1861 *tx19:
1862 // end-sanitize-tx19
1863 {
1864   DELAY_SLOT (GPR[RS]);
1865 }
1866
1867
1868 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1869 {
1870   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1871   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1872   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1873   unsigned int byte;
1874   address_word paddr;
1875   int uncached;
1876   unsigned64 memval;
1877   address_word vaddr;
1878
1879   vaddr = base + offset;
1880   if ((vaddr & access) != 0)
1881     SignalExceptionAddressLoad ();
1882   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1883   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1884   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1885   byte = ((vaddr & mask) ^ bigendiancpu);
1886   return (memval >> (8 * byte));
1887 }
1888
1889
1890 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1891 "lb r<RT>, <OFFSET>(r<BASE>)"
1892 *mipsI,mipsII,mipsIII,mipsIV:
1893 *vr5000:
1894 // start-sanitize-vr4320
1895 *vr4320:
1896 // end-sanitize-vr4320
1897 // start-sanitize-cygnus
1898 *vr5400:
1899 // end-sanitize-cygnus
1900 // start-sanitize-r5900
1901 *r5900:
1902 // end-sanitize-r5900
1903 *r3900:
1904 // start-sanitize-tx19
1905 *tx19:
1906 // end-sanitize-tx19
1907 {
1908   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1909 }
1910
1911
1912 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1913 "lbu r<RT>, <OFFSET>(r<BASE>)"
1914 *mipsI,mipsII,mipsIII,mipsIV:
1915 *vr5000:
1916 // start-sanitize-vr4320
1917 *vr4320:
1918 // end-sanitize-vr4320
1919 // start-sanitize-cygnus
1920 *vr5400:
1921 // end-sanitize-cygnus
1922 // start-sanitize-r5900
1923 *r5900:
1924 // end-sanitize-r5900
1925 *r3900:
1926 // start-sanitize-tx19
1927 *tx19:
1928 // end-sanitize-tx19
1929 {
1930   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1931 }
1932
1933
1934 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1935 "ld r<RT>, <OFFSET>(r<BASE>)"
1936 *mipsIII:
1937 *mipsIV:
1938 *vr5000:
1939 // start-sanitize-vr4320
1940 *vr4320:
1941 // end-sanitize-vr4320
1942 // start-sanitize-cygnus
1943 *vr5400:
1944 // end-sanitize-cygnus
1945 // start-sanitize-r5900
1946 *r5900:
1947 // end-sanitize-r5900
1948 // start-sanitize-tx19
1949 *tx19:
1950 // end-sanitize-tx19
1951 {
1952   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1953 }
1954
1955
1956 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1957 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1958 *mipsII:
1959 *mipsIII:
1960 *mipsIV:
1961 *vr5000:
1962 // start-sanitize-vr4320
1963 *vr4320:
1964 // end-sanitize-vr4320
1965 // start-sanitize-cygnus
1966 *vr5400:
1967 // end-sanitize-cygnus
1968 *r3900:
1969 // start-sanitize-tx19
1970 *tx19:
1971 // end-sanitize-tx19
1972 {
1973   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1974 }
1975
1976
1977
1978
1979 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1980 "ldl r<RT>, <OFFSET>(r<BASE>)"
1981 *mipsIII:
1982 *mipsIV:
1983 *vr5000:
1984 // start-sanitize-vr4320
1985 *vr4320:
1986 // end-sanitize-vr4320
1987 // start-sanitize-cygnus
1988 *vr5400:
1989 // end-sanitize-cygnus
1990 // start-sanitize-r5900
1991 *r5900:
1992 // end-sanitize-r5900
1993 // start-sanitize-tx19
1994 *tx19:
1995 // end-sanitize-tx19
1996 {
1997   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1998 }
1999
2000
2001 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2002 "ldr r<RT>, <OFFSET>(r<BASE>)"
2003 *mipsIII:
2004 *mipsIV:
2005 *vr5000:
2006 // start-sanitize-vr4320
2007 *vr4320:
2008 // end-sanitize-vr4320
2009 // start-sanitize-cygnus
2010 *vr5400:
2011 // end-sanitize-cygnus
2012 // start-sanitize-r5900
2013 *r5900:
2014 // end-sanitize-r5900
2015 // start-sanitize-tx19
2016 *tx19:
2017 // end-sanitize-tx19
2018 {
2019   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2020 }
2021
2022
2023 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2024 "lh r<RT>, <OFFSET>(r<BASE>)"
2025 *mipsI,mipsII,mipsIII,mipsIV:
2026 *vr5000:
2027 // start-sanitize-vr4320
2028 *vr4320:
2029 // end-sanitize-vr4320
2030 // start-sanitize-cygnus
2031 *vr5400:
2032 // end-sanitize-cygnus
2033 // start-sanitize-r5900
2034 *r5900:
2035 // end-sanitize-r5900
2036 *r3900:
2037 // start-sanitize-tx19
2038 *tx19:
2039 // end-sanitize-tx19
2040 {
2041   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2042 }
2043
2044
2045 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2046 "lhu r<RT>, <OFFSET>(r<BASE>)"
2047 *mipsI,mipsII,mipsIII,mipsIV:
2048 *vr5000:
2049 // start-sanitize-vr4320
2050 *vr4320:
2051 // end-sanitize-vr4320
2052 // start-sanitize-cygnus
2053 *vr5400:
2054 // end-sanitize-cygnus
2055 // start-sanitize-r5900
2056 *r5900:
2057 // end-sanitize-r5900
2058 *r3900:
2059 // start-sanitize-tx19
2060 *tx19:
2061 // end-sanitize-tx19
2062 {
2063   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2064 }
2065
2066
2067 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2068 "ll r<RT>, <OFFSET>(r<BASE>)"
2069 *mipsII:
2070 *mipsIII:
2071 *mipsIV:
2072 *vr5000:
2073 // start-sanitize-vr4320
2074 *vr4320:
2075 // end-sanitize-vr4320
2076 // start-sanitize-cygnus
2077 *vr5400:
2078 // end-sanitize-cygnus
2079 // start-sanitize-r5900
2080 *r5900:
2081 // end-sanitize-r5900
2082 // start-sanitize-tx19
2083 *tx19:
2084 // end-sanitize-tx19
2085 {
2086   unsigned32 instruction = instruction_0;
2087   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2088   int destreg = ((instruction >> 16) & 0x0000001F);
2089   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2090   {
2091     address_word vaddr = ((unsigned64)op1 + offset);
2092     address_word paddr;
2093     int uncached;
2094     if ((vaddr & 3) != 0)
2095       SignalExceptionAddressLoad();
2096     else
2097       {
2098         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2099           {
2100             unsigned64 memval = 0;
2101             unsigned64 memval1 = 0;
2102             unsigned64 mask = 0x7;
2103             unsigned int shift = 2;
2104             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2105             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2106             unsigned int byte;
2107             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2108             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2109             byte = ((vaddr & mask) ^ (bigend << shift));
2110             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2111             LLBIT = 1;
2112           }
2113       }
2114   }
2115 }
2116
2117
2118 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2119 "lld r<RT>, <OFFSET>(r<BASE>)"
2120 *mipsIII:
2121 *mipsIV:
2122 *vr5000:
2123 // start-sanitize-vr4320
2124 *vr4320:
2125 // end-sanitize-vr4320
2126 // start-sanitize-cygnus
2127 *vr5400:
2128 // end-sanitize-cygnus
2129 // start-sanitize-r5900
2130 *r5900:
2131 // end-sanitize-r5900
2132 // start-sanitize-tx19
2133 *tx19:
2134 // end-sanitize-tx19
2135 {
2136   unsigned32 instruction = instruction_0;
2137   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2138   int destreg = ((instruction >> 16) & 0x0000001F);
2139   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2140   {
2141     address_word vaddr = ((unsigned64)op1 + offset);
2142     address_word paddr;
2143     int uncached;
2144     if ((vaddr & 7) != 0)
2145       SignalExceptionAddressLoad();
2146     else
2147       {
2148         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2149           {
2150             unsigned64 memval = 0;
2151             unsigned64 memval1 = 0;
2152             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2153             GPR[destreg] = memval;
2154             LLBIT = 1;
2155           }
2156       }
2157   }
2158 }
2159
2160
2161 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2162 "lui r<RT>, <IMMEDIATE>"
2163 *mipsI,mipsII,mipsIII,mipsIV:
2164 *vr5000:
2165 // start-sanitize-vr4320
2166 *vr4320:
2167 // end-sanitize-vr4320
2168 // start-sanitize-cygnus
2169 *vr5400:
2170 // end-sanitize-cygnus
2171 // start-sanitize-r5900
2172 *r5900:
2173 // end-sanitize-r5900
2174 *r3900:
2175 // start-sanitize-tx19
2176 *tx19:
2177 // end-sanitize-tx19
2178 {
2179   TRACE_ALU_INPUT1 (IMMEDIATE);
2180   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2181   TRACE_ALU_RESULT (GPR[RT]);
2182 }
2183
2184
2185 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2186 "lw r<RT>, <OFFSET>(r<BASE>)"
2187 *mipsI,mipsII,mipsIII,mipsIV:
2188 *vr5000:
2189 // start-sanitize-vr4320
2190 *vr4320:
2191 // end-sanitize-vr4320
2192 // start-sanitize-cygnus
2193 *vr5400:
2194 // end-sanitize-cygnus
2195 // start-sanitize-r5900
2196 *r5900:
2197 // end-sanitize-r5900
2198 *r3900:
2199 // start-sanitize-tx19
2200 *tx19:
2201 // end-sanitize-tx19
2202 {
2203   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2204 }
2205
2206
2207 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2208 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2209 *mipsI,mipsII,mipsIII,mipsIV:
2210 *vr5000:
2211 // start-sanitize-vr4320
2212 *vr4320:
2213 // end-sanitize-vr4320
2214 // start-sanitize-cygnus
2215 *vr5400:
2216 // end-sanitize-cygnus
2217 // start-sanitize-r5900
2218 *r5900:
2219 // end-sanitize-r5900
2220 *r3900:
2221 // start-sanitize-tx19
2222 *tx19:
2223 // end-sanitize-tx19
2224 {
2225   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2226 }
2227
2228
2229 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2230 {
2231   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2232   address_word reverseendian = (ReverseEndian ? -1 : 0);
2233   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2234   unsigned int byte;
2235   unsigned int word;
2236   address_word paddr;
2237   int uncached;
2238   unsigned64 memval;
2239   address_word vaddr;
2240   int nr_lhs_bits;
2241   int nr_rhs_bits;
2242   unsigned_word lhs_mask;
2243   unsigned_word temp;
2244
2245   vaddr = base + offset;
2246   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2247   paddr = (paddr ^ (reverseendian & mask));
2248   if (BigEndianMem == 0)
2249     paddr = paddr & ~access;
2250
2251   /* compute where within the word/mem we are */
2252   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2253   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2254   nr_lhs_bits = 8 * byte + 8;
2255   nr_rhs_bits = 8 * access - 8 * byte;
2256   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2257
2258   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2259            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2260            (long) ((unsigned64) paddr >> 32), (long) paddr,
2261            word, byte, nr_lhs_bits, nr_rhs_bits); */
2262
2263   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2264   if (word == 0)
2265     {
2266       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2267       temp = (memval << nr_rhs_bits);
2268     }
2269   else
2270     {
2271       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2272       temp = (memval >> nr_lhs_bits);
2273     }
2274   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2275   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2276
2277   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2278            (long) ((unsigned64) memval >> 32), (long) memval,
2279            (long) ((unsigned64) temp >> 32), (long) temp,
2280            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2281            (long) (rt >> 32), (long) rt); */
2282   return rt;
2283 }
2284
2285
2286 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2287 "lwl r<RT>, <OFFSET>(r<BASE>)"
2288 *mipsI,mipsII,mipsIII,mipsIV:
2289 *vr5000:
2290 // start-sanitize-vr4320
2291 *vr4320:
2292 // end-sanitize-vr4320
2293 // start-sanitize-cygnus
2294 *vr5400:
2295 // end-sanitize-cygnus
2296 // start-sanitize-r5900
2297 *r5900:
2298 // end-sanitize-r5900
2299 *r3900:
2300 // start-sanitize-tx19
2301 *tx19:
2302 // end-sanitize-tx19
2303 {
2304   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2305 }
2306
2307
2308 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2309 {
2310   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2311   address_word reverseendian = (ReverseEndian ? -1 : 0);
2312   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2313   unsigned int byte;
2314   address_word paddr;
2315   int uncached;
2316   unsigned64 memval;
2317   address_word vaddr;
2318
2319   vaddr = base + offset;
2320   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2321   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2322   paddr = (paddr ^ (reverseendian & mask));
2323   if (BigEndianMem != 0)
2324     paddr = paddr & ~access;
2325   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2326   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2327   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2328   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2329      (long) paddr, byte, (long) paddr, (long) memval); */
2330   {
2331     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2332     rt &= ~screen;
2333     rt |= (memval >> (8 * byte)) & screen;
2334   }
2335   return rt;
2336 }
2337
2338
2339 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2340 "lwr r<RT>, <OFFSET>(r<BASE>)"
2341 *mipsI,mipsII,mipsIII,mipsIV:
2342 *vr5000:
2343 // start-sanitize-vr4320
2344 *vr4320:
2345 // end-sanitize-vr4320
2346 // start-sanitize-cygnus
2347 *vr5400:
2348 // end-sanitize-cygnus
2349 // start-sanitize-r5900
2350 *r5900:
2351 // end-sanitize-r5900
2352 *r3900:
2353 // start-sanitize-tx19
2354 *tx19:
2355 // end-sanitize-tx19
2356 {
2357   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2358 }
2359
2360
2361 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2362 "lwu r<RT>, <OFFSET>(r<BASE>)"
2363 *mipsIII:
2364 *mipsIV:
2365 *vr5000:
2366 // start-sanitize-vr4320
2367 *vr4320:
2368 // end-sanitize-vr4320
2369 // start-sanitize-cygnus
2370 *vr5400:
2371 // end-sanitize-cygnus
2372 // start-sanitize-r5900
2373 *r5900:
2374 // end-sanitize-r5900
2375 // start-sanitize-tx19
2376 *tx19:
2377 // end-sanitize-tx19
2378 {
2379   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2380 }
2381
2382
2383 :function:::void:do_mfhi:int rd
2384 {
2385   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2386   TRACE_ALU_INPUT1 (HI);
2387   GPR[rd] = HI;
2388   TRACE_ALU_RESULT (GPR[rd]);
2389 }
2390
2391 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2392 "mfhi r<RD>"
2393 *mipsI,mipsII,mipsIII,mipsIV:
2394 *vr5000:
2395 // start-sanitize-vr4320
2396 *vr4320:
2397 // end-sanitize-vr4320
2398 // start-sanitize-cygnus
2399 *vr5400:
2400 // end-sanitize-cygnus
2401 // start-sanitize-r5900
2402 *r5900:
2403 // end-sanitize-r5900
2404 *r3900:
2405 // start-sanitize-tx19
2406 *tx19:
2407 // end-sanitize-tx19
2408 {
2409   do_mfhi (SD_, RD);
2410 }
2411
2412
2413
2414 :function:::void:do_mflo:int rd
2415 {
2416   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2417   TRACE_ALU_INPUT1 (LO);
2418   GPR[rd] = LO;
2419   TRACE_ALU_RESULT (GPR[rd]);
2420 }
2421
2422 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2423 "mflo r<RD>"
2424 *mipsI,mipsII,mipsIII,mipsIV:
2425 *vr5000:
2426 // start-sanitize-vr4320
2427 *vr4320:
2428 // end-sanitize-vr4320
2429 // start-sanitize-cygnus
2430 *vr5400:
2431 // end-sanitize-cygnus
2432 // start-sanitize-r5900
2433 *r5900:
2434 // end-sanitize-r5900
2435 *r3900:
2436 // start-sanitize-tx19
2437 *tx19:
2438 // end-sanitize-tx19
2439 {
2440   do_mflo (SD_, RD);
2441 }
2442
2443
2444
2445 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2446 "movn r<RD>, r<RS>, r<RT>"
2447 *mipsIV:
2448 *vr5000:
2449 // start-sanitize-vr4320
2450 *vr4320:
2451 // end-sanitize-vr4320
2452 // start-sanitize-cygnus
2453 *vr5400:
2454 // end-sanitize-cygnus
2455 // start-sanitize-r5900
2456 *r5900:
2457 // end-sanitize-r5900
2458 {
2459   if (GPR[RT] != 0)
2460     GPR[RD] = GPR[RS];
2461 }
2462
2463
2464
2465 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2466 "movz r<RD>, r<RS>, r<RT>"
2467 *mipsIV:
2468 *vr5000:
2469 // start-sanitize-vr4320
2470 *vr4320:
2471 // end-sanitize-vr4320
2472 // start-sanitize-cygnus
2473 *vr5400:
2474 // end-sanitize-cygnus
2475 // start-sanitize-r5900
2476 *r5900:
2477 // end-sanitize-r5900
2478 {
2479   if (GPR[RT] == 0)
2480     GPR[RD] = GPR[RS];
2481 }
2482
2483
2484
2485 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2486 "mthi r<RS>"
2487 *mipsI,mipsII,mipsIII,mipsIV:
2488 *vr5000:
2489 // start-sanitize-vr4320
2490 *vr4320:
2491 // end-sanitize-vr4320
2492 // start-sanitize-cygnus
2493 *vr5400:
2494 // end-sanitize-cygnus
2495 // start-sanitize-r5900
2496 *r5900:
2497 // end-sanitize-r5900
2498 *r3900:
2499 // start-sanitize-tx19
2500 *tx19:
2501 // end-sanitize-tx19
2502 {
2503   check_mt_hilo (SD_, HIHISTORY);
2504   HI = GPR[RS];
2505 }
2506
2507
2508
2509 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2510 "mtlo r<RS>"
2511 *mipsI,mipsII,mipsIII,mipsIV:
2512 *vr5000:
2513 // start-sanitize-vr4320
2514 *vr4320:
2515 // end-sanitize-vr4320
2516 // start-sanitize-cygnus
2517 *vr5400:
2518 // end-sanitize-cygnus
2519 // start-sanitize-r5900
2520 *r5900:
2521 // end-sanitize-r5900
2522 *r3900:
2523 // start-sanitize-tx19
2524 *tx19:
2525 // end-sanitize-tx19
2526 {
2527   check_mt_hilo (SD_, LOHISTORY);
2528   LO = GPR[RS];
2529 }
2530
2531
2532
2533 :function:::void:do_mult:int rs, int rt, int rd
2534 {
2535   signed64 prod;
2536   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2537   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2538   prod = (((signed64)(signed32) GPR[rs])
2539           * ((signed64)(signed32) GPR[rt]));
2540   LO = EXTEND32 (VL4_8 (prod));
2541   HI = EXTEND32 (VH4_8 (prod));
2542   if (rd != 0)
2543     GPR[rd] = LO;
2544   TRACE_ALU_RESULT2 (HI, LO);
2545 }
2546
2547 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2548 "mult r<RS>, r<RT>"
2549 *mipsI,mipsII,mipsIII,mipsIV:
2550 // start-sanitize-vr4320
2551 *vr4320:
2552 // end-sanitize-vr4320
2553 {
2554   do_mult (SD_, RS, RT, 0);
2555 }
2556
2557
2558 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2559 "mult r<RD>, r<RS>, r<RT>"
2560 *vr5000:
2561 // start-sanitize-cygnus
2562 *vr5400:
2563 // end-sanitize-cygnus
2564 // start-sanitize-r5900
2565 *r5900:
2566 // end-sanitize-r5900
2567 *r3900:
2568 // start-sanitize-tx19
2569 *tx19:
2570 // end-sanitize-tx19
2571 {
2572   do_mult (SD_, RS, RT, RD);
2573 }
2574
2575
2576 :function:::void:do_multu:int rs, int rt, int rd
2577 {
2578   unsigned64 prod;
2579   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2580   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2581   prod = (((unsigned64)(unsigned32) GPR[rs])
2582           * ((unsigned64)(unsigned32) GPR[rt]));
2583   LO = EXTEND32 (VL4_8 (prod));
2584   HI = EXTEND32 (VH4_8 (prod));
2585   if (rd != 0)
2586     GPR[rd] = LO;
2587   TRACE_ALU_RESULT2 (HI, LO);
2588 }
2589
2590 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2591 "multu r<RS>, r<RT>"
2592 *mipsI,mipsII,mipsIII,mipsIV:
2593 // start-sanitize-vr4320
2594 *vr4320:
2595 // end-sanitize-vr4320
2596 {
2597   do_multu (SD_, RS, RT, 0);
2598 }
2599
2600 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2601 "multu r<RD>, r<RS>, r<RT>"
2602 *vr5000:
2603 // start-sanitize-cygnus
2604 *vr5400:
2605 // end-sanitize-cygnus
2606 // start-sanitize-r5900
2607 *r5900:
2608 // end-sanitize-r5900
2609 *r3900:
2610 // start-sanitize-tx19
2611 *tx19:
2612 // end-sanitize-tx19
2613 {
2614   do_multu (SD_, RS, RT, 0);
2615 }
2616
2617
2618 :function:::void:do_nor:int rs, int rt, int rd
2619 {
2620   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2621   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2622   TRACE_ALU_RESULT (GPR[rd]);
2623 }
2624
2625 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2626 "nor r<RD>, r<RS>, r<RT>"
2627 *mipsI,mipsII,mipsIII,mipsIV:
2628 *vr5000:
2629 // start-sanitize-vr4320
2630 *vr4320:
2631 // end-sanitize-vr4320
2632 // start-sanitize-cygnus
2633 *vr5400:
2634 // end-sanitize-cygnus
2635 // start-sanitize-r5900
2636 *r5900:
2637 // end-sanitize-r5900
2638 *r3900:
2639 // start-sanitize-tx19
2640 *tx19:
2641 // end-sanitize-tx19
2642 {
2643   do_nor (SD_, RS, RT, RD);
2644 }
2645
2646
2647 :function:::void:do_or:int rs, int rt, int rd
2648 {
2649   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2650   GPR[rd] = (GPR[rs] | GPR[rt]);
2651   TRACE_ALU_RESULT (GPR[rd]);
2652 }
2653
2654 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2655 "or r<RD>, r<RS>, r<RT>"
2656 *mipsI,mipsII,mipsIII,mipsIV:
2657 *vr5000:
2658 // start-sanitize-vr4320
2659 *vr4320:
2660 // end-sanitize-vr4320
2661 // start-sanitize-cygnus
2662 *vr5400:
2663 // end-sanitize-cygnus
2664 // start-sanitize-r5900
2665 *r5900:
2666 // end-sanitize-r5900
2667 *r3900:
2668 // start-sanitize-tx19
2669 *tx19:
2670 // end-sanitize-tx19
2671 {
2672   do_or (SD_, RS, RT, RD);
2673 }
2674
2675
2676
2677 :function:::void:do_ori:int rs, int rt, unsigned immediate
2678 {
2679   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2680   GPR[rt] = (GPR[rs] | immediate);
2681   TRACE_ALU_RESULT (GPR[rt]);
2682 }
2683
2684 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2685 "ori r<RT>, r<RS>, <IMMEDIATE>"
2686 *mipsI,mipsII,mipsIII,mipsIV:
2687 *vr5000:
2688 // start-sanitize-vr4320
2689 *vr4320:
2690 // end-sanitize-vr4320
2691 // start-sanitize-cygnus
2692 *vr5400:
2693 // end-sanitize-cygnus
2694 // start-sanitize-r5900
2695 *r5900:
2696 // end-sanitize-r5900
2697 *r3900:
2698 // start-sanitize-tx19
2699 *tx19:
2700 // end-sanitize-tx19
2701 {
2702   do_ori (SD_, RS, RT, IMMEDIATE);
2703 }
2704
2705
2706 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2707 *mipsIV:
2708 *vr5000:
2709 // start-sanitize-vr4320
2710 *vr4320:
2711 // end-sanitize-vr4320
2712 // start-sanitize-cygnus
2713 *vr5400:
2714 // end-sanitize-cygnus
2715 // start-sanitize-r5900
2716 *r5900:
2717 // end-sanitize-r5900
2718 {
2719   unsigned32 instruction = instruction_0;
2720   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2721   int hint = ((instruction >> 16) & 0x0000001F);
2722   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2723   {
2724     address_word vaddr = ((unsigned64)op1 + offset);
2725     address_word paddr;
2726     int uncached;
2727     {
2728       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2729         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2730     }
2731   }
2732 }
2733
2734 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2735 {
2736   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2737   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2738   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2739   unsigned int byte;
2740   address_word paddr;
2741   int uncached;
2742   unsigned64 memval;
2743   address_word vaddr;
2744
2745   vaddr = base + offset;
2746   if ((vaddr & access) != 0)
2747     SignalExceptionAddressStore ();
2748   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2749   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2750   byte = ((vaddr & mask) ^ bigendiancpu);
2751   memval = (word << (8 * byte));
2752   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2753 }
2754
2755
2756 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2757 "sb r<RT>, <OFFSET>(r<BASE>)"
2758 *mipsI,mipsII,mipsIII,mipsIV:
2759 *vr5000:
2760 // start-sanitize-vr4320
2761 *vr4320:
2762 // end-sanitize-vr4320
2763 // start-sanitize-cygnus
2764 *vr5400:
2765 // end-sanitize-cygnus
2766 // start-sanitize-r5900
2767 *r5900:
2768 // end-sanitize-r5900
2769 *r3900:
2770 // start-sanitize-tx19
2771 *tx19:
2772 // end-sanitize-tx19
2773 {
2774   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2775 }
2776
2777
2778 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2779 "sc r<RT>, <OFFSET>(r<BASE>)"
2780 *mipsII:
2781 *mipsIII:
2782 *mipsIV:
2783 *vr5000:
2784 // start-sanitize-vr4320
2785 *vr4320:
2786 // end-sanitize-vr4320
2787 // start-sanitize-cygnus
2788 *vr5400:
2789 // end-sanitize-cygnus
2790 // start-sanitize-r5900
2791 *r5900:
2792 // end-sanitize-r5900
2793 // start-sanitize-tx19
2794 *tx19:
2795 // end-sanitize-tx19
2796 {
2797   unsigned32 instruction = instruction_0;
2798   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2799   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2800   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2801   {
2802     address_word vaddr = ((unsigned64)op1 + offset);
2803     address_word paddr;
2804     int uncached;
2805     if ((vaddr & 3) != 0)
2806       SignalExceptionAddressStore();
2807     else
2808       {
2809         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2810           {
2811             unsigned64 memval = 0;
2812             unsigned64 memval1 = 0;
2813             unsigned64 mask = 0x7;
2814             unsigned int byte;
2815             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2816             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2817             memval = ((unsigned64) op2 << (8 * byte));
2818             if (LLBIT)
2819               {
2820                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2821               }
2822             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2823           }
2824       }
2825   }
2826 }
2827
2828
2829 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2830 "scd r<RT>, <OFFSET>(r<BASE>)"
2831 *mipsIII:
2832 *mipsIV:
2833 *vr5000:
2834 // start-sanitize-vr4320
2835 *vr4320:
2836 // end-sanitize-vr4320
2837 // start-sanitize-cygnus
2838 *vr5400:
2839 // end-sanitize-cygnus
2840 // start-sanitize-r5900
2841 *r5900:
2842 // end-sanitize-r5900
2843 // start-sanitize-tx19
2844 *tx19:
2845 // end-sanitize-tx19
2846 {
2847   unsigned32 instruction = instruction_0;
2848   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2849   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2850   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2851   {
2852     address_word vaddr = ((unsigned64)op1 + offset);
2853     address_word paddr;
2854     int uncached;
2855     if ((vaddr & 7) != 0)
2856       SignalExceptionAddressStore();
2857     else
2858       {
2859         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2860           {
2861             unsigned64 memval = 0;
2862             unsigned64 memval1 = 0;
2863             memval = op2;
2864             if (LLBIT)
2865               {
2866                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2867               }
2868             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2869           }
2870       }
2871   }
2872 }
2873
2874
2875 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2876 "sd r<RT>, <OFFSET>(r<BASE>)"
2877 *mipsIII:
2878 *mipsIV:
2879 *vr5000:
2880 // start-sanitize-vr4320
2881 *vr4320:
2882 // end-sanitize-vr4320
2883 // start-sanitize-cygnus
2884 *vr5400:
2885 // end-sanitize-cygnus
2886 // start-sanitize-r5900
2887 *r5900:
2888 // end-sanitize-r5900
2889 // start-sanitize-tx19
2890 *tx19:
2891 // end-sanitize-tx19
2892 {
2893   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2894 }
2895
2896
2897 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2898 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2899 *mipsII:
2900 *mipsIII:
2901 *mipsIV:
2902 *vr5000:
2903 // start-sanitize-vr4320
2904 *vr4320:
2905 // end-sanitize-vr4320
2906 // start-sanitize-cygnus
2907 *vr5400:
2908 // end-sanitize-cygnus
2909 // start-sanitize-tx19
2910 *tx19:
2911 // end-sanitize-tx19
2912 {
2913   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2914 }
2915
2916
2917 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2918 "sdl r<RT>, <OFFSET>(r<BASE>)"
2919 *mipsIII:
2920 *mipsIV:
2921 *vr5000:
2922 // start-sanitize-vr4320
2923 *vr4320:
2924 // end-sanitize-vr4320
2925 // start-sanitize-cygnus
2926 *vr5400:
2927 // end-sanitize-cygnus
2928 // start-sanitize-r5900
2929 *r5900:
2930 // end-sanitize-r5900
2931 // start-sanitize-tx19
2932 *tx19:
2933 // end-sanitize-tx19
2934 {
2935   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2936 }
2937
2938
2939 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2940 "sdr r<RT>, <OFFSET>(r<BASE>)"
2941 *mipsIII:
2942 *mipsIV:
2943 *vr5000:
2944 // start-sanitize-vr4320
2945 *vr4320:
2946 // end-sanitize-vr4320
2947 // start-sanitize-cygnus
2948 *vr5400:
2949 // end-sanitize-cygnus
2950 // start-sanitize-r5900
2951 *r5900:
2952 // end-sanitize-r5900
2953 // start-sanitize-tx19
2954 *tx19:
2955 // end-sanitize-tx19
2956 {
2957   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2958 }
2959
2960
2961 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2962 "sh r<RT>, <OFFSET>(r<BASE>)"
2963 *mipsI,mipsII,mipsIII,mipsIV:
2964 *vr5000:
2965 // start-sanitize-vr4320
2966 *vr4320:
2967 // end-sanitize-vr4320
2968 // start-sanitize-cygnus
2969 *vr5400:
2970 // end-sanitize-cygnus
2971 // start-sanitize-r5900
2972 *r5900:
2973 // end-sanitize-r5900
2974 *r3900:
2975 // start-sanitize-tx19
2976 *tx19:
2977 // end-sanitize-tx19
2978 {
2979   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2980 }
2981
2982
2983 :function:::void:do_sll:int rt, int rd, int shift
2984 {
2985   unsigned32 temp = (GPR[rt] << shift);
2986   TRACE_ALU_INPUT2 (GPR[rt], shift);
2987   GPR[rd] = EXTEND32 (temp);
2988   TRACE_ALU_RESULT (GPR[rd]);
2989 }
2990
2991 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2992 "sll r<RD>, r<RT>, <SHIFT>"
2993 *mipsI,mipsII,mipsIII,mipsIV:
2994 *vr5000:
2995 // start-sanitize-vr4320
2996 *vr4320:
2997 // end-sanitize-vr4320
2998 // start-sanitize-cygnus
2999 *vr5400:
3000 // end-sanitize-cygnus
3001 // start-sanitize-r5900
3002 *r5900:
3003 // end-sanitize-r5900
3004 *r3900:
3005 // start-sanitize-tx19
3006 *tx19:
3007 // end-sanitize-tx19
3008 {
3009   do_sll (SD_, RT, RD, SHIFT);
3010 }
3011
3012
3013 :function:::void:do_sllv:int rs, int rt, int rd
3014 {
3015   int s = MASKED (GPR[rs], 4, 0);
3016   unsigned32 temp = (GPR[rt] << s);
3017   TRACE_ALU_INPUT2 (GPR[rt], s);
3018   GPR[rd] = EXTEND32 (temp);
3019   TRACE_ALU_RESULT (GPR[rd]);
3020 }
3021
3022 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3023 "sllv r<RD>, r<RT>, r<RS>"
3024 *mipsI,mipsII,mipsIII,mipsIV:
3025 *vr5000:
3026 // start-sanitize-vr4320
3027 *vr4320:
3028 // end-sanitize-vr4320
3029 // start-sanitize-cygnus
3030 *vr5400:
3031 // end-sanitize-cygnus
3032 // start-sanitize-r5900
3033 *r5900:
3034 // end-sanitize-r5900
3035 *r3900:
3036 // start-sanitize-tx19
3037 *tx19:
3038 // end-sanitize-tx19
3039 {
3040   do_sllv (SD_, RS, RT, RD);
3041 }
3042
3043
3044 :function:::void:do_slt:int rs, int rt, int rd
3045 {
3046   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3047   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3048   TRACE_ALU_RESULT (GPR[rd]);
3049 }
3050
3051 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3052 "slt r<RD>, r<RS>, r<RT>"
3053 *mipsI,mipsII,mipsIII,mipsIV:
3054 *vr5000:
3055 // start-sanitize-vr4320
3056 *vr4320:
3057 // end-sanitize-vr4320
3058 // start-sanitize-cygnus
3059 *vr5400:
3060 // end-sanitize-cygnus
3061 // start-sanitize-r5900
3062 *r5900:
3063 // end-sanitize-r5900
3064 *r3900:
3065 // start-sanitize-tx19
3066 *tx19:
3067 // end-sanitize-tx19
3068 {
3069   do_slt (SD_, RS, RT, RD);
3070 }
3071
3072
3073 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3074 {
3075   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3076   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3077   TRACE_ALU_RESULT (GPR[rt]);
3078 }
3079
3080 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3081 "slti r<RT>, r<RS>, <IMMEDIATE>"
3082 *mipsI,mipsII,mipsIII,mipsIV:
3083 *vr5000:
3084 // start-sanitize-vr4320
3085 *vr4320:
3086 // end-sanitize-vr4320
3087 // start-sanitize-cygnus
3088 *vr5400:
3089 // end-sanitize-cygnus
3090 // start-sanitize-r5900
3091 *r5900:
3092 // end-sanitize-r5900
3093 *r3900:
3094 // start-sanitize-tx19
3095 *tx19:
3096 // end-sanitize-tx19
3097 {
3098   do_slti (SD_, RS, RT, IMMEDIATE);
3099 }
3100
3101
3102 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3103 {
3104   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3105   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3106   TRACE_ALU_RESULT (GPR[rt]);
3107 }
3108
3109 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3110 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3111 *mipsI,mipsII,mipsIII,mipsIV:
3112 *vr5000:
3113 // start-sanitize-vr4320
3114 *vr4320:
3115 // end-sanitize-vr4320
3116 // start-sanitize-cygnus
3117 *vr5400:
3118 // end-sanitize-cygnus
3119 // start-sanitize-r5900
3120 *r5900:
3121 // end-sanitize-r5900
3122 *r3900:
3123 // start-sanitize-tx19
3124 *tx19:
3125 // end-sanitize-tx19
3126 {
3127   do_sltiu (SD_, RS, RT, IMMEDIATE);
3128 }
3129
3130
3131
3132 :function:::void:do_sltu:int rs, int rt, int rd
3133 {
3134   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3135   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3136   TRACE_ALU_RESULT (GPR[rd]);
3137 }
3138
3139 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3140 "sltu r<RD>, r<RS>, r<RT>"
3141 *mipsI,mipsII,mipsIII,mipsIV:
3142 *vr5000:
3143 // start-sanitize-vr4320
3144 *vr4320:
3145 // end-sanitize-vr4320
3146 // start-sanitize-cygnus
3147 *vr5400:
3148 // end-sanitize-cygnus
3149 // start-sanitize-r5900
3150 *r5900:
3151 // end-sanitize-r5900
3152 *r3900:
3153 // start-sanitize-tx19
3154 *tx19:
3155 // end-sanitize-tx19
3156 {
3157   do_sltu (SD_, RS, RT, RD);
3158 }
3159
3160
3161 :function:::void:do_sra:int rt, int rd, int shift
3162 {
3163   signed32 temp = (signed32) GPR[rt] >> shift;
3164   TRACE_ALU_INPUT2 (GPR[rt], shift);
3165   GPR[rd] = EXTEND32 (temp);
3166   TRACE_ALU_RESULT (GPR[rd]);
3167 }
3168
3169 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3170 "sra r<RD>, r<RT>, <SHIFT>"
3171 *mipsI,mipsII,mipsIII,mipsIV:
3172 *vr5000:
3173 // start-sanitize-vr4320
3174 *vr4320:
3175 // end-sanitize-vr4320
3176 // start-sanitize-cygnus
3177 *vr5400:
3178 // end-sanitize-cygnus
3179 // start-sanitize-r5900
3180 *r5900:
3181 // end-sanitize-r5900
3182 *r3900:
3183 // start-sanitize-tx19
3184 *tx19:
3185 // end-sanitize-tx19
3186 {
3187   do_sra (SD_, RT, RD, SHIFT);
3188 }
3189
3190
3191
3192 :function:::void:do_srav:int rs, int rt, int rd
3193 {
3194   int s = MASKED (GPR[rs], 4, 0);
3195   signed32 temp = (signed32) GPR[rt] >> s;
3196   TRACE_ALU_INPUT2 (GPR[rt], s);
3197   GPR[rd] = EXTEND32 (temp);
3198   TRACE_ALU_RESULT (GPR[rd]);
3199 }
3200
3201 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3202 "srav r<RD>, r<RT>, r<RS>"
3203 *mipsI,mipsII,mipsIII,mipsIV:
3204 *vr5000:
3205 // start-sanitize-vr4320
3206 *vr4320:
3207 // end-sanitize-vr4320
3208 // start-sanitize-cygnus
3209 *vr5400:
3210 // end-sanitize-cygnus
3211 // start-sanitize-r5900
3212 *r5900:
3213 // end-sanitize-r5900
3214 *r3900:
3215 // start-sanitize-tx19
3216 *tx19:
3217 // end-sanitize-tx19
3218 {
3219   do_srav (SD_, RS, RT, RD);
3220 }
3221
3222
3223
3224 :function:::void:do_srl:int rt, int rd, int shift
3225 {
3226   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3227   TRACE_ALU_INPUT2 (GPR[rt], shift);
3228   GPR[rd] = EXTEND32 (temp);
3229   TRACE_ALU_RESULT (GPR[rd]);
3230 }
3231
3232 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3233 "srl r<RD>, r<RT>, <SHIFT>"
3234 *mipsI,mipsII,mipsIII,mipsIV:
3235 *vr5000:
3236 // start-sanitize-vr4320
3237 *vr4320:
3238 // end-sanitize-vr4320
3239 // start-sanitize-cygnus
3240 *vr5400:
3241 // end-sanitize-cygnus
3242 // start-sanitize-r5900
3243 *r5900:
3244 // end-sanitize-r5900
3245 *r3900:
3246 // start-sanitize-tx19
3247 *tx19:
3248 // end-sanitize-tx19
3249 {
3250   do_srl (SD_, RT, RD, SHIFT);
3251 }
3252
3253
3254 :function:::void:do_srlv:int rs, int rt, int rd
3255 {
3256   int s = MASKED (GPR[rs], 4, 0);
3257   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3258   TRACE_ALU_INPUT2 (GPR[rt], s);
3259   GPR[rd] = EXTEND32 (temp);
3260   TRACE_ALU_RESULT (GPR[rd]);
3261 }
3262
3263 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3264 "srlv r<RD>, r<RT>, r<RS>"
3265 *mipsI,mipsII,mipsIII,mipsIV:
3266 *vr5000:
3267 // start-sanitize-vr4320
3268 *vr4320:
3269 // end-sanitize-vr4320
3270 // start-sanitize-cygnus
3271 *vr5400:
3272 // end-sanitize-cygnus
3273 // start-sanitize-r5900
3274 *r5900:
3275 // end-sanitize-r5900
3276 *r3900:
3277 // start-sanitize-tx19
3278 *tx19:
3279 // end-sanitize-tx19
3280 {
3281   do_srlv (SD_, RS, RT, RD);
3282 }
3283
3284
3285 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3286 "sub r<RD>, r<RS>, r<RT>"
3287 *mipsI,mipsII,mipsIII,mipsIV:
3288 *vr5000:
3289 // start-sanitize-vr4320
3290 *vr4320:
3291 // end-sanitize-vr4320
3292 // start-sanitize-cygnus
3293 *vr5400:
3294 // end-sanitize-cygnus
3295 // start-sanitize-r5900
3296 *r5900:
3297 // end-sanitize-r5900
3298 *r3900:
3299 // start-sanitize-tx19
3300 *tx19:
3301 // end-sanitize-tx19
3302 {
3303   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3304   {
3305     ALU32_BEGIN (GPR[RS]);
3306     ALU32_SUB (GPR[RT]);
3307     ALU32_END (GPR[RD]);
3308   }
3309   TRACE_ALU_RESULT (GPR[RD]);
3310 }
3311
3312
3313 :function:::void:do_subu:int rs, int rt, int rd
3314 {
3315   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3316   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3317   TRACE_ALU_RESULT (GPR[rd]);
3318 }
3319
3320 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3321 "subu r<RD>, r<RS>, r<RT>"
3322 *mipsI,mipsII,mipsIII,mipsIV:
3323 *vr5000:
3324 // start-sanitize-vr4320
3325 *vr4320:
3326 // end-sanitize-vr4320
3327 // start-sanitize-cygnus
3328 *vr5400:
3329 // end-sanitize-cygnus
3330 // start-sanitize-r5900
3331 *r5900:
3332 // end-sanitize-r5900
3333 *r3900:
3334 // start-sanitize-tx19
3335 *tx19:
3336 // end-sanitize-tx19
3337 {
3338   do_subu (SD_, RS, RT, RD);
3339 }
3340
3341
3342 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3343 "sw r<RT>, <OFFSET>(r<BASE>)"
3344 *mipsI,mipsII,mipsIII,mipsIV:
3345 // start-sanitize-tx19
3346 *tx19:
3347 // end-sanitize-tx19
3348 *r3900:
3349 // start-sanitize-vr4320
3350 *vr4320:
3351 // end-sanitize-vr4320
3352 *vr5000:
3353 // start-sanitize-cygnus
3354 *vr5400:
3355 // end-sanitize-cygnus
3356 // start-sanitize-r5900
3357 *r5900:
3358 // end-sanitize-r5900
3359 {
3360   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3361 }
3362
3363
3364 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3365 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3366 *mipsI,mipsII,mipsIII,mipsIV:
3367 *vr5000:
3368 // start-sanitize-vr4320
3369 *vr4320:
3370 // end-sanitize-vr4320
3371 // start-sanitize-cygnus
3372 *vr5400:
3373 // end-sanitize-cygnus
3374 *r3900:
3375 // start-sanitize-tx19
3376 *tx19:
3377 // end-sanitize-tx19
3378 {
3379   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3380 }
3381
3382
3383
3384 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3385 {
3386   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3387   address_word reverseendian = (ReverseEndian ? -1 : 0);
3388   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3389   unsigned int byte;
3390   unsigned int word;
3391   address_word paddr;
3392   int uncached;
3393   unsigned64 memval;
3394   address_word vaddr;
3395   int nr_lhs_bits;
3396   int nr_rhs_bits;
3397
3398   vaddr = base + offset;
3399   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3400   paddr = (paddr ^ (reverseendian & mask));
3401   if (BigEndianMem == 0)
3402     paddr = paddr & ~access;
3403
3404   /* compute where within the word/mem we are */
3405   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3406   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3407   nr_lhs_bits = 8 * byte + 8;
3408   nr_rhs_bits = 8 * access - 8 * byte;
3409   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3410   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3411            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3412            (long) ((unsigned64) paddr >> 32), (long) paddr,
3413            word, byte, nr_lhs_bits, nr_rhs_bits); */
3414
3415   if (word == 0)
3416     {
3417       memval = (rt >> nr_rhs_bits);
3418     }
3419   else
3420     {
3421       memval = (rt << nr_lhs_bits);
3422     }
3423   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3424            (long) ((unsigned64) rt >> 32), (long) rt,
3425            (long) ((unsigned64) memval >> 32), (long) memval); */
3426   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3427 }
3428
3429
3430 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3431 "swl r<RT>, <OFFSET>(r<BASE>)"
3432 *mipsI,mipsII,mipsIII,mipsIV:
3433 *vr5000:
3434 // start-sanitize-vr4320
3435 *vr4320:
3436 // end-sanitize-vr4320
3437 // start-sanitize-cygnus
3438 *vr5400:
3439 // end-sanitize-cygnus
3440 // start-sanitize-r5900
3441 *r5900:
3442 // end-sanitize-r5900
3443 *r3900:
3444 // start-sanitize-tx19
3445 *tx19:
3446 // end-sanitize-tx19
3447 {
3448   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3449 }
3450
3451
3452 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3453 {
3454   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3455   address_word reverseendian = (ReverseEndian ? -1 : 0);
3456   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3457   unsigned int byte;
3458   address_word paddr;
3459   int uncached;
3460   unsigned64 memval;
3461   address_word vaddr;
3462
3463   vaddr = base + offset;
3464   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3465   paddr = (paddr ^ (reverseendian & mask));
3466   if (BigEndianMem != 0)
3467     paddr &= ~access;
3468   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3469   memval = (rt << (byte * 8));
3470   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3471 }
3472
3473 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3474 "swr r<RT>, <OFFSET>(r<BASE>)"
3475 *mipsI,mipsII,mipsIII,mipsIV:
3476 *vr5000:
3477 // start-sanitize-vr4320
3478 *vr4320:
3479 // end-sanitize-vr4320
3480 // start-sanitize-cygnus
3481 *vr5400:
3482 // end-sanitize-cygnus
3483 // start-sanitize-r5900
3484 *r5900:
3485 // end-sanitize-r5900
3486 *r3900:
3487 // start-sanitize-tx19
3488 *tx19:
3489 // end-sanitize-tx19
3490 {
3491   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3492 }
3493
3494
3495 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3496 "sync":STYPE == 0
3497 "sync <STYPE>"
3498 *mipsII:
3499 *mipsIII:
3500 *mipsIV:
3501 *vr5000:
3502 // start-sanitize-vr4320
3503 *vr4320:
3504 // end-sanitize-vr4320
3505 // start-sanitize-cygnus
3506 *vr5400:
3507 // end-sanitize-cygnus
3508 // start-sanitize-r5900
3509 *r5900:
3510 // end-sanitize-r5900
3511 *r3900:
3512 // start-sanitize-tx19
3513 *tx19:
3514 // end-sanitize-tx19
3515 {
3516   SyncOperation (STYPE);
3517 }
3518
3519
3520 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3521 "syscall <CODE>"
3522 *mipsI,mipsII,mipsIII,mipsIV:
3523 *vr5000:
3524 // start-sanitize-vr4320
3525 *vr4320:
3526 // end-sanitize-vr4320
3527 // start-sanitize-cygnus
3528 *vr5400:
3529 // end-sanitize-cygnus
3530 // start-sanitize-r5900
3531 *r5900:
3532 // end-sanitize-r5900
3533 *r3900:
3534 // start-sanitize-tx19
3535 *tx19:
3536 // end-sanitize-tx19
3537 {
3538   SignalException(SystemCall, instruction_0);
3539 }
3540
3541
3542 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3543 "teq r<RS>, r<RT>"
3544 *mipsII:
3545 *mipsIII:
3546 *mipsIV:
3547 *vr5000:
3548 // start-sanitize-vr4320
3549 *vr4320:
3550 // end-sanitize-vr4320
3551 // start-sanitize-cygnus
3552 *vr5400:
3553 // end-sanitize-cygnus
3554 // start-sanitize-r5900
3555 *r5900:
3556 // end-sanitize-r5900
3557 // start-sanitize-tx19
3558 *tx19:
3559 // end-sanitize-tx19
3560 {
3561   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3562     SignalException(Trap, instruction_0);
3563 }
3564
3565
3566 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3567 "teqi r<RS>, <IMMEDIATE>"
3568 *mipsII:
3569 *mipsIII:
3570 *mipsIV:
3571 *vr5000:
3572 // start-sanitize-vr4320
3573 *vr4320:
3574 // end-sanitize-vr4320
3575 // start-sanitize-cygnus
3576 *vr5400:
3577 // end-sanitize-cygnus
3578 // start-sanitize-r5900
3579 *r5900:
3580 // end-sanitize-r5900
3581 // start-sanitize-tx19
3582 *tx19:
3583 // end-sanitize-tx19
3584 {
3585   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3586     SignalException(Trap, instruction_0);
3587 }
3588
3589
3590 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3591 "tge r<RS>, r<RT>"
3592 *mipsII:
3593 *mipsIII:
3594 *mipsIV:
3595 *vr5000:
3596 // start-sanitize-vr4320
3597 *vr4320:
3598 // end-sanitize-vr4320
3599 // start-sanitize-cygnus
3600 *vr5400:
3601 // end-sanitize-cygnus
3602 // start-sanitize-r5900
3603 *r5900:
3604 // end-sanitize-r5900
3605 // start-sanitize-tx19
3606 *tx19:
3607 // end-sanitize-tx19
3608 {
3609   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3610     SignalException(Trap, instruction_0);
3611 }
3612
3613
3614 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3615 "tgei r<RS>, <IMMEDIATE>"
3616 *mipsII:
3617 *mipsIII:
3618 *mipsIV:
3619 *vr5000:
3620 // start-sanitize-vr4320
3621 *vr4320:
3622 // end-sanitize-vr4320
3623 // start-sanitize-cygnus
3624 *vr5400:
3625 // end-sanitize-cygnus
3626 // start-sanitize-r5900
3627 *r5900:
3628 // end-sanitize-r5900
3629 // start-sanitize-tx19
3630 *tx19:
3631 // end-sanitize-tx19
3632 {
3633   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3634     SignalException(Trap, instruction_0);
3635 }
3636
3637
3638 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3639 "tgeiu r<RS>, <IMMEDIATE>"
3640 *mipsII:
3641 *mipsIII:
3642 *mipsIV:
3643 *vr5000:
3644 // start-sanitize-vr4320
3645 *vr4320:
3646 // end-sanitize-vr4320
3647 // start-sanitize-cygnus
3648 *vr5400:
3649 // end-sanitize-cygnus
3650 // start-sanitize-r5900
3651 *r5900:
3652 // end-sanitize-r5900
3653 // start-sanitize-tx19
3654 *tx19:
3655 // end-sanitize-tx19
3656 {
3657   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3658     SignalException(Trap, instruction_0);
3659 }
3660
3661
3662 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3663 "tgeu r<RS>, r<RT>"
3664 *mipsII:
3665 *mipsIII:
3666 *mipsIV:
3667 *vr5000:
3668 // start-sanitize-vr4320
3669 *vr4320:
3670 // end-sanitize-vr4320
3671 // start-sanitize-cygnus
3672 *vr5400:
3673 // end-sanitize-cygnus
3674 // start-sanitize-r5900
3675 *r5900:
3676 // end-sanitize-r5900
3677 // start-sanitize-tx19
3678 *tx19:
3679 // end-sanitize-tx19
3680 {
3681   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3682     SignalException(Trap, instruction_0);
3683 }
3684
3685
3686 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3687 "tlt r<RS>, r<RT>"
3688 *mipsII:
3689 *mipsIII:
3690 *mipsIV:
3691 *vr5000:
3692 // start-sanitize-vr4320
3693 *vr4320:
3694 // end-sanitize-vr4320
3695 // start-sanitize-cygnus
3696 *vr5400:
3697 // end-sanitize-cygnus
3698 // start-sanitize-r5900
3699 *r5900:
3700 // end-sanitize-r5900
3701 // start-sanitize-tx19
3702 *tx19:
3703 // end-sanitize-tx19
3704 {
3705   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3706     SignalException(Trap, instruction_0);
3707 }
3708
3709
3710 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3711 "tlti r<RS>, <IMMEDIATE>"
3712 *mipsII:
3713 *mipsIII:
3714 *mipsIV:
3715 *vr5000:
3716 // start-sanitize-vr4320
3717 *vr4320:
3718 // end-sanitize-vr4320
3719 // start-sanitize-cygnus
3720 *vr5400:
3721 // end-sanitize-cygnus
3722 // start-sanitize-r5900
3723 *r5900:
3724 // end-sanitize-r5900
3725 // start-sanitize-tx19
3726 *tx19:
3727 // end-sanitize-tx19
3728 {
3729   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3730     SignalException(Trap, instruction_0);
3731 }
3732
3733
3734 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3735 "tltiu r<RS>, <IMMEDIATE>"
3736 *mipsII:
3737 *mipsIII:
3738 *mipsIV:
3739 *vr5000:
3740 // start-sanitize-vr4320
3741 *vr4320:
3742 // end-sanitize-vr4320
3743 // start-sanitize-cygnus
3744 *vr5400:
3745 // end-sanitize-cygnus
3746 // start-sanitize-r5900
3747 *r5900:
3748 // end-sanitize-r5900
3749 // start-sanitize-tx19
3750 *tx19:
3751 // end-sanitize-tx19
3752 {
3753   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3754     SignalException(Trap, instruction_0);
3755 }
3756
3757
3758 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3759 "tltu r<RS>, r<RT>"
3760 *mipsII:
3761 *mipsIII:
3762 *mipsIV:
3763 *vr5000:
3764 // start-sanitize-vr4320
3765 *vr4320:
3766 // end-sanitize-vr4320
3767 // start-sanitize-cygnus
3768 *vr5400:
3769 // end-sanitize-cygnus
3770 // start-sanitize-r5900
3771 *r5900:
3772 // end-sanitize-r5900
3773 // start-sanitize-tx19
3774 *tx19:
3775 // end-sanitize-tx19
3776 {
3777   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3778     SignalException(Trap, instruction_0);
3779 }
3780
3781
3782 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3783 "tne r<RS>, r<RT>"
3784 *mipsII:
3785 *mipsIII:
3786 *mipsIV:
3787 *vr5000:
3788 // start-sanitize-vr4320
3789 *vr4320:
3790 // end-sanitize-vr4320
3791 // start-sanitize-cygnus
3792 *vr5400:
3793 // end-sanitize-cygnus
3794 // start-sanitize-r5900
3795 *r5900:
3796 // end-sanitize-r5900
3797 // start-sanitize-tx19
3798 *tx19:
3799 // end-sanitize-tx19
3800 {
3801   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3802     SignalException(Trap, instruction_0);
3803 }
3804
3805
3806 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3807 "tne r<RS>, <IMMEDIATE>"
3808 *mipsII:
3809 *mipsIII:
3810 *mipsIV:
3811 *vr5000:
3812 // start-sanitize-vr4320
3813 *vr4320:
3814 // end-sanitize-vr4320
3815 // start-sanitize-cygnus
3816 *vr5400:
3817 // end-sanitize-cygnus
3818 // start-sanitize-r5900
3819 *r5900:
3820 // end-sanitize-r5900
3821 // start-sanitize-tx19
3822 *tx19:
3823 // end-sanitize-tx19
3824 {
3825   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3826     SignalException(Trap, instruction_0);
3827 }
3828
3829
3830 :function:::void:do_xor:int rs, int rt, int rd
3831 {
3832   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3833   GPR[rd] = GPR[rs] ^ GPR[rt];
3834   TRACE_ALU_RESULT (GPR[rd]);
3835 }
3836
3837 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3838 "xor r<RD>, r<RS>, r<RT>"
3839 *mipsI,mipsII,mipsIII,mipsIV:
3840 *vr5000:
3841 // start-sanitize-vr4320
3842 *vr4320:
3843 // end-sanitize-vr4320
3844 // start-sanitize-cygnus
3845 *vr5400:
3846 // end-sanitize-cygnus
3847 // start-sanitize-r5900
3848 *r5900:
3849 // end-sanitize-r5900
3850 *r3900:
3851 // start-sanitize-tx19
3852 *tx19:
3853 // end-sanitize-tx19
3854 {
3855   do_xor (SD_, RS, RT, RD);
3856 }
3857
3858
3859 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3860 {
3861   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3862   GPR[rt] = GPR[rs] ^ immediate;
3863   TRACE_ALU_RESULT (GPR[rt]);
3864 }
3865
3866 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3867 "xori r<RT>, r<RS>, <IMMEDIATE>"
3868 *mipsI,mipsII,mipsIII,mipsIV:
3869 *vr5000:
3870 // start-sanitize-vr4320
3871 *vr4320:
3872 // end-sanitize-vr4320
3873 // start-sanitize-cygnus
3874 *vr5400:
3875 // end-sanitize-cygnus
3876 // start-sanitize-r5900
3877 *r5900:
3878 // end-sanitize-r5900
3879 *r3900:
3880 // start-sanitize-tx19
3881 *tx19:
3882 // end-sanitize-tx19
3883 {
3884   do_xori (SD_, RS, RT, IMMEDIATE);
3885 }
3886
3887 \f
3888 //
3889 // MIPS Architecture:
3890 //
3891 //        FPU Instruction Set (COP1 & COP1X)
3892 //
3893
3894
3895 :%s::::FMT:int fmt
3896 {
3897   switch (fmt)
3898     {
3899     case fmt_single: return "s";
3900     case fmt_double: return "d";
3901     case fmt_word: return "w";
3902     case fmt_long: return "l";
3903     default: return "?";
3904     }
3905 }
3906
3907 :%s::::X:int x
3908 {
3909   switch (x)
3910     {
3911     case 0: return "f";
3912     case 1: return "t";
3913     default: return "?";
3914     }
3915 }
3916
3917 :%s::::TF:int tf
3918 {
3919   if (tf)
3920     return "t";
3921   else
3922     return "f";
3923 }
3924
3925 :%s::::ND:int nd
3926 {
3927   if (nd)
3928     return "l";
3929   else
3930     return "";
3931 }
3932
3933 :%s::::COND:int cond
3934 {
3935   switch (cond)
3936     {
3937     case 00: return "f";
3938     case 01: return "un";
3939     case 02: return "eq";
3940     case 03: return "ueq";
3941     case 04: return "olt";
3942     case 05: return "ult";
3943     case 06: return "ole";
3944     case 07: return "ule";
3945     case 010: return "sf";
3946     case 011: return "ngle";
3947     case 012: return "seq";
3948     case 013: return "ngl";
3949     case 014: return "lt";
3950     case 015: return "nge";
3951     case 016: return "le";
3952     case 017: return "ngt";
3953     default: return "?";
3954     }
3955 }
3956
3957
3958 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3959 "abs.%s<FMT> f<FD>, f<FS>"
3960 *mipsI,mipsII,mipsIII,mipsIV:
3961 *vr5000:
3962 // start-sanitize-vr4320
3963 *vr4320:
3964 // end-sanitize-vr4320
3965 // start-sanitize-cygnus
3966 *vr5400:
3967 // end-sanitize-cygnus
3968 *r3900:
3969 // start-sanitize-tx19
3970 *tx19:
3971 // end-sanitize-tx19
3972 {
3973   unsigned32 instruction = instruction_0;
3974   int destreg = ((instruction >> 6) & 0x0000001F);
3975   int fs = ((instruction >> 11) & 0x0000001F);
3976   int format = ((instruction >> 21) & 0x00000007);
3977   {
3978     if ((format != fmt_single) && (format != fmt_double))
3979       SignalException(ReservedInstruction,instruction);
3980     else
3981       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3982   }
3983 }
3984
3985
3986
3987 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3988 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3989 *mipsI,mipsII,mipsIII,mipsIV:
3990 *vr5000:
3991 // start-sanitize-vr4320
3992 *vr4320:
3993 // end-sanitize-vr4320
3994 // start-sanitize-cygnus
3995 *vr5400:
3996 // end-sanitize-cygnus
3997 *r3900:
3998 // start-sanitize-tx19
3999 *tx19:
4000 // end-sanitize-tx19
4001 {
4002   unsigned32 instruction = instruction_0;
4003   int destreg = ((instruction >> 6) & 0x0000001F);
4004   int fs = ((instruction >> 11) & 0x0000001F);
4005   int ft = ((instruction >> 16) & 0x0000001F);
4006   int format = ((instruction >> 21) & 0x00000007);
4007   {
4008     if ((format != fmt_single) && (format != fmt_double))
4009       SignalException(ReservedInstruction, instruction);
4010     else
4011       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4012   }
4013 }
4014
4015
4016
4017 // BC1F
4018 // BC1FL
4019 // BC1T
4020 // BC1TL
4021
4022 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4023 "bc1%s<TF>%s<ND> <OFFSET>"
4024 *mipsI,mipsII,mipsIII:
4025 // start-sanitize-r5900
4026 *r5900:
4027 // end-sanitize-r5900
4028 {
4029   check_branch_bug ();
4030   TRACE_BRANCH_INPUT (PREVCOC1());
4031   if (PREVCOC1() == TF)
4032     {
4033       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4034       TRACE_BRANCH_RESULT (dest);
4035       mark_branch_bug (dest);
4036       DELAY_SLOT (dest);
4037     }
4038   else if (ND)
4039     {
4040       TRACE_BRANCH_RESULT (0);
4041       NULLIFY_NEXT_INSTRUCTION ();
4042     }
4043   else
4044     {
4045       TRACE_BRANCH_RESULT (NIA);
4046     }
4047 }
4048
4049 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4050 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4051 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4052 *mipsIV:
4053 *vr5000:
4054 // start-sanitize-vr4320
4055 *vr4320:
4056 // end-sanitize-vr4320
4057 // start-sanitize-cygnus
4058 *vr5400:
4059 // end-sanitize-cygnus
4060 *r3900:
4061 // start-sanitize-tx19
4062 *tx19:
4063 // end-sanitize-tx19
4064 {
4065   check_branch_bug ();
4066   if (GETFCC(CC) == TF)
4067     {
4068       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4069       mark_branch_bug (dest);
4070       DELAY_SLOT (dest);
4071     }
4072   else if (ND)
4073     {
4074       NULLIFY_NEXT_INSTRUCTION ();
4075     }
4076 }
4077
4078
4079
4080
4081
4082
4083 // C.EQ.S
4084 // C.EQ.D
4085 // ...
4086
4087 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4088 {
4089   if ((fmt != fmt_single) && (fmt != fmt_double))
4090     SignalException (ReservedInstruction, insn);
4091   else
4092     {
4093       int less;
4094       int equal;
4095       int unordered;
4096       int condition;
4097       unsigned64 ofs = ValueFPR (fs, fmt);
4098       unsigned64 oft = ValueFPR (ft, fmt);
4099       if (NaN (ofs, fmt) || NaN (oft, fmt))
4100         {
4101           if (FCSR & FP_ENABLE (IO))
4102             {
4103               FCSR |= FP_CAUSE (IO);
4104               SignalExceptionFPE ();
4105             }
4106           less = 0;
4107           equal = 0;
4108           unordered = 1;
4109         }
4110       else
4111         {
4112           less = Less (ofs, oft, fmt);
4113           equal = Equal (ofs, oft, fmt);
4114           unordered = 0;
4115         }
4116       condition = (((cond & (1 << 2)) && less)
4117                    || ((cond & (1 << 1)) && equal)
4118                    || ((cond & (1 << 0)) && unordered));
4119       SETFCC (cc, condition);
4120     }
4121 }
4122
4123 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4124 *mipsI,mipsII,mipsIII:
4125 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4126 {
4127   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4128 }
4129
4130 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4131 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4132 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4133 *mipsIV:
4134 *vr5000:
4135 // start-sanitize-vr4320
4136 *vr4320:
4137 // end-sanitize-vr4320
4138 // start-sanitize-cygnus
4139 *vr5400:
4140 // end-sanitize-cygnus
4141 *r3900:
4142 // start-sanitize-tx19
4143 *tx19:
4144 // end-sanitize-tx19
4145 {
4146   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4147 }
4148
4149
4150 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4151 "ceil.l.%s<FMT> f<FD>, f<FS>"
4152 *mipsIII:
4153 *mipsIV:
4154 *vr5000:
4155 // start-sanitize-vr4320
4156 *vr4320:
4157 // end-sanitize-vr4320
4158 // start-sanitize-cygnus
4159 *vr5400:
4160 // end-sanitize-cygnus
4161 // start-sanitize-r5900
4162 *r5900:
4163 // end-sanitize-r5900
4164 *r3900:
4165 // start-sanitize-tx19
4166 *tx19:
4167 // end-sanitize-tx19
4168 {
4169   unsigned32 instruction = instruction_0;
4170   int destreg = ((instruction >> 6) & 0x0000001F);
4171   int fs = ((instruction >> 11) & 0x0000001F);
4172   int format = ((instruction >> 21) & 0x00000007);
4173   {
4174     if ((format != fmt_single) && (format != fmt_double))
4175       SignalException(ReservedInstruction,instruction);
4176     else
4177       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4178   }
4179 }
4180
4181
4182 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4183 *mipsII:
4184 *mipsIII:
4185 *mipsIV:
4186 *vr5000:
4187 // start-sanitize-vr4320
4188 *vr4320:
4189 // end-sanitize-vr4320
4190 // start-sanitize-cygnus
4191 *vr5400:
4192 // end-sanitize-cygnus
4193 // start-sanitize-r5900
4194 *r5900:
4195 // end-sanitize-r5900
4196 *r3900:
4197 // start-sanitize-tx19
4198 *tx19:
4199 // end-sanitize-tx19
4200 {
4201   unsigned32 instruction = instruction_0;
4202   int destreg = ((instruction >> 6) & 0x0000001F);
4203   int fs = ((instruction >> 11) & 0x0000001F);
4204   int format = ((instruction >> 21) & 0x00000007);
4205   {
4206   if ((format != fmt_single) && (format != fmt_double))
4207    SignalException(ReservedInstruction,instruction);
4208   else
4209    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4210   }
4211 }
4212
4213
4214 // CFC1
4215 // CTC1
4216 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4217 "c%s<X>c1 r<RT>, f<FS>"
4218 *mipsI:
4219 *mipsII:
4220 *mipsIII:
4221 {
4222   if (X)
4223     {
4224       if (FS == 0)
4225         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4226       else if (FS == 31)
4227         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4228       /* else NOP */
4229       PENDING_FILL(COCIDX,0); /* special case */
4230     }
4231   else
4232     { /* control from */
4233       if (FS == 0)
4234         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4235       else if (FS == 31)
4236         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4237       /* else NOP */
4238     }
4239 }
4240 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4241 "c%s<X>c1 r<RT>, f<FS>"
4242 *mipsIV:
4243 *vr5000:
4244 // start-sanitize-vr4320
4245 *vr4320:
4246 // end-sanitize-vr4320
4247 // start-sanitize-cygnus
4248 *vr5400:
4249 // end-sanitize-cygnus
4250 *r3900:
4251 // start-sanitize-tx19
4252 *tx19:
4253 // end-sanitize-tx19
4254 {
4255   if (X)
4256     {
4257       /* control to */
4258       TRACE_ALU_INPUT1 (GPR[RT]);
4259       if (FS == 0)
4260         {
4261           FCR0 = VL4_8(GPR[RT]);
4262           TRACE_ALU_RESULT (FCR0);
4263         }
4264       else if (FS == 31)
4265         {
4266           FCR31 = VL4_8(GPR[RT]);
4267           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4268           TRACE_ALU_RESULT (FCR31);
4269         }
4270       else
4271         {
4272           TRACE_ALU_RESULT0 ();
4273         }
4274       /* else NOP */
4275     }
4276   else
4277     { /* control from */
4278       if (FS == 0)
4279         {
4280           TRACE_ALU_INPUT1 (FCR0);
4281           GPR[RT] = SIGNEXTEND (FCR0, 32);
4282         }
4283       else if (FS == 31)
4284         {
4285           TRACE_ALU_INPUT1 (FCR31);
4286           GPR[RT] = SIGNEXTEND (FCR31, 32);
4287         }
4288       TRACE_ALU_RESULT (GPR[RT]);
4289       /* else NOP */
4290     }
4291 }
4292
4293
4294 //
4295 // FIXME: Does not correctly differentiate between mips*
4296 //
4297 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4298 "cvt.d.%s<FMT> f<FD>, f<FS>"
4299 *mipsI,mipsII,mipsIII,mipsIV:
4300 *vr5000:
4301 // start-sanitize-vr4320
4302 *vr4320:
4303 // end-sanitize-vr4320
4304 // start-sanitize-cygnus
4305 *vr5400:
4306 // end-sanitize-cygnus
4307 *r3900:
4308 // start-sanitize-tx19
4309 *tx19:
4310 // end-sanitize-tx19
4311 {
4312   unsigned32 instruction = instruction_0;
4313   int destreg = ((instruction >> 6) & 0x0000001F);
4314   int fs = ((instruction >> 11) & 0x0000001F);
4315   int format = ((instruction >> 21) & 0x00000007);
4316   {
4317     if ((format == fmt_double) | 0)
4318       SignalException(ReservedInstruction,instruction);
4319     else
4320       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4321   }
4322 }
4323
4324
4325 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4326 "cvt.l.%s<FMT> f<FD>, f<FS>"
4327 *mipsIII:
4328 *mipsIV:
4329 *vr5000:
4330 // start-sanitize-vr4320
4331 *vr4320:
4332 // end-sanitize-vr4320
4333 // start-sanitize-cygnus
4334 *vr5400:
4335 // end-sanitize-cygnus
4336 *r3900:
4337 // start-sanitize-tx19
4338 *tx19:
4339 // end-sanitize-tx19
4340 {
4341   unsigned32 instruction = instruction_0;
4342   int destreg = ((instruction >> 6) & 0x0000001F);
4343   int fs = ((instruction >> 11) & 0x0000001F);
4344   int format = ((instruction >> 21) & 0x00000007);
4345   {
4346     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4347       SignalException(ReservedInstruction,instruction);
4348     else
4349       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4350   }
4351 }
4352
4353
4354 //
4355 // FIXME: Does not correctly differentiate between mips*
4356 //
4357 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4358 "cvt.s.%s<FMT> f<FD>, f<FS>"
4359 *mipsI,mipsII,mipsIII,mipsIV:
4360 *vr5000:
4361 // start-sanitize-vr4320
4362 *vr4320:
4363 // end-sanitize-vr4320
4364 // start-sanitize-cygnus
4365 *vr5400:
4366 // end-sanitize-cygnus
4367 *r3900:
4368 // start-sanitize-tx19
4369 *tx19:
4370 // end-sanitize-tx19
4371 {
4372   unsigned32 instruction = instruction_0;
4373   int destreg = ((instruction >> 6) & 0x0000001F);
4374   int fs = ((instruction >> 11) & 0x0000001F);
4375   int format = ((instruction >> 21) & 0x00000007);
4376   {
4377     if ((format == fmt_single) | 0)
4378       SignalException(ReservedInstruction,instruction);
4379     else
4380       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4381   }
4382 }
4383
4384
4385 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4386 "cvt.w.%s<FMT> f<FD>, f<FS>"
4387 *mipsI,mipsII,mipsIII,mipsIV:
4388 *vr5000:
4389 // start-sanitize-vr4320
4390 *vr4320:
4391 // end-sanitize-vr4320
4392 // start-sanitize-cygnus
4393 *vr5400:
4394 // end-sanitize-cygnus
4395 *r3900:
4396 // start-sanitize-tx19
4397 *tx19:
4398 // end-sanitize-tx19
4399 {
4400   unsigned32 instruction = instruction_0;
4401   int destreg = ((instruction >> 6) & 0x0000001F);
4402   int fs = ((instruction >> 11) & 0x0000001F);
4403   int format = ((instruction >> 21) & 0x00000007);
4404   {
4405     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4406       SignalException(ReservedInstruction,instruction);
4407     else
4408       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4409   }
4410 }
4411
4412
4413 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4414 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4415 *mipsI,mipsII,mipsIII,mipsIV:
4416 *vr5000:
4417 // start-sanitize-vr4320
4418 *vr4320:
4419 // end-sanitize-vr4320
4420 // start-sanitize-cygnus
4421 *vr5400:
4422 // end-sanitize-cygnus
4423 *r3900:
4424 // start-sanitize-tx19
4425 *tx19:
4426 // end-sanitize-tx19
4427 {
4428   unsigned32 instruction = instruction_0;
4429   int destreg = ((instruction >> 6) & 0x0000001F);
4430   int fs = ((instruction >> 11) & 0x0000001F);
4431   int ft = ((instruction >> 16) & 0x0000001F);
4432   int format = ((instruction >> 21) & 0x00000007);
4433   {
4434     if ((format != fmt_single) && (format != fmt_double))
4435       SignalException(ReservedInstruction,instruction);
4436     else
4437       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4438   }
4439 }
4440
4441
4442 // DMFC1
4443 // DMTC1
4444 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4445 "dm%s<X>c1 r<RT>, f<FS>"
4446 *mipsIII:
4447 {
4448   if (X)
4449     {
4450       if (SizeFGR() == 64)
4451         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4452       else if ((FS & 0x1) == 0)
4453         {
4454           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4455           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4456         }
4457     }
4458   else
4459     {
4460       if (SizeFGR() == 64)
4461         PENDING_FILL(RT,FGR[FS]);
4462       else if ((FS & 0x1) == 0)
4463         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4464       else
4465         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4466     }
4467 }
4468 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4469 "dm%s<X>c1 r<RT>, f<FS>"
4470 *mipsIV:
4471 *vr5000:
4472 // start-sanitize-vr4320
4473 *vr4320:
4474 // end-sanitize-vr4320
4475 // start-sanitize-cygnus
4476 *vr5400:
4477 // end-sanitize-cygnus
4478 // start-sanitize-r5900
4479 *r5900:
4480 // end-sanitize-r5900
4481 *r3900:
4482 // start-sanitize-tx19
4483 *tx19:
4484 // end-sanitize-tx19
4485 {
4486   if (X)
4487     {
4488       if (SizeFGR() == 64)
4489         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4490       else if ((FS & 0x1) == 0)
4491         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4492     }
4493   else
4494     {
4495       if (SizeFGR() == 64)
4496         GPR[RT] = FGR[FS];
4497       else if ((FS & 0x1) == 0)
4498         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4499       else
4500         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4501     }
4502 }
4503
4504
4505 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4506 "floor.l.%s<FMT> f<FD>, f<FS>"
4507 *mipsIII:
4508 *mipsIV:
4509 *vr5000:
4510 // start-sanitize-vr4320
4511 *vr4320:
4512 // end-sanitize-vr4320
4513 // start-sanitize-cygnus
4514 *vr5400:
4515 // end-sanitize-cygnus
4516 // start-sanitize-r5900
4517 *r5900:
4518 // end-sanitize-r5900
4519 *r3900:
4520 // start-sanitize-tx19
4521 *tx19:
4522 // end-sanitize-tx19
4523 {
4524   unsigned32 instruction = instruction_0;
4525   int destreg = ((instruction >> 6) & 0x0000001F);
4526   int fs = ((instruction >> 11) & 0x0000001F);
4527   int format = ((instruction >> 21) & 0x00000007);
4528   {
4529     if ((format != fmt_single) && (format != fmt_double))
4530       SignalException(ReservedInstruction,instruction);
4531     else
4532       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4533   }
4534 }
4535
4536
4537 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4538 "floor.w.%s<FMT> f<FD>, f<FS>"
4539 *mipsII:
4540 *mipsIII:
4541 *mipsIV:
4542 *vr5000:
4543 // start-sanitize-vr4320
4544 *vr4320:
4545 // end-sanitize-vr4320
4546 // start-sanitize-cygnus
4547 *vr5400:
4548 // end-sanitize-cygnus
4549 // start-sanitize-r5900
4550 *r5900:
4551 // end-sanitize-r5900
4552 *r3900:
4553 // start-sanitize-tx19
4554 *tx19:
4555 // end-sanitize-tx19
4556 {
4557   unsigned32 instruction = instruction_0;
4558   int destreg = ((instruction >> 6) & 0x0000001F);
4559   int fs = ((instruction >> 11) & 0x0000001F);
4560   int format = ((instruction >> 21) & 0x00000007);
4561   {
4562     if ((format != fmt_single) && (format != fmt_double))
4563       SignalException(ReservedInstruction,instruction);
4564     else
4565       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4566   }
4567 }
4568
4569
4570 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4571 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4572 *mipsII:
4573 *mipsIII:
4574 *mipsIV:
4575 *vr5000:
4576 // start-sanitize-vr4320
4577 *vr4320:
4578 // end-sanitize-vr4320
4579 // start-sanitize-cygnus
4580 *vr5400:
4581 // end-sanitize-cygnus
4582 *r3900:
4583 // start-sanitize-tx19
4584 *tx19:
4585 // end-sanitize-tx19
4586 {
4587   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4588 }
4589
4590
4591 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4592 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4593 *mipsIV:
4594 *vr5000:
4595 // start-sanitize-vr4320
4596 *vr4320:
4597 // end-sanitize-vr4320
4598 // start-sanitize-cygnus
4599 *vr5400:
4600 // end-sanitize-cygnus
4601 {
4602   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4603 }
4604
4605
4606
4607 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4608 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4609 *mipsI,mipsII,mipsIII,mipsIV:
4610 *vr5000:
4611 // start-sanitize-vr4320
4612 *vr4320:
4613 // end-sanitize-vr4320
4614 // start-sanitize-cygnus
4615 *vr5400:
4616 // end-sanitize-cygnus
4617 // start-sanitize-r5900
4618 *r5900:
4619 // end-sanitize-r5900
4620 *r3900:
4621 // start-sanitize-tx19
4622 *tx19:
4623 // end-sanitize-tx19
4624 {
4625   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4626 }
4627
4628
4629 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4630 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4631 *mipsIV:
4632 *vr5000:
4633 // start-sanitize-vr4320
4634 *vr4320:
4635 // end-sanitize-vr4320
4636 // start-sanitize-cygnus
4637 *vr5400:
4638 // end-sanitize-cygnus
4639 {
4640   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4641 }
4642
4643
4644
4645 //
4646 // FIXME: Not correct for mips*
4647 //
4648 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4649 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4650 *mipsIV:
4651 *vr5000:
4652 // start-sanitize-vr4320
4653 *vr4320:
4654 // end-sanitize-vr4320
4655 // start-sanitize-cygnus
4656 *vr5400:
4657 // end-sanitize-cygnus
4658 {
4659   unsigned32 instruction = instruction_0;
4660   int destreg = ((instruction >> 6) & 0x0000001F);
4661   int fs = ((instruction >> 11) & 0x0000001F);
4662   int ft = ((instruction >> 16) & 0x0000001F);
4663   int fr = ((instruction >> 21) & 0x0000001F);
4664   {
4665     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4666   }
4667 }
4668
4669
4670 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4671 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4672 *mipsIV:
4673 *vr5000:
4674 // start-sanitize-vr4320
4675 *vr4320:
4676 // end-sanitize-vr4320
4677 // start-sanitize-cygnus
4678 *vr5400:
4679 // end-sanitize-cygnus
4680 {
4681   unsigned32 instruction = instruction_0;
4682   int destreg = ((instruction >> 6) & 0x0000001F);
4683   int fs = ((instruction >> 11) & 0x0000001F);
4684   int ft = ((instruction >> 16) & 0x0000001F);
4685   int fr = ((instruction >> 21) & 0x0000001F);
4686   {
4687     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4688   }
4689 }
4690
4691
4692 // MFC1
4693 // MTC1
4694 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4695 "m%s<X>c1 r<RT>, f<FS>"
4696 *mipsI:
4697 *mipsII:
4698 *mipsIII:
4699 {
4700   if (X)
4701     { /*MTC1*/
4702       if (SizeFGR() == 64)
4703         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4704       else
4705         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4706     }
4707   else /*MFC1*/
4708     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4709 }
4710 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4711 "m%s<X>c1 r<RT>, f<FS>"
4712 *mipsIV:
4713 *vr5000:
4714 // start-sanitize-vr4320
4715 *vr4320:
4716 // end-sanitize-vr4320
4717 // start-sanitize-cygnus
4718 *vr5400:
4719 // end-sanitize-cygnus
4720 *r3900:
4721 // start-sanitize-tx19
4722 *tx19:
4723 // end-sanitize-tx19
4724 {
4725   if (X)
4726     /*MTC1*/
4727     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4728   else /*MFC1*/
4729     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4730 }
4731
4732
4733 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4734 "mov.%s<FMT> f<FD>, f<FS>"
4735 *mipsI,mipsII,mipsIII,mipsIV:
4736 *vr5000:
4737 // start-sanitize-vr4320
4738 *vr4320:
4739 // end-sanitize-vr4320
4740 // start-sanitize-cygnus
4741 *vr5400:
4742 // end-sanitize-cygnus
4743 *r3900:
4744 // start-sanitize-tx19
4745 *tx19:
4746 // end-sanitize-tx19
4747 {
4748   unsigned32 instruction = instruction_0;
4749   int destreg = ((instruction >> 6) & 0x0000001F);
4750   int fs = ((instruction >> 11) & 0x0000001F);
4751   int format = ((instruction >> 21) & 0x00000007);
4752   {
4753     StoreFPR(destreg,format,ValueFPR(fs,format));
4754   }
4755 }
4756
4757
4758 // MOVF
4759 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4760 "mov%s<TF> r<RD>, r<RS>, <CC>"
4761 *mipsIV:
4762 *vr5000:
4763 // start-sanitize-vr4320
4764 *vr4320:
4765 // end-sanitize-vr4320
4766 // start-sanitize-cygnus
4767 *vr5400:
4768 // end-sanitize-cygnus
4769 // start-sanitize-r5900
4770 *r5900:
4771 // end-sanitize-r5900
4772 {
4773   if (GETFCC(CC) == TF)
4774     GPR[RD] = GPR[RS];
4775 }
4776
4777
4778 // MOVF.fmt
4779 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4780 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4781 *mipsIV:
4782 *vr5000:
4783 // start-sanitize-vr4320
4784 *vr4320:
4785 // end-sanitize-vr4320
4786 // start-sanitize-cygnus
4787 *vr5400:
4788 // end-sanitize-cygnus
4789 // start-sanitize-r5900
4790 *r5900:
4791 // end-sanitize-r5900
4792 {
4793   unsigned32 instruction = instruction_0;
4794   int format = ((instruction >> 21) & 0x00000007);
4795   {
4796    if (GETFCC(CC) == TF)
4797      StoreFPR (FD, format, ValueFPR (FS, format));
4798    else
4799      StoreFPR (FD, format, ValueFPR (FD, format));
4800   }
4801 }
4802
4803
4804 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4805 *mipsIV:
4806 *vr5000:
4807 // start-sanitize-vr4320
4808 *vr4320:
4809 // end-sanitize-vr4320
4810 // start-sanitize-cygnus
4811 *vr5400:
4812 // end-sanitize-cygnus
4813 // start-sanitize-r5900
4814 *r5900:
4815 // end-sanitize-r5900
4816 {
4817   unsigned32 instruction = instruction_0;
4818   int destreg = ((instruction >> 6) & 0x0000001F);
4819   int fs = ((instruction >> 11) & 0x0000001F);
4820   int format = ((instruction >> 21) & 0x00000007);
4821   {
4822     StoreFPR(destreg,format,ValueFPR(fs,format));
4823   }
4824 }
4825
4826
4827 // MOVT see MOVtf
4828
4829
4830 // MOVT.fmt see MOVtf.fmt
4831
4832
4833
4834 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4835 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4836 *mipsIV:
4837 *vr5000:
4838 // start-sanitize-vr4320
4839 *vr4320:
4840 // end-sanitize-vr4320
4841 // start-sanitize-cygnus
4842 *vr5400:
4843 // end-sanitize-cygnus
4844 // start-sanitize-r5900
4845 *r5900:
4846 // end-sanitize-r5900
4847 {
4848   unsigned32 instruction = instruction_0;
4849   int destreg = ((instruction >> 6) & 0x0000001F);
4850   int fs = ((instruction >> 11) & 0x0000001F);
4851   int format = ((instruction >> 21) & 0x00000007);
4852   {
4853    StoreFPR(destreg,format,ValueFPR(fs,format));
4854   }
4855 }
4856
4857
4858 // MSUB.fmt
4859 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4860 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4861 *mipsIV:
4862 *vr5000:
4863 // start-sanitize-vr4320
4864 *vr4320:
4865 // end-sanitize-vr4320
4866 // start-sanitize-cygnus
4867 *vr5400:
4868 // end-sanitize-cygnus
4869 // start-sanitize-r5900
4870 *r5900:
4871 // end-sanitize-r5900
4872 {
4873   unsigned32 instruction = instruction_0;
4874   int destreg = ((instruction >> 6) & 0x0000001F);
4875   int fs = ((instruction >> 11) & 0x0000001F);
4876   int ft = ((instruction >> 16) & 0x0000001F);
4877   int fr = ((instruction >> 21) & 0x0000001F);
4878   {
4879     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4880   }
4881 }
4882
4883
4884 // MSUB.fmt
4885 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4886 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4887 *mipsIV:
4888 *vr5000:
4889 // start-sanitize-vr4320
4890 *vr4320:
4891 // end-sanitize-vr4320
4892 // start-sanitize-cygnus
4893 *vr5400:
4894 // end-sanitize-cygnus
4895 // start-sanitize-r5900
4896 *r5900:
4897 // end-sanitize-r5900
4898 {
4899   unsigned32 instruction = instruction_0;
4900   int destreg = ((instruction >> 6) & 0x0000001F);
4901   int fs = ((instruction >> 11) & 0x0000001F);
4902   int ft = ((instruction >> 16) & 0x0000001F);
4903   int fr = ((instruction >> 21) & 0x0000001F);
4904   {
4905    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4906   }
4907 }
4908
4909
4910 // MTC1 see MxC1
4911
4912
4913 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4914 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4915 *mipsI,mipsII,mipsIII,mipsIV:
4916 *vr5000:
4917 // start-sanitize-vr4320
4918 *vr4320:
4919 // end-sanitize-vr4320
4920 // start-sanitize-cygnus
4921 *vr5400:
4922 // end-sanitize-cygnus
4923 *r3900:
4924 // start-sanitize-tx19
4925 *tx19:
4926 // end-sanitize-tx19
4927 {
4928   unsigned32 instruction = instruction_0;
4929   int destreg = ((instruction >> 6) & 0x0000001F);
4930   int fs = ((instruction >> 11) & 0x0000001F);
4931   int ft = ((instruction >> 16) & 0x0000001F);
4932   int format = ((instruction >> 21) & 0x00000007);
4933   {
4934     if ((format != fmt_single) && (format != fmt_double))
4935       SignalException(ReservedInstruction,instruction);
4936     else
4937       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4938   }
4939 }
4940
4941
4942 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4943 "neg.%s<FMT> f<FD>, f<FS>"
4944 *mipsI,mipsII,mipsIII,mipsIV:
4945 *vr5000:
4946 // start-sanitize-vr4320
4947 *vr4320:
4948 // end-sanitize-vr4320
4949 // start-sanitize-cygnus
4950 *vr5400:
4951 // end-sanitize-cygnus
4952 *r3900:
4953 // start-sanitize-tx19
4954 *tx19:
4955 // end-sanitize-tx19
4956 {
4957   unsigned32 instruction = instruction_0;
4958   int destreg = ((instruction >> 6) & 0x0000001F);
4959   int fs = ((instruction >> 11) & 0x0000001F);
4960   int format = ((instruction >> 21) & 0x00000007);
4961   {
4962     if ((format != fmt_single) && (format != fmt_double))
4963       SignalException(ReservedInstruction,instruction);
4964     else
4965       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4966   }
4967 }
4968
4969
4970 // NMADD.fmt
4971 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4972 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4973 *mipsIV:
4974 *vr5000:
4975 // start-sanitize-vr4320
4976 *vr4320:
4977 // end-sanitize-vr4320
4978 // start-sanitize-cygnus
4979 *vr5400:
4980 // end-sanitize-cygnus
4981 {
4982   unsigned32 instruction = instruction_0;
4983   int destreg = ((instruction >> 6) & 0x0000001F);
4984   int fs = ((instruction >> 11) & 0x0000001F);
4985   int ft = ((instruction >> 16) & 0x0000001F);
4986   int fr = ((instruction >> 21) & 0x0000001F);
4987   {
4988    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4989   }
4990 }
4991
4992
4993 // NMADD.fmt
4994 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4995 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4996 *mipsIV:
4997 *vr5000:
4998 // start-sanitize-vr4320
4999 *vr4320:
5000 // end-sanitize-vr4320
5001 // start-sanitize-cygnus
5002 *vr5400:
5003 // end-sanitize-cygnus
5004 {
5005   unsigned32 instruction = instruction_0;
5006   int destreg = ((instruction >> 6) & 0x0000001F);
5007   int fs = ((instruction >> 11) & 0x0000001F);
5008   int ft = ((instruction >> 16) & 0x0000001F);
5009   int fr = ((instruction >> 21) & 0x0000001F);
5010   {
5011    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5012   }
5013 }
5014
5015
5016 // NMSUB.fmt
5017 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5018 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5019 *mipsIV:
5020 *vr5000:
5021 // start-sanitize-vr4320
5022 *vr4320:
5023 // end-sanitize-vr4320
5024 // start-sanitize-cygnus
5025 *vr5400:
5026 // end-sanitize-cygnus
5027 {
5028   unsigned32 instruction = instruction_0;
5029   int destreg = ((instruction >> 6) & 0x0000001F);
5030   int fs = ((instruction >> 11) & 0x0000001F);
5031   int ft = ((instruction >> 16) & 0x0000001F);
5032   int fr = ((instruction >> 21) & 0x0000001F);
5033   {
5034    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5035   }
5036 }
5037
5038
5039 // NMSUB.fmt
5040 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5041 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5042 *mipsIV:
5043 *vr5000:
5044 // start-sanitize-vr4320
5045 *vr4320:
5046 // end-sanitize-vr4320
5047 // start-sanitize-cygnus
5048 *vr5400:
5049 // end-sanitize-cygnus
5050 {
5051   unsigned32 instruction = instruction_0;
5052   int destreg = ((instruction >> 6) & 0x0000001F);
5053   int fs = ((instruction >> 11) & 0x0000001F);
5054   int ft = ((instruction >> 16) & 0x0000001F);
5055   int fr = ((instruction >> 21) & 0x0000001F);
5056   {
5057     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5058   }
5059 }
5060
5061
5062 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5063 "prefx <HINT>, r<INDEX>(r<BASE>)"
5064 *mipsIV:
5065 *vr5000:
5066 // start-sanitize-vr4320
5067 *vr4320:
5068 // end-sanitize-vr4320
5069 // start-sanitize-cygnus
5070 *vr5400:
5071 // end-sanitize-cygnus
5072 {
5073   unsigned32 instruction = instruction_0;
5074   int fs = ((instruction >> 11) & 0x0000001F);
5075   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5076   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5077   {
5078     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5079     address_word paddr;
5080     int uncached;
5081     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5082       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5083   }
5084 }
5085
5086 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5087 *mipsIV:
5088 "recip.%s<FMT> f<FD>, f<FS>"
5089 *vr5000:
5090 // start-sanitize-vr4320
5091 *vr4320:
5092 // end-sanitize-vr4320
5093 // start-sanitize-cygnus
5094 *vr5400:
5095 // end-sanitize-cygnus
5096 {
5097   unsigned32 instruction = instruction_0;
5098   int destreg = ((instruction >> 6) & 0x0000001F);
5099   int fs = ((instruction >> 11) & 0x0000001F);
5100   int format = ((instruction >> 21) & 0x00000007);
5101   {
5102   if ((format != fmt_single) && (format != fmt_double))
5103    SignalException(ReservedInstruction,instruction);
5104   else
5105    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5106   }
5107 }
5108
5109
5110 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5111 "round.l.%s<FMT> f<FD>, f<FS>"
5112 *mipsIII:
5113 *mipsIV:
5114 *vr5000:
5115 // start-sanitize-vr4320
5116 *vr4320:
5117 // end-sanitize-vr4320
5118 // start-sanitize-cygnus
5119 *vr5400:
5120 // end-sanitize-cygnus
5121 // start-sanitize-r5900
5122 *r5900:
5123 // end-sanitize-r5900
5124 *r3900:
5125 // start-sanitize-tx19
5126 *tx19:
5127 // end-sanitize-tx19
5128 {
5129   unsigned32 instruction = instruction_0;
5130   int destreg = ((instruction >> 6) & 0x0000001F);
5131   int fs = ((instruction >> 11) & 0x0000001F);
5132   int format = ((instruction >> 21) & 0x00000007);
5133   {
5134     if ((format != fmt_single) && (format != fmt_double))
5135       SignalException(ReservedInstruction,instruction);
5136     else
5137       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5138   }
5139 }
5140
5141
5142 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5143 "round.w.%s<FMT> f<FD>, f<FS>"
5144 *mipsII:
5145 *mipsIII:
5146 *mipsIV:
5147 *vr5000:
5148 // start-sanitize-vr4320
5149 *vr4320:
5150 // end-sanitize-vr4320
5151 // start-sanitize-cygnus
5152 *vr5400:
5153 // end-sanitize-cygnus
5154 // start-sanitize-r5900
5155 *r5900:
5156 // end-sanitize-r5900
5157 *r3900:
5158 // start-sanitize-tx19
5159 *tx19:
5160 // end-sanitize-tx19
5161 {
5162   unsigned32 instruction = instruction_0;
5163   int destreg = ((instruction >> 6) & 0x0000001F);
5164   int fs = ((instruction >> 11) & 0x0000001F);
5165   int format = ((instruction >> 21) & 0x00000007);
5166   {
5167   if ((format != fmt_single) && (format != fmt_double))
5168    SignalException(ReservedInstruction,instruction);
5169   else
5170    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5171   }
5172 }
5173
5174
5175 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5176 *mipsIV:
5177 "rsqrt.%s<FMT> f<FD>, f<FS>"
5178 *vr5000:
5179 // start-sanitize-vr4320
5180 *vr4320:
5181 // end-sanitize-vr4320
5182 // start-sanitize-cygnus
5183 *vr5400:
5184 // end-sanitize-cygnus
5185 {
5186   unsigned32 instruction = instruction_0;
5187   int destreg = ((instruction >> 6) & 0x0000001F);
5188   int fs = ((instruction >> 11) & 0x0000001F);
5189   int format = ((instruction >> 21) & 0x00000007);
5190   {
5191   if ((format != fmt_single) && (format != fmt_double))
5192    SignalException(ReservedInstruction,instruction);
5193   else
5194    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5195   }
5196 }
5197
5198
5199 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5200 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5201 *mipsII:
5202 *mipsIII:
5203 *mipsIV:
5204 *vr5000:
5205 // start-sanitize-vr4320
5206 *vr4320:
5207 // end-sanitize-vr4320
5208 // start-sanitize-cygnus
5209 *vr5400:
5210 // end-sanitize-cygnus
5211 *r3900:
5212 // start-sanitize-tx19
5213 *tx19:
5214 // end-sanitize-tx19
5215 {
5216   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5217 }
5218
5219
5220 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5221 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5222 *mipsIV:
5223 *vr5000:
5224 // start-sanitize-vr4320
5225 *vr4320:
5226 // end-sanitize-vr4320
5227 // start-sanitize-cygnus
5228 *vr5400:
5229 // end-sanitize-cygnus
5230 {
5231   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5232 }
5233
5234
5235 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5236 "sqrt.%s<FMT> f<FD>, f<FS>"
5237 *mipsII:
5238 *mipsIII:
5239 *mipsIV:
5240 *vr5000:
5241 // start-sanitize-vr4320
5242 *vr4320:
5243 // end-sanitize-vr4320
5244 // start-sanitize-cygnus
5245 *vr5400:
5246 // end-sanitize-cygnus
5247 *r3900:
5248 // start-sanitize-tx19
5249 *tx19:
5250 // end-sanitize-tx19
5251 {
5252   unsigned32 instruction = instruction_0;
5253   int destreg = ((instruction >> 6) & 0x0000001F);
5254   int fs = ((instruction >> 11) & 0x0000001F);
5255   int format = ((instruction >> 21) & 0x00000007);
5256   {
5257     if ((format != fmt_single) && (format != fmt_double))
5258       SignalException(ReservedInstruction,instruction);
5259     else
5260       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5261   }
5262 }
5263
5264
5265 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5266 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5267 *mipsI,mipsII,mipsIII,mipsIV:
5268 *vr5000:
5269 // start-sanitize-vr4320
5270 *vr4320:
5271 // end-sanitize-vr4320
5272 // start-sanitize-cygnus
5273 *vr5400:
5274 // end-sanitize-cygnus
5275 *r3900:
5276 // start-sanitize-tx19
5277 *tx19:
5278 // end-sanitize-tx19
5279 {
5280   unsigned32 instruction = instruction_0;
5281   int destreg = ((instruction >> 6) & 0x0000001F);
5282   int fs = ((instruction >> 11) & 0x0000001F);
5283   int ft = ((instruction >> 16) & 0x0000001F);
5284   int format = ((instruction >> 21) & 0x00000007);
5285   {
5286     if ((format != fmt_single) && (format != fmt_double))
5287       SignalException(ReservedInstruction,instruction);
5288     else
5289       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5290   }
5291 }
5292
5293
5294
5295 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5296 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5297 *mipsI,mipsII,mipsIII,mipsIV:
5298 *vr5000:
5299 // start-sanitize-vr4320
5300 *vr4320:
5301 // end-sanitize-vr4320
5302 // start-sanitize-cygnus
5303 *vr5400:
5304 // end-sanitize-cygnus
5305 // start-sanitize-r5900
5306 *r5900:
5307 // end-sanitize-r5900
5308 *r3900:
5309 // start-sanitize-tx19
5310 *tx19:
5311 // end-sanitize-tx19
5312 {
5313   unsigned32 instruction = instruction_0;
5314   signed_word offset = EXTEND16 (OFFSET);
5315   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5316   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5317   {
5318     address_word vaddr = ((uword64)op1 + offset);
5319     address_word paddr;
5320     int uncached;
5321     if ((vaddr & 3) != 0)
5322       SignalExceptionAddressStore();
5323     else
5324       {
5325         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5326           {
5327             uword64 memval = 0;
5328             uword64 memval1 = 0;
5329             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5330             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5331             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5332             unsigned int byte;
5333             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5334             byte = ((vaddr & mask) ^ bigendiancpu);
5335             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5336             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5337           }
5338       }
5339   }
5340 }
5341
5342
5343 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5344 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5345 *mipsIV:
5346 *vr5000:
5347 // start-sanitize-vr4320
5348 *vr4320:
5349 // end-sanitize-vr4320
5350 // start-sanitize-cygnus
5351 *vr5400:
5352 // end-sanitize-cygnus
5353 {
5354   unsigned32 instruction = instruction_0;
5355   int fs = ((instruction >> 11) & 0x0000001F);
5356   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5357   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5358   {
5359    address_word vaddr = ((unsigned64)op1 + op2);
5360    address_word paddr;
5361    int uncached;
5362    if ((vaddr & 3) != 0)
5363     SignalExceptionAddressStore();
5364    else
5365    {
5366     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5367     {
5368      unsigned64 memval = 0;
5369      unsigned64 memval1 = 0;
5370      unsigned64 mask = 0x7;
5371      unsigned int byte;
5372      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5373      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5374      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5375       {
5376        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5377       }
5378     }
5379    }
5380   }
5381 }
5382
5383
5384 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5385 "trunc.l.%s<FMT> f<FD>, f<FS>"
5386 *mipsIII:
5387 *mipsIV:
5388 *vr5000:
5389 // start-sanitize-vr4320
5390 *vr4320:
5391 // end-sanitize-vr4320
5392 // start-sanitize-cygnus
5393 *vr5400:
5394 // end-sanitize-cygnus
5395 // start-sanitize-r5900
5396 *r5900:
5397 // end-sanitize-r5900
5398 *r3900:
5399 // start-sanitize-tx19
5400 *tx19:
5401 // end-sanitize-tx19
5402 {
5403   unsigned32 instruction = instruction_0;
5404   int destreg = ((instruction >> 6) & 0x0000001F);
5405   int fs = ((instruction >> 11) & 0x0000001F);
5406   int format = ((instruction >> 21) & 0x00000007);
5407   {
5408   if ((format != fmt_single) && (format != fmt_double))
5409    SignalException(ReservedInstruction,instruction);
5410   else
5411    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5412   }
5413 }
5414
5415
5416 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5417 "trunc.w.%s<FMT> f<FD>, f<FS>"
5418 *mipsII:
5419 *mipsIII:
5420 *mipsIV:
5421 *vr5000:
5422 // start-sanitize-vr4320
5423 *vr4320:
5424 // end-sanitize-vr4320
5425 // start-sanitize-cygnus
5426 *vr5400:
5427 // end-sanitize-cygnus
5428 // start-sanitize-r5900
5429 *r5900:
5430 // end-sanitize-r5900
5431 *r3900:
5432 // start-sanitize-tx19
5433 *tx19:
5434 // end-sanitize-tx19
5435 {
5436   unsigned32 instruction = instruction_0;
5437   int destreg = ((instruction >> 6) & 0x0000001F);
5438   int fs = ((instruction >> 11) & 0x0000001F);
5439   int format = ((instruction >> 21) & 0x00000007);
5440   {
5441   if ((format != fmt_single) && (format != fmt_double))
5442    SignalException(ReservedInstruction,instruction);
5443   else
5444    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5445   }
5446 }
5447
5448 \f
5449 //
5450 // MIPS Architecture:
5451 //
5452 //        System Control Instruction Set (COP0)
5453 //
5454
5455
5456 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5457 "bc0f <OFFSET>"
5458 *mipsI,mipsII,mipsIII,mipsIV:
5459 *vr5000:
5460 // start-sanitize-vr4320
5461 *vr4320:
5462 // end-sanitize-vr4320
5463 // start-sanitize-cygnus
5464 *vr5400:
5465 // end-sanitize-cygnus
5466
5467
5468 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5469 "bc0fl <OFFSET>"
5470 *mipsI,mipsII,mipsIII,mipsIV:
5471 *vr5000:
5472 // start-sanitize-vr4320
5473 *vr4320:
5474 // end-sanitize-vr4320
5475 // start-sanitize-cygnus
5476 *vr5400:
5477 // end-sanitize-cygnus
5478
5479
5480 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5481 "bc0t <OFFSET>"
5482 *mipsI,mipsII,mipsIII,mipsIV:
5483
5484
5485
5486 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5487 "bc0tl <OFFSET>"
5488 *mipsI,mipsII,mipsIII,mipsIV:
5489 *vr5000:
5490 // start-sanitize-vr4320
5491 *vr4320:
5492 // end-sanitize-vr4320
5493 // start-sanitize-cygnus
5494 *vr5400:
5495 // end-sanitize-cygnus
5496
5497
5498 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5499 *mipsIII:
5500 *mipsIV:
5501 *vr5000:
5502 // start-sanitize-vr4320
5503 *vr4320:
5504 // end-sanitize-vr4320
5505 // start-sanitize-cygnus
5506 *vr5400:
5507 // end-sanitize-cygnus
5508 *r3900:
5509 // start-sanitize-tx19
5510 *tx19:
5511 // end-sanitize-tx19
5512 {
5513   unsigned32 instruction = instruction_0;
5514   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5515   int hint = ((instruction >> 16) & 0x0000001F);
5516   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5517   {
5518     address_word vaddr = (op1 + offset);
5519     address_word paddr;
5520     int uncached;
5521     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5522       CacheOp(hint,vaddr,paddr,instruction);
5523   }
5524 }
5525
5526
5527 010000,10000,000000000000000,111001:COP0:32::DI
5528 "di"
5529 *mipsI,mipsII,mipsIII,mipsIV:
5530 *vr5000:
5531 // start-sanitize-vr4320
5532 *vr4320:
5533 // end-sanitize-vr4320
5534 // start-sanitize-cygnus
5535 *vr5400:
5536 // end-sanitize-cygnus
5537
5538
5539 010000,10000,000000000000000,111000:COP0:32::EI
5540 "ei"
5541 *mipsI,mipsII,mipsIII,mipsIV:
5542 *vr5000:
5543 // start-sanitize-vr4320
5544 *vr4320:
5545 // end-sanitize-vr4320
5546 // start-sanitize-cygnus
5547 *vr5400:
5548 // end-sanitize-cygnus
5549
5550
5551 010000,10000,000000000000000,011000:COP0:32::ERET
5552 "eret"
5553 *mipsIII:
5554 *mipsIV:
5555 *vr5000:
5556 // start-sanitize-vr4320
5557 *vr4320:
5558 // end-sanitize-vr4320
5559 // start-sanitize-cygnus
5560 *vr5400:
5561 // end-sanitize-cygnus
5562 // start-sanitize-r5900
5563 *r5900:
5564 // end-sanitize-r5900
5565 {
5566   if (SR & status_ERL)
5567     {
5568       /* Oops, not yet available */
5569       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5570       NIA = EPC;
5571       SR &= ~status_ERL;
5572     }
5573   else
5574     {
5575       NIA = EPC;
5576       SR &= ~status_EXL;
5577     }
5578 }
5579
5580
5581 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5582 "mfc0 r<RT>, r<RD> # <REGX>"
5583 *mipsI,mipsII,mipsIII,mipsIV:
5584 *r3900:
5585 *vr5000:
5586 // start-sanitize-vr4320
5587 *vr4320:
5588 // end-sanitize-vr4320
5589 // start-sanitize-cygnus
5590 *vr5400:
5591 // end-sanitize-cygnus
5592 // start-sanitize-r5900
5593 *r5900:
5594 // end-sanitize-r5900
5595 {
5596   TRACE_ALU_INPUT0 ();
5597   DecodeCoproc (instruction_0);
5598   TRACE_ALU_RESULT (GPR[RT]);
5599 }
5600
5601 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5602 "mtc0 r<RT>, r<RD> # <REGX>"
5603 *mipsI,mipsII,mipsIII,mipsIV:
5604 // start-sanitize-tx19
5605 *tx19:
5606 // end-sanitize-tx19
5607 *r3900:
5608 // start-sanitize-vr4320
5609 *vr4320:
5610 // end-sanitize-vr4320
5611 *vr5000:
5612 // start-sanitize-cygnus
5613 *vr5400:
5614 // end-sanitize-cygnus
5615 // start-sanitize-r5900
5616 *r5900:
5617 // end-sanitize-r5900
5618 {
5619   DecodeCoproc (instruction_0);
5620 }
5621
5622
5623 010000,10000,000000000000000,010000:COP0:32::RFE
5624 "rfe"
5625 *mipsI,mipsII,mipsIII,mipsIV:
5626 // start-sanitize-tx19
5627 *tx19:
5628 // end-sanitize-tx19
5629 *r3900:
5630 // start-sanitize-vr4320
5631 *vr4320:
5632 // end-sanitize-vr4320
5633 *vr5000:
5634 // start-sanitize-cygnus
5635 *vr5400:
5636 // end-sanitize-cygnus
5637 // start-sanitize-r5900
5638 *r5900:
5639 // end-sanitize-r5900
5640 {
5641   DecodeCoproc (instruction_0);
5642 }
5643
5644
5645 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5646 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5647 *mipsI,mipsII,mipsIII,mipsIV:
5648 // start-sanitize-r5900
5649 *r5900:
5650 // end-sanitize-r5900
5651 *r3900:
5652 // start-sanitize-tx19
5653 *tx19:
5654 // end-sanitize-tx19
5655 {
5656   DecodeCoproc (instruction_0);
5657 }
5658
5659
5660
5661 010000,10000,000000000000000,001000:COP0:32::TLBP
5662 "tlbp"
5663 *mipsI,mipsII,mipsIII,mipsIV:
5664 *vr5000:
5665 // start-sanitize-vr4320
5666 *vr4320:
5667 // end-sanitize-vr4320
5668 // start-sanitize-cygnus
5669 *vr5400:
5670 // end-sanitize-cygnus
5671
5672
5673 010000,10000,000000000000000,000001:COP0:32::TLBR
5674 "tlbr"
5675 *mipsI,mipsII,mipsIII,mipsIV:
5676 *vr5000:
5677 // start-sanitize-vr4320
5678 *vr4320:
5679 // end-sanitize-vr4320
5680 // start-sanitize-cygnus
5681 *vr5400:
5682 // end-sanitize-cygnus
5683
5684
5685 010000,10000,000000000000000,000010:COP0:32::TLBWI
5686 "tlbwi"
5687 *mipsI,mipsII,mipsIII,mipsIV:
5688 *vr5000:
5689 // start-sanitize-vr4320
5690 *vr4320:
5691 // end-sanitize-vr4320
5692 // start-sanitize-cygnus
5693 *vr5400:
5694 // end-sanitize-cygnus
5695
5696
5697 010000,10000,000000000000000,000110:COP0:32::TLBWR
5698 "tlbwr"
5699 *mipsI,mipsII,mipsIII,mipsIV:
5700 *vr5000:
5701 // start-sanitize-vr4320
5702 *vr4320:
5703 // end-sanitize-vr4320
5704 // start-sanitize-cygnus
5705 *vr5400:
5706 // end-sanitize-cygnus
5707
5708 \f
5709 :include:::m16.igen
5710 // start-sanitize-cygnus
5711 :include:64,f::mdmx.igen
5712 // end-sanitize-cygnus
5713 // start-sanitize-r5900
5714 :include::r5900:r5900.igen
5715 // end-sanitize-r5900
5716 :include:::tx.igen
5717 :include:::vr.igen
5718 \f
5719 // start-sanitize-cygnus-never
5720
5721 // // FIXME FIXME FIXME What is this instruction?
5722 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5723 // *mipsI:
5724 // *mipsII:
5725 // *mipsIII:
5726 // *mipsIV:
5727 // // start-sanitize-r5900
5728 // *r5900:
5729 // // end-sanitize-r5900
5730 // *r3900:
5731 // // start-sanitize-tx19
5732 // *tx19:
5733 // // end-sanitize-tx19
5734 // {
5735 //   unsigned32 instruction = instruction_0;
5736 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5737 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5738 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5739 //   {
5740 //     if (CoProcPresent(3))
5741 //       SignalException(CoProcessorUnusable);
5742 //     else
5743 //       SignalException(ReservedInstruction,instruction);
5744 //   }
5745 // }
5746
5747 // end-sanitize-cygnus-never
5748 // start-sanitize-cygnus-never
5749
5750 // // FIXME FIXME FIXME What is this?
5751 // 11100,******,00001:RR:16::SDBBP
5752 // *mips16:
5753 // {
5754 //   unsigned32 instruction = instruction_0;
5755 //   if (have_extendval)
5756 //     SignalException (ReservedInstruction, instruction);
5757 //   {
5758 //     SignalException(DebugBreakPoint,instruction);
5759 //   }
5760 // }
5761
5762 // end-sanitize-cygnus-never
5763 // start-sanitize-cygnus-never
5764
5765 // // FIXME FIXME FIXME What is this?
5766 // 000000,********************,001110:SPECIAL:32::SDBBP
5767 // *r3900:
5768 // {
5769 //   unsigned32 instruction = instruction_0;
5770 //   {
5771 //     SignalException(DebugBreakPoint,instruction);
5772 //   }
5773 // }
5774
5775 // end-sanitize-cygnus-never