sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 // Helper:
 102 //
 103 // Check that an access to a HI/LO register meets timing requirements
 104 //
 105 // The following requirements exist:
 106 //
 107 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 108 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 109 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 110 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 111 //
 112
 113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 114 {
 115   if (history->mf.timestamp + 3 > time)
 116     {
 117       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 118                         itable[MY_INDEX].name,
 119                         new, (long) CIA,
 120                         (long) history->mf.cia);
 121       return 0;
 122     }
 123   return 1;
 124 }
 125
 126 :function:::int:check_mt_hilo:hilo_history *history
 127 *mipsI,mipsII,mipsIII,mipsIV:
 128 *vr5000:
 129 // start-sanitize-vr4320
 130 *vr4320:
 131 // end-sanitize-vr4320
 132 // start-sanitize-vr5400
 133 *vr5400:
 134 // end-sanitize-vr5400
 135 {
 136   signed64 time = sim_events_time (SD);
 137   int ok = check_mf_cycles (SD_, history, time, "MT");
 138   history->mt.timestamp = time;
 139   history->mt.cia = CIA;
 140   return ok;
 141 }
 142
 143 :function:::int:check_mt_hilo:hilo_history *history
 144 *r3900:
 145 // start-sanitize-tx19
 146 *tx19:
 147 // end-sanitize-tx19
 148 // start-sanitize-r5900
 149 *r5900:
 150 // end-sanitize-r5900
 151 {
 152   signed64 time = sim_events_time (SD);
 153   history->mt.timestamp = time;
 154   history->mt.cia = CIA;
 155   return 1;
 156 }
 157
 158
 159 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 160 *mipsI,mipsII,mipsIII,mipsIV:
 161 *vr5000:
 162 // start-sanitize-vr4320
 163 *vr4320:
 164 // end-sanitize-vr4320
 165 // start-sanitize-vr5400
 166 *vr5400:
 167 // end-sanitize-vr5400
 168 *r3900:
 169 // start-sanitize-tx19
 170 *tx19:
 171 // end-sanitize-tx19
 172 {
 173   signed64 time = sim_events_time (SD);
 174   int ok = 1;
 175   if (peer != NULL
 176       && peer->mt.timestamp > history->op.timestamp
 177       && history->mf.timestamp < history->op.timestamp)
 178     {
 179       /* The peer has been written to since the last OP yet we have
 180          not */
 181       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 182                         itable[MY_INDEX].name,
 183                         (long) CIA,
 184                         (long) history->op.cia,
 185                         (long) peer->mt.cia);
 186       ok = 0;
 187     }
 188   history->mf.timestamp = time;
 189   history->mf.cia = CIA;
 190   return ok;
 191 }
 192
 193 // start-sanitize-r5900
 194 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 195 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 196 // end-sanitize-r5900
 197 // start-sanitize-r5900
 198 *r5900:
 199 // end-sanitize-r5900
 200 // start-sanitize-r5900
 201 {
 202   /* FIXME: could record the fact that a stall occured if we want */
 203   signed64 time = sim_events_time (SD);
 204   history->mf.timestamp = time;
 205   history->mf.cia = CIA;
 206   return 1;
 207 }
 208 // end-sanitize-r5900
 209
 210
 211 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 212 *mipsI,mipsII,mipsIII,mipsIV:
 213 *vr5000:
 214 // start-sanitize-vr4320
 215 *vr4320:
 216 // end-sanitize-vr4320
 217 // start-sanitize-vr5400
 218 *vr5400:
 219 // end-sanitize-vr5400
 220 {
 221   signed64 time = sim_events_time (SD);
 222   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 223             && check_mf_cycles (SD_, lo, time, "OP"));
 224   hi->op.timestamp = time;
 225   lo->op.timestamp = time;
 226   hi->op.cia = CIA;
 227   lo->op.cia = CIA;
 228   return ok;
 229 }
 230
 231 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 232 // a mf{hi,lo}
 233 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 234 *r3900:
 235 // start-sanitize-tx19
 236 *tx19:
 237 // end-sanitize-tx19
 238 // start-sanitize-r5900
 239 *r5900:
 240 // end-sanitize-r5900
 241 {
 242   /* FIXME: could record the fact that a stall occured if we want */
 243   signed64 time = sim_events_time (SD);
 244   hi->op.timestamp = time;
 245   lo->op.timestamp = time;
 246   hi->op.cia = CIA;
 247   lo->op.cia = CIA;
 248   return 1;
 249 }
 250
 251
 252 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 253 *mipsI,mipsII,mipsIII,mipsIV:
 254 *vr5000:
 255 // start-sanitize-vr4320
 256 *vr4320:
 257 // end-sanitize-vr4320
 258 // start-sanitize-vr5400
 259 *vr5400:
 260 // end-sanitize-vr5400
 261 *r3900:
 262 // start-sanitize-tx19
 263 *tx19:
 264 // end-sanitize-tx19
 265 {
 266   signed64 time = sim_events_time (SD);
 267   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 268             && check_mf_cycles (SD_, lo, time, "OP"));
 269   hi->op.timestamp = time;
 270   lo->op.timestamp = time;
 271   hi->op.cia = CIA;
 272   lo->op.cia = CIA;
 273   return ok;
 274 }
 275
 276
 277 // start-sanitize-r5900
 278 // The r5900 div et.al insns _can_ be exectuted immediatly after
 279 // a mf{hi,lo}
 280 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 281 // end-sanitize-r5900
 282 // start-sanitize-r5900
 283 *r5900:
 284 // end-sanitize-r5900
 285 // start-sanitize-r5900
 286 {
 287   /* FIXME: could record the fact that a stall occured if we want */
 288   signed64 time = sim_events_time (SD);
 289   hi->op.timestamp = time;
 290   lo->op.timestamp = time;
 291   hi->op.cia = CIA;
 292   lo->op.cia = CIA;
 293   return 1;
 294 }
 295 // end-sanitize-r5900
 296
 297
 298
 299 //
 300 // Mips Architecture:
 301 //
 302 //        CPU Instruction Set (mipsI - mipsIV)
 303 //
 304
 305
 306
 307 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 308 "add r<RD>, r<RS>, r<RT>"
 309 *mipsI,mipsII,mipsIII,mipsIV:
 310 *vr5000:
 311 // start-sanitize-vr4320
 312 *vr4320:
 313 // end-sanitize-vr4320
 314 // start-sanitize-vr5400
 315 *vr5400:
 316 // end-sanitize-vr5400
 317 // start-sanitize-r5900
 318 *r5900:
 319 // end-sanitize-r5900
 320 *r3900:
 321 // start-sanitize-tx19
 322 *tx19:
 323 // end-sanitize-tx19
 324 {
 325   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 326   {
 327     ALU32_BEGIN (GPR[RS]);
 328     ALU32_ADD (GPR[RT]);
 329     ALU32_END (GPR[RD]);
 330   }
 331   TRACE_ALU_RESULT (GPR[RD]);
 332 }
 333
 334
 335
 336 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 337 "addi r<RT>, r<RS>, IMMEDIATE"
 338 *mipsI,mipsII,mipsIII,mipsIV:
 339 *vr5000:
 340 // start-sanitize-vr4320
 341 *vr4320:
 342 // end-sanitize-vr4320
 343 // start-sanitize-vr5400
 344 *vr5400:
 345 // end-sanitize-vr5400
 346 // start-sanitize-r5900
 347 *r5900:
 348 // end-sanitize-r5900
 349 *r3900:
 350 // start-sanitize-tx19
 351 *tx19:
 352 // end-sanitize-tx19
 353 {
 354   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 355   {
 356     ALU32_BEGIN (GPR[RS]);
 357     ALU32_ADD (EXTEND16 (IMMEDIATE));
 358     ALU32_END (GPR[RT]);
 359   }
 360   TRACE_ALU_RESULT (GPR[RT]);
 361 }
 362
 363
 364
 365 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 366 {
 367   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 368   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 369   TRACE_ALU_RESULT (GPR[rt]);
 370 }
 371
 372 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 373 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 374 *mipsI,mipsII,mipsIII,mipsIV:
 375 *vr5000:
 376 // start-sanitize-vr4320
 377 *vr4320:
 378 // end-sanitize-vr4320
 379 // start-sanitize-vr5400
 380 *vr5400:
 381 // end-sanitize-vr5400
 382 // start-sanitize-r5900
 383 *r5900:
 384 // end-sanitize-r5900
 385 *r3900:
 386 // start-sanitize-tx19
 387 *tx19:
 388 // end-sanitize-tx19
 389 {
 390   do_addiu (SD_, RS, RT, IMMEDIATE);
 391 }
 392
 393
 394
 395 :function:::void:do_addu:int rs, int rt, int rd
 396 {
 397   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 398   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 399   TRACE_ALU_RESULT (GPR[rd]);
 400 }
 401
 402 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 403 "addu r<RD>, r<RS>, r<RT>"
 404 *mipsI,mipsII,mipsIII,mipsIV:
 405 *vr5000:
 406 // start-sanitize-vr4320
 407 *vr4320:
 408 // end-sanitize-vr4320
 409 // start-sanitize-vr5400
 410 *vr5400:
 411 // end-sanitize-vr5400
 412 // start-sanitize-r5900
 413 *r5900:
 414 // end-sanitize-r5900
 415 *r3900:
 416 // start-sanitize-tx19
 417 *tx19:
 418 // end-sanitize-tx19
 419 {
 420   do_addu (SD_, RS, RT, RD);
 421 }
 422
 423
 424
 425 :function:::void:do_and:int rs, int rt, int rd
 426 {
 427   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 428   GPR[rd] = GPR[rs] & GPR[rt];
 429   TRACE_ALU_RESULT (GPR[rd]);
 430 }
 431
 432 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 433 "and r<RD>, r<RS>, r<RT>"
 434 *mipsI,mipsII,mipsIII,mipsIV:
 435 *vr5000:
 436 // start-sanitize-vr4320
 437 *vr4320:
 438 // end-sanitize-vr4320
 439 // start-sanitize-vr5400
 440 *vr5400:
 441 // end-sanitize-vr5400
 442 // start-sanitize-r5900
 443 *r5900:
 444 // end-sanitize-r5900
 445 *r3900:
 446 // start-sanitize-tx19
 447 *tx19:
 448 // end-sanitize-tx19
 449 {
 450   do_and (SD_, RS, RT, RD);
 451 }
 452
 453
 454
 455 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 456 "and r<RT>, r<RS>, <IMMEDIATE>"
 457 *mipsI,mipsII,mipsIII,mipsIV:
 458 *vr5000:
 459 // start-sanitize-vr4320
 460 *vr4320:
 461 // end-sanitize-vr4320
 462 // start-sanitize-vr5400
 463 *vr5400:
 464 // end-sanitize-vr5400
 465 // start-sanitize-r5900
 466 *r5900:
 467 // end-sanitize-r5900
 468 *r3900:
 469 // start-sanitize-tx19
 470 *tx19:
 471 // end-sanitize-tx19
 472 {
 473   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 474   GPR[RT] = GPR[RS] & IMMEDIATE;
 475   TRACE_ALU_RESULT (GPR[RT]);
 476 }
 477
 478
 479
 480 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 481 "beq r<RS>, r<RT>, <OFFSET>"
 482 *mipsI,mipsII,mipsIII,mipsIV:
 483 *vr5000:
 484 // start-sanitize-vr4320
 485 *vr4320:
 486 // end-sanitize-vr4320
 487 // start-sanitize-vr5400
 488 *vr5400:
 489 // end-sanitize-vr5400
 490 // start-sanitize-r5900
 491 *r5900:
 492 // end-sanitize-r5900
 493 *r3900:
 494 // start-sanitize-tx19
 495 *tx19:
 496 // end-sanitize-tx19
 497 {
 498   address_word offset = EXTEND16 (OFFSET) << 2;
 499   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 500     DELAY_SLOT (NIA + offset);
 501 }
 502
 503
 504
 505 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 506 "beql r<RS>, r<RT>, <OFFSET>"
 507 *mipsII:
 508 *mipsIII:
 509 *mipsIV:
 510 *vr5000:
 511 // start-sanitize-vr4320
 512 *vr4320:
 513 // end-sanitize-vr4320
 514 // start-sanitize-vr5400
 515 *vr5400:
 516 // end-sanitize-vr5400
 517 // start-sanitize-r5900
 518 *r5900:
 519 // end-sanitize-r5900
 520 *r3900:
 521 // start-sanitize-tx19
 522 *tx19:
 523 // end-sanitize-tx19
 524 {
 525   address_word offset = EXTEND16 (OFFSET) << 2;
 526   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 527     DELAY_SLOT (NIA + offset);
 528   else
 529     NULLIFY_NEXT_INSTRUCTION ();
 530 }
 531
 532
 533
 534 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 535 "bgez r<RS>, <OFFSET>"
 536 *mipsI,mipsII,mipsIII,mipsIV:
 537 *vr5000:
 538 // start-sanitize-vr4320
 539 *vr4320:
 540 // end-sanitize-vr4320
 541 // start-sanitize-vr5400
 542 *vr5400:
 543 // end-sanitize-vr5400
 544 // start-sanitize-r5900
 545 *r5900:
 546 // end-sanitize-r5900
 547 *r3900:
 548 // start-sanitize-tx19
 549 *tx19:
 550 // end-sanitize-tx19
 551 {
 552   address_word offset = EXTEND16 (OFFSET) << 2;
 553   if ((signed_word) GPR[RS] >= 0)
 554     DELAY_SLOT (NIA + offset);
 555 }
 556
 557
 558
 559 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 560 "bgezal r<RS>, <OFFSET>"
 561 *mipsI,mipsII,mipsIII,mipsIV:
 562 *vr5000:
 563 // start-sanitize-vr4320
 564 *vr4320:
 565 // end-sanitize-vr4320
 566 // start-sanitize-vr5400
 567 *vr5400:
 568 // end-sanitize-vr5400
 569 // start-sanitize-r5900
 570 *r5900:
 571 // end-sanitize-r5900
 572 *r3900:
 573 // start-sanitize-tx19
 574 *tx19:
 575 // end-sanitize-tx19
 576 {
 577   address_word offset = EXTEND16 (OFFSET) << 2;
 578   RA = (CIA + 8);
 579   if ((signed_word) GPR[RS] >= 0)
 580     DELAY_SLOT (NIA + offset);
 581 }
 582
 583
 584
 585 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 586 "bgezall r<RS>, <OFFSET>"
 587 *mipsII:
 588 *mipsIII:
 589 *mipsIV:
 590 *vr5000:
 591 // start-sanitize-vr4320
 592 *vr4320:
 593 // end-sanitize-vr4320
 594 // start-sanitize-vr5400
 595 *vr5400:
 596 // end-sanitize-vr5400
 597 // start-sanitize-r5900
 598 *r5900:
 599 // end-sanitize-r5900
 600 *r3900:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   address_word offset = EXTEND16 (OFFSET) << 2;
 606   RA = (CIA + 8);
 607   /* NOTE: The branch occurs AFTER the next instruction has been
 608      executed */
 609   if ((signed_word) GPR[RS] >= 0)
 610     DELAY_SLOT (NIA + offset);
 611   else
 612     NULLIFY_NEXT_INSTRUCTION ();
 613 }
 614
 615
 616
 617 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 618 "bgezl r<RS>, <OFFSET>"
 619 *mipsII:
 620 *mipsIII:
 621 *mipsIV:
 622 *vr5000:
 623 // start-sanitize-vr4320
 624 *vr4320:
 625 // end-sanitize-vr4320
 626 // start-sanitize-vr5400
 627 *vr5400:
 628 // end-sanitize-vr5400
 629 // start-sanitize-r5900
 630 *r5900:
 631 // end-sanitize-r5900
 632 *r3900:
 633 // start-sanitize-tx19
 634 *tx19:
 635 // end-sanitize-tx19
 636 {
 637   address_word offset = EXTEND16 (OFFSET) << 2;
 638   if ((signed_word) GPR[RS] >= 0)
 639     DELAY_SLOT (NIA + offset);
 640   else
 641     NULLIFY_NEXT_INSTRUCTION ();
 642 }
 643
 644
 645
 646 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 647 "bgtz r<RS>, <OFFSET>"
 648 *mipsI,mipsII,mipsIII,mipsIV:
 649 *vr5000:
 650 // start-sanitize-vr4320
 651 *vr4320:
 652 // end-sanitize-vr4320
 653 // start-sanitize-vr5400
 654 *vr5400:
 655 // end-sanitize-vr5400
 656 // start-sanitize-r5900
 657 *r5900:
 658 // end-sanitize-r5900
 659 *r3900:
 660 // start-sanitize-tx19
 661 *tx19:
 662 // end-sanitize-tx19
 663 {
 664   address_word offset = EXTEND16 (OFFSET) << 2;
 665   if ((signed_word) GPR[RS] > 0)
 666     DELAY_SLOT (NIA + offset);
 667 }
 668
 669
 670
 671 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 672 "bgtzl r<RS>, <OFFSET>"
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *vr5000:
 677 // start-sanitize-vr4320
 678 *vr4320:
 679 // end-sanitize-vr4320
 680 // start-sanitize-vr5400
 681 *vr5400:
 682 // end-sanitize-vr5400
 683 // start-sanitize-r5900
 684 *r5900:
 685 // end-sanitize-r5900
 686 *r3900:
 687 // start-sanitize-tx19
 688 *tx19:
 689 // end-sanitize-tx19
 690 {
 691   address_word offset = EXTEND16 (OFFSET) << 2;
 692   /* NOTE: The branch occurs AFTER the next instruction has been
 693      executed */
 694   if ((signed_word) GPR[RS] > 0)
 695     DELAY_SLOT (NIA + offset);
 696   else
 697     NULLIFY_NEXT_INSTRUCTION ();
 698 }
 699
 700
 701
 702 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 703 "blez r<RS>, <OFFSET>"
 704 *mipsI,mipsII,mipsIII,mipsIV:
 705 *vr5000:
 706 // start-sanitize-vr4320
 707 *vr4320:
 708 // end-sanitize-vr4320
 709 // start-sanitize-vr5400
 710 *vr5400:
 711 // end-sanitize-vr5400
 712 // start-sanitize-r5900
 713 *r5900:
 714 // end-sanitize-r5900
 715 *r3900:
 716 // start-sanitize-tx19
 717 *tx19:
 718 // end-sanitize-tx19
 719 {
 720   address_word offset = EXTEND16 (OFFSET) << 2;
 721   /* NOTE: The branch occurs AFTER the next instruction has been
 722      executed */
 723   if ((signed_word) GPR[RS] <= 0)
 724     DELAY_SLOT (NIA + offset);
 725 }
 726
 727
 728
 729 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 730 "bgezl r<RS>, <OFFSET>"
 731 *mipsII:
 732 *mipsIII:
 733 *mipsIV:
 734 *vr5000:
 735 // start-sanitize-vr4320
 736 *vr4320:
 737 // end-sanitize-vr4320
 738 // start-sanitize-vr5400
 739 *vr5400:
 740 // end-sanitize-vr5400
 741 // start-sanitize-r5900
 742 *r5900:
 743 // end-sanitize-r5900
 744 *r3900:
 745 // start-sanitize-tx19
 746 *tx19:
 747 // end-sanitize-tx19
 748 {
 749   address_word offset = EXTEND16 (OFFSET) << 2;
 750   if ((signed_word) GPR[RS] <= 0)
 751     DELAY_SLOT (NIA + offset);
 752   else
 753     NULLIFY_NEXT_INSTRUCTION ();
 754 }
 755
 756
 757
 758 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 759 "bltz r<RS>, <OFFSET>"
 760 *mipsI,mipsII,mipsIII,mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-vr5400
 766 *vr5400:
 767 // end-sanitize-vr5400
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 *r3900:
 772 // start-sanitize-tx19
 773 *tx19:
 774 // end-sanitize-tx19
 775 {
 776   address_word offset = EXTEND16 (OFFSET) << 2;
 777   if ((signed_word) GPR[RS] < 0)
 778     DELAY_SLOT (NIA + offset);
 779 }
 780
 781
 782
 783 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 784 "bltzal r<RS>, <OFFSET>"
 785 *mipsI,mipsII,mipsIII,mipsIV:
 786 *vr5000:
 787 // start-sanitize-vr4320
 788 *vr4320:
 789 // end-sanitize-vr4320
 790 // start-sanitize-vr5400
 791 *vr5400:
 792 // end-sanitize-vr5400
 793 // start-sanitize-r5900
 794 *r5900:
 795 // end-sanitize-r5900
 796 *r3900:
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   address_word offset = EXTEND16 (OFFSET) << 2;
 802   RA = (CIA + 8);
 803   /* NOTE: The branch occurs AFTER the next instruction has been
 804      executed */
 805   if ((signed_word) GPR[RS] < 0)
 806     DELAY_SLOT (NIA + offset);
 807 }
 808
 809
 810
 811 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 812 "bltzall r<RS>, <OFFSET>"
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *vr5000:
 817 // start-sanitize-vr4320
 818 *vr4320:
 819 // end-sanitize-vr4320
 820 // start-sanitize-vr5400
 821 *vr5400:
 822 // end-sanitize-vr5400
 823 // start-sanitize-r5900
 824 *r5900:
 825 // end-sanitize-r5900
 826 *r3900:
 827 // start-sanitize-tx19
 828 *tx19:
 829 // end-sanitize-tx19
 830 {
 831   address_word offset = EXTEND16 (OFFSET) << 2;
 832   RA = (CIA + 8);
 833   if ((signed_word) GPR[RS] < 0)
 834     DELAY_SLOT (NIA + offset);
 835   else
 836     NULLIFY_NEXT_INSTRUCTION ();
 837 }
 838
 839
 840
 841 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 842 "bltzl r<RS>, <OFFSET>"
 843 *mipsII:
 844 *mipsIII:
 845 *mipsIV:
 846 *vr5000:
 847 // start-sanitize-vr4320
 848 *vr4320:
 849 // end-sanitize-vr4320
 850 // start-sanitize-vr5400
 851 *vr5400:
 852 // end-sanitize-vr5400
 853 // start-sanitize-r5900
 854 *r5900:
 855 // end-sanitize-r5900
 856 *r3900:
 857 // start-sanitize-tx19
 858 *tx19:
 859 // end-sanitize-tx19
 860 {
 861   address_word offset = EXTEND16 (OFFSET) << 2;
 862   /* NOTE: The branch occurs AFTER the next instruction has been
 863      executed */
 864   if ((signed_word) GPR[RS] < 0)
 865     DELAY_SLOT (NIA + offset);
 866   else
 867     NULLIFY_NEXT_INSTRUCTION ();
 868 }
 869
 870
 871
 872 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 873 "bne r<RS>, r<RT>, <OFFSET>"
 874 *mipsI,mipsII,mipsIII,mipsIV:
 875 *vr5000:
 876 // start-sanitize-vr4320
 877 *vr4320:
 878 // end-sanitize-vr4320
 879 // start-sanitize-vr5400
 880 *vr5400:
 881 // end-sanitize-vr5400
 882 // start-sanitize-r5900
 883 *r5900:
 884 // end-sanitize-r5900
 885 *r3900:
 886 // start-sanitize-tx19
 887 *tx19:
 888 // end-sanitize-tx19
 889 {
 890   address_word offset = EXTEND16 (OFFSET) << 2;
 891   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 892     DELAY_SLOT (NIA + offset);
 893 }
 894
 895
 896
 897 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 898 "bnel r<RS>, r<RT>, <OFFSET>"
 899 *mipsII:
 900 *mipsIII:
 901 *mipsIV:
 902 *vr5000:
 903 // start-sanitize-vr4320
 904 *vr4320:
 905 // end-sanitize-vr4320
 906 // start-sanitize-vr5400
 907 *vr5400:
 908 // end-sanitize-vr5400
 909 // start-sanitize-r5900
 910 *r5900:
 911 // end-sanitize-r5900
 912 *r3900:
 913 // start-sanitize-tx19
 914 *tx19:
 915 // end-sanitize-tx19
 916 {
 917   address_word offset = EXTEND16 (OFFSET) << 2;
 918   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 919     DELAY_SLOT (NIA + offset);
 920   else
 921     NULLIFY_NEXT_INSTRUCTION ();
 922 }
 923
 924
 925
 926 000000,20.CODE,001101:SPECIAL:32::BREAK
 927 "break"
 928 *mipsI,mipsII,mipsIII,mipsIV:
 929 *vr5000:
 930 // start-sanitize-vr4320
 931 *vr4320:
 932 // end-sanitize-vr4320
 933 // start-sanitize-vr5400
 934 *vr5400:
 935 // end-sanitize-vr5400
 936 // start-sanitize-r5900
 937 *r5900:
 938 // end-sanitize-r5900
 939 *r3900:
 940 // start-sanitize-tx19
 941 *tx19:
 942 // end-sanitize-tx19
 943 {
 944   /* Check for some break instruction which are reserved for use by the simulator.  */
 945   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 946   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 947       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 948     {
 949       sim_engine_halt (SD, CPU, NULL, cia,
 950                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 951     }
 952   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 953            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 954     {
 955       if (STATE & simDELAYSLOT)
 956         PC = cia - 4; /* reference the branch instruction */
 957       else
 958         PC = cia;
 959       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
 960     }
 961 // start-sanitize-sky
 962   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
 963     {
 964       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
 965     }
 966   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
 967     {
 968       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
 969     }
 970 // end-sanitize-sky
 971
 972   /* If we get this far, we're not an instruction reserved by the sim.  Raise
 973      the exception. */
 974   SignalException(BreakPoint, instruction_0);
 975 }
 976
 977
 978
 979
 980
 981
 982 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 983 "dadd r<RD>, r<RS>, r<RT>"
 984 *mipsIII:
 985 *mipsIV:
 986 *vr5000:
 987 // start-sanitize-vr4320
 988 *vr4320:
 989 // end-sanitize-vr4320
 990 // start-sanitize-vr5400
 991 *vr5400:
 992 // end-sanitize-vr5400
 993 // start-sanitize-r5900
 994 *r5900:
 995 // end-sanitize-r5900
 996 // start-sanitize-tx19
 997 *tx19:
 998 // end-sanitize-tx19
 999 {
1000   /* this check's for overflow */
1001   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1002   {
1003     ALU64_BEGIN (GPR[RS]);
1004     ALU64_ADD (GPR[RT]);
1005     ALU64_END (GPR[RD]);
1006   }
1007   TRACE_ALU_RESULT (GPR[RD]);
1008 }
1009
1010
1011
1012 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1013 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1014 *mipsIII:
1015 *mipsIV:
1016 *vr5000:
1017 // start-sanitize-vr4320
1018 *vr4320:
1019 // end-sanitize-vr4320
1020 // start-sanitize-vr5400
1021 *vr5400:
1022 // end-sanitize-vr5400
1023 // start-sanitize-r5900
1024 *r5900:
1025 // end-sanitize-r5900
1026 // start-sanitize-tx19
1027 *tx19:
1028 // end-sanitize-tx19
1029 {
1030   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1031   {
1032     ALU64_BEGIN (GPR[RS]);
1033     ALU64_ADD (EXTEND16 (IMMEDIATE));
1034     ALU64_END (GPR[RT]);
1035   }
1036   TRACE_ALU_RESULT (GPR[RT]);
1037 }
1038
1039
1040
1041 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1042 {
1043   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1044   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1045   TRACE_ALU_RESULT (GPR[rt]);
1046 }
1047
1048 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1049 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1050 *mipsIII:
1051 *mipsIV:
1052 *vr5000:
1053 // start-sanitize-vr4320
1054 *vr4320:
1055 // end-sanitize-vr4320
1056 // start-sanitize-vr5400
1057 *vr5400:
1058 // end-sanitize-vr5400
1059 // start-sanitize-r5900
1060 *r5900:
1061 // end-sanitize-r5900
1062 // start-sanitize-tx19
1063 *tx19:
1064 // end-sanitize-tx19
1065 {
1066   do_daddiu (SD_, RS, RT, IMMEDIATE);
1067 }
1068
1069
1070
1071 :function:::void:do_daddu:int rs, int rt, int rd
1072 {
1073   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1074   GPR[rd] = GPR[rs] + GPR[rt];
1075   TRACE_ALU_RESULT (GPR[rd]);
1076 }
1077
1078 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1079 "daddu r<RD>, r<RS>, r<RT>"
1080 *mipsIII:
1081 *mipsIV:
1082 *vr5000:
1083 // start-sanitize-vr4320
1084 *vr4320:
1085 // end-sanitize-vr4320
1086 // start-sanitize-vr5400
1087 *vr5400:
1088 // end-sanitize-vr5400
1089 // start-sanitize-r5900
1090 *r5900:
1091 // end-sanitize-r5900
1092 // start-sanitize-tx19
1093 *tx19:
1094 // end-sanitize-tx19
1095 {
1096   do_daddu (SD_, RS, RT, RD);
1097 }
1098
1099
1100
1101 :function:64::void:do_ddiv:int rs, int rt
1102 {
1103   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1104   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1105   {
1106     signed64 n = GPR[rs];
1107     signed64 d = GPR[rt];
1108     if (d == 0)
1109       {
1110         LO = SIGNED64 (0x8000000000000000);
1111         HI = 0;
1112       }
1113     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1114       {
1115         LO = SIGNED64 (0x8000000000000000);
1116         HI = 0;
1117       }
1118     else
1119       {
1120         LO = (n / d);
1121         HI = (n % d);
1122       }
1123   }
1124   TRACE_ALU_RESULT2 (HI, LO);
1125 }
1126
1127 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1128 "ddiv r<RS>, r<RT>"
1129 *mipsIII:
1130 *mipsIV:
1131 *vr5000:
1132 // start-sanitize-vr4320
1133 *vr4320:
1134 // end-sanitize-vr4320
1135 // start-sanitize-vr5400
1136 *vr5400:
1137 // end-sanitize-vr5400
1138 // start-sanitize-r5900
1139 *r5900:
1140 // end-sanitize-r5900
1141 // start-sanitize-tx19
1142 *tx19:
1143 // end-sanitize-tx19
1144 {
1145   do_ddiv (SD_, RS, RT);
1146 }
1147
1148
1149
1150 :function:64::void:do_ddivu:int rs, int rt
1151 {
1152   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1153   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1154   {
1155     unsigned64 n = GPR[rs];
1156     unsigned64 d = GPR[rt];
1157     if (d == 0)
1158       {
1159         LO = SIGNED64 (0x8000000000000000);
1160         HI = 0;
1161       }
1162     else
1163       {
1164         LO = (n / d);
1165         HI = (n % d);
1166       }
1167   }
1168   TRACE_ALU_RESULT2 (HI, LO);
1169 }
1170
1171 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1172 "ddivu r<RS>, r<RT>"
1173 *mipsIII:
1174 *mipsIV:
1175 *vr5000:
1176 // start-sanitize-vr4320
1177 *vr4320:
1178 // end-sanitize-vr4320
1179 // start-sanitize-vr5400
1180 *vr5400:
1181 // end-sanitize-vr5400
1182 // start-sanitize-tx19
1183 *tx19:
1184 // end-sanitize-tx19
1185 {
1186   do_ddivu (SD_, RS, RT);
1187 }
1188
1189
1190
1191 :function:::void:do_div:int rs, int rt
1192 {
1193   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1194   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1195   {
1196     signed32 n = GPR[rs];
1197     signed32 d = GPR[rt];
1198     if (d == 0)
1199       {
1200         LO = EXTEND32 (0x80000000);
1201         HI = EXTEND32 (0);
1202       }
1203     else if (n == SIGNED32 (0x80000000) && d == -1)
1204       {
1205         LO = EXTEND32 (0x80000000);
1206         HI = EXTEND32 (0);
1207       }
1208     else
1209       {
1210         LO = EXTEND32 (n / d);
1211         HI = EXTEND32 (n % d);
1212       }
1213   }
1214   TRACE_ALU_RESULT2 (HI, LO);
1215 }
1216
1217 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1218 "div r<RS>, r<RT>"
1219 *mipsI,mipsII,mipsIII,mipsIV:
1220 *vr5000:
1221 // start-sanitize-vr4320
1222 *vr4320:
1223 // end-sanitize-vr4320
1224 // start-sanitize-vr5400
1225 *vr5400:
1226 // end-sanitize-vr5400
1227 // start-sanitize-r5900
1228 *r5900:
1229 // end-sanitize-r5900
1230 *r3900:
1231 // start-sanitize-tx19
1232 *tx19:
1233 // end-sanitize-tx19
1234 {
1235   do_div (SD_, RS, RT);
1236 }
1237
1238
1239
1240 :function:::void:do_divu:int rs, int rt
1241 {
1242   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1243   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1244   {
1245     unsigned32 n = GPR[rs];
1246     unsigned32 d = GPR[rt];
1247     if (d == 0)
1248       {
1249         LO = EXTEND32 (0x80000000);
1250         HI = EXTEND32 (0);
1251       }
1252    else
1253      {
1254        LO = EXTEND32 (n / d);
1255        HI = EXTEND32 (n % d);
1256      }
1257   }
1258   TRACE_ALU_RESULT2 (HI, LO);
1259 }
1260
1261 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1262 "divu r<RS>, r<RT>"
1263 *mipsI,mipsII,mipsIII,mipsIV:
1264 *vr5000:
1265 // start-sanitize-vr4320
1266 *vr4320:
1267 // end-sanitize-vr4320
1268 // start-sanitize-vr5400
1269 *vr5400:
1270 // end-sanitize-vr5400
1271 // start-sanitize-r5900
1272 *r5900:
1273 // end-sanitize-r5900
1274 *r3900:
1275 // start-sanitize-tx19
1276 *tx19:
1277 // end-sanitize-tx19
1278 {
1279   do_divu (SD_, RS, RT);
1280 }
1281
1282
1283
1284 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1285 {
1286   unsigned64 lo;
1287   unsigned64 hi;
1288   unsigned64 m00;
1289   unsigned64 m01;
1290   unsigned64 m10;
1291   unsigned64 m11;
1292   unsigned64 mid;
1293   int sign;
1294   unsigned64 op1 = GPR[rs];
1295   unsigned64 op2 = GPR[rt];
1296   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1297   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1298   /* make signed multiply unsigned */
1299   sign = 0;
1300   if (signed_p)
1301     {
1302       if (op1 < 0)
1303         {
1304           op1 = - op1;
1305           ++sign;
1306         }
1307       if (op2 < 0)
1308         {
1309           op2 = - op2;
1310           ++sign;
1311         }
1312     }
1313   /* multuply out the 4 sub products */
1314   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1315   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1316   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1317   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1318   /* add the products */
1319   mid = ((unsigned64) VH4_8 (m00)
1320          + (unsigned64) VL4_8 (m10)
1321          + (unsigned64) VL4_8 (m01));
1322   lo = U8_4 (mid, m00);
1323   hi = (m11
1324         + (unsigned64) VH4_8 (mid)
1325         + (unsigned64) VH4_8 (m01)
1326         + (unsigned64) VH4_8 (m10));
1327   /* fix the sign */
1328   if (sign & 1)
1329     {
1330       lo = -lo;
1331       if (lo == 0)
1332         hi = -hi;
1333       else
1334         hi = -hi - 1;
1335     }
1336   /* save the result HI/LO (and a gpr) */
1337   LO = lo;
1338   HI = hi;
1339   if (rd != 0)
1340     GPR[rd] = lo;
1341   TRACE_ALU_RESULT2 (HI, LO);
1342 }
1343
1344 :function:::void:do_dmult:int rs, int rt, int rd
1345 {
1346   do_dmultx (SD_, rs, rt, rd, 1);
1347 }
1348
1349 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1350 "dmult r<RS>, r<RT>"
1351 *mipsIII,mipsIV:
1352 // start-sanitize-tx19
1353 *tx19:
1354 // end-sanitize-tx19
1355 // start-sanitize-vr4320
1356 *vr4320:
1357 // end-sanitize-vr4320
1358 {
1359   do_dmult (SD_, RS, RT, 0);
1360 }
1361
1362 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1363 "dmult r<RS>, r<RT>":RD == 0
1364 "dmult r<RD>, r<RS>, r<RT>"
1365 *vr5000:
1366 // start-sanitize-vr5400
1367 *vr5400:
1368 // end-sanitize-vr5400
1369 {
1370   do_dmult (SD_, RS, RT, RD);
1371 }
1372
1373
1374
1375 :function:::void:do_dmultu:int rs, int rt, int rd
1376 {
1377   do_dmultx (SD_, rs, rt, rd, 0);
1378 }
1379
1380 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1381 "dmultu r<RS>, r<RT>"
1382 *mipsIII,mipsIV:
1383 // start-sanitize-tx19
1384 *tx19:
1385 // end-sanitize-tx19
1386 // start-sanitize-vr4320
1387 *vr4320:
1388 // end-sanitize-vr4320
1389 {
1390   do_dmultu (SD_, RS, RT, 0);
1391 }
1392
1393 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1394 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1395 "dmultu r<RS>, r<RT>"
1396 *vr5000:
1397 // start-sanitize-vr5400
1398 *vr5400:
1399 // end-sanitize-vr5400
1400 {
1401   do_dmultu (SD_, RS, RT, RD);
1402 }
1403
1404
1405
1406 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1407 "dsll r<RD>, r<RT>, <SHIFT>"
1408 *mipsIII:
1409 *mipsIV:
1410 *vr5000:
1411 // start-sanitize-vr4320
1412 *vr4320:
1413 // end-sanitize-vr4320
1414 // start-sanitize-vr5400
1415 *vr5400:
1416 // end-sanitize-vr5400
1417 // start-sanitize-r5900
1418 *r5900:
1419 // end-sanitize-r5900
1420 // start-sanitize-tx19
1421 *tx19:
1422 // end-sanitize-tx19
1423 {
1424   int s = SHIFT;
1425   GPR[RD] = GPR[RT] << s;
1426 }
1427
1428
1429 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1430 "dsll32 r<RD>, r<RT>, <SHIFT>"
1431 *mipsIII:
1432 *mipsIV:
1433 *vr5000:
1434 // start-sanitize-vr4320
1435 *vr4320:
1436 // end-sanitize-vr4320
1437 // start-sanitize-vr5400
1438 *vr5400:
1439 // end-sanitize-vr5400
1440 // start-sanitize-r5900
1441 *r5900:
1442 // end-sanitize-r5900
1443 // start-sanitize-tx19
1444 *tx19:
1445 // end-sanitize-tx19
1446 {
1447   int s = 32 + SHIFT;
1448   GPR[RD] = GPR[RT] << s;
1449 }
1450
1451
1452
1453 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1454 "dsllv r<RD>, r<RT>, r<RS>"
1455 *mipsIII:
1456 *mipsIV:
1457 *vr5000:
1458 // start-sanitize-vr4320
1459 *vr4320:
1460 // end-sanitize-vr4320
1461 // start-sanitize-vr5400
1462 *vr5400:
1463 // end-sanitize-vr5400
1464 // start-sanitize-r5900
1465 *r5900:
1466 // end-sanitize-r5900
1467 // start-sanitize-tx19
1468 *tx19:
1469 // end-sanitize-tx19
1470 {
1471   int s = MASKED64 (GPR[RS], 5, 0);
1472   GPR[RD] = GPR[RT] << s;
1473 }
1474
1475
1476
1477 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1478 "dsra r<RD>, r<RT>, <SHIFT>"
1479 *mipsIII:
1480 *mipsIV:
1481 *vr5000:
1482 // start-sanitize-vr4320
1483 *vr4320:
1484 // end-sanitize-vr4320
1485 // start-sanitize-vr5400
1486 *vr5400:
1487 // end-sanitize-vr5400
1488 // start-sanitize-r5900
1489 *r5900:
1490 // end-sanitize-r5900
1491 // start-sanitize-tx19
1492 *tx19:
1493 // end-sanitize-tx19
1494 {
1495   int s = SHIFT;
1496   GPR[RD] = ((signed64) GPR[RT]) >> s;
1497 }
1498
1499
1500 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1501 "dsra32 r<RT>, r<RD>, <SHIFT>"
1502 *mipsIII:
1503 *mipsIV:
1504 *vr5000:
1505 // start-sanitize-vr4320
1506 *vr4320:
1507 // end-sanitize-vr4320
1508 // start-sanitize-vr5400
1509 *vr5400:
1510 // end-sanitize-vr5400
1511 // start-sanitize-r5900
1512 *r5900:
1513 // end-sanitize-r5900
1514 // start-sanitize-tx19
1515 *tx19:
1516 // end-sanitize-tx19
1517 {
1518   int s = 32 + SHIFT;
1519   GPR[RD] = ((signed64) GPR[RT]) >> s;
1520 }
1521
1522
1523 :function:::void:do_dsrav:int rs, int rt, int rd
1524 {
1525   int s = MASKED64 (GPR[rs], 5, 0);
1526   TRACE_ALU_INPUT2 (GPR[rt], s);
1527   GPR[rd] = ((signed64) GPR[rt]) >> s;
1528   TRACE_ALU_RESULT (GPR[rd]);
1529 }
1530
1531 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1532 "dsra32 r<RT>, r<RD>, r<RS>"
1533 *mipsIII:
1534 *mipsIV:
1535 *vr5000:
1536 // start-sanitize-vr4320
1537 *vr4320:
1538 // end-sanitize-vr4320
1539 // start-sanitize-vr5400
1540 *vr5400:
1541 // end-sanitize-vr5400
1542 // start-sanitize-r5900
1543 *r5900:
1544 // end-sanitize-r5900
1545 // start-sanitize-tx19
1546 *tx19:
1547 // end-sanitize-tx19
1548 {
1549   do_dsrav (SD_, RS, RT, RD);
1550 }
1551
1552
1553 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1554 "dsrl r<RD>, r<RT>, <SHIFT>"
1555 *mipsIII:
1556 *mipsIV:
1557 *vr5000:
1558 // start-sanitize-vr4320
1559 *vr4320:
1560 // end-sanitize-vr4320
1561 // start-sanitize-vr5400
1562 *vr5400:
1563 // end-sanitize-vr5400
1564 // start-sanitize-r5900
1565 *r5900:
1566 // end-sanitize-r5900
1567 // start-sanitize-tx19
1568 *tx19:
1569 // end-sanitize-tx19
1570 {
1571   int s = SHIFT;
1572   GPR[RD] = (unsigned64) GPR[RT] >> s;
1573 }
1574
1575
1576 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1577 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1578 *mipsIII:
1579 *mipsIV:
1580 *vr5000:
1581 // start-sanitize-vr4320
1582 *vr4320:
1583 // end-sanitize-vr4320
1584 // start-sanitize-vr5400
1585 *vr5400:
1586 // end-sanitize-vr5400
1587 // start-sanitize-r5900
1588 *r5900:
1589 // end-sanitize-r5900
1590 // start-sanitize-tx19
1591 *tx19:
1592 // end-sanitize-tx19
1593 {
1594   int s = 32 + SHIFT;
1595   GPR[RD] = (unsigned64) GPR[RT] >> s;
1596 }
1597
1598
1599 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1600 "dsrl32 r<RD>, r<RT>, r<RS>"
1601 *mipsIII:
1602 *mipsIV:
1603 *vr5000:
1604 // start-sanitize-vr4320
1605 *vr4320:
1606 // end-sanitize-vr4320
1607 // start-sanitize-vr5400
1608 *vr5400:
1609 // end-sanitize-vr5400
1610 // start-sanitize-r5900
1611 *r5900:
1612 // end-sanitize-r5900
1613 // start-sanitize-tx19
1614 *tx19:
1615 // end-sanitize-tx19
1616 {
1617   int s = MASKED64 (GPR[RS], 5, 0);
1618   GPR[RD] = (unsigned64) GPR[RT] >> s;
1619 }
1620
1621
1622 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1623 "dsub r<RD>, r<RS>, r<RT>"
1624 *mipsIII:
1625 *mipsIV:
1626 *vr5000:
1627 // start-sanitize-vr4320
1628 *vr4320:
1629 // end-sanitize-vr4320
1630 // start-sanitize-vr5400
1631 *vr5400:
1632 // end-sanitize-vr5400
1633 // start-sanitize-r5900
1634 *r5900:
1635 // end-sanitize-r5900
1636 // start-sanitize-tx19
1637 *tx19:
1638 // end-sanitize-tx19
1639 {
1640   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1641   {
1642     ALU64_BEGIN (GPR[RS]);
1643     ALU64_SUB (GPR[RT]);
1644     ALU64_END (GPR[RD]);
1645   }
1646   TRACE_ALU_RESULT (GPR[RD]);
1647 }
1648
1649
1650 :function:::void:do_dsubu:int rs, int rt, int rd
1651 {
1652   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1653   GPR[rd] = GPR[rs] - GPR[rt];
1654   TRACE_ALU_RESULT (GPR[rd]);
1655 }
1656
1657 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1658 "dsubu r<RD>, r<RS>, r<RT>"
1659 *mipsIII:
1660 *mipsIV:
1661 *vr5000:
1662 // start-sanitize-vr4320
1663 *vr4320:
1664 // end-sanitize-vr4320
1665 // start-sanitize-vr5400
1666 *vr5400:
1667 // end-sanitize-vr5400
1668 // start-sanitize-r5900
1669 *r5900:
1670 // end-sanitize-r5900
1671 // start-sanitize-tx19
1672 *tx19:
1673 // end-sanitize-tx19
1674 {
1675   do_dsubu (SD_, RS, RT, RD);
1676 }
1677
1678
1679 000010,26.INSTR_INDEX:NORMAL:32::J
1680 "j <INSTR_INDEX>"
1681 *mipsI,mipsII,mipsIII,mipsIV:
1682 *vr5000:
1683 // start-sanitize-vr4320
1684 *vr4320:
1685 // end-sanitize-vr4320
1686 // start-sanitize-vr5400
1687 *vr5400:
1688 // end-sanitize-vr5400
1689 // start-sanitize-r5900
1690 *r5900:
1691 // end-sanitize-r5900
1692 *r3900:
1693 // start-sanitize-tx19
1694 *tx19:
1695 // end-sanitize-tx19
1696 {
1697   /* NOTE: The region used is that of the delay slot NIA and NOT the
1698      current instruction */
1699   address_word region = (NIA & MASK (63, 28));
1700   DELAY_SLOT (region | (INSTR_INDEX << 2));
1701 }
1702
1703
1704 000011,26.INSTR_INDEX:NORMAL:32::JAL
1705 "jal <INSTR_INDEX>"
1706 *mipsI,mipsII,mipsIII,mipsIV:
1707 *vr5000:
1708 // start-sanitize-vr4320
1709 *vr4320:
1710 // end-sanitize-vr4320
1711 // start-sanitize-vr5400
1712 *vr5400:
1713 // end-sanitize-vr5400
1714 // start-sanitize-r5900
1715 *r5900:
1716 // end-sanitize-r5900
1717 *r3900:
1718 // start-sanitize-tx19
1719 *tx19:
1720 // end-sanitize-tx19
1721 {
1722   /* NOTE: The region used is that of the delay slot and NOT the
1723      current instruction */
1724   address_word region = (NIA & MASK (63, 28));
1725   GPR[31] = CIA + 8;
1726   DELAY_SLOT (region | (INSTR_INDEX << 2));
1727 }
1728
1729
1730 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1731 "jalr r<RS>":RD == 31
1732 "jalr r<RD>, r<RS>"
1733 *mipsI,mipsII,mipsIII,mipsIV:
1734 *vr5000:
1735 // start-sanitize-vr4320
1736 *vr4320:
1737 // end-sanitize-vr4320
1738 // start-sanitize-vr5400
1739 *vr5400:
1740 // end-sanitize-vr5400
1741 // start-sanitize-r5900
1742 *r5900:
1743 // end-sanitize-r5900
1744 *r3900:
1745 // start-sanitize-tx19
1746 *tx19:
1747 // end-sanitize-tx19
1748 {
1749   address_word temp = GPR[RS];
1750   GPR[RD] = CIA + 8;
1751   DELAY_SLOT (temp);
1752 }
1753
1754
1755 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1756 "jr r<RS>"
1757 *mipsI,mipsII,mipsIII,mipsIV:
1758 *vr5000:
1759 // start-sanitize-vr4320
1760 *vr4320:
1761 // end-sanitize-vr4320
1762 // start-sanitize-vr5400
1763 *vr5400:
1764 // end-sanitize-vr5400
1765 // start-sanitize-r5900
1766 *r5900:
1767 // end-sanitize-r5900
1768 *r3900:
1769 // start-sanitize-tx19
1770 *tx19:
1771 // end-sanitize-tx19
1772 {
1773   DELAY_SLOT (GPR[RS]);
1774 }
1775
1776
1777 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1778 {
1779   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1780   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1781   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1782   unsigned int byte;
1783   address_word paddr;
1784   int uncached;
1785   unsigned64 memval;
1786   address_word vaddr;
1787
1788   vaddr = base + offset;
1789   if ((vaddr & access) != 0)
1790     SignalExceptionAddressLoad ();
1791   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1792   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1793   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1794   byte = ((vaddr & mask) ^ bigendiancpu);
1795   return (memval >> (8 * byte));
1796 }
1797
1798
1799 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1800 "lb r<RT>, <OFFSET>(r<BASE>)"
1801 *mipsI,mipsII,mipsIII,mipsIV:
1802 *vr5000:
1803 // start-sanitize-vr4320
1804 *vr4320:
1805 // end-sanitize-vr4320
1806 // start-sanitize-vr5400
1807 *vr5400:
1808 // end-sanitize-vr5400
1809 // start-sanitize-r5900
1810 *r5900:
1811 // end-sanitize-r5900
1812 *r3900:
1813 // start-sanitize-tx19
1814 *tx19:
1815 // end-sanitize-tx19
1816 {
1817   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1818 }
1819
1820
1821 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1822 "lbu r<RT>, <OFFSET>(r<BASE>)"
1823 *mipsI,mipsII,mipsIII,mipsIV:
1824 *vr5000:
1825 // start-sanitize-vr4320
1826 *vr4320:
1827 // end-sanitize-vr4320
1828 // start-sanitize-vr5400
1829 *vr5400:
1830 // end-sanitize-vr5400
1831 // start-sanitize-r5900
1832 *r5900:
1833 // end-sanitize-r5900
1834 *r3900:
1835 // start-sanitize-tx19
1836 *tx19:
1837 // end-sanitize-tx19
1838 {
1839   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1840 }
1841
1842
1843 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1844 "ld r<RT>, <OFFSET>(r<BASE>)"
1845 *mipsIII:
1846 *mipsIV:
1847 *vr5000:
1848 // start-sanitize-vr4320
1849 *vr4320:
1850 // end-sanitize-vr4320
1851 // start-sanitize-vr5400
1852 *vr5400:
1853 // end-sanitize-vr5400
1854 // start-sanitize-r5900
1855 *r5900:
1856 // end-sanitize-r5900
1857 // start-sanitize-tx19
1858 *tx19:
1859 // end-sanitize-tx19
1860 {
1861   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1862 }
1863
1864
1865 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1866 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1867 *mipsII:
1868 *mipsIII:
1869 *mipsIV:
1870 *vr5000:
1871 // start-sanitize-vr4320
1872 *vr4320:
1873 // end-sanitize-vr4320
1874 // start-sanitize-vr5400
1875 *vr5400:
1876 // end-sanitize-vr5400
1877 *r3900:
1878 // start-sanitize-tx19
1879 *tx19:
1880 // end-sanitize-tx19
1881 {
1882   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1883 }
1884
1885
1886
1887
1888 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1889 "ldl r<RT>, <OFFSET>(r<BASE>)"
1890 *mipsIII:
1891 *mipsIV:
1892 *vr5000:
1893 // start-sanitize-vr4320
1894 *vr4320:
1895 // end-sanitize-vr4320
1896 // start-sanitize-vr5400
1897 *vr5400:
1898 // end-sanitize-vr5400
1899 // start-sanitize-r5900
1900 *r5900:
1901 // end-sanitize-r5900
1902 // start-sanitize-tx19
1903 *tx19:
1904 // end-sanitize-tx19
1905 {
1906   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1907 }
1908
1909
1910 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1911 "ldr r<RT>, <OFFSET>(r<BASE>)"
1912 *mipsIII:
1913 *mipsIV:
1914 *vr5000:
1915 // start-sanitize-vr4320
1916 *vr4320:
1917 // end-sanitize-vr4320
1918 // start-sanitize-vr5400
1919 *vr5400:
1920 // end-sanitize-vr5400
1921 // start-sanitize-r5900
1922 *r5900:
1923 // end-sanitize-r5900
1924 // start-sanitize-tx19
1925 *tx19:
1926 // end-sanitize-tx19
1927 {
1928   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1929 }
1930
1931
1932 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1933 "lh r<RT>, <OFFSET>(r<BASE>)"
1934 *mipsI,mipsII,mipsIII,mipsIV:
1935 *vr5000:
1936 // start-sanitize-vr4320
1937 *vr4320:
1938 // end-sanitize-vr4320
1939 // start-sanitize-vr5400
1940 *vr5400:
1941 // end-sanitize-vr5400
1942 // start-sanitize-r5900
1943 *r5900:
1944 // end-sanitize-r5900
1945 *r3900:
1946 // start-sanitize-tx19
1947 *tx19:
1948 // end-sanitize-tx19
1949 {
1950   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1951 }
1952
1953
1954 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1955 "lhu r<RT>, <OFFSET>(r<BASE>)"
1956 *mipsI,mipsII,mipsIII,mipsIV:
1957 *vr5000:
1958 // start-sanitize-vr4320
1959 *vr4320:
1960 // end-sanitize-vr4320
1961 // start-sanitize-vr5400
1962 *vr5400:
1963 // end-sanitize-vr5400
1964 // start-sanitize-r5900
1965 *r5900:
1966 // end-sanitize-r5900
1967 *r3900:
1968 // start-sanitize-tx19
1969 *tx19:
1970 // end-sanitize-tx19
1971 {
1972   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1973 }
1974
1975
1976 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1977 "ll r<RT>, <OFFSET>(r<BASE>)"
1978 *mipsII:
1979 *mipsIII:
1980 *mipsIV:
1981 *vr5000:
1982 // start-sanitize-vr4320
1983 *vr4320:
1984 // end-sanitize-vr4320
1985 // start-sanitize-vr5400
1986 *vr5400:
1987 // end-sanitize-vr5400
1988 // start-sanitize-r5900
1989 *r5900:
1990 // end-sanitize-r5900
1991 // start-sanitize-tx19
1992 *tx19:
1993 // end-sanitize-tx19
1994 {
1995   unsigned32 instruction = instruction_0;
1996   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1997   int destreg = ((instruction >> 16) & 0x0000001F);
1998   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1999   {
2000     address_word vaddr = ((unsigned64)op1 + offset);
2001     address_word paddr;
2002     int uncached;
2003     if ((vaddr & 3) != 0)
2004       SignalExceptionAddressLoad();
2005     else
2006       {
2007         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2008           {
2009             unsigned64 memval = 0;
2010             unsigned64 memval1 = 0;
2011             unsigned64 mask = 0x7;
2012             unsigned int shift = 2;
2013             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2014             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2015             unsigned int byte;
2016             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2017             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2018             byte = ((vaddr & mask) ^ (bigend << shift));
2019             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2020             LLBIT = 1;
2021           }
2022       }
2023   }
2024 }
2025
2026
2027 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2028 "lld r<RT>, <OFFSET>(r<BASE>)"
2029 *mipsIII:
2030 *mipsIV:
2031 *vr5000:
2032 // start-sanitize-vr4320
2033 *vr4320:
2034 // end-sanitize-vr4320
2035 // start-sanitize-vr5400
2036 *vr5400:
2037 // end-sanitize-vr5400
2038 // start-sanitize-r5900
2039 *r5900:
2040 // end-sanitize-r5900
2041 // start-sanitize-tx19
2042 *tx19:
2043 // end-sanitize-tx19
2044 {
2045   unsigned32 instruction = instruction_0;
2046   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2047   int destreg = ((instruction >> 16) & 0x0000001F);
2048   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2049   {
2050     address_word vaddr = ((unsigned64)op1 + offset);
2051     address_word paddr;
2052     int uncached;
2053     if ((vaddr & 7) != 0)
2054       SignalExceptionAddressLoad();
2055     else
2056       {
2057         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2058           {
2059             unsigned64 memval = 0;
2060             unsigned64 memval1 = 0;
2061             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2062             GPR[destreg] = memval;
2063             LLBIT = 1;
2064           }
2065       }
2066   }
2067 }
2068
2069
2070 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2071 "lui r<RT>, <IMMEDIATE>"
2072 *mipsI,mipsII,mipsIII,mipsIV:
2073 *vr5000:
2074 // start-sanitize-vr4320
2075 *vr4320:
2076 // end-sanitize-vr4320
2077 // start-sanitize-vr5400
2078 *vr5400:
2079 // end-sanitize-vr5400
2080 // start-sanitize-r5900
2081 *r5900:
2082 // end-sanitize-r5900
2083 *r3900:
2084 // start-sanitize-tx19
2085 *tx19:
2086 // end-sanitize-tx19
2087 {
2088   TRACE_ALU_INPUT1 (IMMEDIATE);
2089   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2090   TRACE_ALU_RESULT (GPR[RT]);
2091 }
2092
2093
2094 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2095 "lw r<RT>, <OFFSET>(r<BASE>)"
2096 *mipsI,mipsII,mipsIII,mipsIV:
2097 *vr5000:
2098 // start-sanitize-vr4320
2099 *vr4320:
2100 // end-sanitize-vr4320
2101 // start-sanitize-vr5400
2102 *vr5400:
2103 // end-sanitize-vr5400
2104 // start-sanitize-r5900
2105 *r5900:
2106 // end-sanitize-r5900
2107 *r3900:
2108 // start-sanitize-tx19
2109 *tx19:
2110 // end-sanitize-tx19
2111 {
2112   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2113 }
2114
2115
2116 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2117 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2118 *mipsI,mipsII,mipsIII,mipsIV:
2119 *vr5000:
2120 // start-sanitize-vr4320
2121 *vr4320:
2122 // end-sanitize-vr4320
2123 // start-sanitize-vr5400
2124 *vr5400:
2125 // end-sanitize-vr5400
2126 // start-sanitize-r5900
2127 *r5900:
2128 // end-sanitize-r5900
2129 *r3900:
2130 // start-sanitize-tx19
2131 *tx19:
2132 // end-sanitize-tx19
2133 {
2134   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2135 }
2136
2137
2138 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2139 {
2140   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2141   address_word reverseendian = (ReverseEndian ? -1 : 0);
2142   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2143   unsigned int byte;
2144   unsigned int word;
2145   address_word paddr;
2146   int uncached;
2147   unsigned64 memval;
2148   address_word vaddr;
2149   int nr_lhs_bits;
2150   int nr_rhs_bits;
2151   unsigned_word lhs_mask;
2152   unsigned_word temp;
2153
2154   vaddr = base + offset;
2155   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2156   paddr = (paddr ^ (reverseendian & mask));
2157   if (BigEndianMem == 0)
2158     paddr = paddr & ~access;
2159
2160   /* compute where within the word/mem we are */
2161   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2162   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2163   nr_lhs_bits = 8 * byte + 8;
2164   nr_rhs_bits = 8 * access - 8 * byte;
2165   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2166
2167   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2168            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2169            (long) ((unsigned64) paddr >> 32), (long) paddr,
2170            word, byte, nr_lhs_bits, nr_rhs_bits); */
2171
2172   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2173   if (word == 0)
2174     {
2175       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2176       temp = (memval << nr_rhs_bits);
2177     }
2178   else
2179     {
2180       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2181       temp = (memval >> nr_lhs_bits);
2182     }
2183   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2184   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2185
2186   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2187            (long) ((unsigned64) memval >> 32), (long) memval,
2188            (long) ((unsigned64) temp >> 32), (long) temp,
2189            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2190            (long) (rt >> 32), (long) rt); */
2191   return rt;
2192 }
2193
2194
2195 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2196 "lwl r<RT>, <OFFSET>(r<BASE>)"
2197 *mipsI,mipsII,mipsIII,mipsIV:
2198 *vr5000:
2199 // start-sanitize-vr4320
2200 *vr4320:
2201 // end-sanitize-vr4320
2202 // start-sanitize-vr5400
2203 *vr5400:
2204 // end-sanitize-vr5400
2205 // start-sanitize-r5900
2206 *r5900:
2207 // end-sanitize-r5900
2208 *r3900:
2209 // start-sanitize-tx19
2210 *tx19:
2211 // end-sanitize-tx19
2212 {
2213   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2214 }
2215
2216
2217 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2218 {
2219   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2220   address_word reverseendian = (ReverseEndian ? -1 : 0);
2221   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2222   unsigned int byte;
2223   address_word paddr;
2224   int uncached;
2225   unsigned64 memval;
2226   address_word vaddr;
2227
2228   vaddr = base + offset;
2229   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2230   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2231   paddr = (paddr ^ (reverseendian & mask));
2232   if (BigEndianMem != 0)
2233     paddr = paddr & ~access;
2234   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2235   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2236   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2237   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2238      (long) paddr, byte, (long) paddr, (long) memval); */
2239   {
2240     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2241     rt &= ~screen;
2242     rt |= (memval >> (8 * byte)) & screen;
2243   }
2244   return rt;
2245 }
2246
2247
2248 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2249 "lwr r<RT>, <OFFSET>(r<BASE>)"
2250 *mipsI,mipsII,mipsIII,mipsIV:
2251 *vr5000:
2252 // start-sanitize-vr4320
2253 *vr4320:
2254 // end-sanitize-vr4320
2255 // start-sanitize-vr5400
2256 *vr5400:
2257 // end-sanitize-vr5400
2258 // start-sanitize-r5900
2259 *r5900:
2260 // end-sanitize-r5900
2261 *r3900:
2262 // start-sanitize-tx19
2263 *tx19:
2264 // end-sanitize-tx19
2265 {
2266   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2267 }
2268
2269
2270 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2271 "lwu r<RT>, <OFFSET>(r<BASE>)"
2272 *mipsIII:
2273 *mipsIV:
2274 *vr5000:
2275 // start-sanitize-vr4320
2276 *vr4320:
2277 // end-sanitize-vr4320
2278 // start-sanitize-vr5400
2279 *vr5400:
2280 // end-sanitize-vr5400
2281 // start-sanitize-r5900
2282 *r5900:
2283 // end-sanitize-r5900
2284 // start-sanitize-tx19
2285 *tx19:
2286 // end-sanitize-tx19
2287 {
2288   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2289 }
2290
2291
2292 :function:::void:do_mfhi:int rd
2293 {
2294   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2295   TRACE_ALU_INPUT1 (HI);
2296   GPR[rd] = HI;
2297   TRACE_ALU_RESULT (GPR[rd]);
2298 }
2299
2300 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2301 "mfhi r<RD>"
2302 *mipsI,mipsII,mipsIII,mipsIV:
2303 *vr5000:
2304 // start-sanitize-vr4320
2305 *vr4320:
2306 // end-sanitize-vr4320
2307 // start-sanitize-vr5400
2308 *vr5400:
2309 // end-sanitize-vr5400
2310 // start-sanitize-r5900
2311 *r5900:
2312 // end-sanitize-r5900
2313 *r3900:
2314 // start-sanitize-tx19
2315 *tx19:
2316 // end-sanitize-tx19
2317 {
2318   do_mfhi (SD_, RD);
2319 }
2320
2321
2322
2323 :function:::void:do_mflo:int rd
2324 {
2325   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2326   TRACE_ALU_INPUT1 (LO);
2327   GPR[rd] = LO;
2328   TRACE_ALU_RESULT (GPR[rd]);
2329 }
2330
2331 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2332 "mflo r<RD>"
2333 *mipsI,mipsII,mipsIII,mipsIV:
2334 *vr5000:
2335 // start-sanitize-vr4320
2336 *vr4320:
2337 // end-sanitize-vr4320
2338 // start-sanitize-vr5400
2339 *vr5400:
2340 // end-sanitize-vr5400
2341 // start-sanitize-r5900
2342 *r5900:
2343 // end-sanitize-r5900
2344 *r3900:
2345 // start-sanitize-tx19
2346 *tx19:
2347 // end-sanitize-tx19
2348 {
2349   do_mflo (SD_, RD);
2350 }
2351
2352
2353
2354 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2355 "movn r<RD>, r<RS>, r<RT>"
2356 *mipsIV:
2357 *vr5000:
2358 // start-sanitize-vr4320
2359 *vr4320:
2360 // end-sanitize-vr4320
2361 // start-sanitize-vr5400
2362 *vr5400:
2363 // end-sanitize-vr5400
2364 // start-sanitize-r5900
2365 *r5900:
2366 // end-sanitize-r5900
2367 {
2368   if (GPR[RT] != 0)
2369     GPR[RD] = GPR[RS];
2370 }
2371
2372
2373
2374 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2375 "movz r<RD>, r<RS>, r<RT>"
2376 *mipsIV:
2377 *vr5000:
2378 // start-sanitize-vr4320
2379 *vr4320:
2380 // end-sanitize-vr4320
2381 // start-sanitize-vr5400
2382 *vr5400:
2383 // end-sanitize-vr5400
2384 // start-sanitize-r5900
2385 *r5900:
2386 // end-sanitize-r5900
2387 {
2388   if (GPR[RT] == 0)
2389     GPR[RD] = GPR[RS];
2390 }
2391
2392
2393
2394 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2395 "mthi r<RS>"
2396 *mipsI,mipsII,mipsIII,mipsIV:
2397 *vr5000:
2398 // start-sanitize-vr4320
2399 *vr4320:
2400 // end-sanitize-vr4320
2401 // start-sanitize-vr5400
2402 *vr5400:
2403 // end-sanitize-vr5400
2404 // start-sanitize-r5900
2405 *r5900:
2406 // end-sanitize-r5900
2407 *r3900:
2408 // start-sanitize-tx19
2409 *tx19:
2410 // end-sanitize-tx19
2411 {
2412   check_mt_hilo (SD_, HIHISTORY);
2413   HI = GPR[RS];
2414 }
2415
2416
2417
2418 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2419 "mtlo r<RS>"
2420 *mipsI,mipsII,mipsIII,mipsIV:
2421 *vr5000:
2422 // start-sanitize-vr4320
2423 *vr4320:
2424 // end-sanitize-vr4320
2425 // start-sanitize-vr5400
2426 *vr5400:
2427 // end-sanitize-vr5400
2428 // start-sanitize-r5900
2429 *r5900:
2430 // end-sanitize-r5900
2431 *r3900:
2432 // start-sanitize-tx19
2433 *tx19:
2434 // end-sanitize-tx19
2435 {
2436   check_mt_hilo (SD_, LOHISTORY);
2437   LO = GPR[RS];
2438 }
2439
2440
2441
2442 :function:::void:do_mult:int rs, int rt, int rd
2443 {
2444   signed64 prod;
2445   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2446   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2447   prod = (((signed64)(signed32) GPR[rs])
2448           * ((signed64)(signed32) GPR[rt]));
2449   LO = EXTEND32 (VL4_8 (prod));
2450   HI = EXTEND32 (VH4_8 (prod));
2451   if (rd != 0)
2452     GPR[rd] = LO;
2453   TRACE_ALU_RESULT2 (HI, LO);
2454 }
2455
2456 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2457 "mult r<RS>, r<RT>"
2458 *mipsI,mipsII,mipsIII,mipsIV:
2459 // start-sanitize-vr4320
2460 *vr4320:
2461 // end-sanitize-vr4320
2462 {
2463   do_mult (SD_, RS, RT, 0);
2464 }
2465
2466
2467 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2468 "mult r<RD>, r<RS>, r<RT>"
2469 *vr5000:
2470 // start-sanitize-vr5400
2471 *vr5400:
2472 // end-sanitize-vr5400
2473 // start-sanitize-r5900
2474 *r5900:
2475 // end-sanitize-r5900
2476 *r3900:
2477 // start-sanitize-tx19
2478 *tx19:
2479 // end-sanitize-tx19
2480 {
2481   do_mult (SD_, RS, RT, RD);
2482 }
2483
2484
2485 :function:::void:do_multu:int rs, int rt, int rd
2486 {
2487   unsigned64 prod;
2488   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2489   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2490   prod = (((unsigned64)(unsigned32) GPR[rs])
2491           * ((unsigned64)(unsigned32) GPR[rt]));
2492   LO = EXTEND32 (VL4_8 (prod));
2493   HI = EXTEND32 (VH4_8 (prod));
2494   if (rd != 0)
2495     GPR[rd] = LO;
2496   TRACE_ALU_RESULT2 (HI, LO);
2497 }
2498
2499 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2500 "multu r<RS>, r<RT>"
2501 *mipsI,mipsII,mipsIII,mipsIV:
2502 // start-sanitize-vr4320
2503 *vr4320:
2504 // end-sanitize-vr4320
2505 {
2506   do_multu (SD_, RS, RT, 0);
2507 }
2508
2509 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2510 "multu r<RD>, r<RS>, r<RT>"
2511 *vr5000:
2512 // start-sanitize-vr5400
2513 *vr5400:
2514 // end-sanitize-vr5400
2515 // start-sanitize-r5900
2516 *r5900:
2517 // end-sanitize-r5900
2518 *r3900:
2519 // start-sanitize-tx19
2520 *tx19:
2521 // end-sanitize-tx19
2522 {
2523   do_multu (SD_, RS, RT, 0);
2524 }
2525
2526
2527 :function:::void:do_nor:int rs, int rt, int rd
2528 {
2529   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2530   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2531   TRACE_ALU_RESULT (GPR[rd]);
2532 }
2533
2534 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2535 "nor r<RD>, r<RS>, r<RT>"
2536 *mipsI,mipsII,mipsIII,mipsIV:
2537 *vr5000:
2538 // start-sanitize-vr4320
2539 *vr4320:
2540 // end-sanitize-vr4320
2541 // start-sanitize-vr5400
2542 *vr5400:
2543 // end-sanitize-vr5400
2544 // start-sanitize-r5900
2545 *r5900:
2546 // end-sanitize-r5900
2547 *r3900:
2548 // start-sanitize-tx19
2549 *tx19:
2550 // end-sanitize-tx19
2551 {
2552   do_nor (SD_, RS, RT, RD);
2553 }
2554
2555
2556 :function:::void:do_or:int rs, int rt, int rd
2557 {
2558   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2559   GPR[rd] = (GPR[rs] | GPR[rt]);
2560   TRACE_ALU_RESULT (GPR[rd]);
2561 }
2562
2563 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2564 "or r<RD>, r<RS>, r<RT>"
2565 *mipsI,mipsII,mipsIII,mipsIV:
2566 *vr5000:
2567 // start-sanitize-vr4320
2568 *vr4320:
2569 // end-sanitize-vr4320
2570 // start-sanitize-vr5400
2571 *vr5400:
2572 // end-sanitize-vr5400
2573 // start-sanitize-r5900
2574 *r5900:
2575 // end-sanitize-r5900
2576 *r3900:
2577 // start-sanitize-tx19
2578 *tx19:
2579 // end-sanitize-tx19
2580 {
2581   do_or (SD_, RS, RT, RD);
2582 }
2583
2584
2585
2586 :function:::void:do_ori:int rs, int rt, unsigned immediate
2587 {
2588   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2589   GPR[rt] = (GPR[rs] | immediate);
2590   TRACE_ALU_RESULT (GPR[rt]);
2591 }
2592
2593 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2594 "ori r<RT>, r<RS>, <IMMEDIATE>"
2595 *mipsI,mipsII,mipsIII,mipsIV:
2596 *vr5000:
2597 // start-sanitize-vr4320
2598 *vr4320:
2599 // end-sanitize-vr4320
2600 // start-sanitize-vr5400
2601 *vr5400:
2602 // end-sanitize-vr5400
2603 // start-sanitize-r5900
2604 *r5900:
2605 // end-sanitize-r5900
2606 *r3900:
2607 // start-sanitize-tx19
2608 *tx19:
2609 // end-sanitize-tx19
2610 {
2611   do_ori (SD_, RS, RT, IMMEDIATE);
2612 }
2613
2614
2615 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2616 *mipsIV:
2617 *vr5000:
2618 // start-sanitize-vr4320
2619 *vr4320:
2620 // end-sanitize-vr4320
2621 // start-sanitize-vr5400
2622 *vr5400:
2623 // end-sanitize-vr5400
2624 // start-sanitize-r5900
2625 *r5900:
2626 // end-sanitize-r5900
2627 {
2628   unsigned32 instruction = instruction_0;
2629   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2630   int hint = ((instruction >> 16) & 0x0000001F);
2631   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2632   {
2633     address_word vaddr = ((unsigned64)op1 + offset);
2634     address_word paddr;
2635     int uncached;
2636     {
2637       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2638         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2639     }
2640   }
2641 }
2642
2643 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2644 {
2645   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2646   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2647   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2648   unsigned int byte;
2649   address_word paddr;
2650   int uncached;
2651   unsigned64 memval;
2652   address_word vaddr;
2653
2654   vaddr = base + offset;
2655   if ((vaddr & access) != 0)
2656     SignalExceptionAddressStore ();
2657   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2658   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2659   byte = ((vaddr & mask) ^ bigendiancpu);
2660   memval = (word << (8 * byte));
2661   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2662 }
2663
2664
2665 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2666 "sb r<RT>, <OFFSET>(r<BASE>)"
2667 *mipsI,mipsII,mipsIII,mipsIV:
2668 *vr5000:
2669 // start-sanitize-vr4320
2670 *vr4320:
2671 // end-sanitize-vr4320
2672 // start-sanitize-vr5400
2673 *vr5400:
2674 // end-sanitize-vr5400
2675 // start-sanitize-r5900
2676 *r5900:
2677 // end-sanitize-r5900
2678 *r3900:
2679 // start-sanitize-tx19
2680 *tx19:
2681 // end-sanitize-tx19
2682 {
2683   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2684 }
2685
2686
2687 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2688 "sc r<RT>, <OFFSET>(r<BASE>)"
2689 *mipsII:
2690 *mipsIII:
2691 *mipsIV:
2692 *vr5000:
2693 // start-sanitize-vr4320
2694 *vr4320:
2695 // end-sanitize-vr4320
2696 // start-sanitize-vr5400
2697 *vr5400:
2698 // end-sanitize-vr5400
2699 // start-sanitize-r5900
2700 *r5900:
2701 // end-sanitize-r5900
2702 // start-sanitize-tx19
2703 *tx19:
2704 // end-sanitize-tx19
2705 {
2706   unsigned32 instruction = instruction_0;
2707   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2708   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2709   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2710   {
2711     address_word vaddr = ((unsigned64)op1 + offset);
2712     address_word paddr;
2713     int uncached;
2714     if ((vaddr & 3) != 0)
2715       SignalExceptionAddressStore();
2716     else
2717       {
2718         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2719           {
2720             unsigned64 memval = 0;
2721             unsigned64 memval1 = 0;
2722             unsigned64 mask = 0x7;
2723             unsigned int byte;
2724             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2725             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2726             memval = ((unsigned64) op2 << (8 * byte));
2727             if (LLBIT)
2728               {
2729                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2730               }
2731             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2732           }
2733       }
2734   }
2735 }
2736
2737
2738 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2739 "scd r<RT>, <OFFSET>(r<BASE>)"
2740 *mipsIII:
2741 *mipsIV:
2742 *vr5000:
2743 // start-sanitize-vr4320
2744 *vr4320:
2745 // end-sanitize-vr4320
2746 // start-sanitize-vr5400
2747 *vr5400:
2748 // end-sanitize-vr5400
2749 // start-sanitize-r5900
2750 *r5900:
2751 // end-sanitize-r5900
2752 // start-sanitize-tx19
2753 *tx19:
2754 // end-sanitize-tx19
2755 {
2756   unsigned32 instruction = instruction_0;
2757   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2758   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2759   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2760   {
2761     address_word vaddr = ((unsigned64)op1 + offset);
2762     address_word paddr;
2763     int uncached;
2764     if ((vaddr & 7) != 0)
2765       SignalExceptionAddressStore();
2766     else
2767       {
2768         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2769           {
2770             unsigned64 memval = 0;
2771             unsigned64 memval1 = 0;
2772             memval = op2;
2773             if (LLBIT)
2774               {
2775                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2776               }
2777             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2778           }
2779       }
2780   }
2781 }
2782
2783
2784 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2785 "sd r<RT>, <OFFSET>(r<BASE>)"
2786 *mipsIII:
2787 *mipsIV:
2788 *vr5000:
2789 // start-sanitize-vr4320
2790 *vr4320:
2791 // end-sanitize-vr4320
2792 // start-sanitize-vr5400
2793 *vr5400:
2794 // end-sanitize-vr5400
2795 // start-sanitize-r5900
2796 *r5900:
2797 // end-sanitize-r5900
2798 // start-sanitize-tx19
2799 *tx19:
2800 // end-sanitize-tx19
2801 {
2802   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2803 }
2804
2805
2806 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2807 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2808 *mipsII:
2809 *mipsIII:
2810 *mipsIV:
2811 *vr5000:
2812 // start-sanitize-vr4320
2813 *vr4320:
2814 // end-sanitize-vr4320
2815 // start-sanitize-vr5400
2816 *vr5400:
2817 // end-sanitize-vr5400
2818 // start-sanitize-r5900
2819 *r5900:
2820 // end-sanitize-r5900
2821 // start-sanitize-tx19
2822 *tx19:
2823 // end-sanitize-tx19
2824 {
2825   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2826 }
2827
2828
2829 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2830 "sdl r<RT>, <OFFSET>(r<BASE>)"
2831 *mipsIII:
2832 *mipsIV:
2833 *vr5000:
2834 // start-sanitize-vr4320
2835 *vr4320:
2836 // end-sanitize-vr4320
2837 // start-sanitize-vr5400
2838 *vr5400:
2839 // end-sanitize-vr5400
2840 // start-sanitize-r5900
2841 *r5900:
2842 // end-sanitize-r5900
2843 // start-sanitize-tx19
2844 *tx19:
2845 // end-sanitize-tx19
2846 {
2847   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2848 }
2849
2850
2851 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2852 "sdr r<RT>, <OFFSET>(r<BASE>)"
2853 *mipsIII:
2854 *mipsIV:
2855 *vr5000:
2856 // start-sanitize-vr4320
2857 *vr4320:
2858 // end-sanitize-vr4320
2859 // start-sanitize-vr5400
2860 *vr5400:
2861 // end-sanitize-vr5400
2862 // start-sanitize-r5900
2863 *r5900:
2864 // end-sanitize-r5900
2865 // start-sanitize-tx19
2866 *tx19:
2867 // end-sanitize-tx19
2868 {
2869   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2870 }
2871
2872
2873 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2874 "sh r<RT>, <OFFSET>(r<BASE>)"
2875 *mipsI,mipsII,mipsIII,mipsIV:
2876 *vr5000:
2877 // start-sanitize-vr4320
2878 *vr4320:
2879 // end-sanitize-vr4320
2880 // start-sanitize-vr5400
2881 *vr5400:
2882 // end-sanitize-vr5400
2883 // start-sanitize-r5900
2884 *r5900:
2885 // end-sanitize-r5900
2886 *r3900:
2887 // start-sanitize-tx19
2888 *tx19:
2889 // end-sanitize-tx19
2890 {
2891   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2892 }
2893
2894
2895 :function:::void:do_sll:int rt, int rd, int shift
2896 {
2897   unsigned32 temp = (GPR[rt] << shift);
2898   TRACE_ALU_INPUT2 (GPR[rt], shift);
2899   GPR[rd] = EXTEND32 (temp);
2900   TRACE_ALU_RESULT (GPR[rd]);
2901 }
2902
2903 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2904 "sll r<RD>, r<RT>, <SHIFT>"
2905 *mipsI,mipsII,mipsIII,mipsIV:
2906 *vr5000:
2907 // start-sanitize-vr4320
2908 *vr4320:
2909 // end-sanitize-vr4320
2910 // start-sanitize-vr5400
2911 *vr5400:
2912 // end-sanitize-vr5400
2913 // start-sanitize-r5900
2914 *r5900:
2915 // end-sanitize-r5900
2916 *r3900:
2917 // start-sanitize-tx19
2918 *tx19:
2919 // end-sanitize-tx19
2920 {
2921   do_sll (SD_, RT, RD, SHIFT);
2922 }
2923
2924
2925 :function:::void:do_sllv:int rs, int rt, int rd
2926 {
2927   int s = MASKED (GPR[rs], 4, 0);
2928   unsigned32 temp = (GPR[rt] << s);
2929   TRACE_ALU_INPUT2 (GPR[rt], s);
2930   GPR[rd] = EXTEND32 (temp);
2931   TRACE_ALU_RESULT (GPR[rd]);
2932 }
2933
2934 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2935 "sllv r<RD>, r<RT>, r<RS>"
2936 *mipsI,mipsII,mipsIII,mipsIV:
2937 *vr5000:
2938 // start-sanitize-vr4320
2939 *vr4320:
2940 // end-sanitize-vr4320
2941 // start-sanitize-vr5400
2942 *vr5400:
2943 // end-sanitize-vr5400
2944 // start-sanitize-r5900
2945 *r5900:
2946 // end-sanitize-r5900
2947 *r3900:
2948 // start-sanitize-tx19
2949 *tx19:
2950 // end-sanitize-tx19
2951 {
2952   do_sllv (SD_, RS, RT, RD);
2953 }
2954
2955
2956 :function:::void:do_slt:int rs, int rt, int rd
2957 {
2958   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2959   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2960   TRACE_ALU_RESULT (GPR[rd]);
2961 }
2962
2963 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2964 "slt r<RD>, r<RS>, r<RT>"
2965 *mipsI,mipsII,mipsIII,mipsIV:
2966 *vr5000:
2967 // start-sanitize-vr4320
2968 *vr4320:
2969 // end-sanitize-vr4320
2970 // start-sanitize-vr5400
2971 *vr5400:
2972 // end-sanitize-vr5400
2973 // start-sanitize-r5900
2974 *r5900:
2975 // end-sanitize-r5900
2976 *r3900:
2977 // start-sanitize-tx19
2978 *tx19:
2979 // end-sanitize-tx19
2980 {
2981   do_slt (SD_, RS, RT, RD);
2982 }
2983
2984
2985 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2986 {
2987   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2988   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2989   TRACE_ALU_RESULT (GPR[rt]);
2990 }
2991
2992 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2993 "slti r<RT>, r<RS>, <IMMEDIATE>"
2994 *mipsI,mipsII,mipsIII,mipsIV:
2995 *vr5000:
2996 // start-sanitize-vr4320
2997 *vr4320:
2998 // end-sanitize-vr4320
2999 // start-sanitize-vr5400
3000 *vr5400:
3001 // end-sanitize-vr5400
3002 // start-sanitize-r5900
3003 *r5900:
3004 // end-sanitize-r5900
3005 *r3900:
3006 // start-sanitize-tx19
3007 *tx19:
3008 // end-sanitize-tx19
3009 {
3010   do_slti (SD_, RS, RT, IMMEDIATE);
3011 }
3012
3013
3014 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3015 {
3016   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3017   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3018   TRACE_ALU_RESULT (GPR[rt]);
3019 }
3020
3021 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3022 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3023 *mipsI,mipsII,mipsIII,mipsIV:
3024 *vr5000:
3025 // start-sanitize-vr4320
3026 *vr4320:
3027 // end-sanitize-vr4320
3028 // start-sanitize-vr5400
3029 *vr5400:
3030 // end-sanitize-vr5400
3031 // start-sanitize-r5900
3032 *r5900:
3033 // end-sanitize-r5900
3034 *r3900:
3035 // start-sanitize-tx19
3036 *tx19:
3037 // end-sanitize-tx19
3038 {
3039   do_sltiu (SD_, RS, RT, IMMEDIATE);
3040 }
3041
3042
3043
3044 :function:::void:do_sltu:int rs, int rt, int rd
3045 {
3046   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3047   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3048   TRACE_ALU_RESULT (GPR[rd]);
3049 }
3050
3051 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3052 "sltu r<RD>, r<RS>, r<RT>"
3053 *mipsI,mipsII,mipsIII,mipsIV:
3054 *vr5000:
3055 // start-sanitize-vr4320
3056 *vr4320:
3057 // end-sanitize-vr4320
3058 // start-sanitize-vr5400
3059 *vr5400:
3060 // end-sanitize-vr5400
3061 // start-sanitize-r5900
3062 *r5900:
3063 // end-sanitize-r5900
3064 *r3900:
3065 // start-sanitize-tx19
3066 *tx19:
3067 // end-sanitize-tx19
3068 {
3069   do_sltu (SD_, RS, RT, RD);
3070 }
3071
3072
3073 :function:::void:do_sra:int rt, int rd, int shift
3074 {
3075   signed32 temp = (signed32) GPR[rt] >> shift;
3076   TRACE_ALU_INPUT2 (GPR[rt], shift);
3077   GPR[rd] = EXTEND32 (temp);
3078   TRACE_ALU_RESULT (GPR[rd]);
3079 }
3080
3081 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3082 "sra r<RD>, r<RT>, <SHIFT>"
3083 *mipsI,mipsII,mipsIII,mipsIV:
3084 *vr5000:
3085 // start-sanitize-vr4320
3086 *vr4320:
3087 // end-sanitize-vr4320
3088 // start-sanitize-vr5400
3089 *vr5400:
3090 // end-sanitize-vr5400
3091 // start-sanitize-r5900
3092 *r5900:
3093 // end-sanitize-r5900
3094 *r3900:
3095 // start-sanitize-tx19
3096 *tx19:
3097 // end-sanitize-tx19
3098 {
3099   do_sra (SD_, RT, RD, SHIFT);
3100 }
3101
3102
3103
3104 :function:::void:do_srav:int rs, int rt, int rd
3105 {
3106   int s = MASKED (GPR[rs], 4, 0);
3107   signed32 temp = (signed32) GPR[rt] >> s;
3108   TRACE_ALU_INPUT2 (GPR[rt], s);
3109   GPR[rd] = EXTEND32 (temp);
3110   TRACE_ALU_RESULT (GPR[rd]);
3111 }
3112
3113 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3114 "srav r<RD>, r<RT>, r<RS>"
3115 *mipsI,mipsII,mipsIII,mipsIV:
3116 *vr5000:
3117 // start-sanitize-vr4320
3118 *vr4320:
3119 // end-sanitize-vr4320
3120 // start-sanitize-vr5400
3121 *vr5400:
3122 // end-sanitize-vr5400
3123 // start-sanitize-r5900
3124 *r5900:
3125 // end-sanitize-r5900
3126 *r3900:
3127 // start-sanitize-tx19
3128 *tx19:
3129 // end-sanitize-tx19
3130 {
3131   do_srav (SD_, RS, RT, RD);
3132 }
3133
3134
3135
3136 :function:::void:do_srl:int rt, int rd, int shift
3137 {
3138   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3139   TRACE_ALU_INPUT2 (GPR[rt], shift);
3140   GPR[rd] = EXTEND32 (temp);
3141   TRACE_ALU_RESULT (GPR[rd]);
3142 }
3143
3144 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3145 "srl r<RD>, r<RT>, <SHIFT>"
3146 *mipsI,mipsII,mipsIII,mipsIV:
3147 *vr5000:
3148 // start-sanitize-vr4320
3149 *vr4320:
3150 // end-sanitize-vr4320
3151 // start-sanitize-vr5400
3152 *vr5400:
3153 // end-sanitize-vr5400
3154 // start-sanitize-r5900
3155 *r5900:
3156 // end-sanitize-r5900
3157 *r3900:
3158 // start-sanitize-tx19
3159 *tx19:
3160 // end-sanitize-tx19
3161 {
3162   do_srl (SD_, RT, RD, SHIFT);
3163 }
3164
3165
3166 :function:::void:do_srlv:int rs, int rt, int rd
3167 {
3168   int s = MASKED (GPR[rs], 4, 0);
3169   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3170   TRACE_ALU_INPUT2 (GPR[rt], s);
3171   GPR[rd] = EXTEND32 (temp);
3172   TRACE_ALU_RESULT (GPR[rd]);
3173 }
3174
3175 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3176 "srlv r<RD>, r<RT>, r<RS>"
3177 *mipsI,mipsII,mipsIII,mipsIV:
3178 *vr5000:
3179 // start-sanitize-vr4320
3180 *vr4320:
3181 // end-sanitize-vr4320
3182 // start-sanitize-vr5400
3183 *vr5400:
3184 // end-sanitize-vr5400
3185 // start-sanitize-r5900
3186 *r5900:
3187 // end-sanitize-r5900
3188 *r3900:
3189 // start-sanitize-tx19
3190 *tx19:
3191 // end-sanitize-tx19
3192 {
3193   do_srlv (SD_, RS, RT, RD);
3194 }
3195
3196
3197 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3198 "sub r<RD>, r<RS>, r<RT>"
3199 *mipsI,mipsII,mipsIII,mipsIV:
3200 *vr5000:
3201 // start-sanitize-vr4320
3202 *vr4320:
3203 // end-sanitize-vr4320
3204 // start-sanitize-vr5400
3205 *vr5400:
3206 // end-sanitize-vr5400
3207 // start-sanitize-r5900
3208 *r5900:
3209 // end-sanitize-r5900
3210 *r3900:
3211 // start-sanitize-tx19
3212 *tx19:
3213 // end-sanitize-tx19
3214 {
3215   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3216   {
3217     ALU32_BEGIN (GPR[RS]);
3218     ALU32_SUB (GPR[RT]);
3219     ALU32_END (GPR[RD]);
3220   }
3221   TRACE_ALU_RESULT (GPR[RD]);
3222 }
3223
3224
3225 :function:::void:do_subu:int rs, int rt, int rd
3226 {
3227   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3228   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3229   TRACE_ALU_RESULT (GPR[rd]);
3230 }
3231
3232 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3233 "subu r<RD>, r<RS>, r<RT>"
3234 *mipsI,mipsII,mipsIII,mipsIV:
3235 *vr5000:
3236 // start-sanitize-vr4320
3237 *vr4320:
3238 // end-sanitize-vr4320
3239 // start-sanitize-vr5400
3240 *vr5400:
3241 // end-sanitize-vr5400
3242 // start-sanitize-r5900
3243 *r5900:
3244 // end-sanitize-r5900
3245 *r3900:
3246 // start-sanitize-tx19
3247 *tx19:
3248 // end-sanitize-tx19
3249 {
3250   do_subu (SD_, RS, RT, RD);
3251 }
3252
3253
3254 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3255 "sw r<RT>, <OFFSET>(r<BASE>)"
3256 *mipsI,mipsII,mipsIII,mipsIV:
3257 // start-sanitize-tx19
3258 *tx19:
3259 // end-sanitize-tx19
3260 *r3900:
3261 // start-sanitize-vr4320
3262 *vr4320:
3263 // end-sanitize-vr4320
3264 *vr5000:
3265 // start-sanitize-vr5400
3266 *vr5400:
3267 // end-sanitize-vr5400
3268 // start-sanitize-r5900
3269 *r5900:
3270 // end-sanitize-r5900
3271 {
3272   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3273 }
3274
3275
3276 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3277 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3278 *mipsI,mipsII,mipsIII,mipsIV:
3279 *vr5000:
3280 // start-sanitize-vr4320
3281 *vr4320:
3282 // end-sanitize-vr4320
3283 // start-sanitize-vr5400
3284 *vr5400:
3285 // end-sanitize-vr5400
3286 *r3900:
3287 // start-sanitize-tx19
3288 *tx19:
3289 // end-sanitize-tx19
3290 {
3291   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3292 }
3293
3294
3295
3296 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3297 {
3298   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3299   address_word reverseendian = (ReverseEndian ? -1 : 0);
3300   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3301   unsigned int byte;
3302   unsigned int word;
3303   address_word paddr;
3304   int uncached;
3305   unsigned64 memval;
3306   address_word vaddr;
3307   int nr_lhs_bits;
3308   int nr_rhs_bits;
3309
3310   vaddr = base + offset;
3311   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3312   paddr = (paddr ^ (reverseendian & mask));
3313   if (BigEndianMem == 0)
3314     paddr = paddr & ~access;
3315
3316   /* compute where within the word/mem we are */
3317   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3318   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3319   nr_lhs_bits = 8 * byte + 8;
3320   nr_rhs_bits = 8 * access - 8 * byte;
3321   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3322   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3323            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3324            (long) ((unsigned64) paddr >> 32), (long) paddr,
3325            word, byte, nr_lhs_bits, nr_rhs_bits); */
3326
3327   if (word == 0)
3328     {
3329       memval = (rt >> nr_rhs_bits);
3330     }
3331   else
3332     {
3333       memval = (rt << nr_lhs_bits);
3334     }
3335   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3336            (long) ((unsigned64) rt >> 32), (long) rt,
3337            (long) ((unsigned64) memval >> 32), (long) memval); */
3338   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3339 }
3340
3341
3342 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3343 "swl r<RT>, <OFFSET>(r<BASE>)"
3344 *mipsI,mipsII,mipsIII,mipsIV:
3345 *vr5000:
3346 // start-sanitize-vr4320
3347 *vr4320:
3348 // end-sanitize-vr4320
3349 // start-sanitize-vr5400
3350 *vr5400:
3351 // end-sanitize-vr5400
3352 // start-sanitize-r5900
3353 *r5900:
3354 // end-sanitize-r5900
3355 *r3900:
3356 // start-sanitize-tx19
3357 *tx19:
3358 // end-sanitize-tx19
3359 {
3360   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3361 }
3362
3363
3364 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3365 {
3366   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3367   address_word reverseendian = (ReverseEndian ? -1 : 0);
3368   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3369   unsigned int byte;
3370   address_word paddr;
3371   int uncached;
3372   unsigned64 memval;
3373   address_word vaddr;
3374
3375   vaddr = base + offset;
3376   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3377   paddr = (paddr ^ (reverseendian & mask));
3378   if (BigEndianMem != 0)
3379     paddr &= ~access;
3380   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3381   memval = (rt << (byte * 8));
3382   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3383 }
3384
3385 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3386 "swr r<RT>, <OFFSET>(r<BASE>)"
3387 *mipsI,mipsII,mipsIII,mipsIV:
3388 *vr5000:
3389 // start-sanitize-vr4320
3390 *vr4320:
3391 // end-sanitize-vr4320
3392 // start-sanitize-vr5400
3393 *vr5400:
3394 // end-sanitize-vr5400
3395 // start-sanitize-r5900
3396 *r5900:
3397 // end-sanitize-r5900
3398 *r3900:
3399 // start-sanitize-tx19
3400 *tx19:
3401 // end-sanitize-tx19
3402 {
3403   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3404 }
3405
3406
3407 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3408 "sync":STYPE == 0
3409 "sync <STYPE>"
3410 *mipsII:
3411 *mipsIII:
3412 *mipsIV:
3413 *vr5000:
3414 // start-sanitize-vr4320
3415 *vr4320:
3416 // end-sanitize-vr4320
3417 // start-sanitize-vr5400
3418 *vr5400:
3419 // end-sanitize-vr5400
3420 // start-sanitize-r5900
3421 *r5900:
3422 // end-sanitize-r5900
3423 *r3900:
3424 // start-sanitize-tx19
3425 *tx19:
3426 // end-sanitize-tx19
3427 {
3428   SyncOperation (STYPE);
3429 }
3430
3431
3432 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3433 "syscall <CODE>"
3434 *mipsI,mipsII,mipsIII,mipsIV:
3435 *vr5000:
3436 // start-sanitize-vr4320
3437 *vr4320:
3438 // end-sanitize-vr4320
3439 // start-sanitize-vr5400
3440 *vr5400:
3441 // end-sanitize-vr5400
3442 // start-sanitize-r5900
3443 *r5900:
3444 // end-sanitize-r5900
3445 *r3900:
3446 // start-sanitize-tx19
3447 *tx19:
3448 // end-sanitize-tx19
3449 {
3450   SignalException(SystemCall, instruction_0);
3451 }
3452
3453
3454 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3455 "teq r<RS>, r<RT>"
3456 *mipsII:
3457 *mipsIII:
3458 *mipsIV:
3459 *vr5000:
3460 // start-sanitize-vr4320
3461 *vr4320:
3462 // end-sanitize-vr4320
3463 // start-sanitize-vr5400
3464 *vr5400:
3465 // end-sanitize-vr5400
3466 // start-sanitize-r5900
3467 *r5900:
3468 // end-sanitize-r5900
3469 // start-sanitize-tx19
3470 *tx19:
3471 // end-sanitize-tx19
3472 {
3473   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3474     SignalException(Trap, instruction_0);
3475 }
3476
3477
3478 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3479 "teqi r<RS>, <IMMEDIATE>"
3480 *mipsII:
3481 *mipsIII:
3482 *mipsIV:
3483 *vr5000:
3484 // start-sanitize-vr4320
3485 *vr4320:
3486 // end-sanitize-vr4320
3487 // start-sanitize-vr5400
3488 *vr5400:
3489 // end-sanitize-vr5400
3490 // start-sanitize-r5900
3491 *r5900:
3492 // end-sanitize-r5900
3493 // start-sanitize-tx19
3494 *tx19:
3495 // end-sanitize-tx19
3496 {
3497   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3498     SignalException(Trap, instruction_0);
3499 }
3500
3501
3502 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3503 "tge r<RS>, r<RT>"
3504 *mipsII:
3505 *mipsIII:
3506 *mipsIV:
3507 *vr5000:
3508 // start-sanitize-vr4320
3509 *vr4320:
3510 // end-sanitize-vr4320
3511 // start-sanitize-vr5400
3512 *vr5400:
3513 // end-sanitize-vr5400
3514 // start-sanitize-r5900
3515 *r5900:
3516 // end-sanitize-r5900
3517 // start-sanitize-tx19
3518 *tx19:
3519 // end-sanitize-tx19
3520 {
3521   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3522     SignalException(Trap, instruction_0);
3523 }
3524
3525
3526 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3527 "tgei r<RS>, <IMMEDIATE>"
3528 *mipsII:
3529 *mipsIII:
3530 *mipsIV:
3531 *vr5000:
3532 // start-sanitize-vr4320
3533 *vr4320:
3534 // end-sanitize-vr4320
3535 // start-sanitize-vr5400
3536 *vr5400:
3537 // end-sanitize-vr5400
3538 // start-sanitize-r5900
3539 *r5900:
3540 // end-sanitize-r5900
3541 // start-sanitize-tx19
3542 *tx19:
3543 // end-sanitize-tx19
3544 {
3545   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3546     SignalException(Trap, instruction_0);
3547 }
3548
3549
3550 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3551 "tgeiu r<RS>, <IMMEDIATE>"
3552 *mipsII:
3553 *mipsIII:
3554 *mipsIV:
3555 *vr5000:
3556 // start-sanitize-vr4320
3557 *vr4320:
3558 // end-sanitize-vr4320
3559 // start-sanitize-vr5400
3560 *vr5400:
3561 // end-sanitize-vr5400
3562 // start-sanitize-r5900
3563 *r5900:
3564 // end-sanitize-r5900
3565 // start-sanitize-tx19
3566 *tx19:
3567 // end-sanitize-tx19
3568 {
3569   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3570     SignalException(Trap, instruction_0);
3571 }
3572
3573
3574 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3575 "tgeu r<RS>, r<RT>"
3576 *mipsII:
3577 *mipsIII:
3578 *mipsIV:
3579 *vr5000:
3580 // start-sanitize-vr4320
3581 *vr4320:
3582 // end-sanitize-vr4320
3583 // start-sanitize-vr5400
3584 *vr5400:
3585 // end-sanitize-vr5400
3586 // start-sanitize-r5900
3587 *r5900:
3588 // end-sanitize-r5900
3589 // start-sanitize-tx19
3590 *tx19:
3591 // end-sanitize-tx19
3592 {
3593   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3594     SignalException(Trap, instruction_0);
3595 }
3596
3597
3598 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3599 "tlt r<RS>, r<RT>"
3600 *mipsII:
3601 *mipsIII:
3602 *mipsIV:
3603 *vr5000:
3604 // start-sanitize-vr4320
3605 *vr4320:
3606 // end-sanitize-vr4320
3607 // start-sanitize-vr5400
3608 *vr5400:
3609 // end-sanitize-vr5400
3610 // start-sanitize-r5900
3611 *r5900:
3612 // end-sanitize-r5900
3613 // start-sanitize-tx19
3614 *tx19:
3615 // end-sanitize-tx19
3616 {
3617   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3618     SignalException(Trap, instruction_0);
3619 }
3620
3621
3622 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3623 "tlti r<RS>, <IMMEDIATE>"
3624 *mipsII:
3625 *mipsIII:
3626 *mipsIV:
3627 *vr5000:
3628 // start-sanitize-vr4320
3629 *vr4320:
3630 // end-sanitize-vr4320
3631 // start-sanitize-vr5400
3632 *vr5400:
3633 // end-sanitize-vr5400
3634 // start-sanitize-r5900
3635 *r5900:
3636 // end-sanitize-r5900
3637 // start-sanitize-tx19
3638 *tx19:
3639 // end-sanitize-tx19
3640 {
3641   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3642     SignalException(Trap, instruction_0);
3643 }
3644
3645
3646 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3647 "tltiu r<RS>, <IMMEDIATE>"
3648 *mipsII:
3649 *mipsIII:
3650 *mipsIV:
3651 *vr5000:
3652 // start-sanitize-vr4320
3653 *vr4320:
3654 // end-sanitize-vr4320
3655 // start-sanitize-vr5400
3656 *vr5400:
3657 // end-sanitize-vr5400
3658 // start-sanitize-r5900
3659 *r5900:
3660 // end-sanitize-r5900
3661 // start-sanitize-tx19
3662 *tx19:
3663 // end-sanitize-tx19
3664 {
3665   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3666     SignalException(Trap, instruction_0);
3667 }
3668
3669
3670 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3671 "tltu r<RS>, r<RT>"
3672 *mipsII:
3673 *mipsIII:
3674 *mipsIV:
3675 *vr5000:
3676 // start-sanitize-vr4320
3677 *vr4320:
3678 // end-sanitize-vr4320
3679 // start-sanitize-vr5400
3680 *vr5400:
3681 // end-sanitize-vr5400
3682 // start-sanitize-r5900
3683 *r5900:
3684 // end-sanitize-r5900
3685 // start-sanitize-tx19
3686 *tx19:
3687 // end-sanitize-tx19
3688 {
3689   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3690     SignalException(Trap, instruction_0);
3691 }
3692
3693
3694 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3695 "tne r<RS>, r<RT>"
3696 *mipsII:
3697 *mipsIII:
3698 *mipsIV:
3699 *vr5000:
3700 // start-sanitize-vr4320
3701 *vr4320:
3702 // end-sanitize-vr4320
3703 // start-sanitize-vr5400
3704 *vr5400:
3705 // end-sanitize-vr5400
3706 // start-sanitize-r5900
3707 *r5900:
3708 // end-sanitize-r5900
3709 // start-sanitize-tx19
3710 *tx19:
3711 // end-sanitize-tx19
3712 {
3713   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3714     SignalException(Trap, instruction_0);
3715 }
3716
3717
3718 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3719 "tne r<RS>, <IMMEDIATE>"
3720 *mipsII:
3721 *mipsIII:
3722 *mipsIV:
3723 *vr5000:
3724 // start-sanitize-vr4320
3725 *vr4320:
3726 // end-sanitize-vr4320
3727 // start-sanitize-vr5400
3728 *vr5400:
3729 // end-sanitize-vr5400
3730 // start-sanitize-r5900
3731 *r5900:
3732 // end-sanitize-r5900
3733 // start-sanitize-tx19
3734 *tx19:
3735 // end-sanitize-tx19
3736 {
3737   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3738     SignalException(Trap, instruction_0);
3739 }
3740
3741
3742 :function:::void:do_xor:int rs, int rt, int rd
3743 {
3744   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3745   GPR[rd] = GPR[rs] ^ GPR[rt];
3746   TRACE_ALU_RESULT (GPR[rd]);
3747 }
3748
3749 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3750 "xor r<RD>, r<RS>, r<RT>"
3751 *mipsI,mipsII,mipsIII,mipsIV:
3752 *vr5000:
3753 // start-sanitize-vr4320
3754 *vr4320:
3755 // end-sanitize-vr4320
3756 // start-sanitize-vr5400
3757 *vr5400:
3758 // end-sanitize-vr5400
3759 // start-sanitize-r5900
3760 *r5900:
3761 // end-sanitize-r5900
3762 *r3900:
3763 // start-sanitize-tx19
3764 *tx19:
3765 // end-sanitize-tx19
3766 {
3767   do_xor (SD_, RS, RT, RD);
3768 }
3769
3770
3771 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3772 {
3773   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3774   GPR[rt] = GPR[rs] ^ immediate;
3775   TRACE_ALU_RESULT (GPR[rt]);
3776 }
3777
3778 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3779 "xori r<RT>, r<RS>, <IMMEDIATE>"
3780 *mipsI,mipsII,mipsIII,mipsIV:
3781 *vr5000:
3782 // start-sanitize-vr4320
3783 *vr4320:
3784 // end-sanitize-vr4320
3785 // start-sanitize-vr5400
3786 *vr5400:
3787 // end-sanitize-vr5400
3788 // start-sanitize-r5900
3789 *r5900:
3790 // end-sanitize-r5900
3791 *r3900:
3792 // start-sanitize-tx19
3793 *tx19:
3794 // end-sanitize-tx19
3795 {
3796   do_xori (SD_, RS, RT, IMMEDIATE);
3797 }
3798
3799 \f
3800 //
3801 // MIPS Architecture:
3802 //
3803 //        FPU Instruction Set (COP1 & COP1X)
3804 //
3805
3806
3807 :%s::::FMT:int fmt
3808 {
3809   switch (fmt)
3810     {
3811     case fmt_single: return "s";
3812     case fmt_double: return "d";
3813     case fmt_word: return "w";
3814     case fmt_long: return "l";
3815     default: return "?";
3816     }
3817 }
3818
3819 :%s::::X:int x
3820 {
3821   switch (x)
3822     {
3823     case 0: return "f";
3824     case 1: return "t";
3825     default: return "?";
3826     }
3827 }
3828
3829 :%s::::TF:int tf
3830 {
3831   if (tf)
3832     return "t";
3833   else
3834     return "f";
3835 }
3836
3837 :%s::::ND:int nd
3838 {
3839   if (nd)
3840     return "l";
3841   else
3842     return "";
3843 }
3844
3845 :%s::::COND:int cond
3846 {
3847   switch (cond)
3848     {
3849     case 00: return "f";
3850     case 01: return "un";
3851     case 02: return "eq";
3852     case 03: return "ueq";
3853     case 04: return "olt";
3854     case 05: return "ult";
3855     case 06: return "ole";
3856     case 07: return "ule";
3857     case 010: return "sf";
3858     case 011: return "ngle";
3859     case 012: return "seq";
3860     case 013: return "ngl";
3861     case 014: return "lt";
3862     case 015: return "nge";
3863     case 016: return "le";
3864     case 017: return "ngt";
3865     default: return "?";
3866     }
3867 }
3868
3869
3870 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3871 "abs.%s<FMT> f<FD>, f<FS>"
3872 *mipsI,mipsII,mipsIII,mipsIV:
3873 *vr5000:
3874 // start-sanitize-vr4320
3875 *vr4320:
3876 // end-sanitize-vr4320
3877 // start-sanitize-vr5400
3878 *vr5400:
3879 // end-sanitize-vr5400
3880 *r3900:
3881 // start-sanitize-tx19
3882 *tx19:
3883 // end-sanitize-tx19
3884 {
3885   unsigned32 instruction = instruction_0;
3886   int destreg = ((instruction >> 6) & 0x0000001F);
3887   int fs = ((instruction >> 11) & 0x0000001F);
3888   int format = ((instruction >> 21) & 0x00000007);
3889   {
3890     if ((format != fmt_single) && (format != fmt_double))
3891       SignalException(ReservedInstruction,instruction);
3892     else
3893       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3894   }
3895 }
3896
3897
3898
3899 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3900 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3901 *mipsI,mipsII,mipsIII,mipsIV:
3902 *vr5000:
3903 // start-sanitize-vr4320
3904 *vr4320:
3905 // end-sanitize-vr4320
3906 // start-sanitize-vr5400
3907 *vr5400:
3908 // end-sanitize-vr5400
3909 *r3900:
3910 // start-sanitize-tx19
3911 *tx19:
3912 // end-sanitize-tx19
3913 {
3914   unsigned32 instruction = instruction_0;
3915   int destreg = ((instruction >> 6) & 0x0000001F);
3916   int fs = ((instruction >> 11) & 0x0000001F);
3917   int ft = ((instruction >> 16) & 0x0000001F);
3918   int format = ((instruction >> 21) & 0x00000007);
3919   {
3920     if ((format != fmt_single) && (format != fmt_double))
3921       SignalException(ReservedInstruction, instruction);
3922     else
3923       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3924   }
3925 }
3926
3927
3928
3929 // BC1F
3930 // BC1FL
3931 // BC1T
3932 // BC1TL
3933
3934 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3935 "bc1%s<TF>%s<ND> <OFFSET>"
3936 *mipsI,mipsII,mipsIII:
3937 // start-sanitize-r5900
3938 *r5900:
3939 // end-sanitize-r5900
3940 {
3941   TRACE_BRANCH_INPUT (PREVCOC1());
3942   if (PREVCOC1() == TF)
3943     {
3944       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3945       TRACE_BRANCH_RESULT (dest);
3946       DELAY_SLOT (dest);
3947     }
3948   else if (ND)
3949     {
3950       TRACE_BRANCH_RESULT (0);
3951       NULLIFY_NEXT_INSTRUCTION ();
3952     }
3953   else
3954     {
3955       TRACE_BRANCH_RESULT (NIA);
3956     }
3957 }
3958
3959 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3960 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3961 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3962 *mipsIV:
3963 *vr5000:
3964 // start-sanitize-vr4320
3965 *vr4320:
3966 // end-sanitize-vr4320
3967 // start-sanitize-vr5400
3968 *vr5400:
3969 // end-sanitize-vr5400
3970 *r3900:
3971 // start-sanitize-tx19
3972 *tx19:
3973 // end-sanitize-tx19
3974 {
3975   if (GETFCC(CC) == TF)
3976     {
3977       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3978     }
3979   else if (ND)
3980     {
3981       NULLIFY_NEXT_INSTRUCTION ();
3982     }
3983 }
3984
3985
3986
3987
3988
3989
3990 // C.EQ.S
3991 // C.EQ.D
3992 // ...
3993
3994 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3995 {
3996   if ((fmt != fmt_single) && (fmt != fmt_double))
3997     SignalException (ReservedInstruction, insn);
3998   else
3999     {
4000       int less;
4001       int equal;
4002       int unordered;
4003       int condition;
4004       unsigned64 ofs = ValueFPR (fs, fmt);
4005       unsigned64 oft = ValueFPR (ft, fmt);
4006       if (NaN (ofs, fmt) || NaN (oft, fmt))
4007         {
4008           if (FCSR & FP_ENABLE (IO))
4009             {
4010               FCSR |= FP_CAUSE (IO);
4011               SignalExceptionFPE ();
4012             }
4013           less = 0;
4014           equal = 0;
4015           unordered = 1;
4016         }
4017       else
4018         {
4019           less = Less (ofs, oft, fmt);
4020           equal = Equal (ofs, oft, fmt);
4021           unordered = 0;
4022         }
4023       condition = (((cond & (1 << 2)) && less)
4024                    || ((cond & (1 << 1)) && equal)
4025                    || ((cond & (1 << 0)) && unordered));
4026       SETFCC (cc, condition);
4027     }
4028 }
4029
4030 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4031 *mipsI,mipsII,mipsIII:
4032 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4033 {
4034   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4035 }
4036
4037 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4038 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4039 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4040 *mipsIV:
4041 *vr5000:
4042 // start-sanitize-vr4320
4043 *vr4320:
4044 // end-sanitize-vr4320
4045 // start-sanitize-vr5400
4046 *vr5400:
4047 // end-sanitize-vr5400
4048 *r3900:
4049 // start-sanitize-tx19
4050 *tx19:
4051 // end-sanitize-tx19
4052 {
4053   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4054 }
4055
4056
4057 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4058 "ceil.l.%s<FMT> f<FD>, f<FS>"
4059 *mipsIII:
4060 *mipsIV:
4061 *vr5000:
4062 // start-sanitize-vr4320
4063 *vr4320:
4064 // end-sanitize-vr4320
4065 // start-sanitize-vr5400
4066 *vr5400:
4067 // end-sanitize-vr5400
4068 // start-sanitize-r5900
4069 *r5900:
4070 // end-sanitize-r5900
4071 *r3900:
4072 // start-sanitize-tx19
4073 *tx19:
4074 // end-sanitize-tx19
4075 {
4076   unsigned32 instruction = instruction_0;
4077   int destreg = ((instruction >> 6) & 0x0000001F);
4078   int fs = ((instruction >> 11) & 0x0000001F);
4079   int format = ((instruction >> 21) & 0x00000007);
4080   {
4081     if ((format != fmt_single) && (format != fmt_double))
4082       SignalException(ReservedInstruction,instruction);
4083     else
4084       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4085   }
4086 }
4087
4088
4089 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4090 *mipsII:
4091 *mipsIII:
4092 *mipsIV:
4093 *vr5000:
4094 // start-sanitize-vr4320
4095 *vr4320:
4096 // end-sanitize-vr4320
4097 // start-sanitize-vr5400
4098 *vr5400:
4099 // end-sanitize-vr5400
4100 // start-sanitize-r5900
4101 *r5900:
4102 // end-sanitize-r5900
4103 *r3900:
4104 // start-sanitize-tx19
4105 *tx19:
4106 // end-sanitize-tx19
4107 {
4108   unsigned32 instruction = instruction_0;
4109   int destreg = ((instruction >> 6) & 0x0000001F);
4110   int fs = ((instruction >> 11) & 0x0000001F);
4111   int format = ((instruction >> 21) & 0x00000007);
4112   {
4113   if ((format != fmt_single) && (format != fmt_double))
4114    SignalException(ReservedInstruction,instruction);
4115   else
4116    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4117   }
4118 }
4119
4120
4121 // CFC1
4122 // CTC1
4123 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4124 "c%s<X>c1 r<RT>, f<FS>"
4125 *mipsI:
4126 *mipsII:
4127 *mipsIII:
4128 {
4129   if (X)
4130     {
4131       if (FS == 0)
4132         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4133       else if (FS == 31)
4134         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4135       /* else NOP */
4136       PENDING_FILL(COCIDX,0); /* special case */
4137     }
4138   else
4139     { /* control from */
4140       if (FS == 0)
4141         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4142       else if (FS == 31)
4143         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4144       /* else NOP */
4145     }
4146 }
4147 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4148 "c%s<X>c1 r<RT>, f<FS>"
4149 *mipsIV:
4150 *vr5000:
4151 // start-sanitize-vr4320
4152 *vr4320:
4153 // end-sanitize-vr4320
4154 // start-sanitize-vr5400
4155 *vr5400:
4156 // end-sanitize-vr5400
4157 *r3900:
4158 // start-sanitize-tx19
4159 *tx19:
4160 // end-sanitize-tx19
4161 {
4162   if (X)
4163     {
4164       /* control to */
4165       TRACE_ALU_INPUT1 (GPR[RT]);
4166       if (FS == 0)
4167         {
4168           FCR0 = VL4_8(GPR[RT]);
4169           TRACE_ALU_RESULT (FCR0);
4170         }
4171       else if (FS == 31)
4172         {
4173           FCR31 = VL4_8(GPR[RT]);
4174           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4175           TRACE_ALU_RESULT (FCR31);
4176         }
4177       else
4178         {
4179           TRACE_ALU_RESULT0 ();
4180         }
4181       /* else NOP */
4182     }
4183   else
4184     { /* control from */
4185       if (FS == 0)
4186         {
4187           TRACE_ALU_INPUT1 (FCR0);
4188           GPR[RT] = SIGNEXTEND (FCR0, 32);
4189         }
4190       else if (FS == 31)
4191         {
4192           TRACE_ALU_INPUT1 (FCR31);
4193           GPR[RT] = SIGNEXTEND (FCR31, 32);
4194         }
4195       TRACE_ALU_RESULT (GPR[RT]);
4196       /* else NOP */
4197     }
4198 }
4199
4200
4201 //
4202 // FIXME: Does not correctly differentiate between mips*
4203 //
4204 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4205 "cvt.d.%s<FMT> f<FD>, f<FS>"
4206 *mipsI,mipsII,mipsIII,mipsIV:
4207 *vr5000:
4208 // start-sanitize-vr4320
4209 *vr4320:
4210 // end-sanitize-vr4320
4211 // start-sanitize-vr5400
4212 *vr5400:
4213 // end-sanitize-vr5400
4214 *r3900:
4215 // start-sanitize-tx19
4216 *tx19:
4217 // end-sanitize-tx19
4218 {
4219   unsigned32 instruction = instruction_0;
4220   int destreg = ((instruction >> 6) & 0x0000001F);
4221   int fs = ((instruction >> 11) & 0x0000001F);
4222   int format = ((instruction >> 21) & 0x00000007);
4223   {
4224     if ((format == fmt_double) | 0)
4225       SignalException(ReservedInstruction,instruction);
4226     else
4227       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4228   }
4229 }
4230
4231
4232 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4233 "cvt.l.%s<FMT> f<FD>, f<FS>"
4234 *mipsIII:
4235 *mipsIV:
4236 *vr5000:
4237 // start-sanitize-vr4320
4238 *vr4320:
4239 // end-sanitize-vr4320
4240 // start-sanitize-vr5400
4241 *vr5400:
4242 // end-sanitize-vr5400
4243 *r3900:
4244 // start-sanitize-tx19
4245 *tx19:
4246 // end-sanitize-tx19
4247 {
4248   unsigned32 instruction = instruction_0;
4249   int destreg = ((instruction >> 6) & 0x0000001F);
4250   int fs = ((instruction >> 11) & 0x0000001F);
4251   int format = ((instruction >> 21) & 0x00000007);
4252   {
4253     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4254       SignalException(ReservedInstruction,instruction);
4255     else
4256       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4257   }
4258 }
4259
4260
4261 //
4262 // FIXME: Does not correctly differentiate between mips*
4263 //
4264 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4265 "cvt.s.%s<FMT> f<FD>, f<FS>"
4266 *mipsI,mipsII,mipsIII,mipsIV:
4267 *vr5000:
4268 // start-sanitize-vr4320
4269 *vr4320:
4270 // end-sanitize-vr4320
4271 // start-sanitize-vr5400
4272 *vr5400:
4273 // end-sanitize-vr5400
4274 *r3900:
4275 // start-sanitize-tx19
4276 *tx19:
4277 // end-sanitize-tx19
4278 {
4279   unsigned32 instruction = instruction_0;
4280   int destreg = ((instruction >> 6) & 0x0000001F);
4281   int fs = ((instruction >> 11) & 0x0000001F);
4282   int format = ((instruction >> 21) & 0x00000007);
4283   {
4284     if ((format == fmt_single) | 0)
4285       SignalException(ReservedInstruction,instruction);
4286     else
4287       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4288   }
4289 }
4290
4291
4292 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4293 "cvt.w.%s<FMT> f<FD>, f<FS>"
4294 *mipsI,mipsII,mipsIII,mipsIV:
4295 *vr5000:
4296 // start-sanitize-vr4320
4297 *vr4320:
4298 // end-sanitize-vr4320
4299 // start-sanitize-vr5400
4300 *vr5400:
4301 // end-sanitize-vr5400
4302 *r3900:
4303 // start-sanitize-tx19
4304 *tx19:
4305 // end-sanitize-tx19
4306 {
4307   unsigned32 instruction = instruction_0;
4308   int destreg = ((instruction >> 6) & 0x0000001F);
4309   int fs = ((instruction >> 11) & 0x0000001F);
4310   int format = ((instruction >> 21) & 0x00000007);
4311   {
4312     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4313       SignalException(ReservedInstruction,instruction);
4314     else
4315       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4316   }
4317 }
4318
4319
4320 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4321 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4322 *mipsI,mipsII,mipsIII,mipsIV:
4323 *vr5000:
4324 // start-sanitize-vr4320
4325 *vr4320:
4326 // end-sanitize-vr4320
4327 // start-sanitize-vr5400
4328 *vr5400:
4329 // end-sanitize-vr5400
4330 *r3900:
4331 // start-sanitize-tx19
4332 *tx19:
4333 // end-sanitize-tx19
4334 {
4335   unsigned32 instruction = instruction_0;
4336   int destreg = ((instruction >> 6) & 0x0000001F);
4337   int fs = ((instruction >> 11) & 0x0000001F);
4338   int ft = ((instruction >> 16) & 0x0000001F);
4339   int format = ((instruction >> 21) & 0x00000007);
4340   {
4341     if ((format != fmt_single) && (format != fmt_double))
4342       SignalException(ReservedInstruction,instruction);
4343     else
4344       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4345   }
4346 }
4347
4348
4349 // DMFC1
4350 // DMTC1
4351 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4352 "dm%s<X>c1 r<RT>, f<FS>"
4353 *mipsIII:
4354 {
4355   if (X)
4356     {
4357       if (SizeFGR() == 64)
4358         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4359       else if ((FS & 0x1) == 0)
4360         {
4361           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4362           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4363         }
4364     }
4365   else
4366     {
4367       if (SizeFGR() == 64)
4368         PENDING_FILL(RT,FGR[FS]);
4369       else if ((FS & 0x1) == 0)
4370         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4371       else
4372         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4373     }
4374 }
4375 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4376 "dm%s<X>c1 r<RT>, f<FS>"
4377 *mipsIV:
4378 *vr5000:
4379 // start-sanitize-vr4320
4380 *vr4320:
4381 // end-sanitize-vr4320
4382 // start-sanitize-vr5400
4383 *vr5400:
4384 // end-sanitize-vr5400
4385 // start-sanitize-r5900
4386 *r5900:
4387 // end-sanitize-r5900
4388 *r3900:
4389 // start-sanitize-tx19
4390 *tx19:
4391 // end-sanitize-tx19
4392 {
4393   if (X)
4394     {
4395       if (SizeFGR() == 64)
4396         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4397       else if ((FS & 0x1) == 0)
4398         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4399     }
4400   else
4401     {
4402       if (SizeFGR() == 64)
4403         GPR[RT] = FGR[FS];
4404       else if ((FS & 0x1) == 0)
4405         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4406       else
4407         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4408     }
4409 }
4410
4411
4412 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4413 "floor.l.%s<FMT> f<FD>, f<FS>"
4414 *mipsIII:
4415 *mipsIV:
4416 *vr5000:
4417 // start-sanitize-vr4320
4418 *vr4320:
4419 // end-sanitize-vr4320
4420 // start-sanitize-vr5400
4421 *vr5400:
4422 // end-sanitize-vr5400
4423 // start-sanitize-r5900
4424 *r5900:
4425 // end-sanitize-r5900
4426 *r3900:
4427 // start-sanitize-tx19
4428 *tx19:
4429 // end-sanitize-tx19
4430 {
4431   unsigned32 instruction = instruction_0;
4432   int destreg = ((instruction >> 6) & 0x0000001F);
4433   int fs = ((instruction >> 11) & 0x0000001F);
4434   int format = ((instruction >> 21) & 0x00000007);
4435   {
4436     if ((format != fmt_single) && (format != fmt_double))
4437       SignalException(ReservedInstruction,instruction);
4438     else
4439       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4440   }
4441 }
4442
4443
4444 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4445 "floor.w.%s<FMT> f<FD>, f<FS>"
4446 *mipsII:
4447 *mipsIII:
4448 *mipsIV:
4449 *vr5000:
4450 // start-sanitize-vr4320
4451 *vr4320:
4452 // end-sanitize-vr4320
4453 // start-sanitize-vr5400
4454 *vr5400:
4455 // end-sanitize-vr5400
4456 // start-sanitize-r5900
4457 *r5900:
4458 // end-sanitize-r5900
4459 *r3900:
4460 // start-sanitize-tx19
4461 *tx19:
4462 // end-sanitize-tx19
4463 {
4464   unsigned32 instruction = instruction_0;
4465   int destreg = ((instruction >> 6) & 0x0000001F);
4466   int fs = ((instruction >> 11) & 0x0000001F);
4467   int format = ((instruction >> 21) & 0x00000007);
4468   {
4469     if ((format != fmt_single) && (format != fmt_double))
4470       SignalException(ReservedInstruction,instruction);
4471     else
4472       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4473   }
4474 }
4475
4476
4477 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4478 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4479 *mipsII:
4480 *mipsIII:
4481 *mipsIV:
4482 *vr5000:
4483 // start-sanitize-vr4320
4484 *vr4320:
4485 // end-sanitize-vr4320
4486 // start-sanitize-vr5400
4487 *vr5400:
4488 // end-sanitize-vr5400
4489 *r3900:
4490 // start-sanitize-tx19
4491 *tx19:
4492 // end-sanitize-tx19
4493 {
4494   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4495 }
4496
4497
4498 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4499 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4500 *mipsIV:
4501 *vr5000:
4502 // start-sanitize-vr4320
4503 *vr4320:
4504 // end-sanitize-vr4320
4505 // start-sanitize-vr5400
4506 *vr5400:
4507 // end-sanitize-vr5400
4508 {
4509   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4510 }
4511
4512
4513
4514 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4515 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4516 *mipsI,mipsII,mipsIII,mipsIV:
4517 *vr5000:
4518 // start-sanitize-vr4320
4519 *vr4320:
4520 // end-sanitize-vr4320
4521 // start-sanitize-vr5400
4522 *vr5400:
4523 // end-sanitize-vr5400
4524 // start-sanitize-r5900
4525 *r5900:
4526 // end-sanitize-r5900
4527 *r3900:
4528 // start-sanitize-tx19
4529 *tx19:
4530 // end-sanitize-tx19
4531 {
4532   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4533 }
4534
4535
4536 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4537 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4538 *mipsIV:
4539 *vr5000:
4540 // start-sanitize-vr4320
4541 *vr4320:
4542 // end-sanitize-vr4320
4543 // start-sanitize-vr5400
4544 *vr5400:
4545 // end-sanitize-vr5400
4546 {
4547   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4548 }
4549
4550
4551
4552 //
4553 // FIXME: Not correct for mips*
4554 //
4555 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4556 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4557 *mipsIV:
4558 *vr5000:
4559 // start-sanitize-vr4320
4560 *vr4320:
4561 // end-sanitize-vr4320
4562 // start-sanitize-vr5400
4563 *vr5400:
4564 // end-sanitize-vr5400
4565 {
4566   unsigned32 instruction = instruction_0;
4567   int destreg = ((instruction >> 6) & 0x0000001F);
4568   int fs = ((instruction >> 11) & 0x0000001F);
4569   int ft = ((instruction >> 16) & 0x0000001F);
4570   int fr = ((instruction >> 21) & 0x0000001F);
4571   {
4572     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4573   }
4574 }
4575
4576
4577 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4578 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4579 *mipsIV:
4580 *vr5000:
4581 // start-sanitize-vr4320
4582 *vr4320:
4583 // end-sanitize-vr4320
4584 // start-sanitize-vr5400
4585 *vr5400:
4586 // end-sanitize-vr5400
4587 {
4588   unsigned32 instruction = instruction_0;
4589   int destreg = ((instruction >> 6) & 0x0000001F);
4590   int fs = ((instruction >> 11) & 0x0000001F);
4591   int ft = ((instruction >> 16) & 0x0000001F);
4592   int fr = ((instruction >> 21) & 0x0000001F);
4593   {
4594     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4595   }
4596 }
4597
4598
4599 // MFC1
4600 // MTC1
4601 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4602 "m%s<X>c1 r<RT>, f<FS>"
4603 *mipsI:
4604 *mipsII:
4605 *mipsIII:
4606 {
4607   if (X)
4608     { /*MTC1*/
4609       if (SizeFGR() == 64)
4610         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4611       else
4612         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4613     }
4614   else /*MFC1*/
4615     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4616 }
4617 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4618 "m%s<X>c1 r<RT>, f<FS>"
4619 *mipsIV:
4620 *vr5000:
4621 // start-sanitize-vr4320
4622 *vr4320:
4623 // end-sanitize-vr4320
4624 // start-sanitize-vr5400
4625 *vr5400:
4626 // end-sanitize-vr5400
4627 *r3900:
4628 // start-sanitize-tx19
4629 *tx19:
4630 // end-sanitize-tx19
4631 {
4632   if (X)
4633     /*MTC1*/
4634     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4635   else /*MFC1*/
4636     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4637 }
4638
4639
4640 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4641 "mov.%s<FMT> f<FD>, f<FS>"
4642 *mipsI,mipsII,mipsIII,mipsIV:
4643 *vr5000:
4644 // start-sanitize-vr4320
4645 *vr4320:
4646 // end-sanitize-vr4320
4647 // start-sanitize-vr5400
4648 *vr5400:
4649 // end-sanitize-vr5400
4650 *r3900:
4651 // start-sanitize-tx19
4652 *tx19:
4653 // end-sanitize-tx19
4654 {
4655   unsigned32 instruction = instruction_0;
4656   int destreg = ((instruction >> 6) & 0x0000001F);
4657   int fs = ((instruction >> 11) & 0x0000001F);
4658   int format = ((instruction >> 21) & 0x00000007);
4659   {
4660     StoreFPR(destreg,format,ValueFPR(fs,format));
4661   }
4662 }
4663
4664
4665 // MOVF
4666 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4667 "mov%s<TF> r<RD>, r<RS>, <CC>"
4668 *mipsIV:
4669 *vr5000:
4670 // start-sanitize-vr4320
4671 *vr4320:
4672 // end-sanitize-vr4320
4673 // start-sanitize-vr5400
4674 *vr5400:
4675 // end-sanitize-vr5400
4676 // start-sanitize-r5900
4677 *r5900:
4678 // end-sanitize-r5900
4679 {
4680   if (GETFCC(CC) == TF)
4681     GPR[RD] = GPR[RS];
4682 }
4683
4684
4685 // MOVF.fmt
4686 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4687 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4688 *mipsIV:
4689 *vr5000:
4690 // start-sanitize-vr4320
4691 *vr4320:
4692 // end-sanitize-vr4320
4693 // start-sanitize-vr5400
4694 *vr5400:
4695 // end-sanitize-vr5400
4696 // start-sanitize-r5900
4697 *r5900:
4698 // end-sanitize-r5900
4699 {
4700   unsigned32 instruction = instruction_0;
4701   int format = ((instruction >> 21) & 0x00000007);
4702   {
4703    if (GETFCC(CC) == TF)
4704      StoreFPR (FD, format, ValueFPR (FS, format));
4705    else
4706      StoreFPR (FD, format, ValueFPR (FD, format));
4707   }
4708 }
4709
4710
4711 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4712 *mipsIV:
4713 *vr5000:
4714 // start-sanitize-vr4320
4715 *vr4320:
4716 // end-sanitize-vr4320
4717 // start-sanitize-vr5400
4718 *vr5400:
4719 // end-sanitize-vr5400
4720 // start-sanitize-r5900
4721 *r5900:
4722 // end-sanitize-r5900
4723 {
4724   unsigned32 instruction = instruction_0;
4725   int destreg = ((instruction >> 6) & 0x0000001F);
4726   int fs = ((instruction >> 11) & 0x0000001F);
4727   int format = ((instruction >> 21) & 0x00000007);
4728   {
4729     StoreFPR(destreg,format,ValueFPR(fs,format));
4730   }
4731 }
4732
4733
4734 // MOVT see MOVtf
4735
4736
4737 // MOVT.fmt see MOVtf.fmt
4738
4739
4740
4741 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4742 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4743 *mipsIV:
4744 *vr5000:
4745 // start-sanitize-vr4320
4746 *vr4320:
4747 // end-sanitize-vr4320
4748 // start-sanitize-vr5400
4749 *vr5400:
4750 // end-sanitize-vr5400
4751 // start-sanitize-r5900
4752 *r5900:
4753 // end-sanitize-r5900
4754 {
4755   unsigned32 instruction = instruction_0;
4756   int destreg = ((instruction >> 6) & 0x0000001F);
4757   int fs = ((instruction >> 11) & 0x0000001F);
4758   int format = ((instruction >> 21) & 0x00000007);
4759   {
4760    StoreFPR(destreg,format,ValueFPR(fs,format));
4761   }
4762 }
4763
4764
4765 // MSUB.fmt
4766 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4767 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4768 *mipsIV:
4769 *vr5000:
4770 // start-sanitize-vr4320
4771 *vr4320:
4772 // end-sanitize-vr4320
4773 // start-sanitize-vr5400
4774 *vr5400:
4775 // end-sanitize-vr5400
4776 // start-sanitize-r5900
4777 *r5900:
4778 // end-sanitize-r5900
4779 {
4780   unsigned32 instruction = instruction_0;
4781   int destreg = ((instruction >> 6) & 0x0000001F);
4782   int fs = ((instruction >> 11) & 0x0000001F);
4783   int ft = ((instruction >> 16) & 0x0000001F);
4784   int fr = ((instruction >> 21) & 0x0000001F);
4785   {
4786     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4787   }
4788 }
4789
4790
4791 // MSUB.fmt
4792 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4793 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4794 *mipsIV:
4795 *vr5000:
4796 // start-sanitize-vr4320
4797 *vr4320:
4798 // end-sanitize-vr4320
4799 // start-sanitize-vr5400
4800 *vr5400:
4801 // end-sanitize-vr5400
4802 // start-sanitize-r5900
4803 *r5900:
4804 // end-sanitize-r5900
4805 {
4806   unsigned32 instruction = instruction_0;
4807   int destreg = ((instruction >> 6) & 0x0000001F);
4808   int fs = ((instruction >> 11) & 0x0000001F);
4809   int ft = ((instruction >> 16) & 0x0000001F);
4810   int fr = ((instruction >> 21) & 0x0000001F);
4811   {
4812    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4813   }
4814 }
4815
4816
4817 // MTC1 see MxC1
4818
4819
4820 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4821 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4822 *mipsI,mipsII,mipsIII,mipsIV:
4823 *vr5000:
4824 // start-sanitize-vr4320
4825 *vr4320:
4826 // end-sanitize-vr4320
4827 // start-sanitize-vr5400
4828 *vr5400:
4829 // end-sanitize-vr5400
4830 *r3900:
4831 // start-sanitize-tx19
4832 *tx19:
4833 // end-sanitize-tx19
4834 {
4835   unsigned32 instruction = instruction_0;
4836   int destreg = ((instruction >> 6) & 0x0000001F);
4837   int fs = ((instruction >> 11) & 0x0000001F);
4838   int ft = ((instruction >> 16) & 0x0000001F);
4839   int format = ((instruction >> 21) & 0x00000007);
4840   {
4841     if ((format != fmt_single) && (format != fmt_double))
4842       SignalException(ReservedInstruction,instruction);
4843     else
4844       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4845   }
4846 }
4847
4848
4849 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4850 "neg.%s<FMT> f<FD>, f<FS>"
4851 *mipsI,mipsII,mipsIII,mipsIV:
4852 *vr5000:
4853 // start-sanitize-vr4320
4854 *vr4320:
4855 // end-sanitize-vr4320
4856 // start-sanitize-vr5400
4857 *vr5400:
4858 // end-sanitize-vr5400
4859 *r3900:
4860 // start-sanitize-tx19
4861 *tx19:
4862 // end-sanitize-tx19
4863 {
4864   unsigned32 instruction = instruction_0;
4865   int destreg = ((instruction >> 6) & 0x0000001F);
4866   int fs = ((instruction >> 11) & 0x0000001F);
4867   int format = ((instruction >> 21) & 0x00000007);
4868   {
4869     if ((format != fmt_single) && (format != fmt_double))
4870       SignalException(ReservedInstruction,instruction);
4871     else
4872       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4873   }
4874 }
4875
4876
4877 // NMADD.fmt
4878 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4879 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4880 *mipsIV:
4881 *vr5000:
4882 // start-sanitize-vr4320
4883 *vr4320:
4884 // end-sanitize-vr4320
4885 // start-sanitize-vr5400
4886 *vr5400:
4887 // end-sanitize-vr5400
4888 {
4889   unsigned32 instruction = instruction_0;
4890   int destreg = ((instruction >> 6) & 0x0000001F);
4891   int fs = ((instruction >> 11) & 0x0000001F);
4892   int ft = ((instruction >> 16) & 0x0000001F);
4893   int fr = ((instruction >> 21) & 0x0000001F);
4894   {
4895    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4896   }
4897 }
4898
4899
4900 // NMADD.fmt
4901 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4902 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4903 *mipsIV:
4904 *vr5000:
4905 // start-sanitize-vr4320
4906 *vr4320:
4907 // end-sanitize-vr4320
4908 // start-sanitize-vr5400
4909 *vr5400:
4910 // end-sanitize-vr5400
4911 {
4912   unsigned32 instruction = instruction_0;
4913   int destreg = ((instruction >> 6) & 0x0000001F);
4914   int fs = ((instruction >> 11) & 0x0000001F);
4915   int ft = ((instruction >> 16) & 0x0000001F);
4916   int fr = ((instruction >> 21) & 0x0000001F);
4917   {
4918    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4919   }
4920 }
4921
4922
4923 // NMSUB.fmt
4924 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4925 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4926 *mipsIV:
4927 *vr5000:
4928 // start-sanitize-vr4320
4929 *vr4320:
4930 // end-sanitize-vr4320
4931 // start-sanitize-vr5400
4932 *vr5400:
4933 // end-sanitize-vr5400
4934 {
4935   unsigned32 instruction = instruction_0;
4936   int destreg = ((instruction >> 6) & 0x0000001F);
4937   int fs = ((instruction >> 11) & 0x0000001F);
4938   int ft = ((instruction >> 16) & 0x0000001F);
4939   int fr = ((instruction >> 21) & 0x0000001F);
4940   {
4941    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4942   }
4943 }
4944
4945
4946 // NMSUB.fmt
4947 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4948 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4949 *mipsIV:
4950 *vr5000:
4951 // start-sanitize-vr4320
4952 *vr4320:
4953 // end-sanitize-vr4320
4954 // start-sanitize-vr5400
4955 *vr5400:
4956 // end-sanitize-vr5400
4957 {
4958   unsigned32 instruction = instruction_0;
4959   int destreg = ((instruction >> 6) & 0x0000001F);
4960   int fs = ((instruction >> 11) & 0x0000001F);
4961   int ft = ((instruction >> 16) & 0x0000001F);
4962   int fr = ((instruction >> 21) & 0x0000001F);
4963   {
4964     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4965   }
4966 }
4967
4968
4969 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4970 "prefx <HINT>, r<INDEX>(r<BASE>)"
4971 *mipsIV:
4972 *vr5000:
4973 // start-sanitize-vr4320
4974 *vr4320:
4975 // end-sanitize-vr4320
4976 // start-sanitize-vr5400
4977 *vr5400:
4978 // end-sanitize-vr5400
4979 {
4980   unsigned32 instruction = instruction_0;
4981   int fs = ((instruction >> 11) & 0x0000001F);
4982   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4983   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4984   {
4985     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4986     address_word paddr;
4987     int uncached;
4988     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4989       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4990   }
4991 }
4992
4993 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4994 *mipsIV:
4995 "recip.%s<FMT> f<FD>, f<FS>"
4996 *vr5000:
4997 // start-sanitize-vr4320
4998 *vr4320:
4999 // end-sanitize-vr4320
5000 // start-sanitize-vr5400
5001 *vr5400:
5002 // end-sanitize-vr5400
5003 {
5004   unsigned32 instruction = instruction_0;
5005   int destreg = ((instruction >> 6) & 0x0000001F);
5006   int fs = ((instruction >> 11) & 0x0000001F);
5007   int format = ((instruction >> 21) & 0x00000007);
5008   {
5009   if ((format != fmt_single) && (format != fmt_double))
5010    SignalException(ReservedInstruction,instruction);
5011   else
5012    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5013   }
5014 }
5015
5016
5017 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5018 "round.l.%s<FMT> f<FD>, f<FS>"
5019 *mipsIII:
5020 *mipsIV:
5021 *vr5000:
5022 // start-sanitize-vr4320
5023 *vr4320:
5024 // end-sanitize-vr4320
5025 // start-sanitize-vr5400
5026 *vr5400:
5027 // end-sanitize-vr5400
5028 // start-sanitize-r5900
5029 *r5900:
5030 // end-sanitize-r5900
5031 *r3900:
5032 // start-sanitize-tx19
5033 *tx19:
5034 // end-sanitize-tx19
5035 {
5036   unsigned32 instruction = instruction_0;
5037   int destreg = ((instruction >> 6) & 0x0000001F);
5038   int fs = ((instruction >> 11) & 0x0000001F);
5039   int format = ((instruction >> 21) & 0x00000007);
5040   {
5041     if ((format != fmt_single) && (format != fmt_double))
5042       SignalException(ReservedInstruction,instruction);
5043     else
5044       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5045   }
5046 }
5047
5048
5049 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5050 "round.w.%s<FMT> f<FD>, f<FS>"
5051 *mipsII:
5052 *mipsIII:
5053 *mipsIV:
5054 *vr5000:
5055 // start-sanitize-vr4320
5056 *vr4320:
5057 // end-sanitize-vr4320
5058 // start-sanitize-vr5400
5059 *vr5400:
5060 // end-sanitize-vr5400
5061 // start-sanitize-r5900
5062 *r5900:
5063 // end-sanitize-r5900
5064 *r3900:
5065 // start-sanitize-tx19
5066 *tx19:
5067 // end-sanitize-tx19
5068 {
5069   unsigned32 instruction = instruction_0;
5070   int destreg = ((instruction >> 6) & 0x0000001F);
5071   int fs = ((instruction >> 11) & 0x0000001F);
5072   int format = ((instruction >> 21) & 0x00000007);
5073   {
5074   if ((format != fmt_single) && (format != fmt_double))
5075    SignalException(ReservedInstruction,instruction);
5076   else
5077    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5078   }
5079 }
5080
5081
5082 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5083 *mipsIV:
5084 "rsqrt.%s<FMT> f<FD>, f<FS>"
5085 *vr5000:
5086 // start-sanitize-vr4320
5087 *vr4320:
5088 // end-sanitize-vr4320
5089 // start-sanitize-vr5400
5090 *vr5400:
5091 // end-sanitize-vr5400
5092 {
5093   unsigned32 instruction = instruction_0;
5094   int destreg = ((instruction >> 6) & 0x0000001F);
5095   int fs = ((instruction >> 11) & 0x0000001F);
5096   int format = ((instruction >> 21) & 0x00000007);
5097   {
5098   if ((format != fmt_single) && (format != fmt_double))
5099    SignalException(ReservedInstruction,instruction);
5100   else
5101    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5102   }
5103 }
5104
5105
5106 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5107 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5108 *mipsII:
5109 *mipsIII:
5110 *mipsIV:
5111 *vr5000:
5112 // start-sanitize-vr4320
5113 *vr4320:
5114 // end-sanitize-vr4320
5115 // start-sanitize-vr5400
5116 *vr5400:
5117 // end-sanitize-vr5400
5118 *r3900:
5119 // start-sanitize-tx19
5120 *tx19:
5121 // end-sanitize-tx19
5122 {
5123   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5124 }
5125
5126
5127 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5128 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5129 *mipsIV:
5130 *vr5000:
5131 // start-sanitize-vr4320
5132 *vr4320:
5133 // end-sanitize-vr4320
5134 // start-sanitize-vr5400
5135 *vr5400:
5136 // end-sanitize-vr5400
5137 {
5138   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5139 }
5140
5141
5142 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5143 "sqrt.%s<FMT> f<FD>, f<FS>"
5144 *mipsII:
5145 *mipsIII:
5146 *mipsIV:
5147 *vr5000:
5148 // start-sanitize-vr4320
5149 *vr4320:
5150 // end-sanitize-vr4320
5151 // start-sanitize-vr5400
5152 *vr5400:
5153 // end-sanitize-vr5400
5154 *r3900:
5155 // start-sanitize-tx19
5156 *tx19:
5157 // end-sanitize-tx19
5158 {
5159   unsigned32 instruction = instruction_0;
5160   int destreg = ((instruction >> 6) & 0x0000001F);
5161   int fs = ((instruction >> 11) & 0x0000001F);
5162   int format = ((instruction >> 21) & 0x00000007);
5163   {
5164     if ((format != fmt_single) && (format != fmt_double))
5165       SignalException(ReservedInstruction,instruction);
5166     else
5167       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5168   }
5169 }
5170
5171
5172 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5173 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5174 *mipsI,mipsII,mipsIII,mipsIV:
5175 *vr5000:
5176 // start-sanitize-vr4320
5177 *vr4320:
5178 // end-sanitize-vr4320
5179 // start-sanitize-vr5400
5180 *vr5400:
5181 // end-sanitize-vr5400
5182 *r3900:
5183 // start-sanitize-tx19
5184 *tx19:
5185 // end-sanitize-tx19
5186 {
5187   unsigned32 instruction = instruction_0;
5188   int destreg = ((instruction >> 6) & 0x0000001F);
5189   int fs = ((instruction >> 11) & 0x0000001F);
5190   int ft = ((instruction >> 16) & 0x0000001F);
5191   int format = ((instruction >> 21) & 0x00000007);
5192   {
5193     if ((format != fmt_single) && (format != fmt_double))
5194       SignalException(ReservedInstruction,instruction);
5195     else
5196       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5197   }
5198 }
5199
5200
5201
5202 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5203 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5204 *mipsI,mipsII,mipsIII,mipsIV:
5205 *vr5000:
5206 // start-sanitize-vr4320
5207 *vr4320:
5208 // end-sanitize-vr4320
5209 // start-sanitize-vr5400
5210 *vr5400:
5211 // end-sanitize-vr5400
5212 // start-sanitize-r5900
5213 *r5900:
5214 // end-sanitize-r5900
5215 *r3900:
5216 // start-sanitize-tx19
5217 *tx19:
5218 // end-sanitize-tx19
5219 {
5220   unsigned32 instruction = instruction_0;
5221   signed_word offset = EXTEND16 (OFFSET);
5222   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5223   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5224   {
5225     address_word vaddr = ((uword64)op1 + offset);
5226     address_word paddr;
5227     int uncached;
5228     if ((vaddr & 3) != 0)
5229       SignalExceptionAddressStore();
5230     else
5231       {
5232         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5233           {
5234             uword64 memval = 0;
5235             uword64 memval1 = 0;
5236             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5237             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5238             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5239             unsigned int byte;
5240             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5241             byte = ((vaddr & mask) ^ bigendiancpu);
5242             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5243             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5244           }
5245       }
5246   }
5247 }
5248
5249
5250 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5251 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5252 *mipsIV:
5253 *vr5000:
5254 // start-sanitize-vr4320
5255 *vr4320:
5256 // end-sanitize-vr4320
5257 // start-sanitize-vr5400
5258 *vr5400:
5259 // end-sanitize-vr5400
5260 {
5261   unsigned32 instruction = instruction_0;
5262   int fs = ((instruction >> 11) & 0x0000001F);
5263   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5264   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5265   {
5266    address_word vaddr = ((unsigned64)op1 + op2);
5267    address_word paddr;
5268    int uncached;
5269    if ((vaddr & 3) != 0)
5270     SignalExceptionAddressStore();
5271    else
5272    {
5273     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5274     {
5275      unsigned64 memval = 0;
5276      unsigned64 memval1 = 0;
5277      unsigned64 mask = 0x7;
5278      unsigned int byte;
5279      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5280      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5281      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5282       {
5283        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5284       }
5285     }
5286    }
5287   }
5288 }
5289
5290
5291 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5292 "trunc.l.%s<FMT> f<FD>, f<FS>"
5293 *mipsIII:
5294 *mipsIV:
5295 *vr5000:
5296 // start-sanitize-vr4320
5297 *vr4320:
5298 // end-sanitize-vr4320
5299 // start-sanitize-vr5400
5300 *vr5400:
5301 // end-sanitize-vr5400
5302 // start-sanitize-r5900
5303 *r5900:
5304 // end-sanitize-r5900
5305 *r3900:
5306 // start-sanitize-tx19
5307 *tx19:
5308 // end-sanitize-tx19
5309 {
5310   unsigned32 instruction = instruction_0;
5311   int destreg = ((instruction >> 6) & 0x0000001F);
5312   int fs = ((instruction >> 11) & 0x0000001F);
5313   int format = ((instruction >> 21) & 0x00000007);
5314   {
5315   if ((format != fmt_single) && (format != fmt_double))
5316    SignalException(ReservedInstruction,instruction);
5317   else
5318    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5319   }
5320 }
5321
5322
5323 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5324 "trunc.w.%s<FMT> f<FD>, f<FS>"
5325 *mipsII:
5326 *mipsIII:
5327 *mipsIV:
5328 *vr5000:
5329 // start-sanitize-vr4320
5330 *vr4320:
5331 // end-sanitize-vr4320
5332 // start-sanitize-vr5400
5333 *vr5400:
5334 // end-sanitize-vr5400
5335 // start-sanitize-r5900
5336 *r5900:
5337 // end-sanitize-r5900
5338 *r3900:
5339 // start-sanitize-tx19
5340 *tx19:
5341 // end-sanitize-tx19
5342 {
5343   unsigned32 instruction = instruction_0;
5344   int destreg = ((instruction >> 6) & 0x0000001F);
5345   int fs = ((instruction >> 11) & 0x0000001F);
5346   int format = ((instruction >> 21) & 0x00000007);
5347   {
5348   if ((format != fmt_single) && (format != fmt_double))
5349    SignalException(ReservedInstruction,instruction);
5350   else
5351    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5352   }
5353 }
5354
5355 \f
5356 //
5357 // MIPS Architecture:
5358 //
5359 //        System Control Instruction Set (COP0)
5360 //
5361
5362
5363 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5364 "bc0f <OFFSET>"
5365 *mipsI,mipsII,mipsIII,mipsIV:
5366 *vr5000:
5367 // start-sanitize-vr4320
5368 *vr4320:
5369 // end-sanitize-vr4320
5370 // start-sanitize-vr5400
5371 *vr5400:
5372 // end-sanitize-vr5400
5373 // start-sanitize-r5900
5374 *r5900:
5375 // start-sanitize-sky
5376 {
5377 #ifdef TARGET_SKY
5378   address_word offset = EXTEND16 (OFFSET) << 2;
5379   extern int sky_cpcond0;
5380   if (sky_cpcond0 == 0)
5381     DELAY_SLOT (NIA + offset);
5382 #endif
5383 }
5384 // end-sanitize-sky
5385 // end-sanitize-r5900
5386
5387
5388 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5389 "bc0fl <OFFSET>"
5390 *mipsI,mipsII,mipsIII,mipsIV:
5391 *vr5000:
5392 // start-sanitize-vr4320
5393 *vr4320:
5394 // end-sanitize-vr4320
5395 // start-sanitize-vr5400
5396 *vr5400:
5397 // end-sanitize-vr5400
5398 // start-sanitize-r5900
5399 *r5900:
5400 // start-sanitize-sky
5401 {
5402 #ifdef TARGET_SKY
5403   address_word offset = EXTEND16 (OFFSET) << 2;
5404   extern int sky_cpcond0;
5405   if (sky_cpcond0 == 0)
5406     DELAY_SLOT (NIA + offset);
5407 #endif
5408 }
5409 // end-sanitize-sky
5410 // end-sanitize-r5900
5411
5412
5413 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5414 "bc0t <OFFSET>"
5415 *mipsI,mipsII,mipsIII,mipsIV:
5416 // start-sanitize-r5900
5417 *r5900:
5418 // start-sanitize-sky
5419 {
5420 #ifdef TARGET_SKY
5421   address_word offset = EXTEND16 (OFFSET) << 2;
5422   extern int sky_cpcond0;
5423   if (sky_cpcond0 != 0)
5424     DELAY_SLOT (NIA + offset);
5425 #endif
5426 }
5427 // end-sanitize-sky
5428 // end-sanitize-r5900
5429
5430
5431
5432 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5433 "bc0tl <OFFSET>"
5434 *mipsI,mipsII,mipsIII,mipsIV:
5435 *vr5000:
5436 // start-sanitize-vr4320
5437 *vr4320:
5438 // end-sanitize-vr4320
5439 // start-sanitize-vr5400
5440 *vr5400:
5441 // end-sanitize-vr5400
5442 // start-sanitize-r5900
5443 *r5900:
5444 // start-sanitize-sky
5445 {
5446 #ifdef TARGET_SKY
5447   address_word offset = EXTEND16 (OFFSET) << 2;
5448   extern int sky_cpcond0;
5449   if (sky_cpcond0 != 0)
5450     DELAY_SLOT (NIA + offset);
5451 #endif
5452 }
5453 // end-sanitize-sky
5454 // end-sanitize-r5900
5455
5456
5457 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5458 *mipsIII:
5459 *mipsIV:
5460 *vr5000:
5461 // start-sanitize-vr4320
5462 *vr4320:
5463 // end-sanitize-vr4320
5464 // start-sanitize-vr5400
5465 *vr5400:
5466 // end-sanitize-vr5400
5467 // start-sanitize-r5900
5468 *r5900:
5469 // end-sanitize-r5900
5470 *r3900:
5471 // start-sanitize-tx19
5472 *tx19:
5473 // end-sanitize-tx19
5474 {
5475   unsigned32 instruction = instruction_0;
5476   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5477   int hint = ((instruction >> 16) & 0x0000001F);
5478   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5479   {
5480     address_word vaddr = (op1 + offset);
5481     address_word paddr;
5482     int uncached;
5483     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5484       CacheOp(hint,vaddr,paddr,instruction);
5485   }
5486 }
5487
5488
5489 010000,10000,000000000000000,111001:COP0:32::DI
5490 "di"
5491 *mipsI,mipsII,mipsIII,mipsIV:
5492 *vr5000:
5493 // start-sanitize-vr4320
5494 *vr4320:
5495 // end-sanitize-vr4320
5496 // start-sanitize-vr5400
5497 *vr5400:
5498 // end-sanitize-vr5400
5499 // start-sanitize-r5900
5500 *r5900:
5501 // end-sanitize-r5900
5502
5503
5504 010000,10000,000000000000000,111000:COP0:32::EI
5505 "ei"
5506 *mipsI,mipsII,mipsIII,mipsIV:
5507 *vr5000:
5508 // start-sanitize-vr4320
5509 *vr4320:
5510 // end-sanitize-vr4320
5511 // start-sanitize-vr5400
5512 *vr5400:
5513 // end-sanitize-vr5400
5514 // start-sanitize-r5900
5515 *r5900:
5516 // end-sanitize-r5900
5517
5518
5519 010000,10000,000000000000000,011000:COP0:32::ERET
5520 "eret"
5521 *mipsIII:
5522 *mipsIV:
5523 *vr5000:
5524 // start-sanitize-vr4320
5525 *vr4320:
5526 // end-sanitize-vr4320
5527 // start-sanitize-vr5400
5528 *vr5400:
5529 // end-sanitize-vr5400
5530 // start-sanitize-r5900
5531 *r5900:
5532 // end-sanitize-r5900
5533 {
5534   if (SR & status_ERL)
5535     {
5536       /* Oops, not yet available */
5537       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5538       NIA = EPC;
5539       SR &= ~status_ERL;
5540     }
5541   else
5542     {
5543       NIA = EPC;
5544       SR &= ~status_EXL;
5545     }
5546 }
5547
5548
5549 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5550 "mfc0 r<RT>, r<RD> # <REGX>"
5551 *mipsI,mipsII,mipsIII,mipsIV:
5552 *r3900:
5553 *vr5000:
5554 // start-sanitize-vr4320
5555 *vr4320:
5556 // end-sanitize-vr4320
5557 // start-sanitize-vr5400
5558 *vr5400:
5559 // end-sanitize-vr5400
5560 // start-sanitize-r5900
5561 *r5900:
5562 // end-sanitize-r5900
5563 {
5564   TRACE_ALU_INPUT0 ();
5565   DecodeCoproc (instruction_0);
5566   TRACE_ALU_RESULT (GPR[RT]);
5567 }
5568
5569 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5570 "mtc0 r<RT>, r<RD> # <REGX>"
5571 *mipsI,mipsII,mipsIII,mipsIV:
5572 // start-sanitize-tx19
5573 *tx19:
5574 // end-sanitize-tx19
5575 *r3900:
5576 // start-sanitize-vr4320
5577 *vr4320:
5578 // end-sanitize-vr4320
5579 *vr5000:
5580 // start-sanitize-vr5400
5581 *vr5400:
5582 // end-sanitize-vr5400
5583 // start-sanitize-r5900
5584 *r5900:
5585 // end-sanitize-r5900
5586 {
5587   DecodeCoproc (instruction_0);
5588 }
5589
5590
5591 010000,10000,000000000000000,010000:COP0:32::RFE
5592 "rfe"
5593 *mipsI,mipsII,mipsIII,mipsIV:
5594 // start-sanitize-tx19
5595 *tx19:
5596 // end-sanitize-tx19
5597 *r3900:
5598 // start-sanitize-vr4320
5599 *vr4320:
5600 // end-sanitize-vr4320
5601 *vr5000:
5602 // start-sanitize-vr5400
5603 *vr5400:
5604 // end-sanitize-vr5400
5605 // start-sanitize-r5900
5606 *r5900:
5607 // end-sanitize-r5900
5608 {
5609   DecodeCoproc (instruction_0);
5610 }
5611
5612
5613 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5614 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5615 *mipsI,mipsII,mipsIII,mipsIV:
5616 // start-sanitize-r5900
5617 *r5900:
5618 // end-sanitize-r5900
5619 *r3900:
5620 // start-sanitize-tx19
5621 *tx19:
5622 // end-sanitize-tx19
5623 {
5624   DecodeCoproc (instruction_0);
5625 }
5626
5627
5628
5629 010000,10000,000000000000000,001000:COP0:32::TLBP
5630 "tlbp"
5631 *mipsI,mipsII,mipsIII,mipsIV:
5632 *vr5000:
5633 // start-sanitize-vr4320
5634 *vr4320:
5635 // end-sanitize-vr4320
5636 // start-sanitize-vr5400
5637 *vr5400:
5638 // end-sanitize-vr5400
5639 // start-sanitize-r5900
5640 *r5900:
5641 // end-sanitize-r5900
5642
5643
5644 010000,10000,000000000000000,000001:COP0:32::TLBR
5645 "tlbr"
5646 *mipsI,mipsII,mipsIII,mipsIV:
5647 *vr5000:
5648 // start-sanitize-vr4320
5649 *vr4320:
5650 // end-sanitize-vr4320
5651 // start-sanitize-vr5400
5652 *vr5400:
5653 // end-sanitize-vr5400
5654 // start-sanitize-r5900
5655 *r5900:
5656 // end-sanitize-r5900
5657
5658
5659 010000,10000,000000000000000,000010:COP0:32::TLBWI
5660 "tlbwi"
5661 *mipsI,mipsII,mipsIII,mipsIV:
5662 *vr5000:
5663 // start-sanitize-vr4320
5664 *vr4320:
5665 // end-sanitize-vr4320
5666 // start-sanitize-vr5400
5667 *vr5400:
5668 // end-sanitize-vr5400
5669 // start-sanitize-r5900
5670 *r5900:
5671 // end-sanitize-r5900
5672
5673
5674 010000,10000,000000000000000,000110:COP0:32::TLBWR
5675 "tlbwr"
5676 *mipsI,mipsII,mipsIII,mipsIV:
5677 *vr5000:
5678 // start-sanitize-vr4320
5679 *vr4320:
5680 // end-sanitize-vr4320
5681 // start-sanitize-vr5400
5682 *vr5400:
5683 // end-sanitize-vr5400
5684 // start-sanitize-r5900
5685 *r5900:
5686 // end-sanitize-r5900
5687
5688 \f
5689 :include:::m16.igen
5690 // start-sanitize-vr4320
5691 :include::vr4320:vr4320.igen
5692 // end-sanitize-vr4320
5693 // start-sanitize-vr5400
5694 :include::vr5400:vr5400.igen
5695 :include:64,f::mdmx.igen
5696 // end-sanitize-vr5400
5697 // start-sanitize-r5900
5698 :include::r5900:r5900.igen
5699 // end-sanitize-r5900
5700 :include:::tx.igen
5701 \f
5702 // start-sanitize-cygnus-never
5703
5704 // // FIXME FIXME FIXME What is this instruction?
5705 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5706 // *mipsI:
5707 // *mipsII:
5708 // *mipsIII:
5709 // *mipsIV:
5710 // // start-sanitize-r5900
5711 // *r5900:
5712 // // end-sanitize-r5900
5713 // *r3900:
5714 // // start-sanitize-tx19
5715 // *tx19:
5716 // // end-sanitize-tx19
5717 // {
5718 //   unsigned32 instruction = instruction_0;
5719 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5720 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5721 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5722 //   {
5723 //     if (CoProcPresent(3))
5724 //       SignalException(CoProcessorUnusable);
5725 //     else
5726 //       SignalException(ReservedInstruction,instruction);
5727 //   }
5728 // }
5729
5730 // end-sanitize-cygnus-never
5731 // start-sanitize-cygnus-never
5732
5733 // // FIXME FIXME FIXME What is this?
5734 // 11100,******,00001:RR:16::SDBBP
5735 // *mips16:
5736 // {
5737 //   unsigned32 instruction = instruction_0;
5738 //   if (have_extendval)
5739 //     SignalException (ReservedInstruction, instruction);
5740 //   {
5741 //     SignalException(DebugBreakPoint,instruction);
5742 //   }
5743 // }
5744
5745 // end-sanitize-cygnus-never
5746 // start-sanitize-cygnus-never
5747
5748 // // FIXME FIXME FIXME What is this?
5749 // 000000,********************,001110:SPECIAL:32::SDBBP
5750 // *r3900:
5751 // {
5752 //   unsigned32 instruction = instruction_0;
5753 //   {
5754 //     SignalException(DebugBreakPoint,instruction);
5755 //   }
5756 // }
5757
5758 // end-sanitize-cygnus-never
5759 // start-sanitize-cygnus-never
5760
5761 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5762 // // isn't yet reconized by this simulator.
5763 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5764 // *vr4100:
5765 // {
5766 //   unsigned32 instruction = instruction_0;
5767 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5768 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5769 //   {
5770 //     CHECKHILO("Multiply-Add");
5771 //     {
5772 //       unsigned64 temp = (op1 * op2);
5773 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5774 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5775 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5776 //     }
5777 //   }
5778 // }
5779
5780 // end-sanitize-cygnus-never
5781 // start-sanitize-cygnus-never
5782
5783 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5784 // // isn't yet reconized by this simulator.
5785 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5786 // *vr4100:
5787 // {
5788 //   unsigned32 instruction = instruction_0;
5789 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5790 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5791 //   {
5792 //     CHECKHILO("Multiply-Add");
5793 //     {
5794 //       unsigned64 temp = (op1 * op2);
5795 //       LO = LO + temp;
5796 //     }
5797 //   }
5798 // }
5799
5800 // end-sanitize-cygnus-never