sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 // Helper:
 102 //
 103 // Check that an access to a HI/LO register meets timing requirements
 104 //
 105 // The following requirements exist:
 106 //
 107 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 108 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 109 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 110 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 111 //
 112
 113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 114 {
 115   if (history->mf.timestamp + 3 > time)
 116     {
 117       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 118                         itable[MY_INDEX].name,
 119                         new, (long) CIA,
 120                         (long) history->mf.cia);
 121       return 0;
 122     }
 123   return 1;
 124 }
 125
 126 :function:::int:check_mt_hilo:hilo_history *history
 127 *mipsI,mipsII,mipsIII,mipsIV:
 128 *vr5000:
 129 // start-sanitize-vr4320
 130 *vr4320:
 131 // end-sanitize-vr4320
 132 // start-sanitize-vr5400
 133 *vr5400:
 134 // end-sanitize-vr5400
 135 {
 136   signed64 time = sim_events_time (SD);
 137   int ok = check_mf_cycles (SD_, history, time, "MT");
 138   history->mt.timestamp = time;
 139   history->mt.cia = CIA;
 140   return ok;
 141 }
 142
 143 :function:::int:check_mt_hilo:hilo_history *history
 144 *r3900:
 145 // start-sanitize-tx19
 146 *tx19:
 147 // end-sanitize-tx19
 148 // start-sanitize-r5900
 149 *r5900:
 150 // end-sanitize-r5900
 151 {
 152   signed64 time = sim_events_time (SD);
 153   history->mt.timestamp = time;
 154   history->mt.cia = CIA;
 155   return 1;
 156 }
 157
 158
 159 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 160 *mipsI,mipsII,mipsIII,mipsIV:
 161 *vr5000:
 162 // start-sanitize-vr4320
 163 *vr4320:
 164 // end-sanitize-vr4320
 165 // start-sanitize-vr5400
 166 *vr5400:
 167 // end-sanitize-vr5400
 168 *r3900:
 169 // start-sanitize-tx19
 170 *tx19:
 171 // end-sanitize-tx19
 172 {
 173   signed64 time = sim_events_time (SD);
 174   int ok = 1;
 175   if (peer != NULL
 176       && peer->mt.timestamp > history->op.timestamp
 177       && history->mf.timestamp < history->op.timestamp)
 178     {
 179       /* The peer has been written to since the last OP yet we have
 180          not */
 181       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 182                         itable[MY_INDEX].name,
 183                         (long) CIA,
 184                         (long) history->op.cia,
 185                         (long) peer->mt.cia);
 186       ok = 0;
 187     }
 188   history->mf.timestamp = time;
 189   history->mf.cia = CIA;
 190   return ok;
 191 }
 192
 193 // start-sanitize-r5900
 194 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 195 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 196 // end-sanitize-r5900
 197 // start-sanitize-r5900
 198 *r5900:
 199 // end-sanitize-r5900
 200 // start-sanitize-r5900
 201 {
 202   /* FIXME: could record the fact that a stall occured if we want */
 203   signed64 time = sim_events_time (SD);
 204   history->mf.timestamp = time;
 205   history->mf.cia = CIA;
 206   return 1;
 207 }
 208 // end-sanitize-r5900
 209
 210
 211 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 212 *mipsI,mipsII,mipsIII,mipsIV:
 213 *vr5000:
 214 // start-sanitize-vr4320
 215 *vr4320:
 216 // end-sanitize-vr4320
 217 // start-sanitize-vr5400
 218 *vr5400:
 219 // end-sanitize-vr5400
 220 {
 221   signed64 time = sim_events_time (SD);
 222   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 223             && check_mf_cycles (SD_, lo, time, "OP"));
 224   hi->op.timestamp = time;
 225   lo->op.timestamp = time;
 226   hi->op.cia = CIA;
 227   lo->op.cia = CIA;
 228   return ok;
 229 }
 230
 231 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 232 // a mf{hi,lo}
 233 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 234 *r3900:
 235 // start-sanitize-tx19
 236 *tx19:
 237 // end-sanitize-tx19
 238 // start-sanitize-r5900
 239 *r5900:
 240 // end-sanitize-r5900
 241 {
 242   /* FIXME: could record the fact that a stall occured if we want */
 243   signed64 time = sim_events_time (SD);
 244   hi->op.timestamp = time;
 245   lo->op.timestamp = time;
 246   hi->op.cia = CIA;
 247   lo->op.cia = CIA;
 248   return 1;
 249 }
 250
 251
 252 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 253 *mipsI,mipsII,mipsIII,mipsIV:
 254 *vr5000:
 255 // start-sanitize-vr4320
 256 *vr4320:
 257 // end-sanitize-vr4320
 258 // start-sanitize-vr5400
 259 *vr5400:
 260 // end-sanitize-vr5400
 261 *r3900:
 262 // start-sanitize-tx19
 263 *tx19:
 264 // end-sanitize-tx19
 265 {
 266   signed64 time = sim_events_time (SD);
 267   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 268             && check_mf_cycles (SD_, lo, time, "OP"));
 269   hi->op.timestamp = time;
 270   lo->op.timestamp = time;
 271   hi->op.cia = CIA;
 272   lo->op.cia = CIA;
 273   return ok;
 274 }
 275
 276
 277 // start-sanitize-r5900
 278 // The r5900 div et.al insns _can_ be exectuted immediatly after
 279 // a mf{hi,lo}
 280 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 281 // end-sanitize-r5900
 282 // start-sanitize-r5900
 283 *r5900:
 284 // end-sanitize-r5900
 285 // start-sanitize-r5900
 286 {
 287   /* FIXME: could record the fact that a stall occured if we want */
 288   signed64 time = sim_events_time (SD);
 289   hi->op.timestamp = time;
 290   lo->op.timestamp = time;
 291   hi->op.cia = CIA;
 292   lo->op.cia = CIA;
 293   return 1;
 294 }
 295 // end-sanitize-r5900
 296
 297
 298
 299 //
 300 // Mips Architecture:
 301 //
 302 //        CPU Instruction Set (mipsI - mipsIV)
 303 //
 304
 305
 306
 307 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 308 "add r<RD>, r<RS>, r<RT>"
 309 *mipsI,mipsII,mipsIII,mipsIV:
 310 *vr5000:
 311 // start-sanitize-vr4320
 312 *vr4320:
 313 // end-sanitize-vr4320
 314 // start-sanitize-vr5400
 315 *vr5400:
 316 // end-sanitize-vr5400
 317 // start-sanitize-r5900
 318 *r5900:
 319 // end-sanitize-r5900
 320 *r3900:
 321 // start-sanitize-tx19
 322 *tx19:
 323 // end-sanitize-tx19
 324 {
 325   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 326   {
 327     ALU32_BEGIN (GPR[RS]);
 328     ALU32_ADD (GPR[RT]);
 329     ALU32_END (GPR[RD]);
 330   }
 331   TRACE_ALU_RESULT (GPR[RD]);
 332 }
 333
 334
 335
 336 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 337 "addi r<RT>, r<RS>, IMMEDIATE"
 338 *mipsI,mipsII,mipsIII,mipsIV:
 339 *vr5000:
 340 // start-sanitize-vr4320
 341 *vr4320:
 342 // end-sanitize-vr4320
 343 // start-sanitize-vr5400
 344 *vr5400:
 345 // end-sanitize-vr5400
 346 // start-sanitize-r5900
 347 *r5900:
 348 // end-sanitize-r5900
 349 *r3900:
 350 // start-sanitize-tx19
 351 *tx19:
 352 // end-sanitize-tx19
 353 {
 354   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 355   {
 356     ALU32_BEGIN (GPR[RS]);
 357     ALU32_ADD (EXTEND16 (IMMEDIATE));
 358     ALU32_END (GPR[RT]);
 359   }
 360   TRACE_ALU_RESULT (GPR[RT]);
 361 }
 362
 363
 364
 365 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 366 {
 367   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 368   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 369   TRACE_ALU_RESULT (GPR[rt]);
 370 }
 371
 372 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 373 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 374 *mipsI,mipsII,mipsIII,mipsIV:
 375 *vr5000:
 376 // start-sanitize-vr4320
 377 *vr4320:
 378 // end-sanitize-vr4320
 379 // start-sanitize-vr5400
 380 *vr5400:
 381 // end-sanitize-vr5400
 382 // start-sanitize-r5900
 383 *r5900:
 384 // end-sanitize-r5900
 385 *r3900:
 386 // start-sanitize-tx19
 387 *tx19:
 388 // end-sanitize-tx19
 389 {
 390   do_addiu (SD_, RS, RT, IMMEDIATE);
 391 }
 392
 393
 394
 395 :function:::void:do_addu:int rs, int rt, int rd
 396 {
 397   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 398   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 399   TRACE_ALU_RESULT (GPR[rd]);
 400 }
 401
 402 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 403 "addu r<RD>, r<RS>, r<RT>"
 404 *mipsI,mipsII,mipsIII,mipsIV:
 405 *vr5000:
 406 // start-sanitize-vr4320
 407 *vr4320:
 408 // end-sanitize-vr4320
 409 // start-sanitize-vr5400
 410 *vr5400:
 411 // end-sanitize-vr5400
 412 // start-sanitize-r5900
 413 *r5900:
 414 // end-sanitize-r5900
 415 *r3900:
 416 // start-sanitize-tx19
 417 *tx19:
 418 // end-sanitize-tx19
 419 {
 420   do_addu (SD_, RS, RT, RD);
 421 }
 422
 423
 424
 425 :function:::void:do_and:int rs, int rt, int rd
 426 {
 427   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 428   GPR[rd] = GPR[rs] & GPR[rt];
 429   TRACE_ALU_RESULT (GPR[rd]);
 430 }
 431
 432 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 433 "and r<RD>, r<RS>, r<RT>"
 434 *mipsI,mipsII,mipsIII,mipsIV:
 435 *vr5000:
 436 // start-sanitize-vr4320
 437 *vr4320:
 438 // end-sanitize-vr4320
 439 // start-sanitize-vr5400
 440 *vr5400:
 441 // end-sanitize-vr5400
 442 // start-sanitize-r5900
 443 *r5900:
 444 // end-sanitize-r5900
 445 *r3900:
 446 // start-sanitize-tx19
 447 *tx19:
 448 // end-sanitize-tx19
 449 {
 450   do_and (SD_, RS, RT, RD);
 451 }
 452
 453
 454
 455 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 456 "and r<RT>, r<RS>, <IMMEDIATE>"
 457 *mipsI,mipsII,mipsIII,mipsIV:
 458 *vr5000:
 459 // start-sanitize-vr4320
 460 *vr4320:
 461 // end-sanitize-vr4320
 462 // start-sanitize-vr5400
 463 *vr5400:
 464 // end-sanitize-vr5400
 465 // start-sanitize-r5900
 466 *r5900:
 467 // end-sanitize-r5900
 468 *r3900:
 469 // start-sanitize-tx19
 470 *tx19:
 471 // end-sanitize-tx19
 472 {
 473   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 474   GPR[RT] = GPR[RS] & IMMEDIATE;
 475   TRACE_ALU_RESULT (GPR[RT]);
 476 }
 477
 478
 479
 480 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 481 "beq r<RS>, r<RT>, <OFFSET>"
 482 *mipsI,mipsII,mipsIII,mipsIV:
 483 *vr5000:
 484 // start-sanitize-vr4320
 485 *vr4320:
 486 // end-sanitize-vr4320
 487 // start-sanitize-vr5400
 488 *vr5400:
 489 // end-sanitize-vr5400
 490 // start-sanitize-r5900
 491 *r5900:
 492 // end-sanitize-r5900
 493 *r3900:
 494 // start-sanitize-tx19
 495 *tx19:
 496 // end-sanitize-tx19
 497 {
 498   address_word offset = EXTEND16 (OFFSET) << 2;
 499   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 500     DELAY_SLOT (NIA + offset);
 501 }
 502
 503
 504
 505 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 506 "beql r<RS>, r<RT>, <OFFSET>"
 507 *mipsII:
 508 *mipsIII:
 509 *mipsIV:
 510 *vr5000:
 511 // start-sanitize-vr4320
 512 *vr4320:
 513 // end-sanitize-vr4320
 514 // start-sanitize-vr5400
 515 *vr5400:
 516 // end-sanitize-vr5400
 517 // start-sanitize-r5900
 518 *r5900:
 519 // end-sanitize-r5900
 520 *r3900:
 521 // start-sanitize-tx19
 522 *tx19:
 523 // end-sanitize-tx19
 524 {
 525   address_word offset = EXTEND16 (OFFSET) << 2;
 526   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 527     DELAY_SLOT (NIA + offset);
 528   else
 529     NULLIFY_NEXT_INSTRUCTION ();
 530 }
 531
 532
 533
 534 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 535 "bgez r<RS>, <OFFSET>"
 536 *mipsI,mipsII,mipsIII,mipsIV:
 537 *vr5000:
 538 // start-sanitize-vr4320
 539 *vr4320:
 540 // end-sanitize-vr4320
 541 // start-sanitize-vr5400
 542 *vr5400:
 543 // end-sanitize-vr5400
 544 // start-sanitize-r5900
 545 *r5900:
 546 // end-sanitize-r5900
 547 *r3900:
 548 // start-sanitize-tx19
 549 *tx19:
 550 // end-sanitize-tx19
 551 {
 552   address_word offset = EXTEND16 (OFFSET) << 2;
 553   if ((signed_word) GPR[RS] >= 0)
 554     DELAY_SLOT (NIA + offset);
 555 }
 556
 557
 558
 559 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 560 "bgezal r<RS>, <OFFSET>"
 561 *mipsI,mipsII,mipsIII,mipsIV:
 562 *vr5000:
 563 // start-sanitize-vr4320
 564 *vr4320:
 565 // end-sanitize-vr4320
 566 // start-sanitize-vr5400
 567 *vr5400:
 568 // end-sanitize-vr5400
 569 // start-sanitize-r5900
 570 *r5900:
 571 // end-sanitize-r5900
 572 *r3900:
 573 // start-sanitize-tx19
 574 *tx19:
 575 // end-sanitize-tx19
 576 {
 577   address_word offset = EXTEND16 (OFFSET) << 2;
 578   RA = (CIA + 8);
 579   if ((signed_word) GPR[RS] >= 0)
 580     DELAY_SLOT (NIA + offset);
 581 }
 582
 583
 584
 585 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 586 "bgezall r<RS>, <OFFSET>"
 587 *mipsII:
 588 *mipsIII:
 589 *mipsIV:
 590 *vr5000:
 591 // start-sanitize-vr4320
 592 *vr4320:
 593 // end-sanitize-vr4320
 594 // start-sanitize-vr5400
 595 *vr5400:
 596 // end-sanitize-vr5400
 597 // start-sanitize-r5900
 598 *r5900:
 599 // end-sanitize-r5900
 600 *r3900:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   address_word offset = EXTEND16 (OFFSET) << 2;
 606   RA = (CIA + 8);
 607   /* NOTE: The branch occurs AFTER the next instruction has been
 608      executed */
 609   if ((signed_word) GPR[RS] >= 0)
 610     DELAY_SLOT (NIA + offset);
 611   else
 612     NULLIFY_NEXT_INSTRUCTION ();
 613 }
 614
 615
 616
 617 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 618 "bgezl r<RS>, <OFFSET>"
 619 *mipsII:
 620 *mipsIII:
 621 *mipsIV:
 622 *vr5000:
 623 // start-sanitize-vr4320
 624 *vr4320:
 625 // end-sanitize-vr4320
 626 // start-sanitize-vr5400
 627 *vr5400:
 628 // end-sanitize-vr5400
 629 // start-sanitize-r5900
 630 *r5900:
 631 // end-sanitize-r5900
 632 *r3900:
 633 // start-sanitize-tx19
 634 *tx19:
 635 // end-sanitize-tx19
 636 {
 637   address_word offset = EXTEND16 (OFFSET) << 2;
 638   if ((signed_word) GPR[RS] >= 0)
 639     DELAY_SLOT (NIA + offset);
 640   else
 641     NULLIFY_NEXT_INSTRUCTION ();
 642 }
 643
 644
 645
 646 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 647 "bgtz r<RS>, <OFFSET>"
 648 *mipsI,mipsII,mipsIII,mipsIV:
 649 *vr5000:
 650 // start-sanitize-vr4320
 651 *vr4320:
 652 // end-sanitize-vr4320
 653 // start-sanitize-vr5400
 654 *vr5400:
 655 // end-sanitize-vr5400
 656 // start-sanitize-r5900
 657 *r5900:
 658 // end-sanitize-r5900
 659 *r3900:
 660 // start-sanitize-tx19
 661 *tx19:
 662 // end-sanitize-tx19
 663 {
 664   address_word offset = EXTEND16 (OFFSET) << 2;
 665   if ((signed_word) GPR[RS] > 0)
 666     DELAY_SLOT (NIA + offset);
 667 }
 668
 669
 670
 671 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 672 "bgtzl r<RS>, <OFFSET>"
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *vr5000:
 677 // start-sanitize-vr4320
 678 *vr4320:
 679 // end-sanitize-vr4320
 680 // start-sanitize-vr5400
 681 *vr5400:
 682 // end-sanitize-vr5400
 683 // start-sanitize-r5900
 684 *r5900:
 685 // end-sanitize-r5900
 686 *r3900:
 687 // start-sanitize-tx19
 688 *tx19:
 689 // end-sanitize-tx19
 690 {
 691   address_word offset = EXTEND16 (OFFSET) << 2;
 692   /* NOTE: The branch occurs AFTER the next instruction has been
 693      executed */
 694   if ((signed_word) GPR[RS] > 0)
 695     DELAY_SLOT (NIA + offset);
 696   else
 697     NULLIFY_NEXT_INSTRUCTION ();
 698 }
 699
 700
 701
 702 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 703 "blez r<RS>, <OFFSET>"
 704 *mipsI,mipsII,mipsIII,mipsIV:
 705 *vr5000:
 706 // start-sanitize-vr4320
 707 *vr4320:
 708 // end-sanitize-vr4320
 709 // start-sanitize-vr5400
 710 *vr5400:
 711 // end-sanitize-vr5400
 712 // start-sanitize-r5900
 713 *r5900:
 714 // end-sanitize-r5900
 715 *r3900:
 716 // start-sanitize-tx19
 717 *tx19:
 718 // end-sanitize-tx19
 719 {
 720   address_word offset = EXTEND16 (OFFSET) << 2;
 721   /* NOTE: The branch occurs AFTER the next instruction has been
 722      executed */
 723   if ((signed_word) GPR[RS] <= 0)
 724     DELAY_SLOT (NIA + offset);
 725 }
 726
 727
 728
 729 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 730 "bgezl r<RS>, <OFFSET>"
 731 *mipsII:
 732 *mipsIII:
 733 *mipsIV:
 734 *vr5000:
 735 // start-sanitize-vr4320
 736 *vr4320:
 737 // end-sanitize-vr4320
 738 // start-sanitize-vr5400
 739 *vr5400:
 740 // end-sanitize-vr5400
 741 // start-sanitize-r5900
 742 *r5900:
 743 // end-sanitize-r5900
 744 *r3900:
 745 // start-sanitize-tx19
 746 *tx19:
 747 // end-sanitize-tx19
 748 {
 749   address_word offset = EXTEND16 (OFFSET) << 2;
 750   if ((signed_word) GPR[RS] <= 0)
 751     DELAY_SLOT (NIA + offset);
 752   else
 753     NULLIFY_NEXT_INSTRUCTION ();
 754 }
 755
 756
 757
 758 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 759 "bltz r<RS>, <OFFSET>"
 760 *mipsI,mipsII,mipsIII,mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-vr5400
 766 *vr5400:
 767 // end-sanitize-vr5400
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 *r3900:
 772 // start-sanitize-tx19
 773 *tx19:
 774 // end-sanitize-tx19
 775 {
 776   address_word offset = EXTEND16 (OFFSET) << 2;
 777   if ((signed_word) GPR[RS] < 0)
 778     DELAY_SLOT (NIA + offset);
 779 }
 780
 781
 782
 783 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 784 "bltzal r<RS>, <OFFSET>"
 785 *mipsI,mipsII,mipsIII,mipsIV:
 786 *vr5000:
 787 // start-sanitize-vr4320
 788 *vr4320:
 789 // end-sanitize-vr4320
 790 // start-sanitize-vr5400
 791 *vr5400:
 792 // end-sanitize-vr5400
 793 // start-sanitize-r5900
 794 *r5900:
 795 // end-sanitize-r5900
 796 *r3900:
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   address_word offset = EXTEND16 (OFFSET) << 2;
 802   RA = (CIA + 8);
 803   /* NOTE: The branch occurs AFTER the next instruction has been
 804      executed */
 805   if ((signed_word) GPR[RS] < 0)
 806     DELAY_SLOT (NIA + offset);
 807 }
 808
 809
 810
 811 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 812 "bltzall r<RS>, <OFFSET>"
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *vr5000:
 817 // start-sanitize-vr4320
 818 *vr4320:
 819 // end-sanitize-vr4320
 820 // start-sanitize-vr5400
 821 *vr5400:
 822 // end-sanitize-vr5400
 823 // start-sanitize-r5900
 824 *r5900:
 825 // end-sanitize-r5900
 826 *r3900:
 827 // start-sanitize-tx19
 828 *tx19:
 829 // end-sanitize-tx19
 830 {
 831   address_word offset = EXTEND16 (OFFSET) << 2;
 832   RA = (CIA + 8);
 833   if ((signed_word) GPR[RS] < 0)
 834     DELAY_SLOT (NIA + offset);
 835   else
 836     NULLIFY_NEXT_INSTRUCTION ();
 837 }
 838
 839
 840
 841 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 842 "bltzl r<RS>, <OFFSET>"
 843 *mipsII:
 844 *mipsIII:
 845 *mipsIV:
 846 *vr5000:
 847 // start-sanitize-vr4320
 848 *vr4320:
 849 // end-sanitize-vr4320
 850 // start-sanitize-vr5400
 851 *vr5400:
 852 // end-sanitize-vr5400
 853 // start-sanitize-r5900
 854 *r5900:
 855 // end-sanitize-r5900
 856 *r3900:
 857 // start-sanitize-tx19
 858 *tx19:
 859 // end-sanitize-tx19
 860 {
 861   address_word offset = EXTEND16 (OFFSET) << 2;
 862   /* NOTE: The branch occurs AFTER the next instruction has been
 863      executed */
 864   if ((signed_word) GPR[RS] < 0)
 865     DELAY_SLOT (NIA + offset);
 866   else
 867     NULLIFY_NEXT_INSTRUCTION ();
 868 }
 869
 870
 871
 872 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 873 "bne r<RS>, r<RT>, <OFFSET>"
 874 *mipsI,mipsII,mipsIII,mipsIV:
 875 *vr5000:
 876 // start-sanitize-vr4320
 877 *vr4320:
 878 // end-sanitize-vr4320
 879 // start-sanitize-vr5400
 880 *vr5400:
 881 // end-sanitize-vr5400
 882 // start-sanitize-r5900
 883 *r5900:
 884 // end-sanitize-r5900
 885 *r3900:
 886 // start-sanitize-tx19
 887 *tx19:
 888 // end-sanitize-tx19
 889 {
 890   address_word offset = EXTEND16 (OFFSET) << 2;
 891   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 892     DELAY_SLOT (NIA + offset);
 893 }
 894
 895
 896
 897 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 898 "bnel r<RS>, r<RT>, <OFFSET>"
 899 *mipsII:
 900 *mipsIII:
 901 *mipsIV:
 902 *vr5000:
 903 // start-sanitize-vr4320
 904 *vr4320:
 905 // end-sanitize-vr4320
 906 // start-sanitize-vr5400
 907 *vr5400:
 908 // end-sanitize-vr5400
 909 // start-sanitize-r5900
 910 *r5900:
 911 // end-sanitize-r5900
 912 *r3900:
 913 // start-sanitize-tx19
 914 *tx19:
 915 // end-sanitize-tx19
 916 {
 917   address_word offset = EXTEND16 (OFFSET) << 2;
 918   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 919     DELAY_SLOT (NIA + offset);
 920   else
 921     NULLIFY_NEXT_INSTRUCTION ();
 922 }
 923
 924
 925
 926 000000,20.CODE,001101:SPECIAL:32::BREAK
 927 "break"
 928 *mipsI,mipsII,mipsIII,mipsIV:
 929 *vr5000:
 930 // start-sanitize-vr4320
 931 *vr4320:
 932 // end-sanitize-vr4320
 933 // start-sanitize-vr5400
 934 *vr5400:
 935 // end-sanitize-vr5400
 936 // start-sanitize-r5900
 937 *r5900:
 938 // end-sanitize-r5900
 939 *r3900:
 940 // start-sanitize-tx19
 941 *tx19:
 942 // end-sanitize-tx19
 943 {
 944   /* Check for some break instruction which are reserved for use by the simulator.  */
 945   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 946   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 947       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 948     {
 949       sim_engine_halt (SD, CPU, NULL, cia,
 950                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 951     }
 952   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 953            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 954     {
 955       if (STATE & simDELAYSLOT)
 956         PC = cia - 4; /* reference the branch instruction */
 957       else
 958         PC = cia;
 959       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
 960     }
 961 // start-sanitize-sky
 962   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
 963     {
 964       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
 965     }
 966   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
 967     {
 968       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
 969     }
 970 // end-sanitize-sky
 971
 972   /* If we get this far, we're not an instruction reserved by the sim.  Raise
 973      the exception. */
 974   SignalException(BreakPoint, instruction_0);
 975 }
 976
 977
 978
 979 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 980 "cop<ZZ> <COP_FUN>"
 981 *mipsI,mipsII,mipsIII,mipsIV:
 982 // start-sanitize-r5900
 983 *r5900:
 984 // end-sanitize-r5900
 985 *r3900:
 986 // start-sanitize-tx19
 987 *tx19:
 988 // end-sanitize-tx19
 989 {
 990   DecodeCoproc (instruction_0);
 991 }
 992
 993
 994
 995 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 996 "dadd r<RD>, r<RS>, r<RT>"
 997 *mipsIII:
 998 *mipsIV:
 999 *vr5000:
1000 // start-sanitize-vr4320
1001 *vr4320:
1002 // end-sanitize-vr4320
1003 // start-sanitize-vr5400
1004 *vr5400:
1005 // end-sanitize-vr5400
1006 // start-sanitize-r5900
1007 *r5900:
1008 // end-sanitize-r5900
1009 // start-sanitize-tx19
1010 *tx19:
1011 // end-sanitize-tx19
1012 {
1013   /* this check's for overflow */
1014   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1015   {
1016     ALU64_BEGIN (GPR[RS]);
1017     ALU64_ADD (GPR[RT]);
1018     ALU64_END (GPR[RD]);
1019   }
1020   TRACE_ALU_RESULT (GPR[RD]);
1021 }
1022
1023
1024
1025 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1026 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1027 *mipsIII:
1028 *mipsIV:
1029 *vr5000:
1030 // start-sanitize-vr4320
1031 *vr4320:
1032 // end-sanitize-vr4320
1033 // start-sanitize-vr5400
1034 *vr5400:
1035 // end-sanitize-vr5400
1036 // start-sanitize-r5900
1037 *r5900:
1038 // end-sanitize-r5900
1039 // start-sanitize-tx19
1040 *tx19:
1041 // end-sanitize-tx19
1042 {
1043   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1044   {
1045     ALU64_BEGIN (GPR[RS]);
1046     ALU64_ADD (EXTEND16 (IMMEDIATE));
1047     ALU64_END (GPR[RT]);
1048   }
1049   TRACE_ALU_RESULT (GPR[RT]);
1050 }
1051
1052
1053
1054 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1055 {
1056   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1057   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1058   TRACE_ALU_RESULT (GPR[rt]);
1059 }
1060
1061 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1062 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1063 *mipsIII:
1064 *mipsIV:
1065 *vr5000:
1066 // start-sanitize-vr4320
1067 *vr4320:
1068 // end-sanitize-vr4320
1069 // start-sanitize-vr5400
1070 *vr5400:
1071 // end-sanitize-vr5400
1072 // start-sanitize-r5900
1073 *r5900:
1074 // end-sanitize-r5900
1075 // start-sanitize-tx19
1076 *tx19:
1077 // end-sanitize-tx19
1078 {
1079   do_daddiu (SD_, RS, RT, IMMEDIATE);
1080 }
1081
1082
1083
1084 :function:::void:do_daddu:int rs, int rt, int rd
1085 {
1086   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1087   GPR[rd] = GPR[rs] + GPR[rt];
1088   TRACE_ALU_RESULT (GPR[rd]);
1089 }
1090
1091 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1092 "daddu r<RD>, r<RS>, r<RT>"
1093 *mipsIII:
1094 *mipsIV:
1095 *vr5000:
1096 // start-sanitize-vr4320
1097 *vr4320:
1098 // end-sanitize-vr4320
1099 // start-sanitize-vr5400
1100 *vr5400:
1101 // end-sanitize-vr5400
1102 // start-sanitize-r5900
1103 *r5900:
1104 // end-sanitize-r5900
1105 // start-sanitize-tx19
1106 *tx19:
1107 // end-sanitize-tx19
1108 {
1109   do_daddu (SD_, RS, RT, RD);
1110 }
1111
1112
1113
1114 :function:64::void:do_ddiv:int rs, int rt
1115 {
1116   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1117   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1118   {
1119     signed64 n = GPR[rs];
1120     signed64 d = GPR[rt];
1121     if (d == 0)
1122       {
1123         LO = SIGNED64 (0x8000000000000000);
1124         HI = 0;
1125       }
1126     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1127       {
1128         LO = SIGNED64 (0x8000000000000000);
1129         HI = 0;
1130       }
1131     else
1132       {
1133         LO = (n / d);
1134         HI = (n % d);
1135       }
1136   }
1137   TRACE_ALU_RESULT2 (HI, LO);
1138 }
1139
1140 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1141 "ddiv r<RS>, r<RT>"
1142 *mipsIII:
1143 *mipsIV:
1144 *vr5000:
1145 // start-sanitize-vr4320
1146 *vr4320:
1147 // end-sanitize-vr4320
1148 // start-sanitize-vr5400
1149 *vr5400:
1150 // end-sanitize-vr5400
1151 // start-sanitize-r5900
1152 *r5900:
1153 // end-sanitize-r5900
1154 // start-sanitize-tx19
1155 *tx19:
1156 // end-sanitize-tx19
1157 {
1158   do_ddiv (SD_, RS, RT);
1159 }
1160
1161
1162
1163 :function:64::void:do_ddivu:int rs, int rt
1164 {
1165   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1166   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1167   {
1168     unsigned64 n = GPR[rs];
1169     unsigned64 d = GPR[rt];
1170     if (d == 0)
1171       {
1172         LO = SIGNED64 (0x8000000000000000);
1173         HI = 0;
1174       }
1175     else
1176       {
1177         LO = (n / d);
1178         HI = (n % d);
1179       }
1180   }
1181   TRACE_ALU_RESULT2 (HI, LO);
1182 }
1183
1184 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1185 "ddivu r<RS>, r<RT>"
1186 *mipsIII:
1187 *mipsIV:
1188 *vr5000:
1189 // start-sanitize-vr4320
1190 *vr4320:
1191 // end-sanitize-vr4320
1192 // start-sanitize-vr5400
1193 *vr5400:
1194 // end-sanitize-vr5400
1195 // start-sanitize-tx19
1196 *tx19:
1197 // end-sanitize-tx19
1198 {
1199   do_ddivu (SD_, RS, RT);
1200 }
1201
1202
1203
1204 :function:::void:do_div:int rs, int rt
1205 {
1206   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1207   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1208   {
1209     signed32 n = GPR[rs];
1210     signed32 d = GPR[rt];
1211     if (d == 0)
1212       {
1213         LO = EXTEND32 (0x80000000);
1214         HI = EXTEND32 (0);
1215       }
1216     else if (n == SIGNED32 (0x80000000) && d == -1)
1217       {
1218         LO = EXTEND32 (0x80000000);
1219         HI = EXTEND32 (0);
1220       }
1221     else
1222       {
1223         LO = EXTEND32 (n / d);
1224         HI = EXTEND32 (n % d);
1225       }
1226   }
1227   TRACE_ALU_RESULT2 (HI, LO);
1228 }
1229
1230 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1231 "div r<RS>, r<RT>"
1232 *mipsI,mipsII,mipsIII,mipsIV:
1233 *vr5000:
1234 // start-sanitize-vr4320
1235 *vr4320:
1236 // end-sanitize-vr4320
1237 // start-sanitize-vr5400
1238 *vr5400:
1239 // end-sanitize-vr5400
1240 // start-sanitize-r5900
1241 *r5900:
1242 // end-sanitize-r5900
1243 *r3900:
1244 // start-sanitize-tx19
1245 *tx19:
1246 // end-sanitize-tx19
1247 {
1248   do_div (SD_, RS, RT);
1249 }
1250
1251
1252
1253 :function:::void:do_divu:int rs, int rt
1254 {
1255   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1256   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1257   {
1258     unsigned32 n = GPR[rs];
1259     unsigned32 d = GPR[rt];
1260     if (d == 0)
1261       {
1262         LO = EXTEND32 (0x80000000);
1263         HI = EXTEND32 (0);
1264       }
1265    else
1266      {
1267        LO = EXTEND32 (n / d);
1268        HI = EXTEND32 (n % d);
1269      }
1270   }
1271   TRACE_ALU_RESULT2 (HI, LO);
1272 }
1273
1274 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1275 "divu r<RS>, r<RT>"
1276 *mipsI,mipsII,mipsIII,mipsIV:
1277 *vr5000:
1278 // start-sanitize-vr4320
1279 *vr4320:
1280 // end-sanitize-vr4320
1281 // start-sanitize-vr5400
1282 *vr5400:
1283 // end-sanitize-vr5400
1284 // start-sanitize-r5900
1285 *r5900:
1286 // end-sanitize-r5900
1287 *r3900:
1288 // start-sanitize-tx19
1289 *tx19:
1290 // end-sanitize-tx19
1291 {
1292   do_divu (SD_, RS, RT);
1293 }
1294
1295
1296
1297 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1298 {
1299   unsigned64 lo;
1300   unsigned64 hi;
1301   unsigned64 m00;
1302   unsigned64 m01;
1303   unsigned64 m10;
1304   unsigned64 m11;
1305   unsigned64 mid;
1306   int sign;
1307   unsigned64 op1 = GPR[rs];
1308   unsigned64 op2 = GPR[rt];
1309   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1310   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1311   /* make signed multiply unsigned */
1312   sign = 0;
1313   if (signed_p)
1314     {
1315       if (op1 < 0)
1316         {
1317           op1 = - op1;
1318           ++sign;
1319         }
1320       if (op2 < 0)
1321         {
1322           op2 = - op2;
1323           ++sign;
1324         }
1325     }
1326   /* multuply out the 4 sub products */
1327   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1328   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1329   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1330   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1331   /* add the products */
1332   mid = ((unsigned64) VH4_8 (m00)
1333          + (unsigned64) VL4_8 (m10)
1334          + (unsigned64) VL4_8 (m01));
1335   lo = U8_4 (mid, m00);
1336   hi = (m11
1337         + (unsigned64) VH4_8 (mid)
1338         + (unsigned64) VH4_8 (m01)
1339         + (unsigned64) VH4_8 (m10));
1340   /* fix the sign */
1341   if (sign & 1)
1342     {
1343       lo = -lo;
1344       if (lo == 0)
1345         hi = -hi;
1346       else
1347         hi = -hi - 1;
1348     }
1349   /* save the result HI/LO (and a gpr) */
1350   LO = lo;
1351   HI = hi;
1352   if (rd != 0)
1353     GPR[rd] = lo;
1354   TRACE_ALU_RESULT2 (HI, LO);
1355 }
1356
1357 :function:::void:do_dmult:int rs, int rt, int rd
1358 {
1359   do_dmultx (SD_, rs, rt, rd, 1);
1360 }
1361
1362 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1363 "dmult r<RS>, r<RT>"
1364 *mipsIII,mipsIV:
1365 // start-sanitize-tx19
1366 *tx19:
1367 // end-sanitize-tx19
1368 // start-sanitize-vr4320
1369 *vr4320:
1370 // end-sanitize-vr4320
1371 {
1372   do_dmult (SD_, RS, RT, 0);
1373 }
1374
1375 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1376 "dmult r<RS>, r<RT>":RD == 0
1377 "dmult r<RD>, r<RS>, r<RT>"
1378 *vr5000:
1379 // start-sanitize-vr5400
1380 *vr5400:
1381 // end-sanitize-vr5400
1382 {
1383   do_dmult (SD_, RS, RT, RD);
1384 }
1385
1386
1387
1388 :function:::void:do_dmultu:int rs, int rt, int rd
1389 {
1390   do_dmultx (SD_, rs, rt, rd, 0);
1391 }
1392
1393 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1394 "dmultu r<RS>, r<RT>"
1395 *mipsIII,mipsIV:
1396 // start-sanitize-tx19
1397 *tx19:
1398 // end-sanitize-tx19
1399 // start-sanitize-vr4320
1400 *vr4320:
1401 // end-sanitize-vr4320
1402 {
1403   do_dmultu (SD_, RS, RT, 0);
1404 }
1405
1406 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1407 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1408 "dmultu r<RS>, r<RT>"
1409 *vr5000:
1410 // start-sanitize-vr5400
1411 *vr5400:
1412 // end-sanitize-vr5400
1413 {
1414   do_dmultu (SD_, RS, RT, RD);
1415 }
1416
1417
1418
1419 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1420 "dsll r<RD>, r<RT>, <SHIFT>"
1421 *mipsIII:
1422 *mipsIV:
1423 *vr5000:
1424 // start-sanitize-vr4320
1425 *vr4320:
1426 // end-sanitize-vr4320
1427 // start-sanitize-vr5400
1428 *vr5400:
1429 // end-sanitize-vr5400
1430 // start-sanitize-r5900
1431 *r5900:
1432 // end-sanitize-r5900
1433 // start-sanitize-tx19
1434 *tx19:
1435 // end-sanitize-tx19
1436 {
1437   int s = SHIFT;
1438   GPR[RD] = GPR[RT] << s;
1439 }
1440
1441
1442 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1443 "dsll32 r<RD>, r<RT>, <SHIFT>"
1444 *mipsIII:
1445 *mipsIV:
1446 *vr5000:
1447 // start-sanitize-vr4320
1448 *vr4320:
1449 // end-sanitize-vr4320
1450 // start-sanitize-vr5400
1451 *vr5400:
1452 // end-sanitize-vr5400
1453 // start-sanitize-r5900
1454 *r5900:
1455 // end-sanitize-r5900
1456 // start-sanitize-tx19
1457 *tx19:
1458 // end-sanitize-tx19
1459 {
1460   int s = 32 + SHIFT;
1461   GPR[RD] = GPR[RT] << s;
1462 }
1463
1464
1465
1466 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1467 "dsllv r<RD>, r<RT>, r<RS>"
1468 *mipsIII:
1469 *mipsIV:
1470 *vr5000:
1471 // start-sanitize-vr4320
1472 *vr4320:
1473 // end-sanitize-vr4320
1474 // start-sanitize-vr5400
1475 *vr5400:
1476 // end-sanitize-vr5400
1477 // start-sanitize-r5900
1478 *r5900:
1479 // end-sanitize-r5900
1480 // start-sanitize-tx19
1481 *tx19:
1482 // end-sanitize-tx19
1483 {
1484   int s = MASKED64 (GPR[RS], 5, 0);
1485   GPR[RD] = GPR[RT] << s;
1486 }
1487
1488
1489
1490 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1491 "dsra r<RD>, r<RT>, <SHIFT>"
1492 *mipsIII:
1493 *mipsIV:
1494 *vr5000:
1495 // start-sanitize-vr4320
1496 *vr4320:
1497 // end-sanitize-vr4320
1498 // start-sanitize-vr5400
1499 *vr5400:
1500 // end-sanitize-vr5400
1501 // start-sanitize-r5900
1502 *r5900:
1503 // end-sanitize-r5900
1504 // start-sanitize-tx19
1505 *tx19:
1506 // end-sanitize-tx19
1507 {
1508   int s = SHIFT;
1509   GPR[RD] = ((signed64) GPR[RT]) >> s;
1510 }
1511
1512
1513 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1514 "dsra32 r<RT>, r<RD>, <SHIFT>"
1515 *mipsIII:
1516 *mipsIV:
1517 *vr5000:
1518 // start-sanitize-vr4320
1519 *vr4320:
1520 // end-sanitize-vr4320
1521 // start-sanitize-vr5400
1522 *vr5400:
1523 // end-sanitize-vr5400
1524 // start-sanitize-r5900
1525 *r5900:
1526 // end-sanitize-r5900
1527 // start-sanitize-tx19
1528 *tx19:
1529 // end-sanitize-tx19
1530 {
1531   int s = 32 + SHIFT;
1532   GPR[RD] = ((signed64) GPR[RT]) >> s;
1533 }
1534
1535
1536 :function:::void:do_dsrav:int rs, int rt, int rd
1537 {
1538   int s = MASKED64 (GPR[rs], 5, 0);
1539   TRACE_ALU_INPUT2 (GPR[rt], s);
1540   GPR[rd] = ((signed64) GPR[rt]) >> s;
1541   TRACE_ALU_RESULT (GPR[rd]);
1542 }
1543
1544 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1545 "dsra32 r<RT>, r<RD>, r<RS>"
1546 *mipsIII:
1547 *mipsIV:
1548 *vr5000:
1549 // start-sanitize-vr4320
1550 *vr4320:
1551 // end-sanitize-vr4320
1552 // start-sanitize-vr5400
1553 *vr5400:
1554 // end-sanitize-vr5400
1555 // start-sanitize-r5900
1556 *r5900:
1557 // end-sanitize-r5900
1558 // start-sanitize-tx19
1559 *tx19:
1560 // end-sanitize-tx19
1561 {
1562   do_dsrav (SD_, RS, RT, RD);
1563 }
1564
1565
1566 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1567 "dsrl r<RD>, r<RT>, <SHIFT>"
1568 *mipsIII:
1569 *mipsIV:
1570 *vr5000:
1571 // start-sanitize-vr4320
1572 *vr4320:
1573 // end-sanitize-vr4320
1574 // start-sanitize-vr5400
1575 *vr5400:
1576 // end-sanitize-vr5400
1577 // start-sanitize-r5900
1578 *r5900:
1579 // end-sanitize-r5900
1580 // start-sanitize-tx19
1581 *tx19:
1582 // end-sanitize-tx19
1583 {
1584   int s = SHIFT;
1585   GPR[RD] = (unsigned64) GPR[RT] >> s;
1586 }
1587
1588
1589 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1590 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1591 *mipsIII:
1592 *mipsIV:
1593 *vr5000:
1594 // start-sanitize-vr4320
1595 *vr4320:
1596 // end-sanitize-vr4320
1597 // start-sanitize-vr5400
1598 *vr5400:
1599 // end-sanitize-vr5400
1600 // start-sanitize-r5900
1601 *r5900:
1602 // end-sanitize-r5900
1603 // start-sanitize-tx19
1604 *tx19:
1605 // end-sanitize-tx19
1606 {
1607   int s = 32 + SHIFT;
1608   GPR[RD] = (unsigned64) GPR[RT] >> s;
1609 }
1610
1611
1612 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1613 "dsrl32 r<RD>, r<RT>, r<RS>"
1614 *mipsIII:
1615 *mipsIV:
1616 *vr5000:
1617 // start-sanitize-vr4320
1618 *vr4320:
1619 // end-sanitize-vr4320
1620 // start-sanitize-vr5400
1621 *vr5400:
1622 // end-sanitize-vr5400
1623 // start-sanitize-r5900
1624 *r5900:
1625 // end-sanitize-r5900
1626 // start-sanitize-tx19
1627 *tx19:
1628 // end-sanitize-tx19
1629 {
1630   int s = MASKED64 (GPR[RS], 5, 0);
1631   GPR[RD] = (unsigned64) GPR[RT] >> s;
1632 }
1633
1634
1635 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1636 "dsub r<RD>, r<RS>, r<RT>"
1637 *mipsIII:
1638 *mipsIV:
1639 *vr5000:
1640 // start-sanitize-vr4320
1641 *vr4320:
1642 // end-sanitize-vr4320
1643 // start-sanitize-vr5400
1644 *vr5400:
1645 // end-sanitize-vr5400
1646 // start-sanitize-r5900
1647 *r5900:
1648 // end-sanitize-r5900
1649 // start-sanitize-tx19
1650 *tx19:
1651 // end-sanitize-tx19
1652 {
1653   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1654   {
1655     ALU64_BEGIN (GPR[RS]);
1656     ALU64_SUB (GPR[RT]);
1657     ALU64_END (GPR[RD]);
1658   }
1659   TRACE_ALU_RESULT (GPR[RD]);
1660 }
1661
1662
1663 :function:::void:do_dsubu:int rs, int rt, int rd
1664 {
1665   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1666   GPR[rd] = GPR[rs] - GPR[rt];
1667   TRACE_ALU_RESULT (GPR[rd]);
1668 }
1669
1670 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1671 "dsubu r<RD>, r<RS>, r<RT>"
1672 *mipsIII:
1673 *mipsIV:
1674 *vr5000:
1675 // start-sanitize-vr4320
1676 *vr4320:
1677 // end-sanitize-vr4320
1678 // start-sanitize-vr5400
1679 *vr5400:
1680 // end-sanitize-vr5400
1681 // start-sanitize-r5900
1682 *r5900:
1683 // end-sanitize-r5900
1684 // start-sanitize-tx19
1685 *tx19:
1686 // end-sanitize-tx19
1687 {
1688   do_dsubu (SD_, RS, RT, RD);
1689 }
1690
1691
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1693 "j <INSTR_INDEX>"
1694 *mipsI,mipsII,mipsIII,mipsIV:
1695 *vr5000:
1696 // start-sanitize-vr4320
1697 *vr4320:
1698 // end-sanitize-vr4320
1699 // start-sanitize-vr5400
1700 *vr5400:
1701 // end-sanitize-vr5400
1702 // start-sanitize-r5900
1703 *r5900:
1704 // end-sanitize-r5900
1705 *r3900:
1706 // start-sanitize-tx19
1707 *tx19:
1708 // end-sanitize-tx19
1709 {
1710   /* NOTE: The region used is that of the delay slot NIA and NOT the
1711      current instruction */
1712   address_word region = (NIA & MASK (63, 28));
1713   DELAY_SLOT (region | (INSTR_INDEX << 2));
1714 }
1715
1716
1717 000011,26.INSTR_INDEX:NORMAL:32::JAL
1718 "jal <INSTR_INDEX>"
1719 *mipsI,mipsII,mipsIII,mipsIV:
1720 *vr5000:
1721 // start-sanitize-vr4320
1722 *vr4320:
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1725 *vr5400:
1726 // end-sanitize-vr5400
1727 // start-sanitize-r5900
1728 *r5900:
1729 // end-sanitize-r5900
1730 *r3900:
1731 // start-sanitize-tx19
1732 *tx19:
1733 // end-sanitize-tx19
1734 {
1735   /* NOTE: The region used is that of the delay slot and NOT the
1736      current instruction */
1737   address_word region = (NIA & MASK (63, 28));
1738   GPR[31] = CIA + 8;
1739   DELAY_SLOT (region | (INSTR_INDEX << 2));
1740 }
1741
1742
1743 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1744 "jalr r<RS>":RD == 31
1745 "jalr r<RD>, r<RS>"
1746 *mipsI,mipsII,mipsIII,mipsIV:
1747 *vr5000:
1748 // start-sanitize-vr4320
1749 *vr4320:
1750 // end-sanitize-vr4320
1751 // start-sanitize-vr5400
1752 *vr5400:
1753 // end-sanitize-vr5400
1754 // start-sanitize-r5900
1755 *r5900:
1756 // end-sanitize-r5900
1757 *r3900:
1758 // start-sanitize-tx19
1759 *tx19:
1760 // end-sanitize-tx19
1761 {
1762   address_word temp = GPR[RS];
1763   GPR[RD] = CIA + 8;
1764   DELAY_SLOT (temp);
1765 }
1766
1767
1768 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1769 "jr r<RS>"
1770 *mipsI,mipsII,mipsIII,mipsIV:
1771 *vr5000:
1772 // start-sanitize-vr4320
1773 *vr4320:
1774 // end-sanitize-vr4320
1775 // start-sanitize-vr5400
1776 *vr5400:
1777 // end-sanitize-vr5400
1778 // start-sanitize-r5900
1779 *r5900:
1780 // end-sanitize-r5900
1781 *r3900:
1782 // start-sanitize-tx19
1783 *tx19:
1784 // end-sanitize-tx19
1785 {
1786   DELAY_SLOT (GPR[RS]);
1787 }
1788
1789
1790 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1791 {
1792   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1793   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1794   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1795   unsigned int byte;
1796   address_word paddr;
1797   int uncached;
1798   unsigned64 memval;
1799   address_word vaddr;
1800
1801   vaddr = base + offset;
1802   if ((vaddr & access) != 0)
1803     SignalExceptionAddressLoad ();
1804   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1805   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1806   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1807   byte = ((vaddr & mask) ^ bigendiancpu);
1808   return (memval >> (8 * byte));
1809 }
1810
1811
1812 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1813 "lb r<RT>, <OFFSET>(r<BASE>)"
1814 *mipsI,mipsII,mipsIII,mipsIV:
1815 *vr5000:
1816 // start-sanitize-vr4320
1817 *vr4320:
1818 // end-sanitize-vr4320
1819 // start-sanitize-vr5400
1820 *vr5400:
1821 // end-sanitize-vr5400
1822 // start-sanitize-r5900
1823 *r5900:
1824 // end-sanitize-r5900
1825 *r3900:
1826 // start-sanitize-tx19
1827 *tx19:
1828 // end-sanitize-tx19
1829 {
1830   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1831 }
1832
1833
1834 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1835 "lbu r<RT>, <OFFSET>(r<BASE>)"
1836 *mipsI,mipsII,mipsIII,mipsIV:
1837 *vr5000:
1838 // start-sanitize-vr4320
1839 *vr4320:
1840 // end-sanitize-vr4320
1841 // start-sanitize-vr5400
1842 *vr5400:
1843 // end-sanitize-vr5400
1844 // start-sanitize-r5900
1845 *r5900:
1846 // end-sanitize-r5900
1847 *r3900:
1848 // start-sanitize-tx19
1849 *tx19:
1850 // end-sanitize-tx19
1851 {
1852   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1853 }
1854
1855
1856 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1857 "ld r<RT>, <OFFSET>(r<BASE>)"
1858 *mipsIII:
1859 *mipsIV:
1860 *vr5000:
1861 // start-sanitize-vr4320
1862 *vr4320:
1863 // end-sanitize-vr4320
1864 // start-sanitize-vr5400
1865 *vr5400:
1866 // end-sanitize-vr5400
1867 // start-sanitize-r5900
1868 *r5900:
1869 // end-sanitize-r5900
1870 // start-sanitize-tx19
1871 *tx19:
1872 // end-sanitize-tx19
1873 {
1874   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1875 }
1876
1877
1878 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1879 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1880 *mipsII:
1881 *mipsIII:
1882 *mipsIV:
1883 *vr5000:
1884 // start-sanitize-vr4320
1885 *vr4320:
1886 // end-sanitize-vr4320
1887 // start-sanitize-vr5400
1888 *vr5400:
1889 // end-sanitize-vr5400
1890 *r3900:
1891 // start-sanitize-tx19
1892 *tx19:
1893 // end-sanitize-tx19
1894 {
1895   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1896 }
1897
1898
1899
1900
1901 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1902 "ldl r<RT>, <OFFSET>(r<BASE>)"
1903 *mipsIII:
1904 *mipsIV:
1905 *vr5000:
1906 // start-sanitize-vr4320
1907 *vr4320:
1908 // end-sanitize-vr4320
1909 // start-sanitize-vr5400
1910 *vr5400:
1911 // end-sanitize-vr5400
1912 // start-sanitize-r5900
1913 *r5900:
1914 // end-sanitize-r5900
1915 // start-sanitize-tx19
1916 *tx19:
1917 // end-sanitize-tx19
1918 {
1919   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1920 }
1921
1922
1923 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1924 "ldr r<RT>, <OFFSET>(r<BASE>)"
1925 *mipsIII:
1926 *mipsIV:
1927 *vr5000:
1928 // start-sanitize-vr4320
1929 *vr4320:
1930 // end-sanitize-vr4320
1931 // start-sanitize-vr5400
1932 *vr5400:
1933 // end-sanitize-vr5400
1934 // start-sanitize-r5900
1935 *r5900:
1936 // end-sanitize-r5900
1937 // start-sanitize-tx19
1938 *tx19:
1939 // end-sanitize-tx19
1940 {
1941   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1942 }
1943
1944
1945 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1946 "lh r<RT>, <OFFSET>(r<BASE>)"
1947 *mipsI,mipsII,mipsIII,mipsIV:
1948 *vr5000:
1949 // start-sanitize-vr4320
1950 *vr4320:
1951 // end-sanitize-vr4320
1952 // start-sanitize-vr5400
1953 *vr5400:
1954 // end-sanitize-vr5400
1955 // start-sanitize-r5900
1956 *r5900:
1957 // end-sanitize-r5900
1958 *r3900:
1959 // start-sanitize-tx19
1960 *tx19:
1961 // end-sanitize-tx19
1962 {
1963   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1964 }
1965
1966
1967 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1968 "lhu r<RT>, <OFFSET>(r<BASE>)"
1969 *mipsI,mipsII,mipsIII,mipsIV:
1970 *vr5000:
1971 // start-sanitize-vr4320
1972 *vr4320:
1973 // end-sanitize-vr4320
1974 // start-sanitize-vr5400
1975 *vr5400:
1976 // end-sanitize-vr5400
1977 // start-sanitize-r5900
1978 *r5900:
1979 // end-sanitize-r5900
1980 *r3900:
1981 // start-sanitize-tx19
1982 *tx19:
1983 // end-sanitize-tx19
1984 {
1985   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1986 }
1987
1988
1989 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1990 "ll r<RT>, <OFFSET>(r<BASE>)"
1991 *mipsII:
1992 *mipsIII:
1993 *mipsIV:
1994 *vr5000:
1995 // start-sanitize-vr4320
1996 *vr4320:
1997 // end-sanitize-vr4320
1998 // start-sanitize-vr5400
1999 *vr5400:
2000 // end-sanitize-vr5400
2001 // start-sanitize-r5900
2002 *r5900:
2003 // end-sanitize-r5900
2004 // start-sanitize-tx19
2005 *tx19:
2006 // end-sanitize-tx19
2007 {
2008   unsigned32 instruction = instruction_0;
2009   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2010   int destreg = ((instruction >> 16) & 0x0000001F);
2011   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2012   {
2013     address_word vaddr = ((unsigned64)op1 + offset);
2014     address_word paddr;
2015     int uncached;
2016     if ((vaddr & 3) != 0)
2017       SignalExceptionAddressLoad();
2018     else
2019       {
2020         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2021           {
2022             unsigned64 memval = 0;
2023             unsigned64 memval1 = 0;
2024             unsigned64 mask = 0x7;
2025             unsigned int shift = 2;
2026             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2027             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2028             unsigned int byte;
2029             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2030             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2031             byte = ((vaddr & mask) ^ (bigend << shift));
2032             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2033             LLBIT = 1;
2034           }
2035       }
2036   }
2037 }
2038
2039
2040 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2041 "lld r<RT>, <OFFSET>(r<BASE>)"
2042 *mipsIII:
2043 *mipsIV:
2044 *vr5000:
2045 // start-sanitize-vr4320
2046 *vr4320:
2047 // end-sanitize-vr4320
2048 // start-sanitize-vr5400
2049 *vr5400:
2050 // end-sanitize-vr5400
2051 // start-sanitize-r5900
2052 *r5900:
2053 // end-sanitize-r5900
2054 // start-sanitize-tx19
2055 *tx19:
2056 // end-sanitize-tx19
2057 {
2058   unsigned32 instruction = instruction_0;
2059   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2060   int destreg = ((instruction >> 16) & 0x0000001F);
2061   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2062   {
2063     address_word vaddr = ((unsigned64)op1 + offset);
2064     address_word paddr;
2065     int uncached;
2066     if ((vaddr & 7) != 0)
2067       SignalExceptionAddressLoad();
2068     else
2069       {
2070         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2071           {
2072             unsigned64 memval = 0;
2073             unsigned64 memval1 = 0;
2074             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2075             GPR[destreg] = memval;
2076             LLBIT = 1;
2077           }
2078       }
2079   }
2080 }
2081
2082
2083 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2084 "lui r<RT>, <IMMEDIATE>"
2085 *mipsI,mipsII,mipsIII,mipsIV:
2086 *vr5000:
2087 // start-sanitize-vr4320
2088 *vr4320:
2089 // end-sanitize-vr4320
2090 // start-sanitize-vr5400
2091 *vr5400:
2092 // end-sanitize-vr5400
2093 // start-sanitize-r5900
2094 *r5900:
2095 // end-sanitize-r5900
2096 *r3900:
2097 // start-sanitize-tx19
2098 *tx19:
2099 // end-sanitize-tx19
2100 {
2101   TRACE_ALU_INPUT1 (IMMEDIATE);
2102   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2103   TRACE_ALU_RESULT (GPR[RT]);
2104 }
2105
2106
2107 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2108 "lw r<RT>, <OFFSET>(r<BASE>)"
2109 *mipsI,mipsII,mipsIII,mipsIV:
2110 *vr5000:
2111 // start-sanitize-vr4320
2112 *vr4320:
2113 // end-sanitize-vr4320
2114 // start-sanitize-vr5400
2115 *vr5400:
2116 // end-sanitize-vr5400
2117 // start-sanitize-r5900
2118 *r5900:
2119 // end-sanitize-r5900
2120 *r3900:
2121 // start-sanitize-tx19
2122 *tx19:
2123 // end-sanitize-tx19
2124 {
2125   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2126 }
2127
2128
2129 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2130 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2131 *mipsI,mipsII,mipsIII,mipsIV:
2132 *vr5000:
2133 // start-sanitize-vr4320
2134 *vr4320:
2135 // end-sanitize-vr4320
2136 // start-sanitize-vr5400
2137 *vr5400:
2138 // end-sanitize-vr5400
2139 // start-sanitize-r5900
2140 *r5900:
2141 // end-sanitize-r5900
2142 *r3900:
2143 // start-sanitize-tx19
2144 *tx19:
2145 // end-sanitize-tx19
2146 {
2147   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2148 }
2149
2150
2151 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2152 {
2153   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2154   address_word reverseendian = (ReverseEndian ? -1 : 0);
2155   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2156   unsigned int byte;
2157   unsigned int word;
2158   address_word paddr;
2159   int uncached;
2160   unsigned64 memval;
2161   address_word vaddr;
2162   int nr_lhs_bits;
2163   int nr_rhs_bits;
2164   unsigned_word lhs_mask;
2165   unsigned_word temp;
2166
2167   vaddr = base + offset;
2168   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2169   paddr = (paddr ^ (reverseendian & mask));
2170   if (BigEndianMem == 0)
2171     paddr = paddr & ~access;
2172
2173   /* compute where within the word/mem we are */
2174   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2175   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2176   nr_lhs_bits = 8 * byte + 8;
2177   nr_rhs_bits = 8 * access - 8 * byte;
2178   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2179
2180   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2181            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2182            (long) ((unsigned64) paddr >> 32), (long) paddr,
2183            word, byte, nr_lhs_bits, nr_rhs_bits); */
2184
2185   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2186   if (word == 0)
2187     {
2188       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2189       temp = (memval << nr_rhs_bits);
2190     }
2191   else
2192     {
2193       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2194       temp = (memval >> nr_lhs_bits);
2195     }
2196   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2197   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2198
2199   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2200            (long) ((unsigned64) memval >> 32), (long) memval,
2201            (long) ((unsigned64) temp >> 32), (long) temp,
2202            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2203            (long) (rt >> 32), (long) rt); */
2204   return rt;
2205 }
2206
2207
2208 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2209 "lwl r<RT>, <OFFSET>(r<BASE>)"
2210 *mipsI,mipsII,mipsIII,mipsIV:
2211 *vr5000:
2212 // start-sanitize-vr4320
2213 *vr4320:
2214 // end-sanitize-vr4320
2215 // start-sanitize-vr5400
2216 *vr5400:
2217 // end-sanitize-vr5400
2218 // start-sanitize-r5900
2219 *r5900:
2220 // end-sanitize-r5900
2221 *r3900:
2222 // start-sanitize-tx19
2223 *tx19:
2224 // end-sanitize-tx19
2225 {
2226   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2227 }
2228
2229
2230 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2231 {
2232   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2233   address_word reverseendian = (ReverseEndian ? -1 : 0);
2234   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2235   unsigned int byte;
2236   address_word paddr;
2237   int uncached;
2238   unsigned64 memval;
2239   address_word vaddr;
2240
2241   vaddr = base + offset;
2242   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2243   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2244   paddr = (paddr ^ (reverseendian & mask));
2245   if (BigEndianMem != 0)
2246     paddr = paddr & ~access;
2247   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2248   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2249   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2250   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2251      (long) paddr, byte, (long) paddr, (long) memval); */
2252   {
2253     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2254     rt &= ~screen;
2255     rt |= (memval >> (8 * byte)) & screen;
2256   }
2257   return rt;
2258 }
2259
2260
2261 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2262 "lwr r<RT>, <OFFSET>(r<BASE>)"
2263 *mipsI,mipsII,mipsIII,mipsIV:
2264 *vr5000:
2265 // start-sanitize-vr4320
2266 *vr4320:
2267 // end-sanitize-vr4320
2268 // start-sanitize-vr5400
2269 *vr5400:
2270 // end-sanitize-vr5400
2271 // start-sanitize-r5900
2272 *r5900:
2273 // end-sanitize-r5900
2274 *r3900:
2275 // start-sanitize-tx19
2276 *tx19:
2277 // end-sanitize-tx19
2278 {
2279   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2280 }
2281
2282
2283 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2284 "lwu r<RT>, <OFFSET>(r<BASE>)"
2285 *mipsIII:
2286 *mipsIV:
2287 *vr5000:
2288 // start-sanitize-vr4320
2289 *vr4320:
2290 // end-sanitize-vr4320
2291 // start-sanitize-vr5400
2292 *vr5400:
2293 // end-sanitize-vr5400
2294 // start-sanitize-r5900
2295 *r5900:
2296 // end-sanitize-r5900
2297 // start-sanitize-tx19
2298 *tx19:
2299 // end-sanitize-tx19
2300 {
2301   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2302 }
2303
2304
2305 :function:::void:do_mfhi:int rd
2306 {
2307   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2308   TRACE_ALU_INPUT1 (HI);
2309   GPR[rd] = HI;
2310   TRACE_ALU_RESULT (GPR[rd]);
2311 }
2312
2313 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2314 "mfhi r<RD>"
2315 *mipsI,mipsII,mipsIII,mipsIV:
2316 *vr5000:
2317 // start-sanitize-vr4320
2318 *vr4320:
2319 // end-sanitize-vr4320
2320 // start-sanitize-vr5400
2321 *vr5400:
2322 // end-sanitize-vr5400
2323 // start-sanitize-r5900
2324 *r5900:
2325 // end-sanitize-r5900
2326 *r3900:
2327 // start-sanitize-tx19
2328 *tx19:
2329 // end-sanitize-tx19
2330 {
2331   do_mfhi (SD_, RD);
2332 }
2333
2334
2335
2336 :function:::void:do_mflo:int rd
2337 {
2338   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2339   TRACE_ALU_INPUT1 (LO);
2340   GPR[rd] = LO;
2341   TRACE_ALU_RESULT (GPR[rd]);
2342 }
2343
2344 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2345 "mflo r<RD>"
2346 *mipsI,mipsII,mipsIII,mipsIV:
2347 *vr5000:
2348 // start-sanitize-vr4320
2349 *vr4320:
2350 // end-sanitize-vr4320
2351 // start-sanitize-vr5400
2352 *vr5400:
2353 // end-sanitize-vr5400
2354 // start-sanitize-r5900
2355 *r5900:
2356 // end-sanitize-r5900
2357 *r3900:
2358 // start-sanitize-tx19
2359 *tx19:
2360 // end-sanitize-tx19
2361 {
2362   do_mflo (SD_, RD);
2363 }
2364
2365
2366
2367 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2368 "movn r<RD>, r<RS>, r<RT>"
2369 *mipsIV:
2370 *vr5000:
2371 // start-sanitize-vr4320
2372 *vr4320:
2373 // end-sanitize-vr4320
2374 // start-sanitize-vr5400
2375 *vr5400:
2376 // end-sanitize-vr5400
2377 // start-sanitize-r5900
2378 *r5900:
2379 // end-sanitize-r5900
2380 {
2381   if (GPR[RT] != 0)
2382     GPR[RD] = GPR[RS];
2383 }
2384
2385
2386
2387 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2388 "movz r<RD>, r<RS>, r<RT>"
2389 *mipsIV:
2390 *vr5000:
2391 // start-sanitize-vr4320
2392 *vr4320:
2393 // end-sanitize-vr4320
2394 // start-sanitize-vr5400
2395 *vr5400:
2396 // end-sanitize-vr5400
2397 // start-sanitize-r5900
2398 *r5900:
2399 // end-sanitize-r5900
2400 {
2401   if (GPR[RT] == 0)
2402     GPR[RD] = GPR[RS];
2403 }
2404
2405
2406
2407 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2408 "mthi r<RS>"
2409 *mipsI,mipsII,mipsIII,mipsIV:
2410 *vr5000:
2411 // start-sanitize-vr4320
2412 *vr4320:
2413 // end-sanitize-vr4320
2414 // start-sanitize-vr5400
2415 *vr5400:
2416 // end-sanitize-vr5400
2417 // start-sanitize-r5900
2418 *r5900:
2419 // end-sanitize-r5900
2420 *r3900:
2421 // start-sanitize-tx19
2422 *tx19:
2423 // end-sanitize-tx19
2424 {
2425   check_mt_hilo (SD_, HIHISTORY);
2426   HI = GPR[RS];
2427 }
2428
2429
2430
2431 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2432 "mtlo r<RS>"
2433 *mipsI,mipsII,mipsIII,mipsIV:
2434 *vr5000:
2435 // start-sanitize-vr4320
2436 *vr4320:
2437 // end-sanitize-vr4320
2438 // start-sanitize-vr5400
2439 *vr5400:
2440 // end-sanitize-vr5400
2441 // start-sanitize-r5900
2442 *r5900:
2443 // end-sanitize-r5900
2444 *r3900:
2445 // start-sanitize-tx19
2446 *tx19:
2447 // end-sanitize-tx19
2448 {
2449   check_mt_hilo (SD_, LOHISTORY);
2450   LO = GPR[RS];
2451 }
2452
2453
2454
2455 :function:::void:do_mult:int rs, int rt, int rd
2456 {
2457   signed64 prod;
2458   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2459   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2460   prod = (((signed64)(signed32) GPR[rs])
2461           * ((signed64)(signed32) GPR[rt]));
2462   LO = EXTEND32 (VL4_8 (prod));
2463   HI = EXTEND32 (VH4_8 (prod));
2464   if (rd != 0)
2465     GPR[rd] = LO;
2466   TRACE_ALU_RESULT2 (HI, LO);
2467 }
2468
2469 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2470 "mult r<RS>, r<RT>"
2471 *mipsI,mipsII,mipsIII,mipsIV:
2472 // start-sanitize-vr4320
2473 *vr4320:
2474 // end-sanitize-vr4320
2475 {
2476   do_mult (SD_, RS, RT, 0);
2477 }
2478
2479
2480 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2481 "mult r<RD>, r<RS>, r<RT>"
2482 *vr5000:
2483 // start-sanitize-vr5400
2484 *vr5400:
2485 // end-sanitize-vr5400
2486 // start-sanitize-r5900
2487 *r5900:
2488 // end-sanitize-r5900
2489 *r3900:
2490 // start-sanitize-tx19
2491 *tx19:
2492 // end-sanitize-tx19
2493 {
2494   do_mult (SD_, RS, RT, RD);
2495 }
2496
2497
2498 :function:::void:do_multu:int rs, int rt, int rd
2499 {
2500   unsigned64 prod;
2501   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2502   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2503   prod = (((unsigned64)(unsigned32) GPR[rs])
2504           * ((unsigned64)(unsigned32) GPR[rt]));
2505   LO = EXTEND32 (VL4_8 (prod));
2506   HI = EXTEND32 (VH4_8 (prod));
2507   if (rd != 0)
2508     GPR[rd] = LO;
2509   TRACE_ALU_RESULT2 (HI, LO);
2510 }
2511
2512 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2513 "multu r<RS>, r<RT>"
2514 *mipsI,mipsII,mipsIII,mipsIV:
2515 // start-sanitize-vr4320
2516 *vr4320:
2517 // end-sanitize-vr4320
2518 {
2519   do_multu (SD_, RS, RT, 0);
2520 }
2521
2522 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2523 "multu r<RD>, r<RS>, r<RT>"
2524 *vr5000:
2525 // start-sanitize-vr5400
2526 *vr5400:
2527 // end-sanitize-vr5400
2528 // start-sanitize-r5900
2529 *r5900:
2530 // end-sanitize-r5900
2531 *r3900:
2532 // start-sanitize-tx19
2533 *tx19:
2534 // end-sanitize-tx19
2535 {
2536   do_multu (SD_, RS, RT, 0);
2537 }
2538
2539
2540 :function:::void:do_nor:int rs, int rt, int rd
2541 {
2542   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2543   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2544   TRACE_ALU_RESULT (GPR[rd]);
2545 }
2546
2547 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2548 "nor r<RD>, r<RS>, r<RT>"
2549 *mipsI,mipsII,mipsIII,mipsIV:
2550 *vr5000:
2551 // start-sanitize-vr4320
2552 *vr4320:
2553 // end-sanitize-vr4320
2554 // start-sanitize-vr5400
2555 *vr5400:
2556 // end-sanitize-vr5400
2557 // start-sanitize-r5900
2558 *r5900:
2559 // end-sanitize-r5900
2560 *r3900:
2561 // start-sanitize-tx19
2562 *tx19:
2563 // end-sanitize-tx19
2564 {
2565   do_nor (SD_, RS, RT, RD);
2566 }
2567
2568
2569 :function:::void:do_or:int rs, int rt, int rd
2570 {
2571   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2572   GPR[rd] = (GPR[rs] | GPR[rt]);
2573   TRACE_ALU_RESULT (GPR[rd]);
2574 }
2575
2576 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2577 "or r<RD>, r<RS>, r<RT>"
2578 *mipsI,mipsII,mipsIII,mipsIV:
2579 *vr5000:
2580 // start-sanitize-vr4320
2581 *vr4320:
2582 // end-sanitize-vr4320
2583 // start-sanitize-vr5400
2584 *vr5400:
2585 // end-sanitize-vr5400
2586 // start-sanitize-r5900
2587 *r5900:
2588 // end-sanitize-r5900
2589 *r3900:
2590 // start-sanitize-tx19
2591 *tx19:
2592 // end-sanitize-tx19
2593 {
2594   do_or (SD_, RS, RT, RD);
2595 }
2596
2597
2598
2599 :function:::void:do_ori:int rs, int rt, unsigned immediate
2600 {
2601   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2602   GPR[rt] = (GPR[rs] | immediate);
2603   TRACE_ALU_RESULT (GPR[rt]);
2604 }
2605
2606 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2607 "ori r<RT>, r<RS>, <IMMEDIATE>"
2608 *mipsI,mipsII,mipsIII,mipsIV:
2609 *vr5000:
2610 // start-sanitize-vr4320
2611 *vr4320:
2612 // end-sanitize-vr4320
2613 // start-sanitize-vr5400
2614 *vr5400:
2615 // end-sanitize-vr5400
2616 // start-sanitize-r5900
2617 *r5900:
2618 // end-sanitize-r5900
2619 *r3900:
2620 // start-sanitize-tx19
2621 *tx19:
2622 // end-sanitize-tx19
2623 {
2624   do_ori (SD_, RS, RT, IMMEDIATE);
2625 }
2626
2627
2628 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2629 *mipsIV:
2630 *vr5000:
2631 // start-sanitize-vr4320
2632 *vr4320:
2633 // end-sanitize-vr4320
2634 // start-sanitize-vr5400
2635 *vr5400:
2636 // end-sanitize-vr5400
2637 // start-sanitize-r5900
2638 *r5900:
2639 // end-sanitize-r5900
2640 {
2641   unsigned32 instruction = instruction_0;
2642   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2643   int hint = ((instruction >> 16) & 0x0000001F);
2644   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2645   {
2646     address_word vaddr = ((unsigned64)op1 + offset);
2647     address_word paddr;
2648     int uncached;
2649     {
2650       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2651         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2652     }
2653   }
2654 }
2655
2656 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2657 {
2658   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2659   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2660   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2661   unsigned int byte;
2662   address_word paddr;
2663   int uncached;
2664   unsigned64 memval;
2665   address_word vaddr;
2666
2667   vaddr = base + offset;
2668   if ((vaddr & access) != 0)
2669     SignalExceptionAddressStore ();
2670   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2671   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2672   byte = ((vaddr & mask) ^ bigendiancpu);
2673   memval = (word << (8 * byte));
2674   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2675 }
2676
2677
2678 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2679 "sb r<RT>, <OFFSET>(r<BASE>)"
2680 *mipsI,mipsII,mipsIII,mipsIV:
2681 *vr5000:
2682 // start-sanitize-vr4320
2683 *vr4320:
2684 // end-sanitize-vr4320
2685 // start-sanitize-vr5400
2686 *vr5400:
2687 // end-sanitize-vr5400
2688 // start-sanitize-r5900
2689 *r5900:
2690 // end-sanitize-r5900
2691 *r3900:
2692 // start-sanitize-tx19
2693 *tx19:
2694 // end-sanitize-tx19
2695 {
2696   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2697 }
2698
2699
2700 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2701 "sc r<RT>, <OFFSET>(r<BASE>)"
2702 *mipsII:
2703 *mipsIII:
2704 *mipsIV:
2705 *vr5000:
2706 // start-sanitize-vr4320
2707 *vr4320:
2708 // end-sanitize-vr4320
2709 // start-sanitize-vr5400
2710 *vr5400:
2711 // end-sanitize-vr5400
2712 // start-sanitize-r5900
2713 *r5900:
2714 // end-sanitize-r5900
2715 // start-sanitize-tx19
2716 *tx19:
2717 // end-sanitize-tx19
2718 {
2719   unsigned32 instruction = instruction_0;
2720   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2721   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2722   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2723   {
2724     address_word vaddr = ((unsigned64)op1 + offset);
2725     address_word paddr;
2726     int uncached;
2727     if ((vaddr & 3) != 0)
2728       SignalExceptionAddressStore();
2729     else
2730       {
2731         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2732           {
2733             unsigned64 memval = 0;
2734             unsigned64 memval1 = 0;
2735             unsigned64 mask = 0x7;
2736             unsigned int byte;
2737             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2738             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2739             memval = ((unsigned64) op2 << (8 * byte));
2740             if (LLBIT)
2741               {
2742                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2743               }
2744             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2745           }
2746       }
2747   }
2748 }
2749
2750
2751 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2752 "scd r<RT>, <OFFSET>(r<BASE>)"
2753 *mipsIII:
2754 *mipsIV:
2755 *vr5000:
2756 // start-sanitize-vr4320
2757 *vr4320:
2758 // end-sanitize-vr4320
2759 // start-sanitize-vr5400
2760 *vr5400:
2761 // end-sanitize-vr5400
2762 // start-sanitize-r5900
2763 *r5900:
2764 // end-sanitize-r5900
2765 // start-sanitize-tx19
2766 *tx19:
2767 // end-sanitize-tx19
2768 {
2769   unsigned32 instruction = instruction_0;
2770   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2771   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2772   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2773   {
2774     address_word vaddr = ((unsigned64)op1 + offset);
2775     address_word paddr;
2776     int uncached;
2777     if ((vaddr & 7) != 0)
2778       SignalExceptionAddressStore();
2779     else
2780       {
2781         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2782           {
2783             unsigned64 memval = 0;
2784             unsigned64 memval1 = 0;
2785             memval = op2;
2786             if (LLBIT)
2787               {
2788                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2789               }
2790             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2791           }
2792       }
2793   }
2794 }
2795
2796
2797 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2798 "sd r<RT>, <OFFSET>(r<BASE>)"
2799 *mipsIII:
2800 *mipsIV:
2801 *vr5000:
2802 // start-sanitize-vr4320
2803 *vr4320:
2804 // end-sanitize-vr4320
2805 // start-sanitize-vr5400
2806 *vr5400:
2807 // end-sanitize-vr5400
2808 // start-sanitize-r5900
2809 *r5900:
2810 // end-sanitize-r5900
2811 // start-sanitize-tx19
2812 *tx19:
2813 // end-sanitize-tx19
2814 {
2815   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2816 }
2817
2818
2819 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2820 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2821 *mipsII:
2822 *mipsIII:
2823 *mipsIV:
2824 *vr5000:
2825 // start-sanitize-vr4320
2826 *vr4320:
2827 // end-sanitize-vr4320
2828 // start-sanitize-vr5400
2829 *vr5400:
2830 // end-sanitize-vr5400
2831 // start-sanitize-r5900
2832 *r5900:
2833 // end-sanitize-r5900
2834 // start-sanitize-tx19
2835 *tx19:
2836 // end-sanitize-tx19
2837 {
2838   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2839 }
2840
2841
2842 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2843 "sdl r<RT>, <OFFSET>(r<BASE>)"
2844 *mipsIII:
2845 *mipsIV:
2846 *vr5000:
2847 // start-sanitize-vr4320
2848 *vr4320:
2849 // end-sanitize-vr4320
2850 // start-sanitize-vr5400
2851 *vr5400:
2852 // end-sanitize-vr5400
2853 // start-sanitize-r5900
2854 *r5900:
2855 // end-sanitize-r5900
2856 // start-sanitize-tx19
2857 *tx19:
2858 // end-sanitize-tx19
2859 {
2860   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2861 }
2862
2863
2864 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2865 "sdr r<RT>, <OFFSET>(r<BASE>)"
2866 *mipsIII:
2867 *mipsIV:
2868 *vr5000:
2869 // start-sanitize-vr4320
2870 *vr4320:
2871 // end-sanitize-vr4320
2872 // start-sanitize-vr5400
2873 *vr5400:
2874 // end-sanitize-vr5400
2875 // start-sanitize-r5900
2876 *r5900:
2877 // end-sanitize-r5900
2878 // start-sanitize-tx19
2879 *tx19:
2880 // end-sanitize-tx19
2881 {
2882   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2883 }
2884
2885
2886 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2887 "sh r<RT>, <OFFSET>(r<BASE>)"
2888 *mipsI,mipsII,mipsIII,mipsIV:
2889 *vr5000:
2890 // start-sanitize-vr4320
2891 *vr4320:
2892 // end-sanitize-vr4320
2893 // start-sanitize-vr5400
2894 *vr5400:
2895 // end-sanitize-vr5400
2896 // start-sanitize-r5900
2897 *r5900:
2898 // end-sanitize-r5900
2899 *r3900:
2900 // start-sanitize-tx19
2901 *tx19:
2902 // end-sanitize-tx19
2903 {
2904   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2905 }
2906
2907
2908 :function:::void:do_sll:int rt, int rd, int shift
2909 {
2910   unsigned32 temp = (GPR[rt] << shift);
2911   TRACE_ALU_INPUT2 (GPR[rt], shift);
2912   GPR[rd] = EXTEND32 (temp);
2913   TRACE_ALU_RESULT (GPR[rd]);
2914 }
2915
2916 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2917 "sll r<RD>, r<RT>, <SHIFT>"
2918 *mipsI,mipsII,mipsIII,mipsIV:
2919 *vr5000:
2920 // start-sanitize-vr4320
2921 *vr4320:
2922 // end-sanitize-vr4320
2923 // start-sanitize-vr5400
2924 *vr5400:
2925 // end-sanitize-vr5400
2926 // start-sanitize-r5900
2927 *r5900:
2928 // end-sanitize-r5900
2929 *r3900:
2930 // start-sanitize-tx19
2931 *tx19:
2932 // end-sanitize-tx19
2933 {
2934   do_sll (SD_, RT, RD, SHIFT);
2935 }
2936
2937
2938 :function:::void:do_sllv:int rs, int rt, int rd
2939 {
2940   int s = MASKED (GPR[rs], 4, 0);
2941   unsigned32 temp = (GPR[rt] << s);
2942   TRACE_ALU_INPUT2 (GPR[rt], s);
2943   GPR[rd] = EXTEND32 (temp);
2944   TRACE_ALU_RESULT (GPR[rd]);
2945 }
2946
2947 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2948 "sllv r<RD>, r<RT>, r<RS>"
2949 *mipsI,mipsII,mipsIII,mipsIV:
2950 *vr5000:
2951 // start-sanitize-vr4320
2952 *vr4320:
2953 // end-sanitize-vr4320
2954 // start-sanitize-vr5400
2955 *vr5400:
2956 // end-sanitize-vr5400
2957 // start-sanitize-r5900
2958 *r5900:
2959 // end-sanitize-r5900
2960 *r3900:
2961 // start-sanitize-tx19
2962 *tx19:
2963 // end-sanitize-tx19
2964 {
2965   do_sllv (SD_, RS, RT, RD);
2966 }
2967
2968
2969 :function:::void:do_slt:int rs, int rt, int rd
2970 {
2971   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2972   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2973   TRACE_ALU_RESULT (GPR[rd]);
2974 }
2975
2976 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2977 "slt r<RD>, r<RS>, r<RT>"
2978 *mipsI,mipsII,mipsIII,mipsIV:
2979 *vr5000:
2980 // start-sanitize-vr4320
2981 *vr4320:
2982 // end-sanitize-vr4320
2983 // start-sanitize-vr5400
2984 *vr5400:
2985 // end-sanitize-vr5400
2986 // start-sanitize-r5900
2987 *r5900:
2988 // end-sanitize-r5900
2989 *r3900:
2990 // start-sanitize-tx19
2991 *tx19:
2992 // end-sanitize-tx19
2993 {
2994   do_slt (SD_, RS, RT, RD);
2995 }
2996
2997
2998 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2999 {
3000   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3001   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3002   TRACE_ALU_RESULT (GPR[rt]);
3003 }
3004
3005 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3006 "slti r<RT>, r<RS>, <IMMEDIATE>"
3007 *mipsI,mipsII,mipsIII,mipsIV:
3008 *vr5000:
3009 // start-sanitize-vr4320
3010 *vr4320:
3011 // end-sanitize-vr4320
3012 // start-sanitize-vr5400
3013 *vr5400:
3014 // end-sanitize-vr5400
3015 // start-sanitize-r5900
3016 *r5900:
3017 // end-sanitize-r5900
3018 *r3900:
3019 // start-sanitize-tx19
3020 *tx19:
3021 // end-sanitize-tx19
3022 {
3023   do_slti (SD_, RS, RT, IMMEDIATE);
3024 }
3025
3026
3027 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3028 {
3029   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3030   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3031   TRACE_ALU_RESULT (GPR[rt]);
3032 }
3033
3034 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3035 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3036 *mipsI,mipsII,mipsIII,mipsIV:
3037 *vr5000:
3038 // start-sanitize-vr4320
3039 *vr4320:
3040 // end-sanitize-vr4320
3041 // start-sanitize-vr5400
3042 *vr5400:
3043 // end-sanitize-vr5400
3044 // start-sanitize-r5900
3045 *r5900:
3046 // end-sanitize-r5900
3047 *r3900:
3048 // start-sanitize-tx19
3049 *tx19:
3050 // end-sanitize-tx19
3051 {
3052   do_sltiu (SD_, RS, RT, IMMEDIATE);
3053 }
3054
3055
3056
3057 :function:::void:do_sltu:int rs, int rt, int rd
3058 {
3059   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3060   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3061   TRACE_ALU_RESULT (GPR[rd]);
3062 }
3063
3064 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3065 "sltu r<RD>, r<RS>, r<RT>"
3066 *mipsI,mipsII,mipsIII,mipsIV:
3067 *vr5000:
3068 // start-sanitize-vr4320
3069 *vr4320:
3070 // end-sanitize-vr4320
3071 // start-sanitize-vr5400
3072 *vr5400:
3073 // end-sanitize-vr5400
3074 // start-sanitize-r5900
3075 *r5900:
3076 // end-sanitize-r5900
3077 *r3900:
3078 // start-sanitize-tx19
3079 *tx19:
3080 // end-sanitize-tx19
3081 {
3082   do_sltu (SD_, RS, RT, RD);
3083 }
3084
3085
3086 :function:::void:do_sra:int rt, int rd, int shift
3087 {
3088   signed32 temp = (signed32) GPR[rt] >> shift;
3089   TRACE_ALU_INPUT2 (GPR[rt], shift);
3090   GPR[rd] = EXTEND32 (temp);
3091   TRACE_ALU_RESULT (GPR[rd]);
3092 }
3093
3094 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3095 "sra r<RD>, r<RT>, <SHIFT>"
3096 *mipsI,mipsII,mipsIII,mipsIV:
3097 *vr5000:
3098 // start-sanitize-vr4320
3099 *vr4320:
3100 // end-sanitize-vr4320
3101 // start-sanitize-vr5400
3102 *vr5400:
3103 // end-sanitize-vr5400
3104 // start-sanitize-r5900
3105 *r5900:
3106 // end-sanitize-r5900
3107 *r3900:
3108 // start-sanitize-tx19
3109 *tx19:
3110 // end-sanitize-tx19
3111 {
3112   do_sra (SD_, RT, RD, SHIFT);
3113 }
3114
3115
3116
3117 :function:::void:do_srav:int rs, int rt, int rd
3118 {
3119   int s = MASKED (GPR[rs], 4, 0);
3120   signed32 temp = (signed32) GPR[rt] >> s;
3121   TRACE_ALU_INPUT2 (GPR[rt], s);
3122   GPR[rd] = EXTEND32 (temp);
3123   TRACE_ALU_RESULT (GPR[rd]);
3124 }
3125
3126 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3127 "srav r<RD>, r<RT>, r<RS>"
3128 *mipsI,mipsII,mipsIII,mipsIV:
3129 *vr5000:
3130 // start-sanitize-vr4320
3131 *vr4320:
3132 // end-sanitize-vr4320
3133 // start-sanitize-vr5400
3134 *vr5400:
3135 // end-sanitize-vr5400
3136 // start-sanitize-r5900
3137 *r5900:
3138 // end-sanitize-r5900
3139 *r3900:
3140 // start-sanitize-tx19
3141 *tx19:
3142 // end-sanitize-tx19
3143 {
3144   do_srav (SD_, RS, RT, RD);
3145 }
3146
3147
3148
3149 :function:::void:do_srl:int rt, int rd, int shift
3150 {
3151   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3152   TRACE_ALU_INPUT2 (GPR[rt], shift);
3153   GPR[rd] = EXTEND32 (temp);
3154   TRACE_ALU_RESULT (GPR[rd]);
3155 }
3156
3157 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3158 "srl r<RD>, r<RT>, <SHIFT>"
3159 *mipsI,mipsII,mipsIII,mipsIV:
3160 *vr5000:
3161 // start-sanitize-vr4320
3162 *vr4320:
3163 // end-sanitize-vr4320
3164 // start-sanitize-vr5400
3165 *vr5400:
3166 // end-sanitize-vr5400
3167 // start-sanitize-r5900
3168 *r5900:
3169 // end-sanitize-r5900
3170 *r3900:
3171 // start-sanitize-tx19
3172 *tx19:
3173 // end-sanitize-tx19
3174 {
3175   do_srl (SD_, RT, RD, SHIFT);
3176 }
3177
3178
3179 :function:::void:do_srlv:int rs, int rt, int rd
3180 {
3181   int s = MASKED (GPR[rs], 4, 0);
3182   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3183   TRACE_ALU_INPUT2 (GPR[rt], s);
3184   GPR[rd] = EXTEND32 (temp);
3185   TRACE_ALU_RESULT (GPR[rd]);
3186 }
3187
3188 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3189 "srlv r<RD>, r<RT>, r<RS>"
3190 *mipsI,mipsII,mipsIII,mipsIV:
3191 *vr5000:
3192 // start-sanitize-vr4320
3193 *vr4320:
3194 // end-sanitize-vr4320
3195 // start-sanitize-vr5400
3196 *vr5400:
3197 // end-sanitize-vr5400
3198 // start-sanitize-r5900
3199 *r5900:
3200 // end-sanitize-r5900
3201 *r3900:
3202 // start-sanitize-tx19
3203 *tx19:
3204 // end-sanitize-tx19
3205 {
3206   do_srlv (SD_, RS, RT, RD);
3207 }
3208
3209
3210 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3211 "sub r<RD>, r<RS>, r<RT>"
3212 *mipsI,mipsII,mipsIII,mipsIV:
3213 *vr5000:
3214 // start-sanitize-vr4320
3215 *vr4320:
3216 // end-sanitize-vr4320
3217 // start-sanitize-vr5400
3218 *vr5400:
3219 // end-sanitize-vr5400
3220 // start-sanitize-r5900
3221 *r5900:
3222 // end-sanitize-r5900
3223 *r3900:
3224 // start-sanitize-tx19
3225 *tx19:
3226 // end-sanitize-tx19
3227 {
3228   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3229   {
3230     ALU32_BEGIN (GPR[RS]);
3231     ALU32_SUB (GPR[RT]);
3232     ALU32_END (GPR[RD]);
3233   }
3234   TRACE_ALU_RESULT (GPR[RD]);
3235 }
3236
3237
3238 :function:::void:do_subu:int rs, int rt, int rd
3239 {
3240   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3241   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3242   TRACE_ALU_RESULT (GPR[rd]);
3243 }
3244
3245 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3246 "subu r<RD>, r<RS>, r<RT>"
3247 *mipsI,mipsII,mipsIII,mipsIV:
3248 *vr5000:
3249 // start-sanitize-vr4320
3250 *vr4320:
3251 // end-sanitize-vr4320
3252 // start-sanitize-vr5400
3253 *vr5400:
3254 // end-sanitize-vr5400
3255 // start-sanitize-r5900
3256 *r5900:
3257 // end-sanitize-r5900
3258 *r3900:
3259 // start-sanitize-tx19
3260 *tx19:
3261 // end-sanitize-tx19
3262 {
3263   do_subu (SD_, RS, RT, RD);
3264 }
3265
3266
3267 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3268 "sw r<RT>, <OFFSET>(r<BASE>)"
3269 *mipsI,mipsII,mipsIII,mipsIV:
3270 // start-sanitize-tx19
3271 *tx19:
3272 // end-sanitize-tx19
3273 *r3900:
3274 // start-sanitize-vr4320
3275 *vr4320:
3276 // end-sanitize-vr4320
3277 *vr5000:
3278 // start-sanitize-vr5400
3279 *vr5400:
3280 // end-sanitize-vr5400
3281 // start-sanitize-r5900
3282 *r5900:
3283 // end-sanitize-r5900
3284 {
3285   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3286 }
3287
3288
3289 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3290 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3291 *mipsI,mipsII,mipsIII,mipsIV:
3292 *vr5000:
3293 // start-sanitize-vr4320
3294 *vr4320:
3295 // end-sanitize-vr4320
3296 // start-sanitize-vr5400
3297 *vr5400:
3298 // end-sanitize-vr5400
3299 *r3900:
3300 // start-sanitize-tx19
3301 *tx19:
3302 // end-sanitize-tx19
3303 {
3304   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3305 }
3306
3307
3308
3309 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3310 {
3311   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3312   address_word reverseendian = (ReverseEndian ? -1 : 0);
3313   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3314   unsigned int byte;
3315   unsigned int word;
3316   address_word paddr;
3317   int uncached;
3318   unsigned64 memval;
3319   address_word vaddr;
3320   int nr_lhs_bits;
3321   int nr_rhs_bits;
3322
3323   vaddr = base + offset;
3324   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3325   paddr = (paddr ^ (reverseendian & mask));
3326   if (BigEndianMem == 0)
3327     paddr = paddr & ~access;
3328
3329   /* compute where within the word/mem we are */
3330   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3331   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3332   nr_lhs_bits = 8 * byte + 8;
3333   nr_rhs_bits = 8 * access - 8 * byte;
3334   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3335   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3336            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3337            (long) ((unsigned64) paddr >> 32), (long) paddr,
3338            word, byte, nr_lhs_bits, nr_rhs_bits); */
3339
3340   if (word == 0)
3341     {
3342       memval = (rt >> nr_rhs_bits);
3343     }
3344   else
3345     {
3346       memval = (rt << nr_lhs_bits);
3347     }
3348   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3349            (long) ((unsigned64) rt >> 32), (long) rt,
3350            (long) ((unsigned64) memval >> 32), (long) memval); */
3351   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3352 }
3353
3354
3355 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3356 "swl r<RT>, <OFFSET>(r<BASE>)"
3357 *mipsI,mipsII,mipsIII,mipsIV:
3358 *vr5000:
3359 // start-sanitize-vr4320
3360 *vr4320:
3361 // end-sanitize-vr4320
3362 // start-sanitize-vr5400
3363 *vr5400:
3364 // end-sanitize-vr5400
3365 // start-sanitize-r5900
3366 *r5900:
3367 // end-sanitize-r5900
3368 *r3900:
3369 // start-sanitize-tx19
3370 *tx19:
3371 // end-sanitize-tx19
3372 {
3373   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3374 }
3375
3376
3377 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3378 {
3379   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3380   address_word reverseendian = (ReverseEndian ? -1 : 0);
3381   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3382   unsigned int byte;
3383   address_word paddr;
3384   int uncached;
3385   unsigned64 memval;
3386   address_word vaddr;
3387
3388   vaddr = base + offset;
3389   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3390   paddr = (paddr ^ (reverseendian & mask));
3391   if (BigEndianMem != 0)
3392     paddr &= ~access;
3393   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3394   memval = (rt << (byte * 8));
3395   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3396 }
3397
3398 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3399 "swr r<RT>, <OFFSET>(r<BASE>)"
3400 *mipsI,mipsII,mipsIII,mipsIV:
3401 *vr5000:
3402 // start-sanitize-vr4320
3403 *vr4320:
3404 // end-sanitize-vr4320
3405 // start-sanitize-vr5400
3406 *vr5400:
3407 // end-sanitize-vr5400
3408 // start-sanitize-r5900
3409 *r5900:
3410 // end-sanitize-r5900
3411 *r3900:
3412 // start-sanitize-tx19
3413 *tx19:
3414 // end-sanitize-tx19
3415 {
3416   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3417 }
3418
3419
3420 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3421 "sync":STYPE == 0
3422 "sync <STYPE>"
3423 *mipsII:
3424 *mipsIII:
3425 *mipsIV:
3426 *vr5000:
3427 // start-sanitize-vr4320
3428 *vr4320:
3429 // end-sanitize-vr4320
3430 // start-sanitize-vr5400
3431 *vr5400:
3432 // end-sanitize-vr5400
3433 // start-sanitize-r5900
3434 *r5900:
3435 // end-sanitize-r5900
3436 *r3900:
3437 // start-sanitize-tx19
3438 *tx19:
3439 // end-sanitize-tx19
3440 {
3441   SyncOperation (STYPE);
3442 }
3443
3444
3445 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3446 "syscall <CODE>"
3447 *mipsI,mipsII,mipsIII,mipsIV:
3448 *vr5000:
3449 // start-sanitize-vr4320
3450 *vr4320:
3451 // end-sanitize-vr4320
3452 // start-sanitize-vr5400
3453 *vr5400:
3454 // end-sanitize-vr5400
3455 // start-sanitize-r5900
3456 *r5900:
3457 // end-sanitize-r5900
3458 *r3900:
3459 // start-sanitize-tx19
3460 *tx19:
3461 // end-sanitize-tx19
3462 {
3463   SignalException(SystemCall, instruction_0);
3464 }
3465
3466
3467 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3468 "teq r<RS>, r<RT>"
3469 *mipsII:
3470 *mipsIII:
3471 *mipsIV:
3472 *vr5000:
3473 // start-sanitize-vr4320
3474 *vr4320:
3475 // end-sanitize-vr4320
3476 // start-sanitize-vr5400
3477 *vr5400:
3478 // end-sanitize-vr5400
3479 // start-sanitize-r5900
3480 *r5900:
3481 // end-sanitize-r5900
3482 // start-sanitize-tx19
3483 *tx19:
3484 // end-sanitize-tx19
3485 {
3486   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3487     SignalException(Trap, instruction_0);
3488 }
3489
3490
3491 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3492 "teqi r<RS>, <IMMEDIATE>"
3493 *mipsII:
3494 *mipsIII:
3495 *mipsIV:
3496 *vr5000:
3497 // start-sanitize-vr4320
3498 *vr4320:
3499 // end-sanitize-vr4320
3500 // start-sanitize-vr5400
3501 *vr5400:
3502 // end-sanitize-vr5400
3503 // start-sanitize-r5900
3504 *r5900:
3505 // end-sanitize-r5900
3506 // start-sanitize-tx19
3507 *tx19:
3508 // end-sanitize-tx19
3509 {
3510   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3511     SignalException(Trap, instruction_0);
3512 }
3513
3514
3515 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3516 "tge r<RS>, r<RT>"
3517 *mipsII:
3518 *mipsIII:
3519 *mipsIV:
3520 *vr5000:
3521 // start-sanitize-vr4320
3522 *vr4320:
3523 // end-sanitize-vr4320
3524 // start-sanitize-vr5400
3525 *vr5400:
3526 // end-sanitize-vr5400
3527 // start-sanitize-r5900
3528 *r5900:
3529 // end-sanitize-r5900
3530 // start-sanitize-tx19
3531 *tx19:
3532 // end-sanitize-tx19
3533 {
3534   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3535     SignalException(Trap, instruction_0);
3536 }
3537
3538
3539 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3540 "tgei r<RS>, <IMMEDIATE>"
3541 *mipsII:
3542 *mipsIII:
3543 *mipsIV:
3544 *vr5000:
3545 // start-sanitize-vr4320
3546 *vr4320:
3547 // end-sanitize-vr4320
3548 // start-sanitize-vr5400
3549 *vr5400:
3550 // end-sanitize-vr5400
3551 // start-sanitize-r5900
3552 *r5900:
3553 // end-sanitize-r5900
3554 // start-sanitize-tx19
3555 *tx19:
3556 // end-sanitize-tx19
3557 {
3558   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3559     SignalException(Trap, instruction_0);
3560 }
3561
3562
3563 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3564 "tgeiu r<RS>, <IMMEDIATE>"
3565 *mipsII:
3566 *mipsIII:
3567 *mipsIV:
3568 *vr5000:
3569 // start-sanitize-vr4320
3570 *vr4320:
3571 // end-sanitize-vr4320
3572 // start-sanitize-vr5400
3573 *vr5400:
3574 // end-sanitize-vr5400
3575 // start-sanitize-r5900
3576 *r5900:
3577 // end-sanitize-r5900
3578 // start-sanitize-tx19
3579 *tx19:
3580 // end-sanitize-tx19
3581 {
3582   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3583     SignalException(Trap, instruction_0);
3584 }
3585
3586
3587 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3588 "tgeu r<RS>, r<RT>"
3589 *mipsII:
3590 *mipsIII:
3591 *mipsIV:
3592 *vr5000:
3593 // start-sanitize-vr4320
3594 *vr4320:
3595 // end-sanitize-vr4320
3596 // start-sanitize-vr5400
3597 *vr5400:
3598 // end-sanitize-vr5400
3599 // start-sanitize-r5900
3600 *r5900:
3601 // end-sanitize-r5900
3602 // start-sanitize-tx19
3603 *tx19:
3604 // end-sanitize-tx19
3605 {
3606   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3607     SignalException(Trap, instruction_0);
3608 }
3609
3610
3611 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3612 "tlt r<RS>, r<RT>"
3613 *mipsII:
3614 *mipsIII:
3615 *mipsIV:
3616 *vr5000:
3617 // start-sanitize-vr4320
3618 *vr4320:
3619 // end-sanitize-vr4320
3620 // start-sanitize-vr5400
3621 *vr5400:
3622 // end-sanitize-vr5400
3623 // start-sanitize-r5900
3624 *r5900:
3625 // end-sanitize-r5900
3626 // start-sanitize-tx19
3627 *tx19:
3628 // end-sanitize-tx19
3629 {
3630   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3631     SignalException(Trap, instruction_0);
3632 }
3633
3634
3635 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3636 "tlti r<RS>, <IMMEDIATE>"
3637 *mipsII:
3638 *mipsIII:
3639 *mipsIV:
3640 *vr5000:
3641 // start-sanitize-vr4320
3642 *vr4320:
3643 // end-sanitize-vr4320
3644 // start-sanitize-vr5400
3645 *vr5400:
3646 // end-sanitize-vr5400
3647 // start-sanitize-r5900
3648 *r5900:
3649 // end-sanitize-r5900
3650 // start-sanitize-tx19
3651 *tx19:
3652 // end-sanitize-tx19
3653 {
3654   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3655     SignalException(Trap, instruction_0);
3656 }
3657
3658
3659 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3660 "tltiu r<RS>, <IMMEDIATE>"
3661 *mipsII:
3662 *mipsIII:
3663 *mipsIV:
3664 *vr5000:
3665 // start-sanitize-vr4320
3666 *vr4320:
3667 // end-sanitize-vr4320
3668 // start-sanitize-vr5400
3669 *vr5400:
3670 // end-sanitize-vr5400
3671 // start-sanitize-r5900
3672 *r5900:
3673 // end-sanitize-r5900
3674 // start-sanitize-tx19
3675 *tx19:
3676 // end-sanitize-tx19
3677 {
3678   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3679     SignalException(Trap, instruction_0);
3680 }
3681
3682
3683 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3684 "tltu r<RS>, r<RT>"
3685 *mipsII:
3686 *mipsIII:
3687 *mipsIV:
3688 *vr5000:
3689 // start-sanitize-vr4320
3690 *vr4320:
3691 // end-sanitize-vr4320
3692 // start-sanitize-vr5400
3693 *vr5400:
3694 // end-sanitize-vr5400
3695 // start-sanitize-r5900
3696 *r5900:
3697 // end-sanitize-r5900
3698 // start-sanitize-tx19
3699 *tx19:
3700 // end-sanitize-tx19
3701 {
3702   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3703     SignalException(Trap, instruction_0);
3704 }
3705
3706
3707 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3708 "tne r<RS>, r<RT>"
3709 *mipsII:
3710 *mipsIII:
3711 *mipsIV:
3712 *vr5000:
3713 // start-sanitize-vr4320
3714 *vr4320:
3715 // end-sanitize-vr4320
3716 // start-sanitize-vr5400
3717 *vr5400:
3718 // end-sanitize-vr5400
3719 // start-sanitize-r5900
3720 *r5900:
3721 // end-sanitize-r5900
3722 // start-sanitize-tx19
3723 *tx19:
3724 // end-sanitize-tx19
3725 {
3726   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3727     SignalException(Trap, instruction_0);
3728 }
3729
3730
3731 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3732 "tne r<RS>, <IMMEDIATE>"
3733 *mipsII:
3734 *mipsIII:
3735 *mipsIV:
3736 *vr5000:
3737 // start-sanitize-vr4320
3738 *vr4320:
3739 // end-sanitize-vr4320
3740 // start-sanitize-vr5400
3741 *vr5400:
3742 // end-sanitize-vr5400
3743 // start-sanitize-r5900
3744 *r5900:
3745 // end-sanitize-r5900
3746 // start-sanitize-tx19
3747 *tx19:
3748 // end-sanitize-tx19
3749 {
3750   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3751     SignalException(Trap, instruction_0);
3752 }
3753
3754
3755 :function:::void:do_xor:int rs, int rt, int rd
3756 {
3757   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3758   GPR[rd] = GPR[rs] ^ GPR[rt];
3759   TRACE_ALU_RESULT (GPR[rd]);
3760 }
3761
3762 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3763 "xor r<RD>, r<RS>, r<RT>"
3764 *mipsI,mipsII,mipsIII,mipsIV:
3765 *vr5000:
3766 // start-sanitize-vr4320
3767 *vr4320:
3768 // end-sanitize-vr4320
3769 // start-sanitize-vr5400
3770 *vr5400:
3771 // end-sanitize-vr5400
3772 // start-sanitize-r5900
3773 *r5900:
3774 // end-sanitize-r5900
3775 *r3900:
3776 // start-sanitize-tx19
3777 *tx19:
3778 // end-sanitize-tx19
3779 {
3780   do_xor (SD_, RS, RT, RD);
3781 }
3782
3783
3784 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3785 {
3786   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3787   GPR[rt] = GPR[rs] ^ immediate;
3788   TRACE_ALU_RESULT (GPR[rt]);
3789 }
3790
3791 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3792 "xori r<RT>, r<RS>, <IMMEDIATE>"
3793 *mipsI,mipsII,mipsIII,mipsIV:
3794 *vr5000:
3795 // start-sanitize-vr4320
3796 *vr4320:
3797 // end-sanitize-vr4320
3798 // start-sanitize-vr5400
3799 *vr5400:
3800 // end-sanitize-vr5400
3801 // start-sanitize-r5900
3802 *r5900:
3803 // end-sanitize-r5900
3804 *r3900:
3805 // start-sanitize-tx19
3806 *tx19:
3807 // end-sanitize-tx19
3808 {
3809   do_xori (SD_, RS, RT, IMMEDIATE);
3810 }
3811
3812 \f
3813 //
3814 // MIPS Architecture:
3815 //
3816 //        FPU Instruction Set (COP1 & COP1X)
3817 //
3818
3819
3820 :%s::::FMT:int fmt
3821 {
3822   switch (fmt)
3823     {
3824     case fmt_single: return "s";
3825     case fmt_double: return "d";
3826     case fmt_word: return "w";
3827     case fmt_long: return "l";
3828     default: return "?";
3829     }
3830 }
3831
3832 :%s::::X:int x
3833 {
3834   switch (x)
3835     {
3836     case 0: return "f";
3837     case 1: return "t";
3838     default: return "?";
3839     }
3840 }
3841
3842 :%s::::TF:int tf
3843 {
3844   if (tf)
3845     return "t";
3846   else
3847     return "f";
3848 }
3849
3850 :%s::::ND:int nd
3851 {
3852   if (nd)
3853     return "l";
3854   else
3855     return "";
3856 }
3857
3858 :%s::::COND:int cond
3859 {
3860   switch (cond)
3861     {
3862     case 00: return "f";
3863     case 01: return "un";
3864     case 02: return "eq";
3865     case 03: return "ueq";
3866     case 04: return "olt";
3867     case 05: return "ult";
3868     case 06: return "ole";
3869     case 07: return "ule";
3870     case 010: return "sf";
3871     case 011: return "ngle";
3872     case 012: return "seq";
3873     case 013: return "ngl";
3874     case 014: return "lt";
3875     case 015: return "nge";
3876     case 016: return "le";
3877     case 017: return "ngt";
3878     default: return "?";
3879     }
3880 }
3881
3882
3883 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3884 "abs.%s<FMT> f<FD>, f<FS>"
3885 *mipsI,mipsII,mipsIII,mipsIV:
3886 *vr5000:
3887 // start-sanitize-vr4320
3888 *vr4320:
3889 // end-sanitize-vr4320
3890 // start-sanitize-vr5400
3891 *vr5400:
3892 // end-sanitize-vr5400
3893 *r3900:
3894 // start-sanitize-tx19
3895 *tx19:
3896 // end-sanitize-tx19
3897 {
3898   unsigned32 instruction = instruction_0;
3899   int destreg = ((instruction >> 6) & 0x0000001F);
3900   int fs = ((instruction >> 11) & 0x0000001F);
3901   int format = ((instruction >> 21) & 0x00000007);
3902   {
3903     if ((format != fmt_single) && (format != fmt_double))
3904       SignalException(ReservedInstruction,instruction);
3905     else
3906       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3907   }
3908 }
3909
3910
3911
3912 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3913 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3914 *mipsI,mipsII,mipsIII,mipsIV:
3915 *vr5000:
3916 // start-sanitize-vr4320
3917 *vr4320:
3918 // end-sanitize-vr4320
3919 // start-sanitize-vr5400
3920 *vr5400:
3921 // end-sanitize-vr5400
3922 *r3900:
3923 // start-sanitize-tx19
3924 *tx19:
3925 // end-sanitize-tx19
3926 {
3927   unsigned32 instruction = instruction_0;
3928   int destreg = ((instruction >> 6) & 0x0000001F);
3929   int fs = ((instruction >> 11) & 0x0000001F);
3930   int ft = ((instruction >> 16) & 0x0000001F);
3931   int format = ((instruction >> 21) & 0x00000007);
3932   {
3933     if ((format != fmt_single) && (format != fmt_double))
3934       SignalException(ReservedInstruction, instruction);
3935     else
3936       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3937   }
3938 }
3939
3940
3941
3942 // BC1F
3943 // BC1FL
3944 // BC1T
3945 // BC1TL
3946
3947 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3948 "bc1%s<TF>%s<ND> <OFFSET>"
3949 *mipsI,mipsII,mipsIII:
3950 // start-sanitize-r5900
3951 *r5900:
3952 // end-sanitize-r5900
3953 {
3954   TRACE_BRANCH_INPUT (PREVCOC1());
3955   if (PREVCOC1() == TF)
3956     {
3957       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3958       TRACE_BRANCH_RESULT (dest);
3959       DELAY_SLOT (dest);
3960     }
3961   else if (ND)
3962     {
3963       TRACE_BRANCH_RESULT (0);
3964       NULLIFY_NEXT_INSTRUCTION ();
3965     }
3966   else
3967     {
3968       TRACE_BRANCH_RESULT (NIA);
3969     }
3970 }
3971
3972 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3973 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3974 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3975 *mipsIV:
3976 *vr5000:
3977 // start-sanitize-vr4320
3978 *vr4320:
3979 // end-sanitize-vr4320
3980 // start-sanitize-vr5400
3981 *vr5400:
3982 // end-sanitize-vr5400
3983 *r3900:
3984 // start-sanitize-tx19
3985 *tx19:
3986 // end-sanitize-tx19
3987 {
3988   if (GETFCC(CC) == TF)
3989     {
3990       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3991     }
3992   else if (ND)
3993     {
3994       NULLIFY_NEXT_INSTRUCTION ();
3995     }
3996 }
3997
3998
3999
4000 // C.EQ.S
4001 // C.EQ.D
4002 // ...
4003
4004 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4005 {
4006   if ((fmt != fmt_single) && (fmt != fmt_double))
4007     SignalException (ReservedInstruction, insn);
4008   else
4009     {
4010       int less;
4011       int equal;
4012       int unordered;
4013       int condition;
4014       unsigned64 ofs = ValueFPR (fs, fmt);
4015       unsigned64 oft = ValueFPR (ft, fmt);
4016       if (NaN (ofs, fmt) || NaN (oft, fmt))
4017         {
4018           if (FCSR & FP_ENABLE (IO))
4019             {
4020               FCSR |= FP_CAUSE (IO);
4021               SignalExceptionFPE ();
4022             }
4023           less = 0;
4024           equal = 0;
4025           unordered = 1;
4026         }
4027       else
4028         {
4029           less = Less (ofs, oft, fmt);
4030           equal = Equal (ofs, oft, fmt);
4031           unordered = 0;
4032         }
4033       condition = (((cond & (1 << 2)) && less)
4034                    || ((cond & (1 << 1)) && equal)
4035                    || ((cond & (1 << 0)) && unordered));
4036       SETFCC (cc, condition);
4037     }
4038 }
4039
4040 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4041 *mipsI,mipsII,mipsIII:
4042 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4043 {
4044   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4045 }
4046
4047 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4048 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4049 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4050 *mipsIV:
4051 *vr5000:
4052 // start-sanitize-vr4320
4053 *vr4320:
4054 // end-sanitize-vr4320
4055 // start-sanitize-vr5400
4056 *vr5400:
4057 // end-sanitize-vr5400
4058 *r3900:
4059 // start-sanitize-tx19
4060 *tx19:
4061 // end-sanitize-tx19
4062 {
4063   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4064 }
4065
4066
4067 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4068 "ceil.l.%s<FMT> f<FD>, f<FS>"
4069 *mipsIII:
4070 *mipsIV:
4071 *vr5000:
4072 // start-sanitize-vr4320
4073 *vr4320:
4074 // end-sanitize-vr4320
4075 // start-sanitize-vr5400
4076 *vr5400:
4077 // end-sanitize-vr5400
4078 // start-sanitize-r5900
4079 *r5900:
4080 // end-sanitize-r5900
4081 *r3900:
4082 // start-sanitize-tx19
4083 *tx19:
4084 // end-sanitize-tx19
4085 {
4086   unsigned32 instruction = instruction_0;
4087   int destreg = ((instruction >> 6) & 0x0000001F);
4088   int fs = ((instruction >> 11) & 0x0000001F);
4089   int format = ((instruction >> 21) & 0x00000007);
4090   {
4091     if ((format != fmt_single) && (format != fmt_double))
4092       SignalException(ReservedInstruction,instruction);
4093     else
4094       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4095   }
4096 }
4097
4098
4099 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4100 *mipsII:
4101 *mipsIII:
4102 *mipsIV:
4103 *vr5000:
4104 // start-sanitize-vr4320
4105 *vr4320:
4106 // end-sanitize-vr4320
4107 // start-sanitize-vr5400
4108 *vr5400:
4109 // end-sanitize-vr5400
4110 // start-sanitize-r5900
4111 *r5900:
4112 // end-sanitize-r5900
4113 *r3900:
4114 // start-sanitize-tx19
4115 *tx19:
4116 // end-sanitize-tx19
4117 {
4118   unsigned32 instruction = instruction_0;
4119   int destreg = ((instruction >> 6) & 0x0000001F);
4120   int fs = ((instruction >> 11) & 0x0000001F);
4121   int format = ((instruction >> 21) & 0x00000007);
4122   {
4123   if ((format != fmt_single) && (format != fmt_double))
4124    SignalException(ReservedInstruction,instruction);
4125   else
4126    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4127   }
4128 }
4129
4130
4131 // CFC1
4132 // CTC1
4133 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4134 "c%s<X>c1 r<RT>, f<FS>"
4135 *mipsI:
4136 *mipsII:
4137 *mipsIII:
4138 {
4139   if (X)
4140     {
4141       if (FS == 0)
4142         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4143       else if (FS == 31)
4144         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4145       /* else NOP */
4146       PENDING_FILL(COCIDX,0); /* special case */
4147     }
4148   else
4149     { /* control from */
4150       if (FS == 0)
4151         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4152       else if (FS == 31)
4153         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4154       /* else NOP */
4155     }
4156 }
4157 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4158 "c%s<X>c1 r<RT>, f<FS>"
4159 *mipsIV:
4160 *vr5000:
4161 // start-sanitize-vr4320
4162 *vr4320:
4163 // end-sanitize-vr4320
4164 // start-sanitize-vr5400
4165 *vr5400:
4166 // end-sanitize-vr5400
4167 *r3900:
4168 // start-sanitize-tx19
4169 *tx19:
4170 // end-sanitize-tx19
4171 {
4172   if (X)
4173     {
4174       /* control to */
4175       TRACE_ALU_INPUT1 (GPR[RT]);
4176       if (FS == 0)
4177         {
4178           FCR0 = VL4_8(GPR[RT]);
4179           TRACE_ALU_RESULT (FCR0);
4180         }
4181       else if (FS == 31)
4182         {
4183           FCR31 = VL4_8(GPR[RT]);
4184           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4185           TRACE_ALU_RESULT (FCR31);
4186         }
4187       else
4188         {
4189           TRACE_ALU_RESULT0 ();
4190         }
4191       /* else NOP */
4192     }
4193   else
4194     { /* control from */
4195       if (FS == 0)
4196         {
4197           TRACE_ALU_INPUT1 (FCR0);
4198           GPR[RT] = SIGNEXTEND (FCR0, 32);
4199         }
4200       else if (FS == 31)
4201         {
4202           TRACE_ALU_INPUT1 (FCR31);
4203           GPR[RT] = SIGNEXTEND (FCR31, 32);
4204         }
4205       TRACE_ALU_RESULT (GPR[RT]);
4206       /* else NOP */
4207     }
4208 }
4209
4210
4211 //
4212 // FIXME: Does not correctly differentiate between mips*
4213 //
4214 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4215 "cvt.d.%s<FMT> f<FD>, f<FS>"
4216 *mipsI,mipsII,mipsIII,mipsIV:
4217 *vr5000:
4218 // start-sanitize-vr4320
4219 *vr4320:
4220 // end-sanitize-vr4320
4221 // start-sanitize-vr5400
4222 *vr5400:
4223 // end-sanitize-vr5400
4224 *r3900:
4225 // start-sanitize-tx19
4226 *tx19:
4227 // end-sanitize-tx19
4228 {
4229   unsigned32 instruction = instruction_0;
4230   int destreg = ((instruction >> 6) & 0x0000001F);
4231   int fs = ((instruction >> 11) & 0x0000001F);
4232   int format = ((instruction >> 21) & 0x00000007);
4233   {
4234     if ((format == fmt_double) | 0)
4235       SignalException(ReservedInstruction,instruction);
4236     else
4237       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4238   }
4239 }
4240
4241
4242 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4243 "cvt.l.%s<FMT> f<FD>, f<FS>"
4244 *mipsIII:
4245 *mipsIV:
4246 *vr5000:
4247 // start-sanitize-vr4320
4248 *vr4320:
4249 // end-sanitize-vr4320
4250 // start-sanitize-vr5400
4251 *vr5400:
4252 // end-sanitize-vr5400
4253 *r3900:
4254 // start-sanitize-tx19
4255 *tx19:
4256 // end-sanitize-tx19
4257 {
4258   unsigned32 instruction = instruction_0;
4259   int destreg = ((instruction >> 6) & 0x0000001F);
4260   int fs = ((instruction >> 11) & 0x0000001F);
4261   int format = ((instruction >> 21) & 0x00000007);
4262   {
4263     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4264       SignalException(ReservedInstruction,instruction);
4265     else
4266       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4267   }
4268 }
4269
4270
4271 //
4272 // FIXME: Does not correctly differentiate between mips*
4273 //
4274 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4275 "cvt.s.%s<FMT> f<FD>, f<FS>"
4276 *mipsI,mipsII,mipsIII,mipsIV:
4277 *vr5000:
4278 // start-sanitize-vr4320
4279 *vr4320:
4280 // end-sanitize-vr4320
4281 // start-sanitize-vr5400
4282 *vr5400:
4283 // end-sanitize-vr5400
4284 *r3900:
4285 // start-sanitize-tx19
4286 *tx19:
4287 // end-sanitize-tx19
4288 {
4289   unsigned32 instruction = instruction_0;
4290   int destreg = ((instruction >> 6) & 0x0000001F);
4291   int fs = ((instruction >> 11) & 0x0000001F);
4292   int format = ((instruction >> 21) & 0x00000007);
4293   {
4294     if ((format == fmt_single) | 0)
4295       SignalException(ReservedInstruction,instruction);
4296     else
4297       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4298   }
4299 }
4300
4301
4302 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4303 "cvt.w.%s<FMT> f<FD>, f<FS>"
4304 *mipsI,mipsII,mipsIII,mipsIV:
4305 *vr5000:
4306 // start-sanitize-vr4320
4307 *vr4320:
4308 // end-sanitize-vr4320
4309 // start-sanitize-vr5400
4310 *vr5400:
4311 // end-sanitize-vr5400
4312 *r3900:
4313 // start-sanitize-tx19
4314 *tx19:
4315 // end-sanitize-tx19
4316 {
4317   unsigned32 instruction = instruction_0;
4318   int destreg = ((instruction >> 6) & 0x0000001F);
4319   int fs = ((instruction >> 11) & 0x0000001F);
4320   int format = ((instruction >> 21) & 0x00000007);
4321   {
4322     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4323       SignalException(ReservedInstruction,instruction);
4324     else
4325       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4326   }
4327 }
4328
4329
4330 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4331 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4332 *mipsI,mipsII,mipsIII,mipsIV:
4333 *vr5000:
4334 // start-sanitize-vr4320
4335 *vr4320:
4336 // end-sanitize-vr4320
4337 // start-sanitize-vr5400
4338 *vr5400:
4339 // end-sanitize-vr5400
4340 *r3900:
4341 // start-sanitize-tx19
4342 *tx19:
4343 // end-sanitize-tx19
4344 {
4345   unsigned32 instruction = instruction_0;
4346   int destreg = ((instruction >> 6) & 0x0000001F);
4347   int fs = ((instruction >> 11) & 0x0000001F);
4348   int ft = ((instruction >> 16) & 0x0000001F);
4349   int format = ((instruction >> 21) & 0x00000007);
4350   {
4351     if ((format != fmt_single) && (format != fmt_double))
4352       SignalException(ReservedInstruction,instruction);
4353     else
4354       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4355   }
4356 }
4357
4358
4359 // DMFC1
4360 // DMTC1
4361 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4362 "dm%s<X>c1 r<RT>, f<FS>"
4363 *mipsIII:
4364 {
4365   if (X)
4366     {
4367       if (SizeFGR() == 64)
4368         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4369       else if ((FS & 0x1) == 0)
4370         {
4371           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4372           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4373         }
4374     }
4375   else
4376     {
4377       if (SizeFGR() == 64)
4378         PENDING_FILL(RT,FGR[FS]);
4379       else if ((FS & 0x1) == 0)
4380         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4381       else
4382         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4383     }
4384 }
4385 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4386 "dm%s<X>c1 r<RT>, f<FS>"
4387 *mipsIV:
4388 *vr5000:
4389 // start-sanitize-vr4320
4390 *vr4320:
4391 // end-sanitize-vr4320
4392 // start-sanitize-vr5400
4393 *vr5400:
4394 // end-sanitize-vr5400
4395 // start-sanitize-r5900
4396 *r5900:
4397 // end-sanitize-r5900
4398 *r3900:
4399 // start-sanitize-tx19
4400 *tx19:
4401 // end-sanitize-tx19
4402 {
4403   if (X)
4404     {
4405       if (SizeFGR() == 64)
4406         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4407       else if ((FS & 0x1) == 0)
4408         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4409     }
4410   else
4411     {
4412       if (SizeFGR() == 64)
4413         GPR[RT] = FGR[FS];
4414       else if ((FS & 0x1) == 0)
4415         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4416       else
4417         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4418     }
4419 }
4420
4421
4422 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4423 "floor.l.%s<FMT> f<FD>, f<FS>"
4424 *mipsIII:
4425 *mipsIV:
4426 *vr5000:
4427 // start-sanitize-vr4320
4428 *vr4320:
4429 // end-sanitize-vr4320
4430 // start-sanitize-vr5400
4431 *vr5400:
4432 // end-sanitize-vr5400
4433 // start-sanitize-r5900
4434 *r5900:
4435 // end-sanitize-r5900
4436 *r3900:
4437 // start-sanitize-tx19
4438 *tx19:
4439 // end-sanitize-tx19
4440 {
4441   unsigned32 instruction = instruction_0;
4442   int destreg = ((instruction >> 6) & 0x0000001F);
4443   int fs = ((instruction >> 11) & 0x0000001F);
4444   int format = ((instruction >> 21) & 0x00000007);
4445   {
4446     if ((format != fmt_single) && (format != fmt_double))
4447       SignalException(ReservedInstruction,instruction);
4448     else
4449       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4450   }
4451 }
4452
4453
4454 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4455 "floor.w.%s<FMT> f<FD>, f<FS>"
4456 *mipsII:
4457 *mipsIII:
4458 *mipsIV:
4459 *vr5000:
4460 // start-sanitize-vr4320
4461 *vr4320:
4462 // end-sanitize-vr4320
4463 // start-sanitize-vr5400
4464 *vr5400:
4465 // end-sanitize-vr5400
4466 // start-sanitize-r5900
4467 *r5900:
4468 // end-sanitize-r5900
4469 *r3900:
4470 // start-sanitize-tx19
4471 *tx19:
4472 // end-sanitize-tx19
4473 {
4474   unsigned32 instruction = instruction_0;
4475   int destreg = ((instruction >> 6) & 0x0000001F);
4476   int fs = ((instruction >> 11) & 0x0000001F);
4477   int format = ((instruction >> 21) & 0x00000007);
4478   {
4479     if ((format != fmt_single) && (format != fmt_double))
4480       SignalException(ReservedInstruction,instruction);
4481     else
4482       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4483   }
4484 }
4485
4486
4487 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4488 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4489 *mipsII:
4490 *mipsIII:
4491 *mipsIV:
4492 *vr5000:
4493 // start-sanitize-vr4320
4494 *vr4320:
4495 // end-sanitize-vr4320
4496 // start-sanitize-vr5400
4497 *vr5400:
4498 // end-sanitize-vr5400
4499 *r3900:
4500 // start-sanitize-tx19
4501 *tx19:
4502 // end-sanitize-tx19
4503 {
4504   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4505 }
4506
4507
4508 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4509 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4510 *mipsIV:
4511 *vr5000:
4512 // start-sanitize-vr4320
4513 *vr4320:
4514 // end-sanitize-vr4320
4515 // start-sanitize-vr5400
4516 *vr5400:
4517 // end-sanitize-vr5400
4518 {
4519   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4520 }
4521
4522
4523
4524 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4525 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4526 *mipsI,mipsII,mipsIII,mipsIV:
4527 *vr5000:
4528 // start-sanitize-vr4320
4529 *vr4320:
4530 // end-sanitize-vr4320
4531 // start-sanitize-vr5400
4532 *vr5400:
4533 // end-sanitize-vr5400
4534 // start-sanitize-r5900
4535 *r5900:
4536 // end-sanitize-r5900
4537 *r3900:
4538 // start-sanitize-tx19
4539 *tx19:
4540 // end-sanitize-tx19
4541 {
4542   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4543 }
4544
4545
4546 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4547 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4548 *mipsIV:
4549 *vr5000:
4550 // start-sanitize-vr4320
4551 *vr4320:
4552 // end-sanitize-vr4320
4553 // start-sanitize-vr5400
4554 *vr5400:
4555 // end-sanitize-vr5400
4556 {
4557   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4558 }
4559
4560
4561
4562 //
4563 // FIXME: Not correct for mips*
4564 //
4565 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4566 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4567 *mipsIV:
4568 *vr5000:
4569 // start-sanitize-vr4320
4570 *vr4320:
4571 // end-sanitize-vr4320
4572 // start-sanitize-vr5400
4573 *vr5400:
4574 // end-sanitize-vr5400
4575 {
4576   unsigned32 instruction = instruction_0;
4577   int destreg = ((instruction >> 6) & 0x0000001F);
4578   int fs = ((instruction >> 11) & 0x0000001F);
4579   int ft = ((instruction >> 16) & 0x0000001F);
4580   int fr = ((instruction >> 21) & 0x0000001F);
4581   {
4582     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4583   }
4584 }
4585
4586
4587 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4588 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4589 *mipsIV:
4590 *vr5000:
4591 // start-sanitize-vr4320
4592 *vr4320:
4593 // end-sanitize-vr4320
4594 // start-sanitize-vr5400
4595 *vr5400:
4596 // end-sanitize-vr5400
4597 {
4598   unsigned32 instruction = instruction_0;
4599   int destreg = ((instruction >> 6) & 0x0000001F);
4600   int fs = ((instruction >> 11) & 0x0000001F);
4601   int ft = ((instruction >> 16) & 0x0000001F);
4602   int fr = ((instruction >> 21) & 0x0000001F);
4603   {
4604     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4605   }
4606 }
4607
4608
4609 // MFC1
4610 // MTC1
4611 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4612 "m%s<X>c1 r<RT>, f<FS>"
4613 *mipsI:
4614 *mipsII:
4615 *mipsIII:
4616 {
4617   if (X)
4618     { /*MTC1*/
4619       if (SizeFGR() == 64)
4620         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4621       else
4622         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4623     }
4624   else /*MFC1*/
4625     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4626 }
4627 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4628 "m%s<X>c1 r<RT>, f<FS>"
4629 *mipsIV:
4630 *vr5000:
4631 // start-sanitize-vr4320
4632 *vr4320:
4633 // end-sanitize-vr4320
4634 // start-sanitize-vr5400
4635 *vr5400:
4636 // end-sanitize-vr5400
4637 *r3900:
4638 // start-sanitize-tx19
4639 *tx19:
4640 // end-sanitize-tx19
4641 {
4642   if (X)
4643     /*MTC1*/
4644     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4645   else /*MFC1*/
4646     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4647 }
4648
4649
4650 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4651 "mov.%s<FMT> f<FD>, f<FS>"
4652 *mipsI,mipsII,mipsIII,mipsIV:
4653 *vr5000:
4654 // start-sanitize-vr4320
4655 *vr4320:
4656 // end-sanitize-vr4320
4657 // start-sanitize-vr5400
4658 *vr5400:
4659 // end-sanitize-vr5400
4660 *r3900:
4661 // start-sanitize-tx19
4662 *tx19:
4663 // end-sanitize-tx19
4664 {
4665   unsigned32 instruction = instruction_0;
4666   int destreg = ((instruction >> 6) & 0x0000001F);
4667   int fs = ((instruction >> 11) & 0x0000001F);
4668   int format = ((instruction >> 21) & 0x00000007);
4669   {
4670     StoreFPR(destreg,format,ValueFPR(fs,format));
4671   }
4672 }
4673
4674
4675 // MOVF
4676 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4677 "mov%s<TF> r<RD>, r<RS>, <CC>"
4678 *mipsIV:
4679 *vr5000:
4680 // start-sanitize-vr4320
4681 *vr4320:
4682 // end-sanitize-vr4320
4683 // start-sanitize-vr5400
4684 *vr5400:
4685 // end-sanitize-vr5400
4686 // start-sanitize-r5900
4687 *r5900:
4688 // end-sanitize-r5900
4689 {
4690   if (GETFCC(CC) == TF)
4691     GPR[RD] = GPR[RS];
4692 }
4693
4694
4695 // MOVF.fmt
4696 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4697 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4698 *mipsIV:
4699 *vr5000:
4700 // start-sanitize-vr4320
4701 *vr4320:
4702 // end-sanitize-vr4320
4703 // start-sanitize-vr5400
4704 *vr5400:
4705 // end-sanitize-vr5400
4706 // start-sanitize-r5900
4707 *r5900:
4708 // end-sanitize-r5900
4709 {
4710   unsigned32 instruction = instruction_0;
4711   int format = ((instruction >> 21) & 0x00000007);
4712   {
4713    if (GETFCC(CC) == TF)
4714      StoreFPR (FD, format, ValueFPR (FS, format));
4715    else
4716      StoreFPR (FD, format, ValueFPR (FD, format));
4717   }
4718 }
4719
4720
4721 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4722 *mipsIV:
4723 *vr5000:
4724 // start-sanitize-vr4320
4725 *vr4320:
4726 // end-sanitize-vr4320
4727 // start-sanitize-vr5400
4728 *vr5400:
4729 // end-sanitize-vr5400
4730 // start-sanitize-r5900
4731 *r5900:
4732 // end-sanitize-r5900
4733 {
4734   unsigned32 instruction = instruction_0;
4735   int destreg = ((instruction >> 6) & 0x0000001F);
4736   int fs = ((instruction >> 11) & 0x0000001F);
4737   int format = ((instruction >> 21) & 0x00000007);
4738   {
4739     StoreFPR(destreg,format,ValueFPR(fs,format));
4740   }
4741 }
4742
4743
4744 // MOVT see MOVtf
4745
4746
4747 // MOVT.fmt see MOVtf.fmt
4748
4749
4750
4751 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4752 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4753 *mipsIV:
4754 *vr5000:
4755 // start-sanitize-vr4320
4756 *vr4320:
4757 // end-sanitize-vr4320
4758 // start-sanitize-vr5400
4759 *vr5400:
4760 // end-sanitize-vr5400
4761 // start-sanitize-r5900
4762 *r5900:
4763 // end-sanitize-r5900
4764 {
4765   unsigned32 instruction = instruction_0;
4766   int destreg = ((instruction >> 6) & 0x0000001F);
4767   int fs = ((instruction >> 11) & 0x0000001F);
4768   int format = ((instruction >> 21) & 0x00000007);
4769   {
4770    StoreFPR(destreg,format,ValueFPR(fs,format));
4771   }
4772 }
4773
4774
4775 // MSUB.fmt
4776 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4777 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4778 *mipsIV:
4779 *vr5000:
4780 // start-sanitize-vr4320
4781 *vr4320:
4782 // end-sanitize-vr4320
4783 // start-sanitize-vr5400
4784 *vr5400:
4785 // end-sanitize-vr5400
4786 // start-sanitize-r5900
4787 *r5900:
4788 // end-sanitize-r5900
4789 {
4790   unsigned32 instruction = instruction_0;
4791   int destreg = ((instruction >> 6) & 0x0000001F);
4792   int fs = ((instruction >> 11) & 0x0000001F);
4793   int ft = ((instruction >> 16) & 0x0000001F);
4794   int fr = ((instruction >> 21) & 0x0000001F);
4795   {
4796     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4797   }
4798 }
4799
4800
4801 // MSUB.fmt
4802 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4803 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4804 *mipsIV:
4805 *vr5000:
4806 // start-sanitize-vr4320
4807 *vr4320:
4808 // end-sanitize-vr4320
4809 // start-sanitize-vr5400
4810 *vr5400:
4811 // end-sanitize-vr5400
4812 // start-sanitize-r5900
4813 *r5900:
4814 // end-sanitize-r5900
4815 {
4816   unsigned32 instruction = instruction_0;
4817   int destreg = ((instruction >> 6) & 0x0000001F);
4818   int fs = ((instruction >> 11) & 0x0000001F);
4819   int ft = ((instruction >> 16) & 0x0000001F);
4820   int fr = ((instruction >> 21) & 0x0000001F);
4821   {
4822    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4823   }
4824 }
4825
4826
4827 // MTC1 see MxC1
4828
4829
4830 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4831 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4832 *mipsI,mipsII,mipsIII,mipsIV:
4833 *vr5000:
4834 // start-sanitize-vr4320
4835 *vr4320:
4836 // end-sanitize-vr4320
4837 // start-sanitize-vr5400
4838 *vr5400:
4839 // end-sanitize-vr5400
4840 *r3900:
4841 // start-sanitize-tx19
4842 *tx19:
4843 // end-sanitize-tx19
4844 {
4845   unsigned32 instruction = instruction_0;
4846   int destreg = ((instruction >> 6) & 0x0000001F);
4847   int fs = ((instruction >> 11) & 0x0000001F);
4848   int ft = ((instruction >> 16) & 0x0000001F);
4849   int format = ((instruction >> 21) & 0x00000007);
4850   {
4851     if ((format != fmt_single) && (format != fmt_double))
4852       SignalException(ReservedInstruction,instruction);
4853     else
4854       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4855   }
4856 }
4857
4858
4859 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4860 "neg.%s<FMT> f<FD>, f<FS>"
4861 *mipsI,mipsII,mipsIII,mipsIV:
4862 *vr5000:
4863 // start-sanitize-vr4320
4864 *vr4320:
4865 // end-sanitize-vr4320
4866 // start-sanitize-vr5400
4867 *vr5400:
4868 // end-sanitize-vr5400
4869 *r3900:
4870 // start-sanitize-tx19
4871 *tx19:
4872 // end-sanitize-tx19
4873 {
4874   unsigned32 instruction = instruction_0;
4875   int destreg = ((instruction >> 6) & 0x0000001F);
4876   int fs = ((instruction >> 11) & 0x0000001F);
4877   int format = ((instruction >> 21) & 0x00000007);
4878   {
4879     if ((format != fmt_single) && (format != fmt_double))
4880       SignalException(ReservedInstruction,instruction);
4881     else
4882       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4883   }
4884 }
4885
4886
4887 // NMADD.fmt
4888 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4889 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4890 *mipsIV:
4891 *vr5000:
4892 // start-sanitize-vr4320
4893 *vr4320:
4894 // end-sanitize-vr4320
4895 // start-sanitize-vr5400
4896 *vr5400:
4897 // end-sanitize-vr5400
4898 {
4899   unsigned32 instruction = instruction_0;
4900   int destreg = ((instruction >> 6) & 0x0000001F);
4901   int fs = ((instruction >> 11) & 0x0000001F);
4902   int ft = ((instruction >> 16) & 0x0000001F);
4903   int fr = ((instruction >> 21) & 0x0000001F);
4904   {
4905    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4906   }
4907 }
4908
4909
4910 // NMADD.fmt
4911 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4912 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4913 *mipsIV:
4914 *vr5000:
4915 // start-sanitize-vr4320
4916 *vr4320:
4917 // end-sanitize-vr4320
4918 // start-sanitize-vr5400
4919 *vr5400:
4920 // end-sanitize-vr5400
4921 {
4922   unsigned32 instruction = instruction_0;
4923   int destreg = ((instruction >> 6) & 0x0000001F);
4924   int fs = ((instruction >> 11) & 0x0000001F);
4925   int ft = ((instruction >> 16) & 0x0000001F);
4926   int fr = ((instruction >> 21) & 0x0000001F);
4927   {
4928    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4929   }
4930 }
4931
4932
4933 // NMSUB.fmt
4934 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4935 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4936 *mipsIV:
4937 *vr5000:
4938 // start-sanitize-vr4320
4939 *vr4320:
4940 // end-sanitize-vr4320
4941 // start-sanitize-vr5400
4942 *vr5400:
4943 // end-sanitize-vr5400
4944 {
4945   unsigned32 instruction = instruction_0;
4946   int destreg = ((instruction >> 6) & 0x0000001F);
4947   int fs = ((instruction >> 11) & 0x0000001F);
4948   int ft = ((instruction >> 16) & 0x0000001F);
4949   int fr = ((instruction >> 21) & 0x0000001F);
4950   {
4951    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4952   }
4953 }
4954
4955
4956 // NMSUB.fmt
4957 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4958 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4959 *mipsIV:
4960 *vr5000:
4961 // start-sanitize-vr4320
4962 *vr4320:
4963 // end-sanitize-vr4320
4964 // start-sanitize-vr5400
4965 *vr5400:
4966 // end-sanitize-vr5400
4967 {
4968   unsigned32 instruction = instruction_0;
4969   int destreg = ((instruction >> 6) & 0x0000001F);
4970   int fs = ((instruction >> 11) & 0x0000001F);
4971   int ft = ((instruction >> 16) & 0x0000001F);
4972   int fr = ((instruction >> 21) & 0x0000001F);
4973   {
4974     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4975   }
4976 }
4977
4978
4979 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4980 "prefx <HINT>, r<INDEX>(r<BASE>)"
4981 *mipsIV:
4982 *vr5000:
4983 // start-sanitize-vr4320
4984 *vr4320:
4985 // end-sanitize-vr4320
4986 // start-sanitize-vr5400
4987 *vr5400:
4988 // end-sanitize-vr5400
4989 {
4990   unsigned32 instruction = instruction_0;
4991   int fs = ((instruction >> 11) & 0x0000001F);
4992   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4993   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4994   {
4995     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4996     address_word paddr;
4997     int uncached;
4998     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4999       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5000   }
5001 }
5002
5003 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5004 *mipsIV:
5005 "recip.%s<FMT> f<FD>, f<FS>"
5006 *vr5000:
5007 // start-sanitize-vr4320
5008 *vr4320:
5009 // end-sanitize-vr4320
5010 // start-sanitize-vr5400
5011 *vr5400:
5012 // end-sanitize-vr5400
5013 {
5014   unsigned32 instruction = instruction_0;
5015   int destreg = ((instruction >> 6) & 0x0000001F);
5016   int fs = ((instruction >> 11) & 0x0000001F);
5017   int format = ((instruction >> 21) & 0x00000007);
5018   {
5019   if ((format != fmt_single) && (format != fmt_double))
5020    SignalException(ReservedInstruction,instruction);
5021   else
5022    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5023   }
5024 }
5025
5026
5027 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5028 "round.l.%s<FMT> f<FD>, f<FS>"
5029 *mipsIII:
5030 *mipsIV:
5031 *vr5000:
5032 // start-sanitize-vr4320
5033 *vr4320:
5034 // end-sanitize-vr4320
5035 // start-sanitize-vr5400
5036 *vr5400:
5037 // end-sanitize-vr5400
5038 // start-sanitize-r5900
5039 *r5900:
5040 // end-sanitize-r5900
5041 *r3900:
5042 // start-sanitize-tx19
5043 *tx19:
5044 // end-sanitize-tx19
5045 {
5046   unsigned32 instruction = instruction_0;
5047   int destreg = ((instruction >> 6) & 0x0000001F);
5048   int fs = ((instruction >> 11) & 0x0000001F);
5049   int format = ((instruction >> 21) & 0x00000007);
5050   {
5051     if ((format != fmt_single) && (format != fmt_double))
5052       SignalException(ReservedInstruction,instruction);
5053     else
5054       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5055   }
5056 }
5057
5058
5059 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5060 "round.w.%s<FMT> f<FD>, f<FS>"
5061 *mipsII:
5062 *mipsIII:
5063 *mipsIV:
5064 *vr5000:
5065 // start-sanitize-vr4320
5066 *vr4320:
5067 // end-sanitize-vr4320
5068 // start-sanitize-vr5400
5069 *vr5400:
5070 // end-sanitize-vr5400
5071 // start-sanitize-r5900
5072 *r5900:
5073 // end-sanitize-r5900
5074 *r3900:
5075 // start-sanitize-tx19
5076 *tx19:
5077 // end-sanitize-tx19
5078 {
5079   unsigned32 instruction = instruction_0;
5080   int destreg = ((instruction >> 6) & 0x0000001F);
5081   int fs = ((instruction >> 11) & 0x0000001F);
5082   int format = ((instruction >> 21) & 0x00000007);
5083   {
5084   if ((format != fmt_single) && (format != fmt_double))
5085    SignalException(ReservedInstruction,instruction);
5086   else
5087    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5088   }
5089 }
5090
5091
5092 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5093 *mipsIV:
5094 "rsqrt.%s<FMT> f<FD>, f<FS>"
5095 *vr5000:
5096 // start-sanitize-vr4320
5097 *vr4320:
5098 // end-sanitize-vr4320
5099 // start-sanitize-vr5400
5100 *vr5400:
5101 // end-sanitize-vr5400
5102 {
5103   unsigned32 instruction = instruction_0;
5104   int destreg = ((instruction >> 6) & 0x0000001F);
5105   int fs = ((instruction >> 11) & 0x0000001F);
5106   int format = ((instruction >> 21) & 0x00000007);
5107   {
5108   if ((format != fmt_single) && (format != fmt_double))
5109    SignalException(ReservedInstruction,instruction);
5110   else
5111    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5112   }
5113 }
5114
5115
5116 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5117 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5118 *mipsII:
5119 *mipsIII:
5120 *mipsIV:
5121 *vr5000:
5122 // start-sanitize-vr4320
5123 *vr4320:
5124 // end-sanitize-vr4320
5125 // start-sanitize-vr5400
5126 *vr5400:
5127 // end-sanitize-vr5400
5128 *r3900:
5129 // start-sanitize-tx19
5130 *tx19:
5131 // end-sanitize-tx19
5132 {
5133   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5134 }
5135
5136
5137 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5138 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5139 *mipsIV:
5140 *vr5000:
5141 // start-sanitize-vr4320
5142 *vr4320:
5143 // end-sanitize-vr4320
5144 // start-sanitize-vr5400
5145 *vr5400:
5146 // end-sanitize-vr5400
5147 {
5148   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5149 }
5150
5151
5152 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5153 "sqrt.%s<FMT> f<FD>, f<FS>"
5154 *mipsII:
5155 *mipsIII:
5156 *mipsIV:
5157 *vr5000:
5158 // start-sanitize-vr4320
5159 *vr4320:
5160 // end-sanitize-vr4320
5161 // start-sanitize-vr5400
5162 *vr5400:
5163 // end-sanitize-vr5400
5164 *r3900:
5165 // start-sanitize-tx19
5166 *tx19:
5167 // end-sanitize-tx19
5168 {
5169   unsigned32 instruction = instruction_0;
5170   int destreg = ((instruction >> 6) & 0x0000001F);
5171   int fs = ((instruction >> 11) & 0x0000001F);
5172   int format = ((instruction >> 21) & 0x00000007);
5173   {
5174     if ((format != fmt_single) && (format != fmt_double))
5175       SignalException(ReservedInstruction,instruction);
5176     else
5177       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5178   }
5179 }
5180
5181
5182 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5183 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5184 *mipsI,mipsII,mipsIII,mipsIV:
5185 *vr5000:
5186 // start-sanitize-vr4320
5187 *vr4320:
5188 // end-sanitize-vr4320
5189 // start-sanitize-vr5400
5190 *vr5400:
5191 // end-sanitize-vr5400
5192 *r3900:
5193 // start-sanitize-tx19
5194 *tx19:
5195 // end-sanitize-tx19
5196 {
5197   unsigned32 instruction = instruction_0;
5198   int destreg = ((instruction >> 6) & 0x0000001F);
5199   int fs = ((instruction >> 11) & 0x0000001F);
5200   int ft = ((instruction >> 16) & 0x0000001F);
5201   int format = ((instruction >> 21) & 0x00000007);
5202   {
5203     if ((format != fmt_single) && (format != fmt_double))
5204       SignalException(ReservedInstruction,instruction);
5205     else
5206       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5207   }
5208 }
5209
5210
5211
5212 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5213 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5214 *mipsI,mipsII,mipsIII,mipsIV:
5215 *vr5000:
5216 // start-sanitize-vr4320
5217 *vr4320:
5218 // end-sanitize-vr4320
5219 // start-sanitize-vr5400
5220 *vr5400:
5221 // end-sanitize-vr5400
5222 // start-sanitize-r5900
5223 *r5900:
5224 // end-sanitize-r5900
5225 *r3900:
5226 // start-sanitize-tx19
5227 *tx19:
5228 // end-sanitize-tx19
5229 {
5230   unsigned32 instruction = instruction_0;
5231   signed_word offset = EXTEND16 (OFFSET);
5232   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5233   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5234   {
5235     address_word vaddr = ((uword64)op1 + offset);
5236     address_word paddr;
5237     int uncached;
5238     if ((vaddr & 3) != 0)
5239       SignalExceptionAddressStore();
5240     else
5241       {
5242         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5243           {
5244             uword64 memval = 0;
5245             uword64 memval1 = 0;
5246             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5247             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5248             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5249             unsigned int byte;
5250             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5251             byte = ((vaddr & mask) ^ bigendiancpu);
5252             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5253             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5254           }
5255       }
5256   }
5257 }
5258
5259
5260 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5261 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5262 *mipsIV:
5263 *vr5000:
5264 // start-sanitize-vr4320
5265 *vr4320:
5266 // end-sanitize-vr4320
5267 // start-sanitize-vr5400
5268 *vr5400:
5269 // end-sanitize-vr5400
5270 {
5271   unsigned32 instruction = instruction_0;
5272   int fs = ((instruction >> 11) & 0x0000001F);
5273   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5274   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5275   {
5276    address_word vaddr = ((unsigned64)op1 + op2);
5277    address_word paddr;
5278    int uncached;
5279    if ((vaddr & 3) != 0)
5280     SignalExceptionAddressStore();
5281    else
5282    {
5283     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5284     {
5285      unsigned64 memval = 0;
5286      unsigned64 memval1 = 0;
5287      unsigned64 mask = 0x7;
5288      unsigned int byte;
5289      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5290      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5291      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5292       {
5293        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5294       }
5295     }
5296    }
5297   }
5298 }
5299
5300
5301 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5302 "trunc.l.%s<FMT> f<FD>, f<FS>"
5303 *mipsIII:
5304 *mipsIV:
5305 *vr5000:
5306 // start-sanitize-vr4320
5307 *vr4320:
5308 // end-sanitize-vr4320
5309 // start-sanitize-vr5400
5310 *vr5400:
5311 // end-sanitize-vr5400
5312 // start-sanitize-r5900
5313 *r5900:
5314 // end-sanitize-r5900
5315 *r3900:
5316 // start-sanitize-tx19
5317 *tx19:
5318 // end-sanitize-tx19
5319 {
5320   unsigned32 instruction = instruction_0;
5321   int destreg = ((instruction >> 6) & 0x0000001F);
5322   int fs = ((instruction >> 11) & 0x0000001F);
5323   int format = ((instruction >> 21) & 0x00000007);
5324   {
5325   if ((format != fmt_single) && (format != fmt_double))
5326    SignalException(ReservedInstruction,instruction);
5327   else
5328    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5329   }
5330 }
5331
5332
5333 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5334 "trunc.w.%s<FMT> f<FD>, f<FS>"
5335 *mipsII:
5336 *mipsIII:
5337 *mipsIV:
5338 *vr5000:
5339 // start-sanitize-vr4320
5340 *vr4320:
5341 // end-sanitize-vr4320
5342 // start-sanitize-vr5400
5343 *vr5400:
5344 // end-sanitize-vr5400
5345 // start-sanitize-r5900
5346 *r5900:
5347 // end-sanitize-r5900
5348 *r3900:
5349 // start-sanitize-tx19
5350 *tx19:
5351 // end-sanitize-tx19
5352 {
5353   unsigned32 instruction = instruction_0;
5354   int destreg = ((instruction >> 6) & 0x0000001F);
5355   int fs = ((instruction >> 11) & 0x0000001F);
5356   int format = ((instruction >> 21) & 0x00000007);
5357   {
5358   if ((format != fmt_single) && (format != fmt_double))
5359    SignalException(ReservedInstruction,instruction);
5360   else
5361    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5362   }
5363 }
5364
5365 \f
5366 //
5367 // MIPS Architecture:
5368 //
5369 //        System Control Instruction Set (COP0)
5370 //
5371
5372
5373 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5374 "bc0f <OFFSET>"
5375 *mipsI,mipsII,mipsIII,mipsIV:
5376 *vr5000:
5377 // start-sanitize-vr4320
5378 *vr4320:
5379 // end-sanitize-vr4320
5380 // start-sanitize-vr5400
5381 *vr5400:
5382 // end-sanitize-vr5400
5383 // start-sanitize-r5900
5384 *r5900:
5385 // end-sanitize-r5900
5386
5387
5388 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5389 "bc0fl <OFFSET>"
5390 *mipsI,mipsII,mipsIII,mipsIV:
5391 *vr5000:
5392 // start-sanitize-vr4320
5393 *vr4320:
5394 // end-sanitize-vr4320
5395 // start-sanitize-vr5400
5396 *vr5400:
5397 // end-sanitize-vr5400
5398 // start-sanitize-r5900
5399 *r5900:
5400 // end-sanitize-r5900
5401
5402
5403 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5404 "bc0t <OFFSET>"
5405 *mipsI,mipsII,mipsIII,mipsIV:
5406 // start-sanitize-r5900
5407 *r5900:
5408 // end-sanitize-r5900
5409
5410
5411
5412 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5413 "bc0tl <OFFSET>"
5414 *mipsI,mipsII,mipsIII,mipsIV:
5415 *vr5000:
5416 // start-sanitize-vr4320
5417 *vr4320:
5418 // end-sanitize-vr4320
5419 // start-sanitize-vr5400
5420 *vr5400:
5421 // end-sanitize-vr5400
5422 // start-sanitize-r5900
5423 *r5900:
5424 // end-sanitize-r5900
5425
5426
5427 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5428 *mipsIII:
5429 *mipsIV:
5430 *vr5000:
5431 // start-sanitize-vr4320
5432 *vr4320:
5433 // end-sanitize-vr4320
5434 // start-sanitize-vr5400
5435 *vr5400:
5436 // end-sanitize-vr5400
5437 // start-sanitize-r5900
5438 *r5900:
5439 // end-sanitize-r5900
5440 *r3900:
5441 // start-sanitize-tx19
5442 *tx19:
5443 // end-sanitize-tx19
5444 {
5445   unsigned32 instruction = instruction_0;
5446   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5447   int hint = ((instruction >> 16) & 0x0000001F);
5448   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5449   {
5450     address_word vaddr = (op1 + offset);
5451     address_word paddr;
5452     int uncached;
5453     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5454       CacheOp(hint,vaddr,paddr,instruction);
5455   }
5456 }
5457
5458
5459 010000,10000,000000000000000,111001:COP0:32::DI
5460 "di"
5461 *mipsI,mipsII,mipsIII,mipsIV:
5462 *vr5000:
5463 // start-sanitize-vr4320
5464 *vr4320:
5465 // end-sanitize-vr4320
5466 // start-sanitize-vr5400
5467 *vr5400:
5468 // end-sanitize-vr5400
5469 // start-sanitize-r5900
5470 *r5900:
5471 // end-sanitize-r5900
5472
5473
5474 010000,10000,000000000000000,111000:COP0:32::EI
5475 "ei"
5476 *mipsI,mipsII,mipsIII,mipsIV:
5477 *vr5000:
5478 // start-sanitize-vr4320
5479 *vr4320:
5480 // end-sanitize-vr4320
5481 // start-sanitize-vr5400
5482 *vr5400:
5483 // end-sanitize-vr5400
5484 // start-sanitize-r5900
5485 *r5900:
5486 // end-sanitize-r5900
5487
5488
5489 010000,10000,000000000000000,011000:COP0:32::ERET
5490 "eret"
5491 *mipsIII:
5492 *mipsIV:
5493 *vr5000:
5494 // start-sanitize-vr4320
5495 *vr4320:
5496 // end-sanitize-vr4320
5497 // start-sanitize-vr5400
5498 *vr5400:
5499 // end-sanitize-vr5400
5500 // start-sanitize-r5900
5501 *r5900:
5502 // end-sanitize-r5900
5503 {
5504   if (SR & status_ERL)
5505     {
5506       /* Oops, not yet available */
5507       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5508       NIA = EPC;
5509       SR &= ~status_ERL;
5510     }
5511   else
5512     {
5513       NIA = EPC;
5514       SR &= ~status_EXL;
5515     }
5516 }
5517
5518
5519 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5520 "mfc0 r<RT>, r<RD> # <REGX>"
5521 *mipsI,mipsII,mipsIII,mipsIV:
5522 *r3900:
5523 *vr5000:
5524 // start-sanitize-vr4320
5525 *vr4320:
5526 // end-sanitize-vr4320
5527 // start-sanitize-vr5400
5528 *vr5400:
5529 // end-sanitize-vr5400
5530 // start-sanitize-r5900
5531 *r5900:
5532 // end-sanitize-r5900
5533 {
5534   TRACE_ALU_INPUT0 ();
5535   DecodeCoproc (instruction_0);
5536   TRACE_ALU_RESULT (GPR[RT]);
5537 }
5538
5539 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5540 "mtc0 r<RT>, r<RD> # <REGX>"
5541 *mipsI,mipsII,mipsIII,mipsIV:
5542 // start-sanitize-tx19
5543 *tx19:
5544 // end-sanitize-tx19
5545 *r3900:
5546 // start-sanitize-vr4320
5547 *vr4320:
5548 // end-sanitize-vr4320
5549 *vr5000:
5550 // start-sanitize-vr5400
5551 *vr5400:
5552 // end-sanitize-vr5400
5553 // start-sanitize-r5900
5554 *r5900:
5555 // end-sanitize-r5900
5556 {
5557   DecodeCoproc (instruction_0);
5558 }
5559
5560
5561 010000,10000,000000000000000,010000:COP0:32::RFE
5562 "rfe"
5563 *mipsI,mipsII,mipsIII,mipsIV:
5564 // start-sanitize-tx19
5565 *tx19:
5566 // end-sanitize-tx19
5567 *r3900:
5568 // start-sanitize-vr4320
5569 *vr4320:
5570 // end-sanitize-vr4320
5571 *vr5000:
5572 // start-sanitize-vr5400
5573 *vr5400:
5574 // end-sanitize-vr5400
5575 // start-sanitize-r5900
5576 *r5900:
5577 // end-sanitize-r5900
5578 {
5579   DecodeCoproc (instruction_0);
5580 }
5581
5582
5583 010000,10000,000000000000000,001000:COP0:32::TLBP
5584 "tlbp"
5585 *mipsI,mipsII,mipsIII,mipsIV:
5586 *vr5000:
5587 // start-sanitize-vr4320
5588 *vr4320:
5589 // end-sanitize-vr4320
5590 // start-sanitize-vr5400
5591 *vr5400:
5592 // end-sanitize-vr5400
5593 // start-sanitize-r5900
5594 *r5900:
5595 // end-sanitize-r5900
5596
5597
5598 010000,10000,000000000000000,000001:COP0:32::TLBR
5599 "tlbr"
5600 *mipsI,mipsII,mipsIII,mipsIV:
5601 *vr5000:
5602 // start-sanitize-vr4320
5603 *vr4320:
5604 // end-sanitize-vr4320
5605 // start-sanitize-vr5400
5606 *vr5400:
5607 // end-sanitize-vr5400
5608 // start-sanitize-r5900
5609 *r5900:
5610 // end-sanitize-r5900
5611
5612
5613 010000,10000,000000000000000,000010:COP0:32::TLBWI
5614 "tlbwi"
5615 *mipsI,mipsII,mipsIII,mipsIV:
5616 *vr5000:
5617 // start-sanitize-vr4320
5618 *vr4320:
5619 // end-sanitize-vr4320
5620 // start-sanitize-vr5400
5621 *vr5400:
5622 // end-sanitize-vr5400
5623 // start-sanitize-r5900
5624 *r5900:
5625 // end-sanitize-r5900
5626
5627
5628 010000,10000,000000000000000,000110:COP0:32::TLBWR
5629 "tlbwr"
5630 *mipsI,mipsII,mipsIII,mipsIV:
5631 *vr5000:
5632 // start-sanitize-vr4320
5633 *vr4320:
5634 // end-sanitize-vr4320
5635 // start-sanitize-vr5400
5636 *vr5400:
5637 // end-sanitize-vr5400
5638 // start-sanitize-r5900
5639 *r5900:
5640 // end-sanitize-r5900
5641
5642 \f
5643 :include:::m16.igen
5644 // start-sanitize-vr4320
5645 :include::vr4320:vr4320.igen
5646 // end-sanitize-vr4320
5647 // start-sanitize-vr5400
5648 :include::vr5400:vr5400.igen
5649 :include:64,f::mdmx.igen
5650 // end-sanitize-vr5400
5651 // start-sanitize-r5900
5652 :include::r5900:r5900.igen
5653 // end-sanitize-r5900
5654 :include:::tx.igen
5655 \f
5656 // start-sanitize-cygnus-never
5657
5658 // // FIXME FIXME FIXME What is this instruction?
5659 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5660 // *mipsI:
5661 // *mipsII:
5662 // *mipsIII:
5663 // *mipsIV:
5664 // // start-sanitize-r5900
5665 // *r5900:
5666 // // end-sanitize-r5900
5667 // *r3900:
5668 // // start-sanitize-tx19
5669 // *tx19:
5670 // // end-sanitize-tx19
5671 // {
5672 //   unsigned32 instruction = instruction_0;
5673 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5674 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5675 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5676 //   {
5677 //     if (CoProcPresent(3))
5678 //       SignalException(CoProcessorUnusable);
5679 //     else
5680 //       SignalException(ReservedInstruction,instruction);
5681 //   }
5682 // }
5683
5684 // end-sanitize-cygnus-never
5685 // start-sanitize-cygnus-never
5686
5687 // // FIXME FIXME FIXME What is this?
5688 // 11100,******,00001:RR:16::SDBBP
5689 // *mips16:
5690 // {
5691 //   unsigned32 instruction = instruction_0;
5692 //   if (have_extendval)
5693 //     SignalException (ReservedInstruction, instruction);
5694 //   {
5695 //     SignalException(DebugBreakPoint,instruction);
5696 //   }
5697 // }
5698
5699 // end-sanitize-cygnus-never
5700 // start-sanitize-cygnus-never
5701
5702 // // FIXME FIXME FIXME What is this?
5703 // 000000,********************,001110:SPECIAL:32::SDBBP
5704 // *r3900:
5705 // {
5706 //   unsigned32 instruction = instruction_0;
5707 //   {
5708 //     SignalException(DebugBreakPoint,instruction);
5709 //   }
5710 // }
5711
5712 // end-sanitize-cygnus-never
5713 // start-sanitize-cygnus-never
5714
5715 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5716 // // isn't yet reconized by this simulator.
5717 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5718 // *vr4100:
5719 // {
5720 //   unsigned32 instruction = instruction_0;
5721 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5722 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5723 //   {
5724 //     CHECKHILO("Multiply-Add");
5725 //     {
5726 //       unsigned64 temp = (op1 * op2);
5727 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5728 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5729 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5730 //     }
5731 //   }
5732 // }
5733
5734 // end-sanitize-cygnus-never
5735 // start-sanitize-cygnus-never
5736
5737 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5738 // // isn't yet reconized by this simulator.
5739 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5740 // *vr4100:
5741 // {
5742 //   unsigned32 instruction = instruction_0;
5743 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5744 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5745 //   {
5746 //     CHECKHILO("Multiply-Add");
5747 //     {
5748 //       unsigned64 temp = (op1 * op2);
5749 //       LO = LO + temp;
5750 //     }
5751 //   }
5752 // }
5753
5754 // end-sanitize-cygnus-never