sim/mips/mips.igen

   1 //    <insn> ::=
   2 //        <insn-word> { "+" <insn-word> }
   3 //        ":" <format-name>
   4 //        ":" <filter-flags>
   5 //        ":" <options>
   6 //        ":" <name>
   7 //        <nl>
   8 //        { <insn-model> }
   9 //        { <insn-mnemonic> }
  10 //        <code-block>
  11 //
  12
  13
  14 // IGEN config - mips16
  15 :option:16::insn-bit-size:16
  16 :option:16::hi-bit-nr:15
  17 :option:16::insn-specifying-widths:true
  18 :option:16::gen-delayed-branch:false
  19
  20 // IGEN config - mips32/64..
  21 :option:32::insn-bit-size:32
  22 :option:32::hi-bit-nr:31
  23 :option:32::insn-specifying-widths:true
  24 :option:32::gen-delayed-branch:false
  25
  26
  27 // Generate separate simulators for each target
  28 // :option:::multi-sim:true
  29
  30
  31 // Models known by this simulator
  32 :model:::mipsI:mipsI:
  33 :model:::mipsII:mipsII:
  34 :model:::mipsIII:mipsIII:
  35 :model:::mipsIV:mipsIV:
  36 :model:::mips16:mips16:
  37 // start-sanitize-r5900
  38 :model:::r5900:r5900:
  39 // end-sanitize-r5900
  40 :model:::r3900:r3900:
  41 // start-sanitize-tx19
  42 :model:::tx19:tx19:
  43 // end-sanitize-tx19
  44 // start-sanitize-vr5400
  45 :model:::vr5400:vr5400:
  46 // end-sanitize-vr5400
  47
  48
  49
  50 // Pseudo instructions known by IGEN
  51 :internal::::illegal:
  52 {
  53   SignalException (ReservedInstruction, 0);
  54 }
  55
  56
  57 // Pseudo instructions known by interp.c
  58 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  59 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  60 "rsvd <OP>"
  61 {
  62   SignalException (ReservedInstruction, instruction_0);
  63 }
  64
  65
  66
  67 //
  68 // Mips Architecture:
  69 //
  70 //        CPU Instruction Set (mipsI - mipsIV)
  71 //
  72
  73
  74 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  75 "add r<RD>, r<RS>, r<RT>"
  76 *mipsI:
  77 *mipsII:
  78 *mipsIII:
  79 *mipsIV:
  80 // start-sanitize-vr5400
  81 *vr5400:
  82 // end-sanitize-vr5400
  83 // start-sanitize-r5900
  84 *r5900:
  85 // end-sanitize-r5900
  86 *r3900:
  87 // start-sanitize-tx19
  88 *tx19:
  89 // end-sanitize-tx19
  90 {
  91   ALU32_BEGIN (GPR[RS]);
  92   ALU32_ADD (GPR[RT]);
  93   ALU32_END (GPR[RD]);
  94 }
  95
  96
  97 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
  98 "addi r<RT>, r<RS>, IMMEDIATE"
  99 *mipsI:
 100 *mipsII:
 101 *mipsIII:
 102 *mipsIV:
 103 // start-sanitize-vr5400
 104 *vr5400:
 105 // end-sanitize-vr5400
 106 // start-sanitize-r5900
 107 *r5900:
 108 // end-sanitize-r5900
 109 *r3900:
 110 // start-sanitize-tx19
 111 *tx19:
 112 // end-sanitize-tx19
 113 {
 114   ALU32_BEGIN (GPR[RS]);
 115   ALU32_ADD (EXTEND16 (IMMEDIATE));
 116   ALU32_END (GPR[RT]);
 117 }
 118
 119
 120 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 121 "add r<RT>, r<RS>, <IMMEDIATE>"
 122 *mipsI:
 123 *mipsII:
 124 *mipsIII:
 125 *mipsIV:
 126 // start-sanitize-vr5400
 127 *vr5400:
 128 // end-sanitize-vr5400
 129 // start-sanitize-r5900
 130 *r5900:
 131 // end-sanitize-r5900
 132 *r3900:
 133 // start-sanitize-tx19
 134 *tx19:
 135 // end-sanitize-tx19
 136 {
 137   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 138   GPR[RT] = EXTEND32 (temp);
 139 }
 140
 141
 142 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 143 *mipsI:
 144 *mipsII:
 145 *mipsIII:
 146 *mipsIV:
 147 // start-sanitize-vr5400
 148 *vr5400:
 149 // end-sanitize-vr5400
 150 // start-sanitize-r5900
 151 *r5900:
 152 // end-sanitize-r5900
 153 *r3900:
 154 // start-sanitize-tx19
 155 *tx19:
 156 // end-sanitize-tx19
 157 {
 158   signed32 temp = GPR[RS] + GPR[RT];
 159   GPR[RD] = EXTEND32 (temp);
 160 }
 161
 162
 163 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 164 "and r<RD>, r<RS>, r<RT>"
 165 *mipsI:
 166 *mipsII:
 167 *mipsIII:
 168 *mipsIV:
 169 // start-sanitize-vr5400
 170 *vr5400:
 171 // end-sanitize-vr5400
 172 // start-sanitize-r5900
 173 *r5900:
 174 // end-sanitize-r5900
 175 *r3900:
 176 // start-sanitize-tx19
 177 *tx19:
 178 // end-sanitize-tx19
 179 {
 180   GPR[RD] = GPR[RS] & GPR[RT];
 181 }
 182
 183
 184 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 185 "and r<RT>, r<RS>, IMMEDIATE"
 186 *mipsI:
 187 *mipsII:
 188 *mipsIII:
 189 // start-sanitize-vr5400
 190 *vr5400:
 191 // end-sanitize-vr5400
 192 // start-sanitize-r5900
 193 *r5900:
 194 // end-sanitize-r5900
 195 *r3900:
 196 // start-sanitize-tx19
 197 *tx19:
 198 // end-sanitize-tx19
 199 {
 200   GPR[RT] = GPR[RS] & IMMEDIATE;
 201 }
 202
 203
 204 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 205 "beq r<RS>, r<RT>, <OFFSET>"
 206 *mipsI:
 207 *mipsII:
 208 *mipsIII:
 209 *mipsIV:
 210 // start-sanitize-vr5400
 211 *vr5400:
 212 // end-sanitize-vr5400
 213 // start-sanitize-r5900
 214 *r5900:
 215 // end-sanitize-r5900
 216 *r3900:
 217 // start-sanitize-tx19
 218 *tx19:
 219 // end-sanitize-tx19
 220 {
 221   address_word offset = EXTEND16 (OFFSET) << 2;
 222   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 223     DELAY_SLOT (NIA + offset);
 224 }
 225
 226
 227 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 228 "beql r<RS>, r<RT>, <OFFSET>"
 229 *mipsII:
 230 *mipsIII:
 231 *mipsIV:
 232 // start-sanitize-vr5400
 233 *vr5400:
 234 // end-sanitize-vr5400
 235 // start-sanitize-r5900
 236 *r5900:
 237 // end-sanitize-r5900
 238 *r3900:
 239 // start-sanitize-tx19
 240 *tx19:
 241 // end-sanitize-tx19
 242 {
 243   address_word offset = EXTEND16 (OFFSET) << 2;
 244   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 245     DELAY_SLOT (NIA + offset);
 246   else
 247     NULLIFY_NEXT_INSTRUCTION ();
 248 }
 249
 250
 251 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 252 "bgez r<RS>, <OFFSET>"
 253 *mipsI:
 254 *mipsII:
 255 *mipsIII:
 256 *mipsIV:
 257 // start-sanitize-vr5400
 258 *vr5400:
 259 // end-sanitize-vr5400
 260 // start-sanitize-r5900
 261 *r5900:
 262 // end-sanitize-r5900
 263 *r3900:
 264 // start-sanitize-tx19
 265 *tx19:
 266 // end-sanitize-tx19
 267 {
 268   address_word offset = EXTEND16 (OFFSET) << 2;
 269   if ((signed_word) GPR[RS] >= 0)
 270     DELAY_SLOT (NIA + offset);
 271 }
 272
 273
 274 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 275 "bgezal r<RS>, <OFFSET>"
 276 *mipsI:
 277 *mipsII:
 278 *mipsIII:
 279 *mipsIV:
 280 // start-sanitize-vr5400
 281 *vr5400:
 282 // end-sanitize-vr5400
 283 // start-sanitize-r5900
 284 *r5900:
 285 // end-sanitize-r5900
 286 *r3900:
 287 // start-sanitize-tx19
 288 *tx19:
 289 // end-sanitize-tx19
 290 {
 291   address_word offset = EXTEND16 (OFFSET) << 2;
 292   RA = (CIA + 8);
 293   if ((signed_word) GPR[RS] >= 0)
 294     DELAY_SLOT (NIA + offset);
 295 }
 296
 297
 298 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 299 "bgezall r<RS>, <OFFSET>"
 300 *mipsII:
 301 *mipsIII:
 302 *mipsIV:
 303 // start-sanitize-vr5400
 304 *vr5400:
 305 // end-sanitize-vr5400
 306 // start-sanitize-r5900
 307 *r5900:
 308 // end-sanitize-r5900
 309 *r3900:
 310 // start-sanitize-tx19
 311 *tx19:
 312 // end-sanitize-tx19
 313 {
 314   address_word offset = EXTEND16 (OFFSET) << 2;
 315   RA = (CIA + 8);
 316   /* NOTE: The branch occurs AFTER the next instruction has been
 317      executed */
 318   if ((signed_word) GPR[RS] >= 0)
 319     DELAY_SLOT (NIA + offset);
 320   else
 321     NULLIFY_NEXT_INSTRUCTION ();
 322 }
 323
 324
 325 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 326 "bgezl r<RS>, <OFFSET>"
 327 *mipsII:
 328 *mipsIII:
 329 *mipsIV:
 330 // start-sanitize-vr5400
 331 *vr5400:
 332 // end-sanitize-vr5400
 333 // start-sanitize-r5900
 334 *r5900:
 335 // end-sanitize-r5900
 336 *r3900:
 337 // start-sanitize-tx19
 338 *tx19:
 339 // end-sanitize-tx19
 340 {
 341   address_word offset = EXTEND16 (OFFSET) << 2;
 342   if ((signed_word) GPR[RS] >= 0)
 343     DELAY_SLOT (NIA + offset);
 344   else
 345     NULLIFY_NEXT_INSTRUCTION ();
 346 }
 347
 348
 349 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 350 "bgtz r<RS>, <OFFSET>"
 351 *mipsI:
 352 *mipsII:
 353 *mipsIII:
 354 *mipsIV:
 355 // start-sanitize-vr5400
 356 *vr5400:
 357 // end-sanitize-vr5400
 358 // start-sanitize-r5900
 359 *r5900:
 360 // end-sanitize-r5900
 361 *r3900:
 362 // start-sanitize-tx19
 363 *tx19:
 364 // end-sanitize-tx19
 365 {
 366   address_word offset = EXTEND16 (OFFSET) << 2;
 367   if ((signed_word) GPR[RS] > 0)
 368     DELAY_SLOT (NIA + offset);
 369 }
 370
 371
 372 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 373 "bgtzl r<RS>, <OFFSET>"
 374 *mipsII:
 375 *mipsIII:
 376 *mipsIV:
 377 // start-sanitize-vr5400
 378 *vr5400:
 379 // end-sanitize-vr5400
 380 // start-sanitize-r5900
 381 *r5900:
 382 // end-sanitize-r5900
 383 *r3900:
 384 // start-sanitize-tx19
 385 *tx19:
 386 // end-sanitize-tx19
 387 {
 388   address_word offset = EXTEND16 (OFFSET) << 2;
 389   /* NOTE: The branch occurs AFTER the next instruction has been
 390      executed */
 391   if ((signed_word) GPR[RS] > 0)
 392     DELAY_SLOT (NIA + offset);
 393   else
 394     NULLIFY_NEXT_INSTRUCTION ();
 395 }
 396
 397
 398 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 399 "blez r<RS>, <OFFSET>"
 400 *mipsI:
 401 *mipsII:
 402 *mipsIII:
 403 *mipsIV:
 404 // start-sanitize-vr5400
 405 *vr5400:
 406 // end-sanitize-vr5400
 407 // start-sanitize-r5900
 408 *r5900:
 409 // end-sanitize-r5900
 410 *r3900:
 411 // start-sanitize-tx19
 412 *tx19:
 413 // end-sanitize-tx19
 414 {
 415   address_word offset = EXTEND16 (OFFSET) << 2;
 416   /* NOTE: The branch occurs AFTER the next instruction has been
 417      executed */
 418   if ((signed_word) GPR[RS] <= 0)
 419     DELAY_SLOT (NIA + offset);
 420 }
 421
 422
 423 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 424 "bgezl r<RS>, <OFFSET>"
 425 *mipsII:
 426 *mipsIII:
 427 *mipsIV:
 428 // start-sanitize-vr5400
 429 *vr5400:
 430 // end-sanitize-vr5400
 431 // start-sanitize-r5900
 432 *r5900:
 433 // end-sanitize-r5900
 434 *r3900:
 435 // start-sanitize-tx19
 436 *tx19:
 437 // end-sanitize-tx19
 438 {
 439   address_word offset = EXTEND16 (OFFSET) << 2;
 440   if ((signed_word) GPR[RS] <= 0)
 441     DELAY_SLOT (NIA + offset);
 442   else
 443     NULLIFY_NEXT_INSTRUCTION ();
 444 }
 445
 446
 447 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 448 "bltz r<RS>, <OFFSET>"
 449 *mipsI:
 450 *mipsII:
 451 *mipsIII:
 452 *mipsIV:
 453 // start-sanitize-vr5400
 454 *vr5400:
 455 // end-sanitize-vr5400
 456 // start-sanitize-r5900
 457 *r5900:
 458 // end-sanitize-r5900
 459 *r3900:
 460 // start-sanitize-tx19
 461 *tx19:
 462 // end-sanitize-tx19
 463 {
 464   address_word offset = EXTEND16 (OFFSET) << 2;
 465   if ((signed_word) GPR[RS] < 0)
 466     DELAY_SLOT (NIA + offset);
 467 }
 468
 469
 470 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 471 "bltzal r<RS>, <OFFSET>"
 472 *mipsI:
 473 *mipsII:
 474 *mipsIII:
 475 *mipsIV:
 476 // start-sanitize-vr5400
 477 *vr5400:
 478 // end-sanitize-vr5400
 479 // start-sanitize-r5900
 480 *r5900:
 481 // end-sanitize-r5900
 482 *r3900:
 483 // start-sanitize-tx19
 484 *tx19:
 485 // end-sanitize-tx19
 486 {
 487   address_word offset = EXTEND16 (OFFSET) << 2;
 488   RA = (CIA + 8);
 489   /* NOTE: The branch occurs AFTER the next instruction has been
 490      executed */
 491   if ((signed_word) GPR[RS] < 0)
 492     DELAY_SLOT (NIA + offset);
 493 }
 494
 495
 496 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 497 "bltzall r<RS>, <OFFSET>"
 498 *mipsII:
 499 *mipsIII:
 500 *mipsIV:
 501 // start-sanitize-vr5400
 502 *vr5400:
 503 // end-sanitize-vr5400
 504 // start-sanitize-r5900
 505 *r5900:
 506 // end-sanitize-r5900
 507 *r3900:
 508 // start-sanitize-tx19
 509 *tx19:
 510 // end-sanitize-tx19
 511 {
 512   address_word offset = EXTEND16 (OFFSET) << 2;
 513   RA = (CIA + 8);
 514   if ((signed_word) GPR[RS] < 0)
 515     DELAY_SLOT (NIA + offset);
 516   else
 517     NULLIFY_NEXT_INSTRUCTION ();
 518 }
 519
 520
 521 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 522 "bltzl r<RS>, <OFFSET>"
 523 *mipsII:
 524 *mipsIII:
 525 *mipsIV:
 526 // start-sanitize-vr5400
 527 *vr5400:
 528 // end-sanitize-vr5400
 529 // start-sanitize-r5900
 530 *r5900:
 531 // end-sanitize-r5900
 532 *r3900:
 533 // start-sanitize-tx19
 534 *tx19:
 535 // end-sanitize-tx19
 536 {
 537   address_word offset = EXTEND16 (OFFSET) << 2;
 538   /* NOTE: The branch occurs AFTER the next instruction has been
 539      executed */
 540   if ((signed_word) GPR[RS] < 0)
 541     DELAY_SLOT (NIA + offset);
 542   else
 543     NULLIFY_NEXT_INSTRUCTION ();
 544 }
 545
 546
 547 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 548 "bne r<RS>, r<RT>, <OFFSET>"
 549 *mipsI:
 550 *mipsII:
 551 *mipsIII:
 552 *mipsIV:
 553 // start-sanitize-vr5400
 554 *vr5400:
 555 // end-sanitize-vr5400
 556 // start-sanitize-r5900
 557 *r5900:
 558 // end-sanitize-r5900
 559 *r3900:
 560 // start-sanitize-tx19
 561 *tx19:
 562 // end-sanitize-tx19
 563 {
 564   address_word offset = EXTEND16 (OFFSET) << 2;
 565   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 566     DELAY_SLOT (NIA + offset);
 567 }
 568
 569
 570 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 571 "bnel r<RS>, r<RT>, <OFFSET>"
 572 *mipsII:
 573 *mipsIII:
 574 *mipsIV:
 575 // start-sanitize-vr5400
 576 *vr5400:
 577 // end-sanitize-vr5400
 578 // start-sanitize-r5900
 579 *r5900:
 580 // end-sanitize-r5900
 581 *r3900:
 582 // start-sanitize-tx19
 583 *tx19:
 584 // end-sanitize-tx19
 585 {
 586   address_word offset = EXTEND16 (OFFSET) << 2;
 587   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 588     DELAY_SLOT (NIA + offset);
 589   else
 590     NULLIFY_NEXT_INSTRUCTION ();
 591 }
 592
 593
 594 000000,20.CODE,001101:SPECIAL:32::BREAK
 595 "break"
 596 *mipsI:
 597 *mipsII:
 598 *mipsIII:
 599 *mipsIV:
 600 // start-sanitize-vr5400
 601 *vr5400:
 602 // end-sanitize-vr5400
 603 // start-sanitize-r5900
 604 *r5900:
 605 // end-sanitize-r5900
 606 *r3900:
 607 // start-sanitize-tx19
 608 *tx19:
 609 // end-sanitize-tx19
 610 {
 611   SignalException(BreakPoint, instruction_0);
 612 }
 613
 614
 615 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 616 "cop<ZZ> <COP_FUN>"
 617 *mipsI:
 618 *mipsII:
 619 *mipsIII:
 620 *mipsIV:
 621 // start-sanitize-r5900
 622 *r5900:
 623 // end-sanitize-r5900
 624 *r3900:
 625 // start-sanitize-tx19
 626 *tx19:
 627 // end-sanitize-tx19
 628 {
 629   DecodeCoproc (instruction_0);
 630 }
 631
 632
 633 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 634 "dadd r<RD>, r<RS>, r<RT>"
 635 *mipsIII:
 636 *mipsIV:
 637 // start-sanitize-vr5400
 638 *vr5400:
 639 // end-sanitize-vr5400
 640 // start-sanitize-r5900
 641 *r5900:
 642 // end-sanitize-r5900
 643 *r3900:
 644 // start-sanitize-tx19
 645 *tx19:
 646 // end-sanitize-tx19
 647 {
 648   ALU64_BEGIN (GPR[RS]);
 649   ALU64_ADD (GPR[RT]);
 650   ALU64_END (GPR[RT]);
 651 }
 652
 653
 654 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 655 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 656 *mipsIII:
 657 *mipsIV:
 658 // start-sanitize-vr5400
 659 *vr5400:
 660 // end-sanitize-vr5400
 661 // start-sanitize-r5900
 662 *r5900:
 663 // end-sanitize-r5900
 664 *r3900:
 665 // start-sanitize-tx19
 666 *tx19:
 667 // end-sanitize-tx19
 668 {
 669   ALU64_BEGIN (GPR[RS]);
 670   ALU64_ADD (EXTEND16 (IMMEDIATE));
 671   ALU64_END (GPR[RT]);
 672 }
 673
 674
 675 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 676 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 677 *mipsIII:
 678 *mipsIV:
 679 // start-sanitize-vr5400
 680 *vr5400:
 681 // end-sanitize-vr5400
 682 // start-sanitize-r5900
 683 *r5900:
 684 // end-sanitize-r5900
 685 *r3900:
 686 // start-sanitize-tx19
 687 *tx19:
 688 // end-sanitize-tx19
 689 {
 690   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 691 }
 692
 693
 694 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 695 "daddu r<RD>, r<RS>, r<RT>"
 696 *mipsIII:
 697 *mipsIV:
 698 // start-sanitize-vr5400
 699 *vr5400:
 700 // end-sanitize-vr5400
 701 // start-sanitize-r5900
 702 *r5900:
 703 // end-sanitize-r5900
 704 *r3900:
 705 // start-sanitize-tx19
 706 *tx19:
 707 // end-sanitize-tx19
 708 {
 709   GPR[RD] = GPR[RS] + GPR[RT];
 710 }
 711
 712
 713 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 714 "ddiv r<RS>, r<RT>"
 715 *mipsIII:
 716 *mipsIV:
 717 // start-sanitize-vr5400
 718 *vr5400:
 719 // end-sanitize-vr5400
 720 // start-sanitize-r5900
 721 *r5900:
 722 // end-sanitize-r5900
 723 *r3900:
 724 // start-sanitize-tx19
 725 *tx19:
 726 // end-sanitize-tx19
 727 {
 728   CHECKHILO ("Division");
 729   {
 730     signed64 n = GPR[RS];
 731     signed64 d = GPR[RT];
 732     if (d == 0)
 733       {
 734         LO = SIGNED64 (0x8000000000000000);
 735         HI = 0;
 736       }
 737     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 738       {
 739         LO = SIGNED64 (0x8000000000000000);
 740         HI = 0;
 741       }
 742     else
 743       {
 744         LO = (n / d);
 745         HI = (n % d);
 746       }
 747   }
 748 }
 749
 750
 751
 752 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 753 "ddivu r<RS>, r<RT>"
 754 *mipsIII:
 755 *mipsIV:
 756 *r3900:
 757 // start-sanitize-vr5400
 758 *vr5400:
 759 // end-sanitize-vr5400
 760 // start-sanitize-tx19
 761 *tx19:
 762 // end-sanitize-tx19
 763 {
 764   CHECKHILO ("Division");
 765   {
 766     unsigned64 n = GPR[RS];
 767     unsigned64 d = GPR[RT];
 768     if (d == 0)
 769       {
 770         LO = SIGNED64 (0x8000000000000000);
 771         HI = 0;
 772       }
 773     else
 774       {
 775         LO = (n / d);
 776         HI = (n % d);
 777       }
 778   }
 779 }
 780
 781
 782 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 783 "div r<RS>, r<RT>"
 784 *mipsI:
 785 *mipsII:
 786 *mipsIII:
 787 *mipsIV:
 788 // start-sanitize-vr5400
 789 *vr5400:
 790 // end-sanitize-vr5400
 791 // start-sanitize-r5900
 792 *r5900:
 793 // end-sanitize-r5900
 794 *r3900:
 795 // start-sanitize-tx19
 796 *tx19:
 797 // end-sanitize-tx19
 798 {
 799   CHECKHILO("Division");
 800   {
 801     signed32 n = GPR[RS];
 802     signed32 d = GPR[RT];
 803     if (d == 0)
 804       {
 805         LO = EXTEND32 (0x80000000);
 806         HI = EXTEND32 (0);
 807       }
 808     else if (d == -1 && d == 0x80000000)
 809       {
 810         LO = EXTEND32 (0x80000000);
 811         HI = EXTEND32 (0);
 812       }
 813     else
 814       {
 815         LO = EXTEND32 (n / d);
 816         HI = EXTEND32 (n % d);
 817       }
 818   }
 819 }
 820
 821
 822 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 823 "divu r<RS>, r<RT>"
 824 *mipsI:
 825 *mipsII:
 826 *mipsIII:
 827 *mipsIV:
 828 // start-sanitize-vr5400
 829 *vr5400:
 830 // end-sanitize-vr5400
 831 // start-sanitize-r5900
 832 *r5900:
 833 // end-sanitize-r5900
 834 *r3900:
 835 // start-sanitize-tx19
 836 *tx19:
 837 // end-sanitize-tx19
 838 {
 839   CHECKHILO ("Division");
 840   {
 841     unsigned32 n = GPR[RS];
 842     unsigned32 d = GPR[RT];
 843     if (d == 0)
 844       {
 845         LO = EXTEND32 (0x80000000);
 846         HI = EXTEND32 (0);
 847       }
 848    else
 849      {
 850        LO = EXTEND32 (n / d);
 851        HI = EXTEND32 (n % d);
 852      }
 853   }
 854 }
 855
 856
 857 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 858 "dmult r<RS>, r<RT>"
 859 *mipsIII:
 860 *mipsIV:
 861 // start-sanitize-vr5400
 862 *vr5400:
 863 // end-sanitize-vr5400
 864 *r3900:
 865 // start-sanitize-tx19
 866 *tx19:
 867 // end-sanitize-tx19
 868 {
 869   CHECKHILO ("Multiplication");
 870   {
 871     signed64 op1 = GPR[RS];
 872     signed64 op2 = GPR[RT];
 873     unsigned64 lo;
 874     unsigned64 hi;
 875     unsigned64 m00;
 876     unsigned64 m01;
 877     unsigned64 m10;
 878     unsigned64 m11;
 879     unsigned64 mid;
 880     int sign = 0;
 881     /* make it unsigned */
 882     if (op1 < 0)
 883       {
 884         op1 = - op1;
 885         ++sign;
 886       }
 887     if (op2 < 0)
 888       {
 889         op2 = - op2;
 890         ++sign;
 891       }
 892     /* multuply out the 4 sub products */
 893     m00 = (VL4_8 (op1) * VL4_8 (op2));
 894     m10 = (VH4_8 (op1) * VL4_8 (op2));
 895     m01 = (VL4_8 (op1) * VH4_8 (op2));
 896     m11 = (VH4_8 (op1) * VH4_8 (op2));
 897     /* add the products */
 898     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 899     lo = U8_4 (mid, m00);
 900     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 901     /* save the result */
 902     if (sign & 1)
 903       {
 904         LO = -lo;
 905         if (lo == 0)
 906           HI = -hi;
 907         else
 908           HI = -hi - 1;
 909       }
 910     else
 911       {
 912         LO = lo;
 913         HI = hi;
 914       }
 915   }
 916 }
 917
 918
 919 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 920 "dmultu r<RS>, r<RT>"
 921 *mipsIII:
 922 *mipsIV:
 923 // start-sanitize-vr5400
 924 *vr5400:
 925 // end-sanitize-vr5400
 926 *r3900:
 927 // start-sanitize-tx19
 928 *tx19:
 929 // end-sanitize-tx19
 930 {
 931   CHECKHILO ("Multiplication");
 932   {
 933     signed64 op1 = GPR[RS];
 934     signed64 op2 = GPR[RT];
 935     unsigned64 lo;
 936     unsigned64 hi;
 937     unsigned64 m00;
 938     unsigned64 m01;
 939     unsigned64 m10;
 940     unsigned64 m11;
 941     unsigned64 mid;
 942     /* multuply out the 4 sub products */
 943     m00 = (VL4_8 (op1) * VL4_8 (op2));
 944     m10 = (VH4_8 (op1) * VL4_8 (op2));
 945     m01 = (VL4_8 (op1) * VH4_8 (op2));
 946     m11 = (VH4_8 (op1) * VH4_8 (op2));
 947     /* add the products */
 948     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 949     lo = U8_4 (mid, m00);
 950     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 951     /* save the result */
 952     LO = lo;
 953     HI = hi;
 954   }
 955 }
 956
 957
 958 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 959 "dsll r<RD>, r<RT>, <SHIFT>"
 960 *mipsIII:
 961 *mipsIV:
 962 // start-sanitize-vr5400
 963 *vr5400:
 964 // end-sanitize-vr5400
 965 // start-sanitize-r5900
 966 *r5900:
 967 // end-sanitize-r5900
 968 *r3900:
 969 // start-sanitize-tx19
 970 *tx19:
 971 // end-sanitize-tx19
 972 {
 973   int s = SHIFT;
 974   GPR[RD] = GPR[RT] << s;
 975 }
 976
 977
 978 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
 979 "dsll32 r<RD>, r<RT>, <SHIFT>"
 980 *mipsIII:
 981 *mipsIV:
 982 // start-sanitize-vr5400
 983 *vr5400:
 984 // end-sanitize-vr5400
 985 // start-sanitize-r5900
 986 *r5900:
 987 // end-sanitize-r5900
 988 *r3900:
 989 // start-sanitize-tx19
 990 *tx19:
 991 // end-sanitize-tx19
 992 {
 993   int s = 32 + SHIFT;
 994   GPR[RD] = GPR[RT] << s;
 995 }
 996
 997
 998 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 999 "dsllv r<RD>, r<RT>, r<RS>"
1000 *mipsIII:
1001 *mipsIV:
1002 // start-sanitize-vr5400
1003 *vr5400:
1004 // end-sanitize-vr5400
1005 // start-sanitize-r5900
1006 *r5900:
1007 // end-sanitize-r5900
1008 *r3900:
1009 // start-sanitize-tx19
1010 *tx19:
1011 // end-sanitize-tx19
1012 {
1013   int s = MASKED64 (GPR[RS], 5, 0);
1014   GPR[RD] = GPR[RT] << s;
1015 }
1016
1017
1018 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1019 "dsra r<RD>, r<RT>, <SHIFT>"
1020 *mipsIII:
1021 *mipsIV:
1022 // start-sanitize-vr5400
1023 *vr5400:
1024 // end-sanitize-vr5400
1025 // start-sanitize-r5900
1026 *r5900:
1027 // end-sanitize-r5900
1028 *r3900:
1029 // start-sanitize-tx19
1030 *tx19:
1031 // end-sanitize-tx19
1032 {
1033   int s = SHIFT;
1034   GPR[RD] = ((signed64) GPR[RT]) >> s;
1035 }
1036
1037
1038 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1039 "dsra32 r<RT>, r<RD>, <SHIFT>"
1040 *mipsIII:
1041 *mipsIV:
1042 // start-sanitize-vr5400
1043 *vr5400:
1044 // end-sanitize-vr5400
1045 // start-sanitize-r5900
1046 *r5900:
1047 // end-sanitize-r5900
1048 *r3900:
1049 // start-sanitize-tx19
1050 *tx19:
1051 // end-sanitize-tx19
1052 {
1053   int s = 32 + SHIFT;
1054   GPR[RD] = ((signed64) GPR[RT]) >> s;
1055 }
1056
1057
1058 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1059 "dsra32 r<RT>, r<RD>, r<RS>"
1060 *mipsIII:
1061 *mipsIV:
1062 // start-sanitize-vr5400
1063 *vr5400:
1064 // end-sanitize-vr5400
1065 // start-sanitize-r5900
1066 *r5900:
1067 // end-sanitize-r5900
1068 *r3900:
1069 // start-sanitize-tx19
1070 *tx19:
1071 // end-sanitize-tx19
1072 {
1073   int s = MASKED64 (GPR[RS], 5, 0);
1074   GPR[RD] = ((signed64) GPR[RT]) >> s;
1075 }
1076
1077
1078 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1079 "dsrav r<RD>, r<RT>, <SHIFT>"
1080 *mipsIII:
1081 *mipsIV:
1082 // start-sanitize-vr5400
1083 *vr5400:
1084 // end-sanitize-vr5400
1085 // start-sanitize-r5900
1086 *r5900:
1087 // end-sanitize-r5900
1088 *r3900:
1089 // start-sanitize-tx19
1090 *tx19:
1091 // end-sanitize-tx19
1092 {
1093   int s = SHIFT;
1094   GPR[RD] = (unsigned64) GPR[RT] >> s;
1095 }
1096
1097
1098 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1099 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1100 *mipsIII:
1101 *mipsIV:
1102 // start-sanitize-vr5400
1103 *vr5400:
1104 // end-sanitize-vr5400
1105 // start-sanitize-r5900
1106 *r5900:
1107 // end-sanitize-r5900
1108 *r3900:
1109 // start-sanitize-tx19
1110 *tx19:
1111 // end-sanitize-tx19
1112 {
1113   int s = 32 + SHIFT;
1114   GPR[RD] = (unsigned64) GPR[RT] >> s;
1115 }
1116
1117
1118 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1119 "dsrl32 r<RD>, r<RT>, r<RS>"
1120 *mipsIII:
1121 *mipsIV:
1122 // start-sanitize-vr5400
1123 *vr5400:
1124 // end-sanitize-vr5400
1125 // start-sanitize-r5900
1126 *r5900:
1127 // end-sanitize-r5900
1128 *r3900:
1129 // start-sanitize-tx19
1130 *tx19:
1131 // end-sanitize-tx19
1132 {
1133   int s = MASKED64 (GPR[RS], 5, 0);
1134   GPR[RD] = (unsigned64) GPR[RT] >> s;
1135 }
1136
1137
1138 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1139 "dsub r<RD>, r<RS>, r<RT>"
1140 *mipsIII:
1141 *mipsIV:
1142 // start-sanitize-vr5400
1143 *vr5400:
1144 // end-sanitize-vr5400
1145 // start-sanitize-r5900
1146 *r5900:
1147 // end-sanitize-r5900
1148 *r3900:
1149 // start-sanitize-tx19
1150 *tx19:
1151 // end-sanitize-tx19
1152 {
1153   ALU64_BEGIN (GPR[RS]);
1154   ALU64_SUB (GPR[RT]);
1155   ALU64_END (GPR[RD]);
1156 }
1157
1158
1159 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1160 "dsubu r<RD>, r<RS>, r<RT>"
1161 *mipsIII:
1162 *mipsIV:
1163 // start-sanitize-vr5400
1164 *vr5400:
1165 // end-sanitize-vr5400
1166 // start-sanitize-r5900
1167 *r5900:
1168 // end-sanitize-r5900
1169 *r3900:
1170 // start-sanitize-tx19
1171 *tx19:
1172 // end-sanitize-tx19
1173 {
1174   GPR[RD] = GPR[RS] - GPR[RT];
1175 }
1176
1177
1178 000010,26.INSTR_INDEX:NORMAL:32::J
1179 "j <INSTR_INDEX>"
1180 *mipsI:
1181 *mipsII:
1182 *mipsIII:
1183 *mipsIV:
1184 // start-sanitize-vr5400
1185 *vr5400:
1186 // end-sanitize-vr5400
1187 // start-sanitize-r5900
1188 *r5900:
1189 // end-sanitize-r5900
1190 *r3900:
1191 // start-sanitize-tx19
1192 *tx19:
1193 // end-sanitize-tx19
1194 {
1195   /* NOTE: The region used is that of the delay slot NIA and NOT the
1196      current instruction */
1197   address_word region = (NIA & MASK (63, 28));
1198   DELAY_SLOT (region | (INSTR_INDEX << 2));
1199 }
1200
1201
1202 000011,26.INSTR_INDEX:NORMAL:32::JAL
1203 "jal <INSTR_INDEX>"
1204 *mipsI:
1205 *mipsII:
1206 *mipsIII:
1207 *mipsIV:
1208 // start-sanitize-vr5400
1209 *vr5400:
1210 // end-sanitize-vr5400
1211 // start-sanitize-r5900
1212 *r5900:
1213 // end-sanitize-r5900
1214 *r3900:
1215 // start-sanitize-tx19
1216 *tx19:
1217 // end-sanitize-tx19
1218 {
1219   /* NOTE: The region used is that of the delay slot and NOT the
1220      current instruction */
1221   address_word region = (NIA & MASK (63, 28));
1222   GPR[31] = CIA + 8;
1223   DELAY_SLOT (region | (INSTR_INDEX << 2));
1224 }
1225
1226
1227 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1228 "jalr r<RS>":RD == 31
1229 "jalr r<RD>, r<RS>"
1230 *mipsI:
1231 *mipsII:
1232 *mipsIII:
1233 *mipsIV:
1234 // start-sanitize-vr5400
1235 *vr5400:
1236 // end-sanitize-vr5400
1237 // start-sanitize-r5900
1238 *r5900:
1239 // end-sanitize-r5900
1240 *r3900:
1241 // start-sanitize-tx19
1242 *tx19:
1243 // end-sanitize-tx19
1244 {
1245   address_word temp = GPR[RS];
1246   GPR[RD] = CIA + 8;
1247   DELAY_SLOT (temp);
1248 }
1249
1250
1251 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1252 "jr r<RS>"
1253 *mipsI:
1254 *mipsII:
1255 *mipsIII:
1256 *mipsIV:
1257 // start-sanitize-vr5400
1258 *vr5400:
1259 // end-sanitize-vr5400
1260 // start-sanitize-r5900
1261 *r5900:
1262 // end-sanitize-r5900
1263 *r3900:
1264 // start-sanitize-tx19
1265 *tx19:
1266 // end-sanitize-tx19
1267 {
1268   DELAY_SLOT (GPR[RS]);
1269 }
1270
1271
1272 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1273 "lb r<RT>, <OFFSET>(r<BASE>)"
1274 *mipsI:
1275 *mipsII:
1276 *mipsIII:
1277 *mipsIV:
1278 // start-sanitize-vr5400
1279 *vr5400:
1280 // end-sanitize-vr5400
1281 // start-sanitize-r5900
1282 *r5900:
1283 // end-sanitize-r5900
1284 *r3900:
1285 // start-sanitize-tx19
1286 *tx19:
1287 // end-sanitize-tx19
1288 {
1289   unsigned32 instruction = instruction_0;
1290   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1291   int destreg = ((instruction >> 16) & 0x0000001F);
1292   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1293   {
1294     address_word vaddr = ((uword64)op1 + offset);
1295     address_word paddr;
1296     int uncached;
1297     {
1298       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1299         {
1300           uword64 memval = 0;
1301           uword64 memval1 = 0;
1302           uword64 mask = 0x7;
1303           unsigned int shift = 0;
1304           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1305           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1306           unsigned int byte;
1307           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1308           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1309           byte = ((vaddr & mask) ^ (bigend << shift));
1310           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1311         }
1312     }
1313   }
1314 }
1315
1316
1317 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1318 "lbu r<RT>, <OFFSET>(r<BASE>)"
1319 *mipsI:
1320 *mipsII:
1321 *mipsIII:
1322 *mipsIV:
1323 // start-sanitize-vr5400
1324 *vr5400:
1325 // end-sanitize-vr5400
1326 // start-sanitize-r5900
1327 *r5900:
1328 // end-sanitize-r5900
1329 *r3900:
1330 // start-sanitize-tx19
1331 *tx19:
1332 // end-sanitize-tx19
1333 {
1334   unsigned32 instruction = instruction_0;
1335   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1336   int destreg = ((instruction >> 16) & 0x0000001F);
1337   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1338   {
1339     address_word vaddr = ((unsigned64)op1 + offset);
1340     address_word paddr;
1341     int uncached;
1342     {
1343       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1344         {
1345           unsigned64 memval = 0;
1346           unsigned64 memval1 = 0;
1347           unsigned64 mask = 0x7;
1348           unsigned int shift = 0;
1349           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1350           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1351           unsigned int byte;
1352           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1353           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1354           byte = ((vaddr & mask) ^ (bigend << shift));
1355           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1356         }
1357     }
1358   }
1359 }
1360
1361
1362 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1363 "ld r<RT>, <OFFSET>(r<BASE>)"
1364 *mipsIII:
1365 *mipsIV:
1366 // start-sanitize-vr5400
1367 *vr5400:
1368 // end-sanitize-vr5400
1369 // start-sanitize-r5900
1370 *r5900:
1371 // end-sanitize-r5900
1372 *r3900:
1373 // start-sanitize-tx19
1374 *tx19:
1375 // end-sanitize-tx19
1376 {
1377   unsigned32 instruction = instruction_0;
1378   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1379   int destreg = ((instruction >> 16) & 0x0000001F);
1380   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1381   {
1382     address_word vaddr = ((unsigned64)op1 + offset);
1383     address_word paddr;
1384     int uncached;
1385     if ((vaddr & 7) != 0)
1386       SignalExceptionAddressLoad();
1387     else
1388       {
1389         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1390           {
1391             unsigned64 memval = 0;
1392             unsigned64 memval1 = 0;
1393             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1394             GPR[destreg] = memval;
1395           }
1396       }
1397   }
1398 }
1399
1400
1401 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1402 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1403 *mipsII:
1404 *mipsIII:
1405 *mipsIV:
1406 // start-sanitize-vr5400
1407 *vr5400:
1408 // end-sanitize-vr5400
1409 // start-sanitize-r5900
1410 *r5900:
1411 // end-sanitize-r5900
1412 *r3900:
1413 // start-sanitize-tx19
1414 *tx19:
1415 // end-sanitize-tx19
1416 {
1417   unsigned32 instruction = instruction_0;
1418   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1419   int destreg = ((instruction >> 16) & 0x0000001F);
1420   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1421   {
1422     address_word vaddr = ((unsigned64)op1 + offset);
1423     address_word paddr;
1424     int uncached;
1425     if ((vaddr & 7) != 0)
1426       SignalExceptionAddressLoad();
1427     else
1428       {
1429         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1430           {
1431             unsigned64 memval = 0;
1432             unsigned64 memval1 = 0;
1433             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1434             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1435           }
1436       }
1437   }
1438 }
1439
1440
1441 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1442 "ldl r<RT>, <OFFSET>(r<BASE>)"
1443 *mipsIII:
1444 *mipsIV:
1445 // start-sanitize-vr5400
1446 *vr5400:
1447 // end-sanitize-vr5400
1448 // start-sanitize-r5900
1449 *r5900:
1450 // end-sanitize-r5900
1451 *r3900:
1452 // start-sanitize-tx19
1453 *tx19:
1454 // end-sanitize-tx19
1455 {
1456   unsigned32 instruction = instruction_0;
1457   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1458   int destreg = ((instruction >> 16) & 0x0000001F);
1459   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1460   {
1461     address_word vaddr = ((unsigned64)op1 + offset);
1462     address_word paddr;
1463     int uncached;
1464     {
1465       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1466         {
1467           unsigned64 memval = 0;
1468           unsigned64 memval1 = 0;
1469           unsigned64 mask = 7;
1470           unsigned int reverse = (ReverseEndian ? mask : 0);
1471           unsigned int bigend = (BigEndianCPU ? mask : 0);
1472           int byte;
1473           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1474           byte = ((vaddr & mask) ^ bigend);
1475           if (!BigEndianMem)
1476             paddr &= ~mask;
1477           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1478           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1479         }
1480     }
1481   }
1482 }
1483
1484
1485 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1486 "ldr r<RT>, <OFFSET>(r<BASE>)"
1487 *mipsIII:
1488 *mipsIV:
1489 // start-sanitize-vr5400
1490 *vr5400:
1491 // end-sanitize-vr5400
1492 // start-sanitize-r5900
1493 *r5900:
1494 // end-sanitize-r5900
1495 *r3900:
1496 // start-sanitize-tx19
1497 *tx19:
1498 // end-sanitize-tx19
1499 {
1500   unsigned32 instruction = instruction_0;
1501   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1502   int destreg = ((instruction >> 16) & 0x0000001F);
1503   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1504   {
1505     address_word vaddr = ((unsigned64)op1 + offset);
1506     address_word paddr;
1507     int uncached;
1508     {
1509       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1510         {
1511           unsigned64 memval = 0;
1512           unsigned64 memval1 = 0;
1513           unsigned64 mask = 7;
1514           unsigned int reverse = (ReverseEndian ? mask : 0);
1515           unsigned int bigend = (BigEndianCPU ? mask : 0);
1516           int byte;
1517           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1518           byte = ((vaddr & mask) ^ bigend);
1519           if (BigEndianMem)
1520             paddr &= ~mask;
1521           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1522           {
1523             unsigned64 srcmask;
1524             if (byte == 0)
1525               srcmask = 0;
1526             else
1527               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1528             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1529           }
1530         }
1531     }
1532   }
1533 }
1534
1535
1536 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1537 "lh r<RT>, <OFFSET>(r<BASE>)"
1538 *mipsI:
1539 *mipsII:
1540 *mipsIII:
1541 *mipsIV:
1542 // start-sanitize-vr5400
1543 *vr5400:
1544 // end-sanitize-vr5400
1545 // start-sanitize-r5900
1546 *r5900:
1547 // end-sanitize-r5900
1548 *r3900:
1549 // start-sanitize-tx19
1550 *tx19:
1551 // end-sanitize-tx19
1552 {
1553   unsigned32 instruction = instruction_0;
1554   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1555   int destreg = ((instruction >> 16) & 0x0000001F);
1556   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1557   {
1558     address_word vaddr = ((unsigned64)op1 + offset);
1559     address_word paddr;
1560     int uncached;
1561     if ((vaddr & 1) != 0)
1562       SignalExceptionAddressLoad();
1563     else
1564       {
1565         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1566           {
1567             unsigned64 memval = 0;
1568             unsigned64 memval1 = 0;
1569             unsigned64 mask = 0x7;
1570             unsigned int shift = 1;
1571             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1572             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1573             unsigned int byte;
1574             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1575             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1576             byte = ((vaddr & mask) ^ (bigend << shift));
1577             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1578           }
1579       }
1580   }
1581 }
1582
1583
1584 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1585 "lhu r<RT>, <OFFSET>(r<BASE>)"
1586 *mipsI:
1587 *mipsII:
1588 *mipsIII:
1589 *mipsIV:
1590 // start-sanitize-vr5400
1591 *vr5400:
1592 // end-sanitize-vr5400
1593 // start-sanitize-r5900
1594 *r5900:
1595 // end-sanitize-r5900
1596 *r3900:
1597 // start-sanitize-tx19
1598 *tx19:
1599 // end-sanitize-tx19
1600 {
1601   unsigned32 instruction = instruction_0;
1602   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1603   int destreg = ((instruction >> 16) & 0x0000001F);
1604   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1605   {
1606     address_word vaddr = ((unsigned64)op1 + offset);
1607     address_word paddr;
1608     int uncached;
1609     if ((vaddr & 1) != 0)
1610       SignalExceptionAddressLoad();
1611     else
1612       {
1613         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1614           {
1615             unsigned64 memval = 0;
1616             unsigned64 memval1 = 0;
1617             unsigned64 mask = 0x7;
1618             unsigned int shift = 1;
1619             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1620             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1621             unsigned int byte;
1622             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1623             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1624             byte = ((vaddr & mask) ^ (bigend << shift));
1625             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1626           }
1627       }
1628   }
1629 }
1630
1631
1632 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1633 "ll r<RT>, <OFFSET>(r<BASE>)"
1634 *mipsII:
1635 *mipsIII:
1636 *mipsIV:
1637 // start-sanitize-vr5400
1638 *vr5400:
1639 // end-sanitize-vr5400
1640 // start-sanitize-r5900
1641 *r5900:
1642 // end-sanitize-r5900
1643 *r3900:
1644 // start-sanitize-tx19
1645 *tx19:
1646 // end-sanitize-tx19
1647 {
1648   unsigned32 instruction = instruction_0;
1649   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1650   int destreg = ((instruction >> 16) & 0x0000001F);
1651   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1652   {
1653     address_word vaddr = ((unsigned64)op1 + offset);
1654     address_word paddr;
1655     int uncached;
1656     if ((vaddr & 3) != 0)
1657       SignalExceptionAddressLoad();
1658     else
1659       {
1660         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1661           {
1662             unsigned64 memval = 0;
1663             unsigned64 memval1 = 0;
1664             unsigned64 mask = 0x7;
1665             unsigned int shift = 2;
1666             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1667             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1668             unsigned int byte;
1669             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1670             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1671             byte = ((vaddr & mask) ^ (bigend << shift));
1672             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1673             LLBIT = 1;
1674           }
1675       }
1676   }
1677 }
1678
1679
1680 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1681 "lld r<RT>, <OFFSET>(r<BASE>)"
1682 *mipsIII:
1683 *mipsIV:
1684 // start-sanitize-vr5400
1685 *vr5400:
1686 // end-sanitize-vr5400
1687 // start-sanitize-r5900
1688 *r5900:
1689 // end-sanitize-r5900
1690 *r3900:
1691 // start-sanitize-tx19
1692 *tx19:
1693 // end-sanitize-tx19
1694 {
1695   unsigned32 instruction = instruction_0;
1696   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1697   int destreg = ((instruction >> 16) & 0x0000001F);
1698   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1699   {
1700     address_word vaddr = ((unsigned64)op1 + offset);
1701     address_word paddr;
1702     int uncached;
1703     if ((vaddr & 7) != 0)
1704       SignalExceptionAddressLoad();
1705     else
1706       {
1707         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1708           {
1709             unsigned64 memval = 0;
1710             unsigned64 memval1 = 0;
1711             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1712             GPR[destreg] = memval;
1713             LLBIT = 1;
1714           }
1715       }
1716   }
1717 }
1718
1719
1720 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1721 "lui r<RT>, <IMMEDIATE>"
1722 *mipsI:
1723 *mipsII:
1724 *mipsIII:
1725 *mipsIV:
1726 // start-sanitize-vr5400
1727 *vr5400:
1728 // end-sanitize-vr5400
1729 // start-sanitize-r5900
1730 *r5900:
1731 // end-sanitize-r5900
1732 *r3900:
1733 // start-sanitize-tx19
1734 *tx19:
1735 // end-sanitize-tx19
1736 {
1737   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1738 }
1739
1740
1741 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1742 "lw r<RT>, <OFFSET>(r<BASE>)"
1743 *mipsI:
1744 *mipsII:
1745 *mipsIII:
1746 *mipsIV:
1747 // start-sanitize-vr5400
1748 *vr5400:
1749 // end-sanitize-vr5400
1750 // start-sanitize-r5900
1751 *r5900:
1752 // end-sanitize-r5900
1753 *r3900:
1754 // start-sanitize-tx19
1755 *tx19:
1756 // end-sanitize-tx19
1757 {
1758   unsigned32 instruction = instruction_0;
1759   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760   int destreg = ((instruction >> 16) & 0x0000001F);
1761   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1762   {
1763     address_word vaddr = ((unsigned64)op1 + offset);
1764     address_word paddr;
1765     int uncached;
1766     if ((vaddr & 3) != 0)
1767       SignalExceptionAddressLoad();
1768     else
1769       {
1770         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1771           {
1772             unsigned64 memval = 0;
1773             unsigned64 memval1 = 0;
1774             unsigned64 mask = 0x7;
1775             unsigned int shift = 2;
1776             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1778             unsigned int byte;
1779             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781             byte = ((vaddr & mask) ^ (bigend << shift));
1782             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1783           }
1784       }
1785   }
1786 }
1787
1788
1789 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1790 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1791 *mipsI:
1792 *mipsII:
1793 *mipsIII:
1794 *mipsIV:
1795 // start-sanitize-vr5400
1796 *vr5400:
1797 // end-sanitize-vr5400
1798 // start-sanitize-r5900
1799 *r5900:
1800 // end-sanitize-r5900
1801 *r3900:
1802 // start-sanitize-tx19
1803 *tx19:
1804 // end-sanitize-tx19
1805 {
1806   unsigned32 instruction = instruction_0;
1807   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1808   int destreg = ((instruction >> 16) & 0x0000001F);
1809   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1810   {
1811     address_word vaddr = ((unsigned64)op1 + offset);
1812     address_word paddr;
1813     int uncached;
1814     if ((vaddr & 3) != 0)
1815       SignalExceptionAddressLoad();
1816     else
1817       {
1818         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1819           {
1820             unsigned64 memval = 0;
1821             unsigned64 memval1 = 0;
1822             unsigned64 mask = 0x7;
1823             unsigned int shift = 2;
1824             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1825             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1826             unsigned int byte;
1827             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1828             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1829             byte = ((vaddr & mask) ^ (bigend << shift));
1830             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1831           }
1832       }
1833   }
1834 }
1835
1836
1837 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1838 "lwl r<RT>, <OFFSET>(r<BASE>)"
1839 *mipsI:
1840 *mipsII:
1841 *mipsIII:
1842 *mipsIV:
1843 // start-sanitize-vr5400
1844 *vr5400:
1845 // end-sanitize-vr5400
1846 // start-sanitize-r5900
1847 *r5900:
1848 // end-sanitize-r5900
1849 *r3900:
1850 // start-sanitize-tx19
1851 *tx19:
1852 // end-sanitize-tx19
1853 {
1854   unsigned32 instruction = instruction_0;
1855   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1856   int destreg = ((instruction >> 16) & 0x0000001F);
1857   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1858   {
1859     address_word vaddr = ((unsigned64)op1 + offset);
1860     address_word paddr;
1861     int uncached;
1862     {
1863       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1864         {
1865           unsigned64 memval = 0;
1866           unsigned64 memval1 = 0;
1867           unsigned64 mask = 3;
1868           unsigned int reverse = (ReverseEndian ? mask : 0);
1869           unsigned int bigend = (BigEndianCPU ? mask : 0);
1870           int byte;
1871           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1872           byte = ((vaddr & mask) ^ bigend);
1873           if (!BigEndianMem)
1874             paddr &= ~mask;
1875           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1876           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1877             memval >>= 32;
1878           }
1879           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1880           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1881         }
1882     }
1883   }
1884 }
1885
1886
1887 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1888 "lwr r<RT>, <OFFSET>(r<BASE>)"
1889 *mipsI:
1890 *mipsII:
1891 *mipsIII:
1892 *mipsIV:
1893 // start-sanitize-vr5400
1894 *vr5400:
1895 // end-sanitize-vr5400
1896 // start-sanitize-r5900
1897 *r5900:
1898 // end-sanitize-r5900
1899 *r3900:
1900 // start-sanitize-tx19
1901 *tx19:
1902 // end-sanitize-tx19
1903 {
1904   unsigned32 instruction = instruction_0;
1905   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1906   int destreg = ((instruction >> 16) & 0x0000001F);
1907   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1908   {
1909     address_word vaddr = ((unsigned64)op1 + offset);
1910     address_word paddr;
1911     int uncached;
1912     {
1913       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1914         {
1915           unsigned64 memval = 0;
1916           unsigned64 memval1 = 0;
1917           unsigned64 mask = 3;
1918           unsigned int reverse = (ReverseEndian ? mask : 0);
1919           unsigned int bigend = (BigEndianCPU ? mask : 0);
1920           int byte;
1921           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1922           byte = ((vaddr & mask) ^ bigend);
1923           if (BigEndianMem)
1924             paddr &= ~mask;
1925           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1926           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1927             memval >>= 32;
1928           }
1929           {
1930             unsigned64 srcmask;
1931             if (byte == 0)
1932               srcmask = 0;
1933             else
1934               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1935             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1936           }
1937           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1938         }
1939     }
1940   }
1941 }
1942
1943
1944 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1945 "lwu r<RT>, <OFFSET>(r<BASE>)"
1946 *mipsIII:
1947 *mipsIV:
1948 // start-sanitize-vr5400
1949 *vr5400:
1950 // end-sanitize-vr5400
1951 // start-sanitize-r5900
1952 *r5900:
1953 // end-sanitize-r5900
1954 *r3900:
1955 // start-sanitize-tx19
1956 *tx19:
1957 // end-sanitize-tx19
1958 {
1959   unsigned32 instruction = instruction_0;
1960   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1961   int destreg = ((instruction >> 16) & 0x0000001F);
1962   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1963   {
1964     address_word vaddr = ((unsigned64)op1 + offset);
1965     address_word paddr;
1966     int uncached;
1967     if ((vaddr & 3) != 0)
1968       SignalExceptionAddressLoad();
1969     else
1970       {
1971         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1972           {
1973             unsigned64 memval = 0;
1974             unsigned64 memval1 = 0;
1975             unsigned64 mask = 0x7;
1976             unsigned int shift = 2;
1977             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1978             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1979             unsigned int byte;
1980             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1981             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1982             byte = ((vaddr & mask) ^ (bigend << shift));
1983             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1984           }
1985       }
1986   }
1987 }
1988
1989
1990 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1991 "mfhi r<RD>"
1992 *mipsI:
1993 *mipsII:
1994 *mipsIII:
1995 *mipsIV:
1996 // start-sanitize-vr5400
1997 *vr5400:
1998 // end-sanitize-vr5400
1999 // start-sanitize-r5900
2000 *r5900:
2001 // end-sanitize-r5900
2002 *r3900:
2003 // start-sanitize-tx19
2004 *tx19:
2005 // end-sanitize-tx19
2006 {
2007   GPR[RD] = HI;
2008 #if 0
2009   HIACCESS = 3;
2010 #endif
2011 }
2012
2013
2014 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2015 "mflo r<RD>"
2016 *mipsI:
2017 *mipsII:
2018 *mipsIII:
2019 *mipsIV:
2020 // start-sanitize-vr5400
2021 *vr5400:
2022 // end-sanitize-vr5400
2023 // start-sanitize-r5900
2024 *r5900:
2025 // end-sanitize-r5900
2026 *r3900:
2027 // start-sanitize-tx19
2028 *tx19:
2029 // end-sanitize-tx19
2030 {
2031   GPR[RD] = LO;
2032 #if 0
2033   LOACCESS = 3; /* 3rd instruction will be safe */
2034 #endif
2035 }
2036
2037
2038 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2039 "movn r<RD>, r<RS>, r<RT>"
2040 *mipsIV:
2041 // start-sanitize-vr5400
2042 *vr5400:
2043 // end-sanitize-vr5400
2044 // start-sanitize-r5900
2045 *r5900:
2046 // end-sanitize-r5900
2047 {
2048   if (GPR[RT] != 0)
2049     GPR[RD] = GPR[RS];
2050 }
2051
2052
2053 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2054 "movz r<RD>, r<RS>, r<RT>"
2055 *mipsIV:
2056 // start-sanitize-vr5400
2057 *vr5400:
2058 // end-sanitize-vr5400
2059 // start-sanitize-r5900
2060 *r5900:
2061 // end-sanitize-r5900
2062 {
2063   if (GPR[RT] == 0)
2064     GPR[RD] = GPR[RS];
2065 }
2066
2067
2068 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2069 "mthi r<RS>"
2070 *mipsI:
2071 *mipsII:
2072 *mipsIII:
2073 *mipsIV:
2074 // start-sanitize-vr5400
2075 *vr5400:
2076 // end-sanitize-vr5400
2077 // start-sanitize-r5900
2078 *r5900:
2079 // end-sanitize-r5900
2080 *r3900:
2081 // start-sanitize-tx19
2082 *tx19:
2083 // end-sanitize-tx19
2084 {
2085 #if 0
2086   if (HIACCESS != 0)
2087     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2088 #endif
2089   HI = GPR[RS];
2090 #if 0
2091   HIACCESS = 3; /* 3rd instruction will be safe */
2092 #endif
2093 }
2094
2095
2096 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2097 "mtlo r<RS>"
2098 *mipsI:
2099 *mipsII:
2100 *mipsIII:
2101 *mipsIV:
2102 // start-sanitize-vr5400
2103 *vr5400:
2104 // end-sanitize-vr5400
2105 // start-sanitize-r5900
2106 *r5900:
2107 // end-sanitize-r5900
2108 *r3900:
2109 // start-sanitize-tx19
2110 *tx19:
2111 // end-sanitize-tx19
2112 {
2113 #if 0
2114   if (LOACCESS != 0)
2115     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2116 #endif
2117   LO = GPR[RS];
2118 #if 0
2119   LOACCESS = 3; /* 3rd instruction will be safe */
2120 #endif
2121 }
2122
2123
2124 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2125 "mult r<RS>, r<RT>"
2126 *mipsI:
2127 *mipsII:
2128 *mipsIII:
2129 *mipsIV:
2130 {
2131   signed64 prod;
2132   CHECKHILO ("Multiplication");
2133   prod = (((signed64)(signed32) GPR[RS])
2134           * ((signed64)(signed32) GPR[RT]));
2135   LO = EXTEND32 (VL4_8 (prod));
2136   HI = EXTEND32 (VH4_8 (prod));
2137 }
2138 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2139 "mult r<RD>, r<RS>, r<RT>"
2140 // start-sanitize-vr5400
2141 *vr5400:
2142 // end-sanitize-vr5400
2143 // start-sanitize-r5900
2144 *r5900:
2145 // end-sanitize-r5900
2146 *r3900:
2147 // start-sanitize-tx19
2148 *tx19:
2149 // end-sanitize-tx19
2150 {
2151   signed64 prod;
2152   CHECKHILO ("Multiplication");
2153   prod = (((signed64)(signed32) GPR[RS])
2154           * ((signed64)(signed32) GPR[RT]));
2155   LO = EXTEND32 (VL4_8 (prod));
2156   HI = EXTEND32 (VH4_8 (prod));
2157   if (RD != 0)
2158     GPR[RD] = LO;
2159 }
2160
2161
2162 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2163 "multu r<RS>, r<RT>"
2164 *mipsI:
2165 *mipsII:
2166 *mipsIII:
2167 *mipsIV:
2168 {
2169   unsigned64 prod;
2170   CHECKHILO ("Multiplication");
2171   prod = (((unsigned64)(unsigned32) GPR[RS])
2172           * ((unsigned64)(unsigned32) GPR[RT]));
2173   LO = EXTEND32 (VL4_8 (prod));
2174   HI = EXTEND32 (VH4_8 (prod));
2175 }
2176 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2177 "multu r<RD>, r<RS>, r<RT>"
2178 // start-sanitize-vr5400
2179 *vr5400:
2180 // end-sanitize-vr5400
2181 // start-sanitize-r5900
2182 *r5900:
2183 // end-sanitize-r5900
2184 *r3900:
2185 // start-sanitize-tx19
2186 *tx19:
2187 // end-sanitize-tx19
2188 {
2189   unsigned64 prod;
2190   CHECKHILO ("Multiplication");
2191   prod = (((unsigned64)(unsigned32) GPR[RS])
2192           * ((unsigned64)(unsigned32) GPR[RT]));
2193   LO = EXTEND32 (VL4_8 (prod));
2194   HI = EXTEND32 (VH4_8 (prod));
2195   if (RD != 0)
2196     GPR[RD] = LO;
2197 }
2198
2199
2200 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2201 "nor r<RD>, r<RS>, r<RT>"
2202 *mipsI:
2203 *mipsII:
2204 *mipsIII:
2205 *mipsIV:
2206 // start-sanitize-vr5400
2207 *vr5400:
2208 // end-sanitize-vr5400
2209 // start-sanitize-r5900
2210 *r5900:
2211 // end-sanitize-r5900
2212 *r3900:
2213 // start-sanitize-tx19
2214 *tx19:
2215 // end-sanitize-tx19
2216 {
2217   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2218 }
2219
2220
2221 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2222 "or r<RD>, r<RS>, r<RT>"
2223 *mipsI:
2224 *mipsII:
2225 *mipsIII:
2226 *mipsIV:
2227 // start-sanitize-vr5400
2228 *vr5400:
2229 // end-sanitize-vr5400
2230 // start-sanitize-r5900
2231 *r5900:
2232 // end-sanitize-r5900
2233 *r3900:
2234 // start-sanitize-tx19
2235 *tx19:
2236 // end-sanitize-tx19
2237 {
2238   GPR[RD] = (GPR[RS] | GPR[RT]);
2239 }
2240
2241
2242 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2243 "ori r<RT>, r<RS>, <IMMEDIATE>"
2244 *mipsI:
2245 *mipsII:
2246 *mipsIII:
2247 *mipsIV:
2248 // start-sanitize-vr5400
2249 *vr5400:
2250 // end-sanitize-vr5400
2251 // start-sanitize-r5900
2252 *r5900:
2253 // end-sanitize-r5900
2254 *r3900:
2255 // start-sanitize-tx19
2256 *tx19:
2257 // end-sanitize-tx19
2258 {
2259   GPR[RT] = (GPR[RS] | IMMEDIATE);
2260 }
2261
2262
2263 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2264 *mipsIV:
2265 // start-sanitize-vr5400
2266 *vr5400:
2267 // end-sanitize-vr5400
2268 // start-sanitize-r5900
2269 *r5900:
2270 // end-sanitize-r5900
2271 {
2272   unsigned32 instruction = instruction_0;
2273   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2274   int hint = ((instruction >> 16) & 0x0000001F);
2275   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2276   {
2277     address_word vaddr = ((unsigned64)op1 + offset);
2278     address_word paddr;
2279     int uncached;
2280     {
2281       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2282         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2283     }
2284   }
2285 }
2286
2287 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2288 "sb r<RT>, <OFFSET>(r<BASE>)"
2289 *mipsI:
2290 *mipsII:
2291 *mipsIII:
2292 *mipsIV:
2293 // start-sanitize-vr5400
2294 *vr5400:
2295 // end-sanitize-vr5400
2296 // start-sanitize-r5900
2297 *r5900:
2298 // end-sanitize-r5900
2299 *r3900:
2300 // start-sanitize-tx19
2301 *tx19:
2302 // end-sanitize-tx19
2303 {
2304   unsigned32 instruction = instruction_0;
2305   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2306   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2307   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2308   {
2309     address_word vaddr = ((unsigned64)op1 + offset);
2310     address_word paddr;
2311     int uncached;
2312     {
2313       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2314         {
2315           unsigned64 memval = 0;
2316           unsigned64 memval1 = 0;
2317           unsigned64 mask = 0x7;
2318           unsigned int shift = 0;
2319           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2320           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2321           unsigned int byte;
2322           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2323           byte = ((vaddr & mask) ^ (bigend << shift));
2324           memval = ((unsigned64) op2 << (8 * byte));
2325           {
2326             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2327           }
2328         }
2329     }
2330   }
2331 }
2332
2333
2334 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2335 "sc r<RT>, <OFFSET>(r<BASE>)"
2336 *mipsII:
2337 *mipsIII:
2338 *mipsIV:
2339 // start-sanitize-vr5400
2340 *vr5400:
2341 // end-sanitize-vr5400
2342 // start-sanitize-r5900
2343 *r5900:
2344 // end-sanitize-r5900
2345 *r3900:
2346 // start-sanitize-tx19
2347 *tx19:
2348 // end-sanitize-tx19
2349 {
2350   unsigned32 instruction = instruction_0;
2351   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2352   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2353   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2354   {
2355     address_word vaddr = ((unsigned64)op1 + offset);
2356     address_word paddr;
2357     int uncached;
2358     if ((vaddr & 3) != 0)
2359       SignalExceptionAddressStore();
2360     else
2361       {
2362         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2363           {
2364             unsigned64 memval = 0;
2365             unsigned64 memval1 = 0;
2366             unsigned64 mask = 0x7;
2367             unsigned int byte;
2368             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2369             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2370             memval = ((unsigned64) op2 << (8 * byte));
2371             if (LLBIT)
2372               {
2373                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2374               }
2375             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2376           }
2377       }
2378   }
2379 }
2380
2381
2382 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2383 "scd r<RT>, <OFFSET>(r<BASE>)"
2384 *mipsIII:
2385 *mipsIV:
2386 // start-sanitize-vr5400
2387 *vr5400:
2388 // end-sanitize-vr5400
2389 // start-sanitize-r5900
2390 *r5900:
2391 // end-sanitize-r5900
2392 *r3900:
2393 // start-sanitize-tx19
2394 *tx19:
2395 // end-sanitize-tx19
2396 {
2397   unsigned32 instruction = instruction_0;
2398   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2399   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2400   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2401   {
2402     address_word vaddr = ((unsigned64)op1 + offset);
2403     address_word paddr;
2404     int uncached;
2405     if ((vaddr & 7) != 0)
2406       SignalExceptionAddressStore();
2407     else
2408       {
2409         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2410           {
2411             unsigned64 memval = 0;
2412             unsigned64 memval1 = 0;
2413             memval = op2;
2414             if (LLBIT)
2415               {
2416                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2417               }
2418             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2419           }
2420       }
2421   }
2422 }
2423
2424
2425 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2426 "sd r<RT>, <OFFSET>(r<BASE>)"
2427 *mipsIII:
2428 *mipsIV:
2429 // start-sanitize-vr5400
2430 *vr5400:
2431 // end-sanitize-vr5400
2432 // start-sanitize-r5900
2433 *r5900:
2434 // end-sanitize-r5900
2435 *r3900:
2436 // start-sanitize-tx19
2437 *tx19:
2438 // end-sanitize-tx19
2439 {
2440   unsigned32 instruction = instruction_0;
2441   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2442   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2443   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2444   {
2445     address_word vaddr = ((unsigned64)op1 + offset);
2446     address_word paddr;
2447     int uncached;
2448     if ((vaddr & 7) != 0)
2449       SignalExceptionAddressStore();
2450     else
2451       {
2452         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2453           {
2454             unsigned64 memval = 0;
2455             unsigned64 memval1 = 0;
2456             memval = op2;
2457             {
2458               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2459             }
2460           }
2461       }
2462   }
2463 }
2464
2465
2466 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2467 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2468 *mipsII:
2469 *mipsIII:
2470 *mipsIV:
2471 // start-sanitize-vr5400
2472 *vr5400:
2473 // end-sanitize-vr5400
2474 // start-sanitize-r5900
2475 *r5900:
2476 // end-sanitize-r5900
2477 *r3900:
2478 // start-sanitize-tx19
2479 *tx19:
2480 // end-sanitize-tx19
2481 {
2482   unsigned32 instruction = instruction_0;
2483   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2484   int destreg = ((instruction >> 16) & 0x0000001F);
2485   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2486   {
2487     address_word vaddr = ((unsigned64)op1 + offset);
2488     address_word paddr;
2489     int uncached;
2490     if ((vaddr & 7) != 0)
2491       SignalExceptionAddressStore();
2492     else
2493       {
2494         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2495           {
2496             unsigned64 memval = 0;
2497             unsigned64 memval1 = 0;
2498             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2499             {
2500               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2501             }
2502           }
2503       }
2504   }
2505 }
2506
2507
2508 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2509 "sdl r<RT>, <OFFSET>(r<BASE>)"
2510 *mipsIII:
2511 *mipsIV:
2512 // start-sanitize-vr5400
2513 *vr5400:
2514 // end-sanitize-vr5400
2515 // start-sanitize-r5900
2516 *r5900:
2517 // end-sanitize-r5900
2518 *r3900:
2519 // start-sanitize-tx19
2520 *tx19:
2521 // end-sanitize-tx19
2522 {
2523   unsigned32 instruction = instruction_0;
2524   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2525   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2526   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2527   {
2528     address_word vaddr = ((unsigned64)op1 + offset);
2529     address_word paddr;
2530     int uncached;
2531     {
2532       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2533         {
2534           unsigned64 memval = 0;
2535           unsigned64 memval1 = 0;
2536           unsigned64 mask = 7;
2537           unsigned int reverse = (ReverseEndian ? mask : 0);
2538           unsigned int bigend = (BigEndianCPU ? mask : 0);
2539           int byte;
2540           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2541           byte = ((vaddr & mask) ^ bigend);
2542           if (!BigEndianMem)
2543             paddr &= ~mask;
2544           memval = (op2 >> (8 * (7 - byte)));
2545           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2546         }
2547     }
2548   }
2549 }
2550
2551
2552 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2553 "sdr r<RT>, <OFFSET>(r<BASE>)"
2554 *mipsIII:
2555 *mipsIV:
2556 // start-sanitize-vr5400
2557 *vr5400:
2558 // end-sanitize-vr5400
2559 // start-sanitize-r5900
2560 *r5900:
2561 // end-sanitize-r5900
2562 *r3900:
2563 // start-sanitize-tx19
2564 *tx19:
2565 // end-sanitize-tx19
2566 {
2567   unsigned32 instruction = instruction_0;
2568   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2569   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2570   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2571   {
2572     address_word vaddr = ((unsigned64)op1 + offset);
2573     address_word paddr;
2574     int uncached;
2575     {
2576       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2577         {
2578           unsigned64 memval = 0;
2579           unsigned64 memval1 = 0;
2580           unsigned64 mask = 7;
2581           unsigned int reverse = (ReverseEndian ? mask : 0);
2582           unsigned int bigend = (BigEndianCPU ? mask : 0);
2583           int byte;
2584           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2585           byte = ((vaddr & mask) ^ bigend);
2586           if (!BigEndianMem)
2587             paddr &= ~mask;
2588           memval = ((unsigned64) op2 << (byte * 8));
2589           StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2590         }
2591     }
2592   }
2593 }
2594
2595
2596 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2597 "sh r<RT>, <OFFSET>(r<BASE>)"
2598 *mipsI:
2599 *mipsII:
2600 *mipsIII:
2601 *mipsIV:
2602 // start-sanitize-vr5400
2603 *vr5400:
2604 // end-sanitize-vr5400
2605 // start-sanitize-r5900
2606 *r5900:
2607 // end-sanitize-r5900
2608 *r3900:
2609 // start-sanitize-tx19
2610 *tx19:
2611 // end-sanitize-tx19
2612 {
2613   unsigned32 instruction = instruction_0;
2614   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2615   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2616   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2617   {
2618     address_word vaddr = ((unsigned64)op1 + offset);
2619     address_word paddr;
2620     int uncached;
2621     if ((vaddr & 1) != 0)
2622       SignalExceptionAddressStore();
2623     else
2624       {
2625         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2626           {
2627             unsigned64 memval = 0;
2628             unsigned64 memval1 = 0;
2629             unsigned64 mask = 0x7;
2630             unsigned int shift = 1;
2631             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2632             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2633             unsigned int byte;
2634             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2635             byte = ((vaddr & mask) ^ (bigend << shift));
2636             memval = ((unsigned64) op2 << (8 * byte));
2637             {
2638               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2639             }
2640           }
2641       }
2642   }
2643 }
2644
2645
2646 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2647 "sll r<RD>, r<RT>, <SHIFT>"
2648 *mipsI:
2649 *mipsII:
2650 *mipsIII:
2651 *mipsIV:
2652 // start-sanitize-vr5400
2653 *vr5400:
2654 // end-sanitize-vr5400
2655 // start-sanitize-r5900
2656 *r5900:
2657 // end-sanitize-r5900
2658 *r3900:
2659 // start-sanitize-tx19
2660 *tx19:
2661 // end-sanitize-tx19
2662 {
2663   int s = SHIFT;
2664   unsigned32 temp = (GPR[RT] << s);
2665   GPR[RD] = EXTEND32 (temp);
2666 }
2667
2668
2669 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2670 "sllv r<RD>, r<RT>, r<RS>"
2671 *mipsI:
2672 *mipsII:
2673 *mipsIII:
2674 *mipsIV:
2675 // start-sanitize-vr5400
2676 *vr5400:
2677 // end-sanitize-vr5400
2678 // start-sanitize-r5900
2679 *r5900:
2680 // end-sanitize-r5900
2681 *r3900:
2682 // start-sanitize-tx19
2683 *tx19:
2684 // end-sanitize-tx19
2685 {
2686   int s = MASKED (GPR[RS], 4, 0);
2687   unsigned32 temp = (GPR[RT] << s);
2688   GPR[RD] = EXTEND32 (temp);
2689 }
2690
2691
2692 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2693 "slt r<RD>, r<RS>, r<RT>"
2694 *mipsI:
2695 *mipsII:
2696 *mipsIII:
2697 *mipsIV:
2698 // start-sanitize-vr5400
2699 *vr5400:
2700 // end-sanitize-vr5400
2701 // start-sanitize-r5900
2702 *r5900:
2703 // end-sanitize-r5900
2704 *r3900:
2705 // start-sanitize-tx19
2706 *tx19:
2707 // end-sanitize-tx19
2708 {
2709   GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
2710 }
2711
2712
2713 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2714 "slti r<RT>, r<RS>, <IMMEDIATE>"
2715 *mipsI:
2716 *mipsII:
2717 *mipsIII:
2718 *mipsIV:
2719 // start-sanitize-vr5400
2720 *vr5400:
2721 // end-sanitize-vr5400
2722 // start-sanitize-r5900
2723 *r5900:
2724 // end-sanitize-r5900
2725 *r3900:
2726 // start-sanitize-tx19
2727 *tx19:
2728 // end-sanitize-tx19
2729 {
2730   GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
2731 }
2732
2733
2734 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2735 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2736 *mipsI:
2737 *mipsII:
2738 *mipsIII:
2739 *mipsIV:
2740 // start-sanitize-vr5400
2741 *vr5400:
2742 // end-sanitize-vr5400
2743 // start-sanitize-r5900
2744 *r5900:
2745 // end-sanitize-r5900
2746 *r3900:
2747 // start-sanitize-tx19
2748 *tx19:
2749 // end-sanitize-tx19
2750 {
2751   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2752 }
2753
2754 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2755 "sltu r<RD>, r<RS>, r<RT>"
2756 *mipsI:
2757 *mipsII:
2758 *mipsIII:
2759 *mipsIV:
2760 // start-sanitize-vr5400
2761 *vr5400:
2762 // end-sanitize-vr5400
2763 // start-sanitize-r5900
2764 *r5900:
2765 // end-sanitize-r5900
2766 *r3900:
2767 // start-sanitize-tx19
2768 *tx19:
2769 // end-sanitize-tx19
2770 {
2771   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2772 }
2773
2774
2775 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2776 "sra r<RD>, r<RT>, <SHIFT>"
2777 *mipsI:
2778 *mipsII:
2779 *mipsIII:
2780 *mipsIV:
2781 // start-sanitize-vr5400
2782 *vr5400:
2783 // end-sanitize-vr5400
2784 // start-sanitize-r5900
2785 *r5900:
2786 // end-sanitize-r5900
2787 *r3900:
2788 // start-sanitize-tx19
2789 *tx19:
2790 // end-sanitize-tx19
2791 {
2792   int s = SHIFT;
2793   signed32 temp = (signed32) GPR[RT] >> s;
2794   GPR[RD] = EXTEND32 (temp);
2795 }
2796
2797
2798 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2799 "srav r<RD>, r<RT>, r<RS>"
2800 *mipsI:
2801 *mipsII:
2802 *mipsIII:
2803 *mipsIV:
2804 // start-sanitize-vr5400
2805 *vr5400:
2806 // end-sanitize-vr5400
2807 // start-sanitize-r5900
2808 *r5900:
2809 // end-sanitize-r5900
2810 *r3900:
2811 // start-sanitize-tx19
2812 *tx19:
2813 // end-sanitize-tx19
2814 {
2815   int s = MASKED (GPR[RS], 4, 0);
2816   signed32 temp = (signed32) GPR[RT] >> s;
2817   GPR[RD] = EXTEND32 (temp);
2818 }
2819
2820
2821 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2822 "srl r<RD>, r<RT>, <SHIFT>"
2823 *mipsI:
2824 *mipsII:
2825 *mipsIII:
2826 *mipsIV:
2827 // start-sanitize-vr5400
2828 *vr5400:
2829 // end-sanitize-vr5400
2830 // start-sanitize-r5900
2831 *r5900:
2832 // end-sanitize-r5900
2833 *r3900:
2834 // start-sanitize-tx19
2835 *tx19:
2836 // end-sanitize-tx19
2837 {
2838   int s = SHIFT;
2839   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2840   GPR[RD] = EXTEND32 (temp);
2841 }
2842
2843
2844 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2845 "srlv r<RD>, r<RT>, r<RS>"
2846 *mipsI:
2847 *mipsII:
2848 *mipsIII:
2849 *mipsIV:
2850 // start-sanitize-vr5400
2851 *vr5400:
2852 // end-sanitize-vr5400
2853 // start-sanitize-r5900
2854 *r5900:
2855 // end-sanitize-r5900
2856 *r3900:
2857 // start-sanitize-tx19
2858 *tx19:
2859 // end-sanitize-tx19
2860 {
2861   int s = MASKED (GPR[RS], 4, 0);
2862   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2863   GPR[RD] = EXTEND32 (temp);
2864 }
2865
2866
2867 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2868 "sub r<RD>, r<RS>, r<RT>"
2869 *mipsI:
2870 *mipsII:
2871 *mipsIII:
2872 *mipsIV:
2873 // start-sanitize-vr5400
2874 *vr5400:
2875 // end-sanitize-vr5400
2876 // start-sanitize-r5900
2877 *r5900:
2878 // end-sanitize-r5900
2879 *r3900:
2880 // start-sanitize-tx19
2881 *tx19:
2882 // end-sanitize-tx19
2883 {
2884   ALU32_BEGIN (GPR[RS]);
2885   ALU32_SUB (GPR[RT]);
2886   ALU32_END (GPR[RD]);
2887 }
2888
2889
2890 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2891 "subu r<RD>, r<RS>, r<RT>"
2892 *mipsI:
2893 *mipsII:
2894 *mipsIII:
2895 *mipsIV:
2896 // start-sanitize-vr5400
2897 *vr5400:
2898 // end-sanitize-vr5400
2899 // start-sanitize-r5900
2900 *r5900:
2901 // end-sanitize-r5900
2902 *r3900:
2903 // start-sanitize-tx19
2904 *tx19:
2905 // end-sanitize-tx19
2906 {
2907   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2908 }
2909
2910
2911 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2912 "sw r<RT>, <OFFSET>(r<BASE>)"
2913 *mipsI:
2914 *mipsII:
2915 *mipsIII:
2916 *mipsIV:
2917 // start-sanitize-vr5400
2918 *vr5400:
2919 // end-sanitize-vr5400
2920 // start-sanitize-r5900
2921 *r5900:
2922 // end-sanitize-r5900
2923 *r3900:
2924 // start-sanitize-tx19
2925 *tx19:
2926 // end-sanitize-tx19
2927 {
2928   unsigned32 instruction = instruction_0;
2929   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2930   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2931   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2932   {
2933     address_word vaddr = ((unsigned64)op1 + offset);
2934     address_word paddr;
2935     int uncached;
2936     if ((vaddr & 3) != 0)
2937       SignalExceptionAddressStore();
2938     else
2939       {
2940         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2941           {
2942             unsigned64 memval = 0;
2943             unsigned64 memval1 = 0;
2944             unsigned64 mask = 0x7;
2945             unsigned int byte;
2946             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2947             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2948             memval = ((unsigned64) op2 << (8 * byte));
2949             {
2950               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2951             }
2952           }
2953       }
2954   }
2955 }
2956
2957
2958 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2959 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2960 *mipsI:
2961 *mipsII:
2962 *mipsIII:
2963 *mipsIV:
2964 // start-sanitize-vr5400
2965 *vr5400:
2966 // end-sanitize-vr5400
2967 // start-sanitize-r5900
2968 *r5900:
2969 // end-sanitize-r5900
2970 *r3900:
2971 // start-sanitize-tx19
2972 *tx19:
2973 // end-sanitize-tx19
2974 {
2975   unsigned32 instruction = instruction_0;
2976   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2977   int destreg = ((instruction >> 16) & 0x0000001F);
2978   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2979   {
2980     address_word vaddr = ((unsigned64)op1 + offset);
2981     address_word paddr;
2982     int uncached;
2983     if ((vaddr & 3) != 0)
2984       SignalExceptionAddressStore();
2985     else
2986       {
2987         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2988           {
2989             unsigned64 memval = 0;
2990             unsigned64 memval1 = 0;
2991             unsigned64 mask = 0x7;
2992             unsigned int byte;
2993             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2994             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2995             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2996             {
2997               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2998             }
2999           }
3000       }
3001   }
3002 }
3003
3004
3005 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3006 "swl r<RT>, <OFFSET>(r<BASE>)"
3007 *mipsI:
3008 *mipsII:
3009 *mipsIII:
3010 *mipsIV:
3011 // start-sanitize-vr5400
3012 *vr5400:
3013 // end-sanitize-vr5400
3014 // start-sanitize-r5900
3015 *r5900:
3016 // end-sanitize-r5900
3017 *r3900:
3018 // start-sanitize-tx19
3019 *tx19:
3020 // end-sanitize-tx19
3021 {
3022   unsigned32 instruction = instruction_0;
3023   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3024   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3025   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3026   {
3027     address_word vaddr = ((unsigned64)op1 + offset);
3028     address_word paddr;
3029     int uncached;
3030     {
3031       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3032         {
3033           unsigned64 memval = 0;
3034           unsigned64 memval1 = 0;
3035           unsigned64 mask = 3;
3036           unsigned int reverse = (ReverseEndian ? mask : 0);
3037           unsigned int bigend = (BigEndianCPU ? mask : 0);
3038           int byte;
3039           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3040           byte = ((vaddr & mask) ^ bigend);
3041           if (!BigEndianMem)
3042             paddr &= ~mask;
3043           memval = (op2 >> (8 * (3 - byte)));
3044           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3045             memval <<= 32;
3046           }
3047           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3048         }
3049     }
3050   }
3051 }
3052
3053
3054 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3055 "swr r<RT>, <OFFSET>(r<BASE>)"
3056 *mipsI:
3057 *mipsII:
3058 *mipsIII:
3059 *mipsIV:
3060 // start-sanitize-vr5400
3061 *vr5400:
3062 // end-sanitize-vr5400
3063 // start-sanitize-r5900
3064 *r5900:
3065 // end-sanitize-r5900
3066 *r3900:
3067 // start-sanitize-tx19
3068 *tx19:
3069 // end-sanitize-tx19
3070 {
3071   unsigned32 instruction = instruction_0;
3072   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3073   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3074   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3075   {
3076     address_word vaddr = ((unsigned64)op1 + offset);
3077     address_word paddr;
3078     int uncached;
3079     {
3080       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3081         {
3082           unsigned64 memval = 0;
3083           unsigned64 memval1 = 0;
3084           unsigned64 mask = 3;
3085           unsigned int reverse = (ReverseEndian ? mask : 0);
3086           unsigned int bigend = (BigEndianCPU ? mask : 0);
3087           int byte;
3088           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3089           byte = ((vaddr & mask) ^ bigend);
3090           if (!BigEndianMem)
3091             paddr &= ~mask;
3092           memval = ((unsigned64) op2 << (byte * 8));
3093           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3094             memval <<= 32;
3095           }
3096           StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
3097         }
3098     }
3099   }
3100 }
3101
3102
3103 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3104 "sync":STYPE == 0
3105 "sync <STYPE>"
3106 *mipsII:
3107 *mipsIII:
3108 *mipsIV:
3109 // start-sanitize-vr5400
3110 *vr5400:
3111 // end-sanitize-vr5400
3112 // start-sanitize-r5900
3113 *r5900:
3114 // end-sanitize-r5900
3115 *r3900:
3116 // start-sanitize-tx19
3117 *tx19:
3118 // end-sanitize-tx19
3119 {
3120   SyncOperation (STYPE);
3121 }
3122
3123
3124 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3125 "syscall <CODE>"
3126 *mipsI:
3127 *mipsII:
3128 *mipsIII:
3129 *mipsIV:
3130 // start-sanitize-vr5400
3131 *vr5400:
3132 // end-sanitize-vr5400
3133 // start-sanitize-r5900
3134 *r5900:
3135 // end-sanitize-r5900
3136 *r3900:
3137 // start-sanitize-tx19
3138 *tx19:
3139 // end-sanitize-tx19
3140 {
3141   SignalException(SystemCall, instruction_0);
3142 }
3143
3144
3145 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3146 "teq r<RS>, r<RT>"
3147 *mipsII:
3148 *mipsIII:
3149 *mipsIV:
3150 // start-sanitize-vr5400
3151 *vr5400:
3152 // end-sanitize-vr5400
3153 // start-sanitize-r5900
3154 *r5900:
3155 // end-sanitize-r5900
3156 *r3900:
3157 // start-sanitize-tx19
3158 *tx19:
3159 // end-sanitize-tx19
3160 {
3161   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3162     SignalException(Trap, instruction_0);
3163 }
3164
3165
3166 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3167 "teqi r<RS>, <IMMEDIATE>"
3168 *mipsII:
3169 *mipsIII:
3170 *mipsIV:
3171 // start-sanitize-vr5400
3172 *vr5400:
3173 // end-sanitize-vr5400
3174 // start-sanitize-r5900
3175 *r5900:
3176 // end-sanitize-r5900
3177 *r3900:
3178 // start-sanitize-tx19
3179 *tx19:
3180 // end-sanitize-tx19
3181 {
3182   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3183     SignalException(Trap, instruction_0);
3184 }
3185
3186
3187 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3188 "tge r<RS>, r<RT>"
3189 *mipsII:
3190 *mipsIII:
3191 *mipsIV:
3192 // start-sanitize-vr5400
3193 *vr5400:
3194 // end-sanitize-vr5400
3195 // start-sanitize-r5900
3196 *r5900:
3197 // end-sanitize-r5900
3198 *r3900:
3199 // start-sanitize-tx19
3200 *tx19:
3201 // end-sanitize-tx19
3202 {
3203   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3204     SignalException(Trap, instruction_0);
3205 }
3206
3207
3208 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3209 "tgei r<RS>, <IMMEDIATE>"
3210 *mipsII:
3211 *mipsIII:
3212 *mipsIV:
3213 // start-sanitize-vr5400
3214 *vr5400:
3215 // end-sanitize-vr5400
3216 // start-sanitize-r5900
3217 *r5900:
3218 // end-sanitize-r5900
3219 *r3900:
3220 // start-sanitize-tx19
3221 *tx19:
3222 // end-sanitize-tx19
3223 {
3224   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3225     SignalException(Trap, instruction_0);
3226 }
3227
3228
3229 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3230 "tgeiu r<RS>, <IMMEDIATE>"
3231 *mipsII:
3232 *mipsIII:
3233 *mipsIV:
3234 // start-sanitize-vr5400
3235 *vr5400:
3236 // end-sanitize-vr5400
3237 // start-sanitize-r5900
3238 *r5900:
3239 // end-sanitize-r5900
3240 *r3900:
3241 // start-sanitize-tx19
3242 *tx19:
3243 // end-sanitize-tx19
3244 {
3245   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3246     SignalException(Trap, instruction_0);
3247 }
3248
3249
3250 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3251 "tgeu r<RS>, r<RT>"
3252 *mipsII:
3253 *mipsIII:
3254 *mipsIV:
3255 // start-sanitize-vr5400
3256 *vr5400:
3257 // end-sanitize-vr5400
3258 // start-sanitize-r5900
3259 *r5900:
3260 // end-sanitize-r5900
3261 *r3900:
3262 // start-sanitize-tx19
3263 *tx19:
3264 // end-sanitize-tx19
3265 {
3266   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3267     SignalException(Trap, instruction_0);
3268 }
3269
3270
3271 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3272 "tlt r<RS>, r<RT>"
3273 *mipsII:
3274 *mipsIII:
3275 *mipsIV:
3276 // start-sanitize-vr5400
3277 *vr5400:
3278 // end-sanitize-vr5400
3279 // start-sanitize-r5900
3280 *r5900:
3281 // end-sanitize-r5900
3282 *r3900:
3283 // start-sanitize-tx19
3284 *tx19:
3285 // end-sanitize-tx19
3286 {
3287   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3288     SignalException(Trap, instruction_0);
3289 }
3290
3291
3292 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3293 "tlti r<RS>, <IMMEDIATE>"
3294 *mipsII:
3295 *mipsIII:
3296 *mipsIV:
3297 // start-sanitize-vr5400
3298 *vr5400:
3299 // end-sanitize-vr5400
3300 // start-sanitize-r5900
3301 *r5900:
3302 // end-sanitize-r5900
3303 *r3900:
3304 // start-sanitize-tx19
3305 *tx19:
3306 // end-sanitize-tx19
3307 {
3308   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3309     SignalException(Trap, instruction_0);
3310 }
3311
3312
3313 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3314 "tltiu r<RS>, <IMMEDIATE>"
3315 *mipsII:
3316 *mipsIII:
3317 *mipsIV:
3318 // start-sanitize-vr5400
3319 *vr5400:
3320 // end-sanitize-vr5400
3321 // start-sanitize-r5900
3322 *r5900:
3323 // end-sanitize-r5900
3324 *r3900:
3325 // start-sanitize-tx19
3326 *tx19:
3327 // end-sanitize-tx19
3328 {
3329   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3330     SignalException(Trap, instruction_0);
3331 }
3332
3333
3334 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3335 "tltu r<RS>, r<RT>"
3336 *mipsII:
3337 *mipsIII:
3338 *mipsIV:
3339 // start-sanitize-vr5400
3340 *vr5400:
3341 // end-sanitize-vr5400
3342 // start-sanitize-r5900
3343 *r5900:
3344 // end-sanitize-r5900
3345 *r3900:
3346 // start-sanitize-tx19
3347 *tx19:
3348 // end-sanitize-tx19
3349 {
3350   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3351     SignalException(Trap, instruction_0);
3352 }
3353
3354
3355 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3356 "tne r<RS>, r<RT>"
3357 *mipsII:
3358 *mipsIII:
3359 *mipsIV:
3360 // start-sanitize-vr5400
3361 *vr5400:
3362 // end-sanitize-vr5400
3363 // start-sanitize-r5900
3364 *r5900:
3365 // end-sanitize-r5900
3366 *r3900:
3367 // start-sanitize-tx19
3368 *tx19:
3369 // end-sanitize-tx19
3370 {
3371   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3372     SignalException(Trap, instruction_0);
3373 }
3374
3375
3376 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3377 "tne r<RS>, <IMMEDIATE>"
3378 *mipsII:
3379 *mipsIII:
3380 *mipsIV:
3381 // start-sanitize-vr5400
3382 *vr5400:
3383 // end-sanitize-vr5400
3384 // start-sanitize-r5900
3385 *r5900:
3386 // end-sanitize-r5900
3387 *r3900:
3388 // start-sanitize-tx19
3389 *tx19:
3390 // end-sanitize-tx19
3391 {
3392   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3393     SignalException(Trap, instruction_0);
3394 }
3395
3396
3397 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3398 "xor r<RD>, r<RS>, r<RT>"
3399 *mipsI:
3400 *mipsII:
3401 *mipsIII:
3402 *mipsIV:
3403 // start-sanitize-vr5400
3404 *vr5400:
3405 // end-sanitize-vr5400
3406 // start-sanitize-r5900
3407 *r5900:
3408 // end-sanitize-r5900
3409 *r3900:
3410 // start-sanitize-tx19
3411 *tx19:
3412 // end-sanitize-tx19
3413 {
3414   GPR[RD] = GPR[RS] ^ GPR[RT];
3415 }
3416
3417
3418 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3419 "xori r<RT>, r<RS>, <IMMEDIATE>"
3420 *mipsI:
3421 *mipsII:
3422 *mipsIII:
3423 *mipsIV:
3424 // start-sanitize-vr5400
3425 *vr5400:
3426 // end-sanitize-vr5400
3427 // start-sanitize-r5900
3428 *r5900:
3429 // end-sanitize-r5900
3430 *r3900:
3431 // start-sanitize-tx19
3432 *tx19:
3433 // end-sanitize-tx19
3434 {
3435   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3436 }
3437
3438 \f
3439 //
3440 // MIPS Architecture:
3441 //
3442 //        FPU Instruction Set (COP1 & COP1X)
3443 //
3444
3445
3446 :%s::::FMT:int fmt
3447 {
3448   switch (fmt)
3449     {
3450     case fmt_single: return "s";
3451     case fmt_double: return "d";
3452     case fmt_word: return "w";
3453     case fmt_long: return "l";
3454     default: return "?";
3455     }
3456 }
3457
3458 :%s::::X:int x
3459 {
3460   switch (x)
3461     {
3462     case 0: return "f";
3463     case 1: return "t";
3464     default: return "?";
3465     }
3466 }
3467
3468 :%s::::TF:int tf
3469 {
3470   if (tf)
3471     return "t";
3472   else
3473     return "f";
3474 }
3475
3476 :%s::::ND:int nd
3477 {
3478   if (nd)
3479     return "l";
3480   else
3481     return "";
3482 }
3483
3484 :%s::::COND:int cond
3485 {
3486   switch (cond)
3487     {
3488     case 00: return "f";
3489     case 01: return "un";
3490     case 02: return "eq";
3491     case 03: return "ueq";
3492     case 04: return "olt";
3493     case 05: return "ult";
3494     case 06: return "ole";
3495     case 07: return "ule";
3496     case 010: return "sf";
3497     case 011: return "ngle";
3498     case 012: return "seq";
3499     case 013: return "ngl";
3500     case 014: return "lt";
3501     case 015: return "nge";
3502     case 016: return "le";
3503     case 017: return "ngt";
3504     default: return "?";
3505     }
3506 }
3507
3508
3509 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3510 "abs.%s<FMT> f<FD>, f<FS>"
3511 *mipsI:
3512 *mipsII:
3513 *mipsIII:
3514 *mipsIV:
3515 // start-sanitize-vr5400
3516 *vr5400:
3517 // end-sanitize-vr5400
3518 // start-sanitize-r5900
3519 *r5900:
3520 // end-sanitize-r5900
3521 *r3900:
3522 // start-sanitize-tx19
3523 *tx19:
3524 // end-sanitize-tx19
3525 {
3526   unsigned32 instruction = instruction_0;
3527   int destreg = ((instruction >> 6) & 0x0000001F);
3528   int fs = ((instruction >> 11) & 0x0000001F);
3529   int format = ((instruction >> 21) & 0x00000007);
3530   {
3531     if ((format != fmt_single) && (format != fmt_double))
3532       SignalException(ReservedInstruction,instruction);
3533     else
3534       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3535   }
3536 }
3537
3538
3539
3540
3541 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3542 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3543 *mipsI:
3544 *mipsII:
3545 *mipsIII:
3546 *mipsIV:
3547 // start-sanitize-vr5400
3548 *vr5400:
3549 // end-sanitize-vr5400
3550 // start-sanitize-r5900
3551 *r5900:
3552 // end-sanitize-r5900
3553 *r3900:
3554 // start-sanitize-tx19
3555 *tx19:
3556 // end-sanitize-tx19
3557 {
3558   unsigned32 instruction = instruction_0;
3559   int destreg = ((instruction >> 6) & 0x0000001F);
3560   int fs = ((instruction >> 11) & 0x0000001F);
3561   int ft = ((instruction >> 16) & 0x0000001F);
3562   int format = ((instruction >> 21) & 0x00000007);
3563   {
3564     if ((format != fmt_single) && (format != fmt_double))
3565       SignalException(ReservedInstruction, instruction);
3566     else
3567       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3568   }
3569 }
3570
3571
3572 //
3573 // FIXME: This does not correctly resolve mipsI-mipsIV differences.
3574 //
3575 // BC1F
3576 // BC1FL
3577 // BC1T
3578 // BC1TL
3579 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3580 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3581 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3582 *mipsI:
3583 *mipsII:
3584 *mipsIII:
3585 *mipsIV:
3586 // start-sanitize-vr5400
3587 *vr5400:
3588 // end-sanitize-vr5400
3589 // start-sanitize-r5900
3590 *r5900:
3591 // end-sanitize-r5900
3592 *r3900:
3593 // start-sanitize-tx19
3594 *tx19:
3595 // end-sanitize-tx19
3596 {
3597   unsigned32 instruction = instruction_0;
3598   signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3599   int boolean = ((instruction >> 16) & 0x00000001);
3600   int likely = ((instruction >> 17) & 0x00000001);
3601   int condition_code = ((instruction >> 18) & 0x00000007);
3602   {
3603     if (condition_code != 0)
3604       SignalException(ReservedInstruction,instruction);
3605     else {
3606       int condition = (PREVCOC1() == boolean);
3607       /* NOTE: The branch occurs AFTER the next instruction has been executed */
3608       if (condition) {
3609         DELAY_SLOT (NIA + offset);
3610       }
3611       else if (likely) {
3612         NULLIFY_NEXT_INSTRUCTION ();
3613       }
3614     }
3615   }
3616 }
3617
3618
3619 //
3620 // FIXME: This does not correctly differentiate between mips*
3621 //
3622 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3623 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3624 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3625 *mipsI:
3626 *mipsII:
3627 *mipsIII:
3628 *mipsIV:
3629 // start-sanitize-vr5400
3630 *vr5400:
3631 // end-sanitize-vr5400
3632 // start-sanitize-r5900
3633 *r5900:
3634 // end-sanitize-r5900
3635 *r3900:
3636 // start-sanitize-tx19
3637 *tx19:
3638 // end-sanitize-tx19
3639 {
3640   unsigned32 instruction = instruction_0;
3641   int cmpflags = ((instruction >> 0) & 0x0000000F);
3642   int condition_code = ((instruction >> 8) & 0x00000007);
3643   int fs = ((instruction >> 11) & 0x0000001F);
3644   int ft = ((instruction >> 16) & 0x0000001F);
3645   int format = ((instruction >> 21) & 0x00000007);
3646   if (condition_code != 0)
3647     {
3648       SignalException(ReservedInstruction,instruction);
3649     }
3650   else
3651     {
3652       if ((format != fmt_single) && (format != fmt_double))
3653         SignalException(ReservedInstruction,instruction);
3654       else {
3655         if (condition_code != 0)
3656           SignalException(ReservedInstruction,instruction);
3657         else
3658           {
3659             int ignore = 0;
3660             int less = 0;
3661             int equal = 0;
3662             int unordered = 1;
3663             unsigned64 ofs = ValueFPR(fs,format);
3664             unsigned64 oft = ValueFPR(ft,format);
3665             if (NaN(ofs,format) || NaN(oft,format)) {
3666               if (FCSR & FP_ENABLE(IO)) {
3667                 FCSR |= FP_CAUSE(IO);
3668                 SignalExceptionFPE();
3669                 ignore = 1;
3670               }
3671             } else {
3672               less = Less(ofs,oft,format);
3673               equal = Equal(ofs,oft,format);
3674               unordered = 0;
3675             }
3676             if (!ignore) {
3677               int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3678               SETFCC(condition_code,condition);
3679             }
3680           }
3681       }
3682     }
3683 }
3684
3685
3686 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3687 "ceil.l.%s<FMT> f<FD>, f<FS>"
3688 *mipsIII:
3689 *mipsIV:
3690 // start-sanitize-vr5400
3691 *vr5400:
3692 // end-sanitize-vr5400
3693 // start-sanitize-r5900
3694 *r5900:
3695 // end-sanitize-r5900
3696 *r3900:
3697 // start-sanitize-tx19
3698 *tx19:
3699 // end-sanitize-tx19
3700 {
3701   unsigned32 instruction = instruction_0;
3702   int destreg = ((instruction >> 6) & 0x0000001F);
3703   int fs = ((instruction >> 11) & 0x0000001F);
3704   int format = ((instruction >> 21) & 0x00000007);
3705   {
3706     if ((format != fmt_single) && (format != fmt_double))
3707       SignalException(ReservedInstruction,instruction);
3708     else
3709       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3710   }
3711 }
3712
3713
3714 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3715 *mipsII:
3716 *mipsIII:
3717 *mipsIV:
3718 // start-sanitize-vr5400
3719 *vr5400:
3720 // end-sanitize-vr5400
3721 // start-sanitize-r5900
3722 *r5900:
3723 // end-sanitize-r5900
3724 *r3900:
3725 // start-sanitize-tx19
3726 *tx19:
3727 // end-sanitize-tx19
3728 {
3729   unsigned32 instruction = instruction_0;
3730   int destreg = ((instruction >> 6) & 0x0000001F);
3731   int fs = ((instruction >> 11) & 0x0000001F);
3732   int format = ((instruction >> 21) & 0x00000007);
3733   {
3734   if ((format != fmt_single) && (format != fmt_double))
3735    SignalException(ReservedInstruction,instruction);
3736   else
3737    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3738   }
3739 }
3740
3741
3742 // CFC1
3743 // CTC1
3744 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3745 "c%s<X>c1 r<RT>, f<FS>"
3746 *mipsI:
3747 *mipsII:
3748 *mipsIII:
3749 {
3750   if (X)
3751     {
3752       if (FS == 0)
3753         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3754       else if (FS == 31)
3755         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3756       /* else NOP */
3757       PENDING_FILL(COCIDX,0); /* special case */
3758     }
3759   else
3760     { /* control from */
3761       if (FS == 0)
3762         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3763       else if (FS == 31)
3764         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3765       /* else NOP */
3766     }
3767 }
3768 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3769 "c%s<X>c1 r<RT>, f<FS>"
3770 *mipsIV:
3771 // start-sanitize-vr5400
3772 *vr5400:
3773 // end-sanitize-vr5400
3774 // start-sanitize-r5900
3775 *r5900:
3776 // end-sanitize-r5900
3777 *r3900:
3778 // start-sanitize-tx19
3779 *tx19:
3780 // end-sanitize-tx19
3781 {
3782   if (X)
3783     {
3784       if (FS == 0)
3785         FCR0 = VL4_8(GPR[RT]);
3786       else if (FS == 31)
3787         FCR31 = VL4_8(GPR[RT]);
3788       /* else NOP */
3789       SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3790     }
3791   else
3792     { /* control from */
3793       if (FS == 0)
3794         GPR[RT] = SIGNEXTEND (FCR0, 32);
3795       else if (FS == 31)
3796         GPR[RT] = SIGNEXTEND (FCR31, 32);
3797       /* else NOP */
3798     }
3799 }
3800
3801
3802 //
3803 // FIXME: Does not correctly differentiate between mips*
3804 //
3805 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3806 "cvt.d.%s<FMT> f<FD>, f<FS>"
3807 *mipsI:
3808 *mipsII:
3809 *mipsIII:
3810 *mipsIV:
3811 // start-sanitize-vr5400
3812 *vr5400:
3813 // end-sanitize-vr5400
3814 // start-sanitize-r5900
3815 *r5900:
3816 // end-sanitize-r5900
3817 *r3900:
3818 // start-sanitize-tx19
3819 *tx19:
3820 // end-sanitize-tx19
3821 {
3822   unsigned32 instruction = instruction_0;
3823   int destreg = ((instruction >> 6) & 0x0000001F);
3824   int fs = ((instruction >> 11) & 0x0000001F);
3825   int format = ((instruction >> 21) & 0x00000007);
3826   {
3827     if ((format == fmt_double) | 0)
3828       SignalException(ReservedInstruction,instruction);
3829     else
3830       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3831   }
3832 }
3833
3834
3835 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3836 "cvt.l.%s<FMT> f<FD>, f<FS>"
3837 *mipsIII:
3838 *mipsIV:
3839 // start-sanitize-vr5400
3840 *vr5400:
3841 // end-sanitize-vr5400
3842 // start-sanitize-r5900
3843 *r5900:
3844 // end-sanitize-r5900
3845 *r3900:
3846 // start-sanitize-tx19
3847 *tx19:
3848 // end-sanitize-tx19
3849 {
3850   unsigned32 instruction = instruction_0;
3851   int destreg = ((instruction >> 6) & 0x0000001F);
3852   int fs = ((instruction >> 11) & 0x0000001F);
3853   int format = ((instruction >> 21) & 0x00000007);
3854   {
3855     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3856       SignalException(ReservedInstruction,instruction);
3857     else
3858       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3859   }
3860 }
3861
3862
3863 //
3864 // FIXME: Does not correctly differentiate between mips*
3865 //
3866 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3867 "cvt.s.%s<FMT> f<FD>, f<FS>"
3868 *mipsI:
3869 *mipsII:
3870 *mipsIII:
3871 *mipsIV:
3872 // start-sanitize-vr5400
3873 *vr5400:
3874 // end-sanitize-vr5400
3875 // start-sanitize-r5900
3876 *r5900:
3877 // end-sanitize-r5900
3878 *r3900:
3879 // start-sanitize-tx19
3880 *tx19:
3881 // end-sanitize-tx19
3882 {
3883   unsigned32 instruction = instruction_0;
3884   int destreg = ((instruction >> 6) & 0x0000001F);
3885   int fs = ((instruction >> 11) & 0x0000001F);
3886   int format = ((instruction >> 21) & 0x00000007);
3887   {
3888     if ((format == fmt_single) | 0)
3889       SignalException(ReservedInstruction,instruction);
3890     else
3891       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3892   }
3893 }
3894
3895
3896 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3897 "cvt.w.%s<FMT> f<FD>, f<FS>"
3898 *mipsI:
3899 *mipsII:
3900 *mipsIII:
3901 *mipsIV:
3902 // start-sanitize-vr5400
3903 *vr5400:
3904 // end-sanitize-vr5400
3905 // start-sanitize-r5900
3906 *r5900:
3907 // end-sanitize-r5900
3908 *r3900:
3909 // start-sanitize-tx19
3910 *tx19:
3911 // end-sanitize-tx19
3912 {
3913   unsigned32 instruction = instruction_0;
3914   int destreg = ((instruction >> 6) & 0x0000001F);
3915   int fs = ((instruction >> 11) & 0x0000001F);
3916   int format = ((instruction >> 21) & 0x00000007);
3917   {
3918     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3919       SignalException(ReservedInstruction,instruction);
3920     else
3921       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3922   }
3923 }
3924
3925
3926 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3927 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3928 *mipsI:
3929 *mipsII:
3930 *mipsIII:
3931 *mipsIV:
3932 // start-sanitize-vr5400
3933 *vr5400:
3934 // end-sanitize-vr5400
3935 // start-sanitize-r5900
3936 *r5900:
3937 // end-sanitize-r5900
3938 *r3900:
3939 // start-sanitize-tx19
3940 *tx19:
3941 // end-sanitize-tx19
3942 {
3943   unsigned32 instruction = instruction_0;
3944   int destreg = ((instruction >> 6) & 0x0000001F);
3945   int fs = ((instruction >> 11) & 0x0000001F);
3946   int ft = ((instruction >> 16) & 0x0000001F);
3947   int format = ((instruction >> 21) & 0x00000007);
3948   {
3949     if ((format != fmt_single) && (format != fmt_double))
3950       SignalException(ReservedInstruction,instruction);
3951     else
3952       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3953   }
3954 }
3955
3956
3957 // DMFC1
3958 // DMTC1
3959 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3960 "dm%s<X>c1 r<RT>, f<FS>"
3961 *mipsIII:
3962 {
3963   if (X)
3964     {
3965       if (SizeFGR() == 64)
3966         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3967       else if ((FS & 0x1) == 0)
3968         {
3969           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3970           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3971         }
3972     }
3973   else
3974     {
3975       if (SizeFGR() == 64)
3976         PENDING_FILL(RT,FGR[FS]);
3977       else if ((FS & 0x1) == 0)
3978         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3979       else
3980         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3981     }
3982 }
3983 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3984 "dm%s<X>c1 r<RT>, f<FS>"
3985 *mipsIV:
3986 // start-sanitize-vr5400
3987 *vr5400:
3988 // end-sanitize-vr5400
3989 // start-sanitize-r5900
3990 *r5900:
3991 // end-sanitize-r5900
3992 *r3900:
3993 // start-sanitize-tx19
3994 *tx19:
3995 // end-sanitize-tx19
3996 {
3997   if (X)
3998     {
3999       if (SizeFGR() == 64)
4000         FGR[FS] = GPR[RT];
4001       else if ((FS & 0x1) == 0)
4002         {
4003           FGR[FS + 1] = VH4_8 (GPR[RT]);
4004           FGR[FS] = VL4_8 (GPR[RT]);
4005         }
4006     }
4007   else
4008     {
4009       if (SizeFGR() == 64)
4010         GPR[RT] = FGR[FS];
4011       else if ((FS & 0x1) == 0)
4012         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4013       else
4014         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4015     }
4016 }
4017
4018
4019 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4020 "floor.l.%s<FMT> f<FD>, f<FS>"
4021 *mipsIII:
4022 *mipsIV:
4023 // start-sanitize-vr5400
4024 *vr5400:
4025 // end-sanitize-vr5400
4026 // start-sanitize-r5900
4027 *r5900:
4028 // end-sanitize-r5900
4029 *r3900:
4030 // start-sanitize-tx19
4031 *tx19:
4032 // end-sanitize-tx19
4033 {
4034   unsigned32 instruction = instruction_0;
4035   int destreg = ((instruction >> 6) & 0x0000001F);
4036   int fs = ((instruction >> 11) & 0x0000001F);
4037   int format = ((instruction >> 21) & 0x00000007);
4038   {
4039     if ((format != fmt_single) && (format != fmt_double))
4040       SignalException(ReservedInstruction,instruction);
4041     else
4042       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4043   }
4044 }
4045
4046
4047 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4048 "floor.w.%s<FMT> f<FD>, f<FS>"
4049 *mipsII:
4050 *mipsIII:
4051 *mipsIV:
4052 // start-sanitize-vr5400
4053 *vr5400:
4054 // end-sanitize-vr5400
4055 // start-sanitize-r5900
4056 *r5900:
4057 // end-sanitize-r5900
4058 *r3900:
4059 // start-sanitize-tx19
4060 *tx19:
4061 // end-sanitize-tx19
4062 {
4063   unsigned32 instruction = instruction_0;
4064   int destreg = ((instruction >> 6) & 0x0000001F);
4065   int fs = ((instruction >> 11) & 0x0000001F);
4066   int format = ((instruction >> 21) & 0x00000007);
4067   {
4068     if ((format != fmt_single) && (format != fmt_double))
4069       SignalException(ReservedInstruction,instruction);
4070     else
4071       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4072   }
4073 }
4074
4075
4076 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4077 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4078 *mipsII:
4079 *mipsIII:
4080 *mipsIV:
4081 // start-sanitize-vr5400
4082 *vr5400:
4083 // end-sanitize-vr5400
4084 *r3900:
4085 // start-sanitize-tx19
4086 *tx19:
4087 // end-sanitize-tx19
4088 {
4089   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4090   address_word paddr;
4091   int uncached;
4092   if ((vaddr & 7) != 0)
4093     SignalExceptionAddressLoad();
4094   else
4095     {
4096       unsigned64 memval;
4097       AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
4098       LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4099       COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
4100     }
4101 }
4102
4103
4104 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4105 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4106 *mipsIV:
4107 // start-sanitize-vr5400
4108 *vr5400:
4109 // end-sanitize-vr5400
4110 {
4111   unsigned32 instruction = instruction_0;
4112   int destreg = ((instruction >> 6) & 0x0000001F);
4113   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4114   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4115   {
4116     address_word vaddr = ((unsigned64)op1 + op2);
4117     address_word paddr;
4118     int uncached;
4119     if ((vaddr & 7) != 0)
4120       SignalExceptionAddressLoad();
4121     else
4122       {
4123         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4124           {
4125             unsigned64 memval = 0;
4126             unsigned64 memval1 = 0;
4127             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4128             COP_LD(1,destreg,memval);;
4129           }
4130       }
4131   }
4132 }
4133
4134
4135
4136 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4137 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4138 *mipsI:
4139 *mipsII:
4140 *mipsIII:
4141 *mipsIV:
4142 // start-sanitize-vr5400
4143 *vr5400:
4144 // end-sanitize-vr5400
4145 // start-sanitize-r5900
4146 *r5900:
4147 // end-sanitize-r5900
4148 *r3900:
4149 // start-sanitize-tx19
4150 *tx19:
4151 // end-sanitize-tx19
4152 {
4153   unsigned32 instruction = instruction_0;
4154   signed_word offset = EXTEND16 (OFFSET);
4155   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4156   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4157   {
4158     address_word vaddr = ((uword64)op1 + offset);
4159     address_word paddr;
4160     int uncached;
4161     if ((vaddr & 3) != 0)
4162       SignalExceptionAddressLoad();
4163     else
4164       {
4165         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4166           {
4167             uword64 memval = 0;
4168             uword64 memval1 = 0;
4169             uword64 mask = 0x7;
4170             unsigned int shift = 2;
4171             unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
4172             unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
4173             unsigned int byte UNUSED;
4174             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4175             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4176             byte = ((vaddr & mask) ^ (bigend << shift));
4177             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4178           }
4179       }
4180   }
4181 }
4182
4183
4184 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4185 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4186 *mipsIV:
4187 // start-sanitize-vr5400
4188 *vr5400:
4189 // end-sanitize-vr5400
4190 {
4191   unsigned32 instruction = instruction_0;
4192   int destreg = ((instruction >> 6) & 0x0000001F);
4193   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4194   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4195   {
4196    address_word vaddr = ((unsigned64)op1 + op2);
4197    address_word paddr;
4198    int uncached;
4199    if ((vaddr & 3) != 0)
4200     SignalExceptionAddressLoad();
4201    else
4202    {
4203     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4204     {
4205      unsigned64 memval = 0;
4206      unsigned64 memval1 = 0;
4207      unsigned64 mask = 0x7;
4208      unsigned int shift = 2;
4209      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4210      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4211      unsigned int byte;
4212      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4213      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4214      byte = ((vaddr & mask) ^ (bigend << shift));
4215      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4216     }
4217    }
4218   }
4219 }
4220
4221
4222
4223 //
4224 // FIXME: Not correct for mips*
4225 //
4226 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
4227 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4228 *mipsIV:
4229 // start-sanitize-vr5400
4230 *vr5400:
4231 // end-sanitize-vr5400
4232 // start-sanitize-r5900
4233 *r5900:
4234 // end-sanitize-r5900
4235 {
4236   unsigned32 instruction = instruction_0;
4237   int destreg = ((instruction >> 6) & 0x0000001F);
4238   int fs = ((instruction >> 11) & 0x0000001F);
4239   int ft = ((instruction >> 16) & 0x0000001F);
4240   int fr = ((instruction >> 21) & 0x0000001F);
4241   {
4242     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4243   }
4244 }
4245
4246
4247 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
4248 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4249 *mipsIV:
4250 // start-sanitize-vr5400
4251 *vr5400:
4252 // end-sanitize-vr5400
4253 // start-sanitize-r5900
4254 *r5900:
4255 // end-sanitize-r5900
4256 {
4257   unsigned32 instruction = instruction_0;
4258   int destreg = ((instruction >> 6) & 0x0000001F);
4259   int fs = ((instruction >> 11) & 0x0000001F);
4260   int ft = ((instruction >> 16) & 0x0000001F);
4261   int fr = ((instruction >> 21) & 0x0000001F);
4262   {
4263     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4264   }
4265 }
4266
4267
4268 // MFC1
4269 // MTC1
4270 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4271 "m%s<X>c1 r<RT>, f<FS>"
4272 *mipsI:
4273 *mipsII:
4274 *mipsIII:
4275 {
4276   if (X)
4277     { /*MTC1*/
4278       if (SizeFGR() == 64)
4279         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4280       else
4281         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4282     }
4283   else /*MFC1*/
4284     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4285 }
4286 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4287 "m%s<X>c1 r<RT>, f<FS>"
4288 *mipsIV:
4289 // start-sanitize-vr5400
4290 *vr5400:
4291 // end-sanitize-vr5400
4292 // start-sanitize-r5900
4293 *r5900:
4294 // end-sanitize-r5900
4295 *r3900:
4296 // start-sanitize-tx19
4297 *tx19:
4298 // end-sanitize-tx19
4299 {
4300   if (X)
4301     { /*MTC1*/
4302       if (SizeFGR() == 64)
4303         FGR[FS] = (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]));
4304       else
4305         FGR[FS] = VL4_8 (GPR[RT]);
4306     }
4307   else /*MFC1*/
4308     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4309 }
4310
4311
4312 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4313 "mov.%s<FMT> f<FD>, f<FS>"
4314 *mipsI:
4315 *mipsII:
4316 *mipsIII:
4317 *mipsIV:
4318 // start-sanitize-vr5400
4319 *vr5400:
4320 // end-sanitize-vr5400
4321 // start-sanitize-r5900
4322 *r5900:
4323 // end-sanitize-r5900
4324 *r3900:
4325 // start-sanitize-tx19
4326 *tx19:
4327 // end-sanitize-tx19
4328 {
4329   unsigned32 instruction = instruction_0;
4330   int destreg = ((instruction >> 6) & 0x0000001F);
4331   int fs = ((instruction >> 11) & 0x0000001F);
4332   int format = ((instruction >> 21) & 0x00000007);
4333   {
4334     StoreFPR(destreg,format,ValueFPR(fs,format));
4335   }
4336 }
4337
4338
4339 // MOVF
4340 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4341 "mov%s<TF> r<RD>, r<RS>, <CC>"
4342 *mipsIV:
4343 // start-sanitize-vr5400
4344 *vr5400:
4345 // end-sanitize-vr5400
4346 // start-sanitize-r5900
4347 *r5900:
4348 // end-sanitize-r5900
4349 {
4350   if (GETFCC(CC) == TF)
4351     GPR[RD] = GPR[RS];
4352 }
4353
4354
4355 // MOVF.fmt
4356 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4357 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4358 *mipsIV:
4359 // start-sanitize-vr5400
4360 *vr5400:
4361 // end-sanitize-vr5400
4362 // start-sanitize-r5900
4363 *r5900:
4364 // end-sanitize-r5900
4365 {
4366   unsigned32 instruction = instruction_0;
4367   int format = ((instruction >> 21) & 0x00000007);
4368   {
4369    if (GETFCC(CC) == TF)
4370      StoreFPR (FD, format, ValueFPR (FS, format));
4371    else
4372      StoreFPR (FD, format, ValueFPR (FD, format));
4373   }
4374 }
4375
4376
4377 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4378 *mipsIV:
4379 // start-sanitize-vr5400
4380 *vr5400:
4381 // end-sanitize-vr5400
4382 // start-sanitize-r5900
4383 *r5900:
4384 // end-sanitize-r5900
4385 {
4386   unsigned32 instruction = instruction_0;
4387   int destreg = ((instruction >> 6) & 0x0000001F);
4388   int fs = ((instruction >> 11) & 0x0000001F);
4389   int format = ((instruction >> 21) & 0x00000007);
4390   {
4391     StoreFPR(destreg,format,ValueFPR(fs,format));
4392   }
4393 }
4394
4395
4396 // MOVT see MOVtf
4397
4398
4399 // MOVT.fmt see MOVtf.fmt
4400
4401
4402
4403 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4404 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4405 *mipsIV:
4406 // start-sanitize-vr5400
4407 *vr5400:
4408 // end-sanitize-vr5400
4409 // start-sanitize-r5900
4410 *r5900:
4411 // end-sanitize-r5900
4412 {
4413   unsigned32 instruction = instruction_0;
4414   int destreg = ((instruction >> 6) & 0x0000001F);
4415   int fs = ((instruction >> 11) & 0x0000001F);
4416   int format = ((instruction >> 21) & 0x00000007);
4417   {
4418    StoreFPR(destreg,format,ValueFPR(fs,format));
4419   }
4420 }
4421
4422
4423 // MSUB.fmt
4424 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4425 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4426 *mipsIV:
4427 // start-sanitize-vr5400
4428 *vr5400:
4429 // end-sanitize-vr5400
4430 // start-sanitize-r5900
4431 *r5900:
4432 // end-sanitize-r5900
4433 {
4434   unsigned32 instruction = instruction_0;
4435   int destreg = ((instruction >> 6) & 0x0000001F);
4436   int fs = ((instruction >> 11) & 0x0000001F);
4437   int ft = ((instruction >> 16) & 0x0000001F);
4438   int fr = ((instruction >> 21) & 0x0000001F);
4439   {
4440     StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4441   }
4442 }
4443
4444
4445 // MSUB.fmt
4446 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4447 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4448 *mipsIV:
4449 // start-sanitize-vr5400
4450 *vr5400:
4451 // end-sanitize-vr5400
4452 // start-sanitize-r5900
4453 *r5900:
4454 // end-sanitize-r5900
4455 {
4456   unsigned32 instruction = instruction_0;
4457   int destreg = ((instruction >> 6) & 0x0000001F);
4458   int fs = ((instruction >> 11) & 0x0000001F);
4459   int ft = ((instruction >> 16) & 0x0000001F);
4460   int fr = ((instruction >> 21) & 0x0000001F);
4461   {
4462    StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4463   }
4464 }
4465
4466
4467 // MTC1 see MxC1
4468
4469
4470 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4471 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4472 *mipsI:
4473 *mipsII:
4474 *mipsIII:
4475 *mipsIV:
4476 // start-sanitize-vr5400
4477 *vr5400:
4478 // end-sanitize-vr5400
4479 // start-sanitize-r5900
4480 *r5900:
4481 // end-sanitize-r5900
4482 *r3900:
4483 // start-sanitize-tx19
4484 *tx19:
4485 // end-sanitize-tx19
4486 {
4487   unsigned32 instruction = instruction_0;
4488   int destreg = ((instruction >> 6) & 0x0000001F);
4489   int fs = ((instruction >> 11) & 0x0000001F);
4490   int ft = ((instruction >> 16) & 0x0000001F);
4491   int format = ((instruction >> 21) & 0x00000007);
4492   {
4493     if ((format != fmt_single) && (format != fmt_double))
4494       SignalException(ReservedInstruction,instruction);
4495     else
4496       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4497   }
4498 }
4499
4500
4501 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4502 "neg.%s<FMT> f<FD>, f<FS>"
4503 *mipsI:
4504 *mipsII:
4505 *mipsIII:
4506 *mipsIV:
4507 // start-sanitize-vr5400
4508 *vr5400:
4509 // end-sanitize-vr5400
4510 // start-sanitize-r5900
4511 *r5900:
4512 // end-sanitize-r5900
4513 *r3900:
4514 // start-sanitize-tx19
4515 *tx19:
4516 // end-sanitize-tx19
4517 {
4518   unsigned32 instruction = instruction_0;
4519   int destreg = ((instruction >> 6) & 0x0000001F);
4520   int fs = ((instruction >> 11) & 0x0000001F);
4521   int format = ((instruction >> 21) & 0x00000007);
4522   {
4523     if ((format != fmt_single) && (format != fmt_double))
4524       SignalException(ReservedInstruction,instruction);
4525     else
4526       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4527   }
4528 }
4529
4530
4531 // NMADD.fmt
4532 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4533 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4534 *mipsIV:
4535 // start-sanitize-vr5400
4536 *vr5400:
4537 // end-sanitize-vr5400
4538 {
4539   unsigned32 instruction = instruction_0;
4540   int destreg = ((instruction >> 6) & 0x0000001F);
4541   int fs = ((instruction >> 11) & 0x0000001F);
4542   int ft = ((instruction >> 16) & 0x0000001F);
4543   int fr = ((instruction >> 21) & 0x0000001F);
4544   {
4545    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4546   }
4547 }
4548
4549
4550 // NMADD.fmt
4551 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4552 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4553 *mipsIV:
4554 // start-sanitize-vr5400
4555 *vr5400:
4556 // end-sanitize-vr5400
4557 {
4558   unsigned32 instruction = instruction_0;
4559   int destreg = ((instruction >> 6) & 0x0000001F);
4560   int fs = ((instruction >> 11) & 0x0000001F);
4561   int ft = ((instruction >> 16) & 0x0000001F);
4562   int fr = ((instruction >> 21) & 0x0000001F);
4563   {
4564    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4565   }
4566 }
4567
4568
4569 // NMSUB.fmt
4570 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4571 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4572 *mipsIV:
4573 // start-sanitize-vr5400
4574 *vr5400:
4575 // end-sanitize-vr5400
4576 {
4577   unsigned32 instruction = instruction_0;
4578   int destreg = ((instruction >> 6) & 0x0000001F);
4579   int fs = ((instruction >> 11) & 0x0000001F);
4580   int ft = ((instruction >> 16) & 0x0000001F);
4581   int fr = ((instruction >> 21) & 0x0000001F);
4582   {
4583    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4584   }
4585 }
4586
4587
4588 // NMSUB.fmt
4589 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4590 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4591 *mipsIV:
4592 // start-sanitize-vr5400
4593 *vr5400:
4594 // end-sanitize-vr5400
4595 {
4596   unsigned32 instruction = instruction_0;
4597   int destreg = ((instruction >> 6) & 0x0000001F);
4598   int fs = ((instruction >> 11) & 0x0000001F);
4599   int ft = ((instruction >> 16) & 0x0000001F);
4600   int fr = ((instruction >> 21) & 0x0000001F);
4601   {
4602     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4603   }
4604 }
4605
4606
4607 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4608 "prefx <HINT>, r<INDEX>(r<BASE>)"
4609 *mipsIV:
4610 // start-sanitize-vr5400
4611 *vr5400:
4612 // end-sanitize-vr5400
4613 {
4614   unsigned32 instruction = instruction_0;
4615   int fs = ((instruction >> 11) & 0x0000001F);
4616   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4617   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4618   {
4619     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4620     address_word paddr;
4621     int uncached;
4622     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4623       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4624   }
4625 }
4626
4627 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4628 *mipsIV:
4629 "recip.%s<FMT> f<FD>, f<FS>"
4630 // start-sanitize-vr5400
4631 *vr5400:
4632 // end-sanitize-vr5400
4633 {
4634   unsigned32 instruction = instruction_0;
4635   int destreg = ((instruction >> 6) & 0x0000001F);
4636   int fs = ((instruction >> 11) & 0x0000001F);
4637   int format = ((instruction >> 21) & 0x00000007);
4638   {
4639   if ((format != fmt_single) && (format != fmt_double))
4640    SignalException(ReservedInstruction,instruction);
4641   else
4642    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4643   }
4644 }
4645
4646
4647 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4648 "round.l.%s<FMT> f<FD>, f<FS>"
4649 *mipsIII:
4650 *mipsIV:
4651 // start-sanitize-vr5400
4652 *vr5400:
4653 // end-sanitize-vr5400
4654 // start-sanitize-r5900
4655 *r5900:
4656 // end-sanitize-r5900
4657 *r3900:
4658 // start-sanitize-tx19
4659 *tx19:
4660 // end-sanitize-tx19
4661 {
4662   unsigned32 instruction = instruction_0;
4663   int destreg = ((instruction >> 6) & 0x0000001F);
4664   int fs = ((instruction >> 11) & 0x0000001F);
4665   int format = ((instruction >> 21) & 0x00000007);
4666   {
4667     if ((format != fmt_single) && (format != fmt_double))
4668       SignalException(ReservedInstruction,instruction);
4669     else
4670       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4671   }
4672 }
4673
4674
4675 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4676 "round.w.%s<FMT> f<FD>, f<FS>"
4677 *mipsII:
4678 *mipsIII:
4679 *mipsIV:
4680 // start-sanitize-vr5400
4681 *vr5400:
4682 // end-sanitize-vr5400
4683 // start-sanitize-r5900
4684 *r5900:
4685 // end-sanitize-r5900
4686 *r3900:
4687 // start-sanitize-tx19
4688 *tx19:
4689 // end-sanitize-tx19
4690 {
4691   unsigned32 instruction = instruction_0;
4692   int destreg = ((instruction >> 6) & 0x0000001F);
4693   int fs = ((instruction >> 11) & 0x0000001F);
4694   int format = ((instruction >> 21) & 0x00000007);
4695   {
4696   if ((format != fmt_single) && (format != fmt_double))
4697    SignalException(ReservedInstruction,instruction);
4698   else
4699    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4700   }
4701 }
4702
4703
4704 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4705 *mipsIV:
4706 "rsqrt.%s<FMT> f<FD>, f<FS>"
4707 // start-sanitize-vr5400
4708 *vr5400:
4709 // end-sanitize-vr5400
4710 {
4711   unsigned32 instruction = instruction_0;
4712   int destreg = ((instruction >> 6) & 0x0000001F);
4713   int fs = ((instruction >> 11) & 0x0000001F);
4714   int format = ((instruction >> 21) & 0x00000007);
4715   {
4716   if ((format != fmt_single) && (format != fmt_double))
4717    SignalException(ReservedInstruction,instruction);
4718   else
4719    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4720   }
4721 }
4722
4723
4724 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4725 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4726 *mipsII:
4727 *mipsIII:
4728 *mipsIV:
4729 // start-sanitize-vr5400
4730 *vr5400:
4731 // end-sanitize-vr5400
4732 *r3900:
4733 // start-sanitize-tx19
4734 *tx19:
4735 // end-sanitize-tx19
4736 {
4737   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4738   int uncached;
4739   if ((vaddr & 7) != 0)
4740     SignalExceptionAddressStore();
4741   else
4742     {
4743       address_word paddr;
4744       unsigned64 memval;
4745       AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
4746       memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
4747       StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
4748     }
4749 }
4750
4751
4752
4753 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4754 *mipsIV:
4755 // start-sanitize-vr5400
4756 *vr5400:
4757 // end-sanitize-vr5400
4758 {
4759   unsigned32 instruction = instruction_0;
4760   int fs = ((instruction >> 11) & 0x0000001F);
4761   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4762   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4763   {
4764     address_word vaddr = ((unsigned64)op1 + op2);
4765     address_word paddr;
4766     int uncached;
4767     if ((vaddr & 7) != 0)
4768       SignalExceptionAddressStore();
4769     else
4770       {
4771         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4772           {
4773             unsigned64 memval = 0;
4774             unsigned64 memval1 = 0;
4775             memval = (unsigned64)COP_SD(1,fs);
4776             {
4777               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4778             }
4779           }
4780       }
4781   }
4782 }
4783
4784
4785 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4786 "sqrt.%s<FMT> f<FD>, f<FS>"
4787 *mipsII:
4788 *mipsIII:
4789 *mipsIV:
4790 // start-sanitize-vr5400
4791 *vr5400:
4792 // end-sanitize-vr5400
4793 // start-sanitize-r5900
4794 *r5900:
4795 // end-sanitize-r5900
4796 *r3900:
4797 // start-sanitize-tx19
4798 *tx19:
4799 // end-sanitize-tx19
4800 {
4801   unsigned32 instruction = instruction_0;
4802   int destreg = ((instruction >> 6) & 0x0000001F);
4803   int fs = ((instruction >> 11) & 0x0000001F);
4804   int format = ((instruction >> 21) & 0x00000007);
4805   {
4806     if ((format != fmt_single) && (format != fmt_double))
4807       SignalException(ReservedInstruction,instruction);
4808     else
4809       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4810   }
4811 }
4812
4813
4814 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4815 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4816 *mipsI:
4817 *mipsII:
4818 *mipsIII:
4819 *mipsIV:
4820 // start-sanitize-vr5400
4821 *vr5400:
4822 // end-sanitize-vr5400
4823 // start-sanitize-r5900
4824 *r5900:
4825 // end-sanitize-r5900
4826 *r3900:
4827 // start-sanitize-tx19
4828 *tx19:
4829 // end-sanitize-tx19
4830 {
4831   unsigned32 instruction = instruction_0;
4832   int destreg = ((instruction >> 6) & 0x0000001F);
4833   int fs = ((instruction >> 11) & 0x0000001F);
4834   int ft = ((instruction >> 16) & 0x0000001F);
4835   int format = ((instruction >> 21) & 0x00000007);
4836   {
4837     if ((format != fmt_single) && (format != fmt_double))
4838       SignalException(ReservedInstruction,instruction);
4839     else
4840       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4841   }
4842 }
4843
4844
4845
4846 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4847 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4848 *mipsI:
4849 *mipsII:
4850 *mipsIII:
4851 *mipsIV:
4852 // start-sanitize-vr5400
4853 *vr5400:
4854 // end-sanitize-vr5400
4855 // start-sanitize-r5900
4856 *r5900:
4857 // end-sanitize-r5900
4858 *r3900:
4859 // start-sanitize-tx19
4860 *tx19:
4861 // end-sanitize-tx19
4862 {
4863   unsigned32 instruction = instruction_0;
4864   signed_word offset = EXTEND16 (OFFSET);
4865   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4866   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4867   {
4868     address_word vaddr = ((uword64)op1 + offset);
4869     address_word paddr;
4870     int uncached;
4871     if ((vaddr & 3) != 0)
4872       SignalExceptionAddressStore();
4873     else
4874       {
4875         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4876           {
4877             uword64 memval = 0;
4878             uword64 memval1 = 0;
4879             uword64 mask = 0x7;
4880             unsigned int byte;
4881             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4882             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4883             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4884             {
4885               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4886             }
4887           }
4888       }
4889   }
4890 }
4891
4892
4893 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4894 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4895 *mipsIV:
4896 // start-sanitize-vr5400
4897 *vr5400:
4898 // end-sanitize-vr5400
4899 {
4900   unsigned32 instruction = instruction_0;
4901   int fs = ((instruction >> 11) & 0x0000001F);
4902   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4903   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4904   {
4905    address_word vaddr = ((unsigned64)op1 + op2);
4906    address_word paddr;
4907    int uncached;
4908    if ((vaddr & 3) != 0)
4909     SignalExceptionAddressStore();
4910    else
4911    {
4912     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4913     {
4914      unsigned64 memval = 0;
4915      unsigned64 memval1 = 0;
4916      unsigned64 mask = 0x7;
4917      unsigned int byte;
4918      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4919      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4920      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4921       {
4922        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4923       }
4924     }
4925    }
4926   }
4927 }
4928
4929
4930 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4931 "trunc.l.%s<FMT> f<FD>, f<FS>"
4932 *mipsIII:
4933 *mipsIV:
4934 // start-sanitize-vr5400
4935 *vr5400:
4936 // end-sanitize-vr5400
4937 // start-sanitize-r5900
4938 *r5900:
4939 // end-sanitize-r5900
4940 *r3900:
4941 // start-sanitize-tx19
4942 *tx19:
4943 // end-sanitize-tx19
4944 {
4945   unsigned32 instruction = instruction_0;
4946   int destreg = ((instruction >> 6) & 0x0000001F);
4947   int fs = ((instruction >> 11) & 0x0000001F);
4948   int format = ((instruction >> 21) & 0x00000007);
4949   {
4950   if ((format != fmt_single) && (format != fmt_double))
4951    SignalException(ReservedInstruction,instruction);
4952   else
4953    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4954   }
4955 }
4956
4957
4958 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4959 "trunc.w.%s<FMT> f<FD>, f<FS>"
4960 *mipsII:
4961 *mipsIII:
4962 *mipsIV:
4963 // start-sanitize-vr5400
4964 *vr5400:
4965 // end-sanitize-vr5400
4966 // start-sanitize-r5900
4967 *r5900:
4968 // end-sanitize-r5900
4969 *r3900:
4970 // start-sanitize-tx19
4971 *tx19:
4972 // end-sanitize-tx19
4973 {
4974   unsigned32 instruction = instruction_0;
4975   int destreg = ((instruction >> 6) & 0x0000001F);
4976   int fs = ((instruction >> 11) & 0x0000001F);
4977   int format = ((instruction >> 21) & 0x00000007);
4978   {
4979   if ((format != fmt_single) && (format != fmt_double))
4980    SignalException(ReservedInstruction,instruction);
4981   else
4982    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4983   }
4984 }
4985
4986 \f
4987 //
4988 // MIPS Architecture:
4989 //
4990 //        System Control Instruction Set (COP0)
4991 //
4992
4993
4994 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4995 "bc0f <OFFSET>"
4996 *mipsI:
4997 *mipsII:
4998 *mipsIII:
4999 *mipsIV:
5000 // start-sanitize-vr5400
5001 *vr5400:
5002 // end-sanitize-vr5400
5003 // start-sanitize-r5900
5004 *r5900:
5005 // end-sanitize-r5900
5006
5007
5008 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5009 "bc0fl <OFFSET>"
5010 *mipsI:
5011 *mipsII:
5012 *mipsIII:
5013 *mipsIV:
5014 // start-sanitize-vr5400
5015 *vr5400:
5016 // end-sanitize-vr5400
5017 // start-sanitize-r5900
5018 *r5900:
5019 // end-sanitize-r5900
5020
5021
5022 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5023 "bc0t <OFFSET>"
5024 *mipsI:
5025 *mipsII:
5026 *mipsIII:
5027 *mipsIV:
5028 // start-sanitize-r5900
5029 *r5900:
5030 // end-sanitize-r5900
5031
5032
5033
5034 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5035 "bc0tl <OFFSET>"
5036 *mipsI:
5037 *mipsII:
5038 *mipsIII:
5039 *mipsIV:
5040 // start-sanitize-vr5400
5041 *vr5400:
5042 // end-sanitize-vr5400
5043 // start-sanitize-r5900
5044 *r5900:
5045 // end-sanitize-r5900
5046
5047
5048 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5049 *mipsIII:
5050 *mipsIV:
5051 // start-sanitize-vr5400
5052 *vr5400:
5053 // end-sanitize-vr5400
5054 // start-sanitize-r5900
5055 *r5900:
5056 // end-sanitize-r5900
5057 *r3900:
5058 // start-sanitize-tx19
5059 *tx19:
5060 // end-sanitize-tx19
5061 {
5062   unsigned32 instruction = instruction_0;
5063   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5064   int hint = ((instruction >> 16) & 0x0000001F);
5065   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5066   {
5067     address_word vaddr = (op1 + offset);
5068     address_word paddr;
5069     int uncached;
5070     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5071       CacheOp(hint,vaddr,paddr,instruction);
5072   }
5073 }
5074
5075
5076 010000,10000,000000000000000,111001:COP0:32::DI
5077 "di"
5078 *mipsI:
5079 *mipsII:
5080 *mipsIII:
5081 *mipsIV:
5082 // start-sanitize-vr5400
5083 *vr5400:
5084 // end-sanitize-vr5400
5085 // start-sanitize-r5900
5086 *r5900:
5087 // end-sanitize-r5900
5088
5089
5090 010000,10000,000000000000000,111000:COP0:32::EI
5091 "ei"
5092 *mipsI:
5093 *mipsII:
5094 *mipsIII:
5095 *mipsIV:
5096 // start-sanitize-vr5400
5097 *vr5400:
5098 // end-sanitize-vr5400
5099 // start-sanitize-r5900
5100 *r5900:
5101 // end-sanitize-r5900
5102
5103
5104 010000,10000,000000000000000,011000:COP0:32::ERET
5105 "eret"
5106 *mipsIII:
5107 *mipsIV:
5108 // start-sanitize-vr5400
5109 *vr5400:
5110 // end-sanitize-vr5400
5111 // start-sanitize-r5900
5112 *r5900:
5113 // end-sanitize-r5900
5114
5115
5116 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5117 "mfc0 r<RT>, r<RD> # <REGX>"
5118 *mipsI:
5119 *mipsII:
5120 *mipsIII:
5121 *mipsIV:
5122 // start-sanitize-vr5400
5123 *vr5400:
5124 // end-sanitize-vr5400
5125 // start-sanitize-r5900
5126 *r5900:
5127 // end-sanitize-r5900
5128 {
5129   DecodeCoproc (instruction_0);
5130 }
5131
5132 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5133 "mtc0 r<RT>, r<RD> # <REGX>"
5134 *mipsI:
5135 *mipsII:
5136 *mipsIII:
5137 *mipsIV:
5138 // start-sanitize-vr5400
5139 *vr5400:
5140 // end-sanitize-vr5400
5141 // start-sanitize-r5900
5142 *r5900:
5143 // end-sanitize-r5900
5144 {
5145   DecodeCoproc (instruction_0);
5146 }
5147
5148
5149 010000,10000,000000000000000,001000:COP0:32::TLBP
5150 "tlbp"
5151 *mipsI:
5152 *mipsII:
5153 *mipsIII:
5154 *mipsIV:
5155 // start-sanitize-vr5400
5156 *vr5400:
5157 // end-sanitize-vr5400
5158 // start-sanitize-r5900
5159 *r5900:
5160 // end-sanitize-r5900
5161
5162
5163 010000,10000,000000000000000,000001:COP0:32::TLBR
5164 "tlbr"
5165 *mipsI:
5166 *mipsII:
5167 *mipsIII:
5168 *mipsIV:
5169 // start-sanitize-vr5400
5170 *vr5400:
5171 // end-sanitize-vr5400
5172 // start-sanitize-r5900
5173 *r5900:
5174 // end-sanitize-r5900
5175
5176
5177 010000,10000,000000000000000,000010:COP0:32::TLBWI
5178 "tlbwi"
5179 *mipsI:
5180 *mipsII:
5181 *mipsIII:
5182 *mipsIV:
5183 // start-sanitize-vr5400
5184 *vr5400:
5185 // end-sanitize-vr5400
5186 // start-sanitize-r5900
5187 *r5900:
5188 // end-sanitize-r5900
5189
5190
5191 010000,10000,000000000000000,000110:COP0:32::TLBWR
5192 "tlbwr"
5193 *mipsI:
5194 *mipsII:
5195 *mipsIII:
5196 *mipsIV:
5197 // start-sanitize-vr5400
5198 *vr5400:
5199 // end-sanitize-vr5400
5200 // start-sanitize-r5900
5201 *r5900:
5202 // end-sanitize-r5900
5203
5204 \f
5205 :include:::m16.igen
5206 // start-sanitize-vr5400
5207 :include::vr5400:vr5400.igen
5208 // end-sanitize-vr5400
5209 // start-sanitize-r5900
5210 :include::r5900:r5900.igen
5211 // end-sanitize-r5900
5212 \f
5213 // start-sanitize-cygnus-never
5214
5215 // // FIXME FIXME FIXME What is this instruction?
5216 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5217 // *mipsI:
5218 // *mipsII:
5219 // *mipsIII:
5220 // *mipsIV:
5221 // // start-sanitize-r5900
5222 // *r5900:
5223 // // end-sanitize-r5900
5224 // *r3900:
5225 // // start-sanitize-tx19
5226 // *tx19:
5227 // // end-sanitize-tx19
5228 // {
5229 //   unsigned32 instruction = instruction_0;
5230 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5231 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5232 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5233 //   {
5234 //     if (CoProcPresent(3))
5235 //       SignalException(CoProcessorUnusable);
5236 //     else
5237 //       SignalException(ReservedInstruction,instruction);
5238 //   }
5239 // }
5240
5241 // end-sanitize-cygnus-never
5242 // start-sanitize-cygnus-never
5243
5244 // // FIXME FIXME FIXME What is this?
5245 // 11100,******,00001:RR:16::SDBBP
5246 // *mips16:
5247 // {
5248 //   unsigned32 instruction = instruction_0;
5249 //   if (have_extendval)
5250 //     SignalException (ReservedInstruction, instruction);
5251 //   {
5252 //     SignalException(DebugBreakPoint,instruction);
5253 //   }
5254 // }
5255
5256 // end-sanitize-cygnus-never
5257 // start-sanitize-cygnus-never
5258
5259 // // FIXME FIXME FIXME What is this?
5260 // 000000,********************,001110:SPECIAL:32::SDBBP
5261 // *r3900:
5262 // {
5263 //   unsigned32 instruction = instruction_0;
5264 //   {
5265 //     SignalException(DebugBreakPoint,instruction);
5266 //   }
5267 // }
5268
5269 // end-sanitize-cygnus-never
5270 // start-sanitize-cygnus-never
5271
5272 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5273 // // isn't yet reconized by this simulator.
5274 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5275 // *vr4100:
5276 // {
5277 //   unsigned32 instruction = instruction_0;
5278 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5279 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5280 //   {
5281 //     CHECKHILO("Multiply-Add");
5282 //     {
5283 //       unsigned64 temp = (op1 * op2);
5284 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5285 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5286 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5287 //     }
5288 //   }
5289 // }
5290
5291 // end-sanitize-cygnus-never
5292 // start-sanitize-cygnus-never
5293
5294 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5295 // // isn't yet reconized by this simulator.
5296 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5297 // *vr4100:
5298 // {
5299 //   unsigned32 instruction = instruction_0;
5300 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5301 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5302 //   {
5303 //     CHECKHILO("Multiply-Add");
5304 //     {
5305 //       unsigned64 temp = (op1 * op2);
5306 //       LO = LO + temp;
5307 //     }
5308 //   }
5309 // }
5310
5311 // start-sanitize-cygnus-never