sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997-2022 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of the MIPS sim.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef SIM_MAIN_H
  21 #define SIM_MAIN_H
  22
  23 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  24 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  25
  26 #include "sim-basics.h"
  27 #include "sim-base.h"
  28 #include "bfd.h"
  29 #include "elf-bfd.h"
  30 #include "elf/mips.h"
  31
  32 /* Deprecated macros and types for manipulating 64bit values.  Use
  33    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  34
  35 typedef int64_t word64;
  36 typedef uint64_t uword64;
  37
  38 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  39 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  40 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  41 #define SET64HI(t)      (((uword64)(t))<<32)
  42 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  43 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  44
  45 /* Check if a value will fit within a halfword: */
  46 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  47
  48
  49 typedef enum {
  50   cp0_dmfc0,
  51   cp0_dmtc0,
  52   cp0_mfc0,
  53   cp0_mtc0,
  54   cp0_tlbr,
  55   cp0_tlbwi,
  56   cp0_tlbwr,
  57   cp0_tlbp,
  58   cp0_cache,
  59   cp0_eret,
  60   cp0_deret,
  61   cp0_rfe
  62 } CP0_operation;
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67 #include "cp1.h"
  68
  69 /* FPU registers must be one of the following types. All other values
  70    are reserved (and undefined). */
  71 typedef enum {
  72  fmt_single  = 0,
  73  fmt_double  = 1,
  74  fmt_word    = 4,
  75  fmt_long    = 5,
  76  fmt_ps      = 6,
  77  /* The following is a special case for FP conditions where only
  78     the lower 32bits are considered.  This is a HACK.  */
  79  fmt_dc32    = 7,
  80  /* The following are well outside the normal acceptable format
  81     range, and are used in the register status vector. */
  82  fmt_unknown       = 0x10000000,
  83  fmt_uninterpreted = 0x20000000,
  84  fmt_uninterpreted_32 = 0x40000000,
  85  fmt_uninterpreted_64 = 0x80000000U,
  86 } FP_formats;
  87
  88 /* For paired word (pw) operations, the opcode representation is fmt_word,
  89    but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
  90 #define fmt_pw fmt_long
  91
  92 /* This should be the COC1 value at the start of the preceding
  93    instruction: */
  94 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
  95
  96 #ifdef TARGET_ENABLE_FR
  97 /* FIXME: this should be enabled for all targets, but needs testing first. */
  98 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
  99    ? ((SR & status_FR) ? 64 : 32) \
 100    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 101 #else
 102 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 103 #endif
 104
 105
 106
 107
 108
 109 /* HI/LO register accesses */
 110
 111 /* For some MIPS targets, the HI/LO registers have certain timing
 112    restrictions in that, for instance, a read of a HI register must be
 113    separated by at least three instructions from a preceeding read.
 114
 115    The struct below is used to record the last access by each of A MT,
 116    MF or other OP instruction to a HI/LO register.  See mips.igen for
 117    more details. */
 118
 119 typedef struct _hilo_access {
 120   int64_t timestamp;
 121   address_word cia;
 122 } hilo_access;
 123
 124 typedef struct _hilo_history {
 125   hilo_access mt;
 126   hilo_access mf;
 127   hilo_access op;
 128 } hilo_history;
 129
 130
 131
 132
 133 /* Integer ALU operations: */
 134
 135 #include "sim-alu.h"
 136
 137 #define ALU32_END(ANS) \
 138   if (ALU32_HAD_OVERFLOW) \
 139     SignalExceptionIntegerOverflow (); \
 140   (ANS) = (int32_t) ALU32_OVERFLOW_RESULT
 141
 142
 143 #define ALU64_END(ANS) \
 144   if (ALU64_HAD_OVERFLOW) \
 145     SignalExceptionIntegerOverflow (); \
 146   (ANS) = ALU64_OVERFLOW_RESULT;
 147
 148
 149
 150
 151
 152 /* The following is probably not used for MIPS IV onwards: */
 153 /* Slots for delayed register updates. For the moment we just have a
 154    fixed number of slots (rather than a more generic, dynamic
 155    system). This keeps the simulator fast. However, we only allow
 156    for the register update to be delayed for a single instruction
 157    cycle. */
 158 #define PSLOTS (8) /* Maximum number of instruction cycles */
 159
 160 typedef struct _pending_write_queue {
 161   int in;
 162   int out;
 163   int total;
 164   int slot_delay[PSLOTS];
 165   int slot_size[PSLOTS];
 166   int slot_bit[PSLOTS];
 167   void *slot_dest[PSLOTS];
 168   uint64_t slot_value[PSLOTS];
 169 } pending_write_queue;
 170
 171 #ifndef PENDING_TRACE
 172 #define PENDING_TRACE 0
 173 #endif
 174 #define PENDING_IN (MIPS_SIM_CPU (CPU)->pending.in)
 175 #define PENDING_OUT (MIPS_SIM_CPU (CPU)->pending.out)
 176 #define PENDING_TOTAL (MIPS_SIM_CPU (CPU)->pending.total)
 177 #define PENDING_SLOT_SIZE (MIPS_SIM_CPU (CPU)->pending.slot_size)
 178 #define PENDING_SLOT_BIT (MIPS_SIM_CPU (CPU)->pending.slot_bit)
 179 #define PENDING_SLOT_DELAY (MIPS_SIM_CPU (CPU)->pending.slot_delay)
 180 #define PENDING_SLOT_DEST (MIPS_SIM_CPU (CPU)->pending.slot_dest)
 181 #define PENDING_SLOT_VALUE (MIPS_SIM_CPU (CPU)->pending.slot_value)
 182
 183 /* Invalidate the pending write queue, all pending writes are
 184    discarded. */
 185
 186 #define PENDING_INVALIDATE() \
 187 memset (&MIPS_SIM_CPU (CPU)->pending, 0, sizeof (MIPS_SIM_CPU (CPU)->pending))
 188
 189 /* Schedule a write to DEST for N cycles time.  For 64 bit
 190    destinations, schedule two writes.  For floating point registers,
 191    the caller should schedule a write to both the dest register and
 192    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 193    is updated. */
 194
 195 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 196   do {                                                                  \
 197     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 198       sim_engine_abort (SD, CPU, cia,                                   \
 199                         "PENDING_SCHED - buffer overflow\n");           \
 200     if (PENDING_TRACE)                                                  \
 201       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 202                       (unsigned long) cia, (unsigned long) &(DEST),     \
 203                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 204                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 205     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 206     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 207     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 208     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 209     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 210     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 211     PENDING_TOTAL += 1;                                                 \
 212   } while (0)
 213
 214 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 215 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 216
 217 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 218
 219 #define PENDING_FLUSH() abort () /* think about this one */
 220 #define PENDING_FP() abort () /* think about this one */
 221
 222 /* For backward compatibility */
 223 #define PENDING_FILL(R,VAL)                                             \
 224 do {                                                                    \
 225   if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                       \
 226     {                                                                   \
 227       PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                   \
 228       PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
 229     }                                                                   \
 230   else                                                                  \
 231     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 232 } while (0)
 233
 234
 235 enum float_operation
 236   {
 237     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 238     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 239     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 240   };
 241
 242
 243 /* The internal representation of an MDMX accumulator.
 244    Note that 24 and 48 bit accumulator elements are represented in
 245    32 or 64 bits.  Since the accumulators are 2's complement with
 246    overflow suppressed, high-order bits can be ignored in most contexts.  */
 247
 248 typedef int32_t signed24;
 249 typedef int64_t signed48;
 250
 251 typedef union {
 252   signed24  ob[8];
 253   signed48  qh[4];
 254 } MDMX_accumulator;
 255
 256
 257 /* Conventional system arguments.  */
 258 #define SIM_STATE  sim_cpu *cpu, address_word cia
 259 #define SIM_ARGS   CPU, cia
 260
 261 struct mips_sim_cpu {
 262
 263   /* The following are internal simulator state variables: */
 264   address_word dspc;  /* delay-slot PC */
 265 #define DSPC (MIPS_SIM_CPU (CPU)->dspc)
 266
 267 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 268 #define FORBIDDEN_SLOT() { NIA = forbiddenslot32 (SD_); }
 269 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 270
 271
 272   /* State of the simulator */
 273   unsigned int state;
 274   unsigned int dsstate;
 275 #define STATE (MIPS_SIM_CPU (CPU)->state)
 276 #define DSSTATE (MIPS_SIM_CPU (CPU)->dsstate)
 277
 278 /* Flags in the "state" variable: */
 279 #define simHALTEX        (1 << 2)  /* 0 = run; 1 = halt on exception */
 280 #define simHALTIN        (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 281 #define simTRACE         (1 << 8)  /* 1 = trace address activity */
 282 #define simPCOC0         (1 << 17) /* COC[1] from current */
 283 #define simPCOC1         (1 << 18) /* COC[1] from previous */
 284 #define simDELAYSLOT     (1 << 24) /* 1 = delay slot entry exists */
 285 #define simSKIPNEXT      (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 286 #define simSIGINT        (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 287 #define simJALDELAYSLOT  (1 << 29) /* 1 = in jal delay slot */
 288 #define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */
 289
 290 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 291 #define ENGINE_ISSUE_PREFIX_HOOK() \
 292   { \
 293     /* Perform any pending writes */ \
 294     PENDING_TICK(); \
 295     /* Set previous flag, depending on current: */ \
 296     if (STATE & simPCOC0) \
 297      STATE |= simPCOC1; \
 298     else \
 299      STATE &= ~simPCOC1; \
 300     /* and update the current value: */ \
 301     if (GETFCC(0)) \
 302      STATE |= simPCOC0; \
 303     else \
 304      STATE &= ~simPCOC0; \
 305   }
 306 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 307
 308
 309 /* This is nasty, since we have to rely on matching the register
 310    numbers used by GDB. Unfortunately, depending on the MIPS target
 311    GDB uses different register numbers. We cannot just include the
 312    relevant "gdb/tm.h" link, since GDB may not be configured before
 313    the sim world, and also the GDB header file requires too much other
 314    state. */
 315
 316 #ifndef TM_MIPS_H
 317 #define LAST_EMBED_REGNUM (96)
 318 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 319
 320 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 321 #define FCRCS_REGNUM 70         /* FP control/status */
 322 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 323 #endif
 324
 325
 326 /* To keep this default simulator simple, and fast, we use a direct
 327    vector of registers. The internal simulator engine then uses
 328    manifests to access the correct slot. */
 329
 330   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 331
 332   int register_widths[NUM_REGS];
 333 #define REGISTERS       (MIPS_SIM_CPU (CPU)->registers)
 334
 335 #define GPR     (&REGISTERS[0])
 336 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 337
 338 #define LO      (REGISTERS[33])
 339 #define HI      (REGISTERS[34])
 340 #define PCIDX   37
 341 #define PC      (REGISTERS[PCIDX])
 342 #define CAUSE   (REGISTERS[36])
 343 #define SRIDX   (32)
 344 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 345 #define FCR0IDX  (71)
 346 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 347 #define FCR31IDX (70)
 348 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 349 #define FCSR    (FCR31)
 350 #define Debug   (REGISTERS[86])
 351 #define DEPC    (REGISTERS[87])
 352 #define EPC     (REGISTERS[88])
 353 #define ACX     (REGISTERS[89])
 354
 355 #define AC0LOIDX        (33)    /* Must be the same register as LO */
 356 #define AC0HIIDX        (34)    /* Must be the same register as HI */
 357 #define AC1LOIDX        (90)
 358 #define AC1HIIDX        (91)
 359 #define AC2LOIDX        (92)
 360 #define AC2HIIDX        (93)
 361 #define AC3LOIDX        (94)
 362 #define AC3HIIDX        (95)
 363
 364 #define DSPLO(N)        (REGISTERS[DSPLO_REGNUM[N]])
 365 #define DSPHI(N)        (REGISTERS[DSPHI_REGNUM[N]])
 366
 367 #define DSPCRIDX        (96)    /* DSP control register */
 368 #define DSPCR           (REGISTERS[DSPCRIDX])
 369
 370 #define DSPCR_POS_SHIFT         (0)
 371 #define DSPCR_POS_MASK          (0x3f)
 372 #define DSPCR_POS_SMASK         (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
 373
 374 #define DSPCR_SCOUNT_SHIFT      (7)
 375 #define DSPCR_SCOUNT_MASK       (0x3f)
 376 #define DSPCR_SCOUNT_SMASK      (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
 377
 378 #define DSPCR_CARRY_SHIFT       (13)
 379 #define DSPCR_CARRY_MASK        (1)
 380 #define DSPCR_CARRY_SMASK       (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
 381 #define DSPCR_CARRY             (1 << DSPCR_CARRY_SHIFT)
 382
 383 #define DSPCR_EFI_SHIFT         (14)
 384 #define DSPCR_EFI_MASK          (1)
 385 #define DSPCR_EFI_SMASK         (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
 386 #define DSPCR_EFI               (1 << DSPCR_EFI_MASK)
 387
 388 #define DSPCR_OUFLAG_SHIFT      (16)
 389 #define DSPCR_OUFLAG_MASK       (0xff)
 390 #define DSPCR_OUFLAG_SMASK      (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
 391 #define DSPCR_OUFLAG4           (1 << (DSPCR_OUFLAG_SHIFT + 4))
 392 #define DSPCR_OUFLAG5           (1 << (DSPCR_OUFLAG_SHIFT + 5))
 393 #define DSPCR_OUFLAG6           (1 << (DSPCR_OUFLAG_SHIFT + 6))
 394 #define DSPCR_OUFLAG7           (1 << (DSPCR_OUFLAG_SHIFT + 7))
 395
 396 #define DSPCR_CCOND_SHIFT       (24)
 397 #define DSPCR_CCOND_MASK        (0xf)
 398 #define DSPCR_CCOND_SMASK       (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
 399
 400   /* All internal state modified by signal_exception() that may need to be
 401      rolled back for passing moment-of-exception image back to gdb. */
 402   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 403   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 404   int exc_suspended;
 405
 406 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 407 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 408 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 409
 410   unsigned_word c0_config_reg;
 411 #define C0_CONFIG (MIPS_SIM_CPU (CPU)->c0_config_reg)
 412
 413 /* The following are pseudonyms for standard registers */
 414 #define ZERO    (REGISTERS[0])
 415 #define V0      (REGISTERS[2])
 416 #define A0      (REGISTERS[4])
 417 #define A1      (REGISTERS[5])
 418 #define A2      (REGISTERS[6])
 419 #define A3      (REGISTERS[7])
 420 #define T8IDX   24
 421 #define T8      (REGISTERS[T8IDX])
 422 #define SPIDX   29
 423 #define SP      (REGISTERS[SPIDX])
 424 #define RAIDX   31
 425 #define RA      (REGISTERS[RAIDX])
 426
 427   /* While space is allocated in the main registers arrray for some of
 428      the COP0 registers, that space isn't sufficient.  Unknown COP0
 429      registers overflow into the array below */
 430
 431 #define NR_COP0_GPR     32
 432   unsigned_word cop0_gpr[NR_COP0_GPR];
 433 #define COP0_GPR        (MIPS_SIM_CPU (CPU)->cop0_gpr)
 434 #define COP0_BADVADDR   (COP0_GPR[8])
 435
 436   /* While space is allocated for the floating point registers in the
 437      main registers array, they are stored separatly.  This is because
 438      their size may not necessarily match the size of either the
 439      general-purpose or system specific registers.  */
 440 #define NR_FGR    (32)
 441 #define FGR_BASE  FP0_REGNUM
 442   fp_word fgr[NR_FGR];
 443 #define FGR       (MIPS_SIM_CPU (CPU)->fgr)
 444
 445   /* Keep the current format state for each register: */
 446   FP_formats fpr_state[32];
 447 #define FPR_STATE (MIPS_SIM_CPU (CPU)->fpr_state)
 448
 449   pending_write_queue pending;
 450
 451   /* The MDMX accumulator (used only for MDMX ASE).  */
 452   MDMX_accumulator acc;
 453 #define ACC             (MIPS_SIM_CPU (CPU)->acc)
 454
 455   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 456      read-write instructions. It is set when a linked load occurs. It
 457      is tested and cleared by the conditional store. It is cleared
 458      (during other CPU operations) when a store to the location would
 459      no longer be atomic. In particular, it is cleared by exception
 460      return instructions. */
 461   int llbit;
 462 #define LLBIT (MIPS_SIM_CPU (CPU)->llbit)
 463
 464
 465 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 466    corruptions caused by using the HI or LO register too close to a
 467    following operation is spotted. See mips.igen for more details. */
 468
 469   hilo_history hi_history;
 470 #define HIHISTORY (&MIPS_SIM_CPU (CPU)->hi_history)
 471   hilo_history lo_history;
 472 #define LOHISTORY (&MIPS_SIM_CPU (CPU)->lo_history)
 473 };
 474 #define MIPS_SIM_CPU(cpu) ((struct mips_sim_cpu *) CPU_ARCH_DATA (cpu))
 475
 476 extern void mips_sim_close (SIM_DESC sd, int quitting);
 477 #define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)
 478
 479 /* FIXME: At present much of the simulator is still static */
 480 struct mips_sim_state {
 481   /* microMIPS ISA mode.  */
 482   int isa_mode;
 483 };
 484 #define MIPS_SIM_STATE(sd) ((struct mips_sim_state *) STATE_ARCH_DATA (sd))
 485
 486
 487 /* Status information: */
 488
 489 /* TODO : these should be the bitmasks for these bits within the
 490    status register. At the moment the following are VR4300
 491    bit-positions: */
 492 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 493 #define status_KSU_shift (3)            /* shift for field */
 494 #define ksu_kernel       (0x0)
 495 #define ksu_supervisor   (0x1)
 496 #define ksu_user         (0x2)
 497 #define ksu_unknown      (0x3)
 498
 499 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 500
 501 #define status_IE        (1 <<  0)      /* Interrupt enable */
 502 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 503 #define status_EXL       (1 <<  1)      /* Exception level */
 504 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 505 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 506 #define status_SR        (1 << 20)      /* soft reset or NMI */
 507 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 508 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 509 #define status_ERL       (1 <<  2)      /* Error level */
 510 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 511 #define status_RP        (1 << 27)      /* Reduced Power mode */
 512
 513 /* Specializations for TX39 family */
 514 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 515 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 516 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 517 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 518 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 519 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 520 #define status_IM_mask   (0xff)         /* Interrupt mask */
 521 #define status_IM_shift  (8)
 522 #define status_NMI       (1 << 20)      /* NMI */
 523 #define status_NMI       (1 << 20)      /* NMI */
 524
 525 /* Status bits used by MIPS32/MIPS64.  */
 526 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 527 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 528 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 529 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 530 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 531 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 532 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 533 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 534 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 535 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 536 /* Bits reserved for implementations:  */
 537 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 538
 539 /* From R6 onwards, some instructions (e.g. ADDIUPC) change behaviour based
 540  * on the Status.UX bits to either sign extend, or act as full 64 bit. */
 541 #define status_optional_EXTEND32(x) ((SR & status_UX) ? x : EXTEND32(x))
 542
 543 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 544 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 545 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 546 #define cause_CE_shift    28
 547 #define cause_EXC2_mask   0x00070000
 548 #define cause_EXC2_shift  16
 549 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 550 #define cause_SIOP        (1 << 12)     /* SIO pending */
 551 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 552 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 553
 554 #define cause_EXC_mask  (0x1c)          /* Exception code */
 555 #define cause_EXC_shift (2)
 556
 557 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 558 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 559 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 560 #define cause_IP_shift  (10)
 561
 562 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 563 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 564
 565
 566 /* NOTE: We keep the following status flags as bit values (1 for true,
 567    0 for false). This allows them to be used in binary boolean
 568    operations without worrying about what exactly the non-zero true
 569    value is. */
 570
 571 /* UserMode */
 572 #ifdef SUBTARGET_R3900
 573 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 574 #else
 575 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 576 #endif /* SUBTARGET_R3900 */
 577
 578 /* BigEndianMem */
 579 /* Hardware configuration. Affects endianness of LoadMemory and
 580    StoreMemory and the endianness of Kernel and Supervisor mode
 581    execution. The value is 0 for little-endian; 1 for big-endian. */
 582 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 583 /*(state & simBE) ? 1 : 0)*/
 584
 585 /* ReverseEndian */
 586 /* This mode is selected if in User mode with the RE bit being set in
 587    SR (Status Register). It reverses the endianness of load and store
 588    instructions. */
 589 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 590
 591 /* BigEndianCPU */
 592 /* The endianness for load and store instructions (0=little;1=big). In
 593    User mode this endianness may be switched by setting the state_RE
 594    bit in the SR register. Thus, BigEndianCPU may be computed as
 595    (BigEndianMem EOR ReverseEndian). */
 596 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 597
 598
 599
 600 /* Exceptions: */
 601
 602 /* NOTE: These numbers depend on the processor architecture being
 603    simulated: */
 604 enum ExceptionCause {
 605   Interrupt               = 0,
 606   TLBModification         = 1,
 607   TLBLoad                 = 2,
 608   TLBStore                = 3,
 609   AddressLoad             = 4,
 610   AddressStore            = 5,
 611   InstructionFetch        = 6,
 612   DataReference           = 7,
 613   SystemCall              = 8,
 614   BreakPoint              = 9,
 615   ReservedInstruction     = 10,
 616   CoProcessorUnusable     = 11,
 617   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 618   Trap                    = 13,
 619   FPE                     = 15,
 620   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 621   MDMX                    = 22,
 622   Watch                   = 23,
 623   MCheck                  = 24,
 624   CacheErr                = 30,
 625   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 626
 627
 628 /* The following exception code is actually private to the simulator
 629    world. It is *NOT* a processor feature, and is used to signal
 630    run-time errors in the simulator. */
 631   SimulatorFault          = 0xFFFFFFFF
 632 };
 633
 634 #define TLB_REFILL  (0)
 635 #define TLB_INVALID (1)
 636
 637
 638 /* The following break instructions are reserved for use by the
 639    simulator.  The first is used to halt the simulation.  The second
 640    is used by gdb for break-points.  NOTE: Care must be taken, since
 641    this value may be used in later revisions of the MIPS ISA. */
 642 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 643
 644 #define HALT_INSTRUCTION        (0x03ff000d)
 645 #define HALT_INSTRUCTION2       (0x0000ffcd)
 646
 647
 648 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 649 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 650
 651
 652
 653 void interrupt_event (SIM_DESC sd, void *data);
 654
 655 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 656 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 657 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 658 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 659 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 660 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 661 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 662 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 663 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 664 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 665 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 666 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 667 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 668 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 669 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 670 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 671 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 672 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 673 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 674 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 675 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 676
 677 /* Co-processor accesses */
 678
 679 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 680 #define COP_Usable(coproc_num)          (coproc_num == 1)
 681
 682 void cop_lw  (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
 683 void cop_ld  (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
 684 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
 685 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
 686
 687 #define COP_LW(coproc_num,coproc_reg,memword) \
 688 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 689 #define COP_LD(coproc_num,coproc_reg,memword) \
 690 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 691 #define COP_SW(coproc_num,coproc_reg) \
 692 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 693 #define COP_SD(coproc_num,coproc_reg) \
 694 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 695
 696
 697 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
 698                     unsigned int instruction, int coprocnum, CP0_operation op,
 699                     int rt, int rd, int sel);
 700 #define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \
 701   decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \
 702                  (rt), (rd), (sel))
 703
 704 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 705
 706
 707 /* FPR access.  */
 708 uint64_t value_fpr (SIM_STATE, int fpr, FP_formats);
 709 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 710 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, uint64_t value);
 711 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 712 uint64_t ps_lower (SIM_STATE, uint64_t op);
 713 #define PSLower(op) ps_lower (SIM_ARGS, op)
 714 uint64_t ps_upper (SIM_STATE, uint64_t op);
 715 #define PSUpper(op) ps_upper (SIM_ARGS, op)
 716 uint64_t pack_ps (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats from);
 717 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
 718
 719
 720 /* FCR access.  */
 721 unsigned_word value_fcr (SIM_STATE, int fcr);
 722 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
 723 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
 724 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
 725 void test_fcsr (SIM_STATE);
 726 #define TestFCSR() test_fcsr (SIM_ARGS)
 727
 728
 729 /* FPU operations.  */
 730 /* Non-signalling */
 731 #define FP_R6CMP_AF  0x0
 732 #define FP_R6CMP_EQ  0x2
 733 #define FP_R6CMP_LE  0x6
 734 #define FP_R6CMP_LT  0x4
 735 #define FP_R6CMP_NE  0x13
 736 #define FP_R6CMP_OR  0x11
 737 #define FP_R6CMP_UEQ 0x3
 738 #define FP_R6CMP_ULE 0x7
 739 #define FP_R6CMP_ULT 0x5
 740 #define FP_R6CMP_UN  0x1
 741 #define FP_R6CMP_UNE 0x12
 742
 743 /* Signalling */
 744 #define FP_R6CMP_SAF  0x8
 745 #define FP_R6CMP_SEQ  0xa
 746 #define FP_R6CMP_SLE  0xe
 747 #define FP_R6CMP_SLT  0xc
 748 #define FP_R6CMP_SNE  0x1b
 749 #define FP_R6CMP_SOR  0x19
 750 #define FP_R6CMP_SUEQ 0xb
 751 #define FP_R6CMP_SULE 0xf
 752 #define FP_R6CMP_SULT 0xd
 753 #define FP_R6CMP_SUN  0x9
 754 #define FP_R6CMP_SUNE 0x1a
 755
 756 /* FPU Class */
 757 #define FP_R6CLASS_SNAN    (1<<0)
 758 #define FP_R6CLASS_QNAN    (1<<1)
 759 #define FP_R6CLASS_NEGINF  (1<<2)
 760 #define FP_R6CLASS_NEGNORM (1<<3)
 761 #define FP_R6CLASS_NEGSUB  (1<<4)
 762 #define FP_R6CLASS_NEGZERO (1<<5)
 763 #define FP_R6CLASS_POSINF  (1<<6)
 764 #define FP_R6CLASS_POSNORM (1<<7)
 765 #define FP_R6CLASS_POSSUB  (1<<8)
 766 #define FP_R6CLASS_POSZERO (1<<9)
 767
 768 void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt,
 769              int abs, int cond, int cc);
 770 #define Compare(op1,op2,fmt,cond,cc)  \
 771   fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
 772 uint64_t fp_r6_cmp (SIM_STATE, uint64_t op1, uint64_t op2,
 773                       FP_formats fmt, int cond);
 774 #define R6Compare(op1,op2,fmt,cond) fp_r6_cmp(SIM_ARGS, op1, op2, fmt, cond)
 775 uint64_t fp_classify(SIM_STATE, uint64_t op, FP_formats fmt);
 776 #define Classify(op, fmt) fp_classify(SIM_ARGS, op, fmt)
 777 int fp_rint(SIM_STATE, uint64_t op, uint64_t *ans, FP_formats fmt);
 778 #define RoundToIntegralExact(op, ans, fmt) fp_rint(SIM_ARGS, op, ans, fmt)
 779 uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt);
 780 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 781 uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt);
 782 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
 783 uint64_t fp_add (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 784 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
 785 uint64_t fp_sub (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 786 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
 787 uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 788 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
 789 uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 790 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
 791 uint64_t fp_min (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 792 #define Min(op1,op2,fmt) fp_min(SIM_ARGS, op1, op2, fmt)
 793 uint64_t fp_max (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 794 #define Max(op1,op2,fmt) fp_max(SIM_ARGS, op1, op2, fmt)
 795 uint64_t fp_mina (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 796 #define MinA(op1,op2,fmt) fp_mina(SIM_ARGS, op1, op2, fmt)
 797 uint64_t fp_maxa (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 798 #define MaxA(op1,op2,fmt) fp_maxa(SIM_ARGS, op1, op2, fmt)
 799 uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt);
 800 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 801 uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt);
 802 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 803 uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt);
 804 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
 805 uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2,
 806                     uint64_t op3, FP_formats fmt);
 807 #define FusedMultiplyAdd(op1,op2,op3,fmt) fp_fmadd(SIM_ARGS, op1, op2, op3, fmt)
 808 uint64_t fp_fmadd (SIM_STATE, uint64_t op1, uint64_t op2,
 809                      uint64_t op3, FP_formats fmt);
 810 #define FusedMultiplySub(op1,op2,op3,fmt) fp_fmsub(SIM_ARGS, op1, op2, op3, fmt)
 811 uint64_t fp_fmsub (SIM_STATE, uint64_t op1, uint64_t op2,
 812                      uint64_t op3, FP_formats fmt);
 813 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
 814 uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2,
 815                     uint64_t op3, FP_formats fmt);
 816 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
 817 uint64_t fp_nmadd (SIM_STATE, uint64_t op1, uint64_t op2,
 818                      uint64_t op3, FP_formats fmt);
 819 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
 820 uint64_t fp_nmsub (SIM_STATE, uint64_t op1, uint64_t op2,
 821                      uint64_t op3, FP_formats fmt);
 822 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
 823 uint64_t convert (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to);
 824 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 825 uint64_t convert_ps (SIM_STATE, int rm, uint64_t op, FP_formats from,
 826                        FP_formats to);
 827 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
 828
 829
 830 /* MIPS-3D ASE operations.  */
 831 #define CompareAbs(op1,op2,fmt,cond,cc) \
 832 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
 833 uint64_t fp_add_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 834 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
 835 uint64_t fp_mul_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 836 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
 837 uint64_t fp_recip1 (SIM_STATE, uint64_t op, FP_formats fmt);
 838 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
 839 uint64_t fp_recip2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 840 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
 841 uint64_t fp_rsqrt1 (SIM_STATE, uint64_t op, FP_formats fmt);
 842 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
 843 uint64_t fp_rsqrt2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
 844 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
 845
 846
 847 /* MDMX access.  */
 848
 849 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 850 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 851 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 852
 853 #define fmt_mdmx fmt_uninterpreted
 854
 855 #define MX_VECT_AND  (0)
 856 #define MX_VECT_NOR  (1)
 857 #define MX_VECT_OR   (2)
 858 #define MX_VECT_XOR  (3)
 859 #define MX_VECT_SLL  (4)
 860 #define MX_VECT_SRL  (5)
 861 #define MX_VECT_ADD  (6)
 862 #define MX_VECT_SUB  (7)
 863 #define MX_VECT_MIN  (8)
 864 #define MX_VECT_MAX  (9)
 865 #define MX_VECT_MUL  (10)
 866 #define MX_VECT_MSGN (11)
 867 #define MX_VECT_SRA  (12)
 868 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 869 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 870
 871 uint64_t mdmx_cpr_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel);
 872 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 873 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 874 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 875 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 876 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 877 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 878 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 879 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 880 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 881 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 882 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 883 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 884 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 885 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 886 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 887
 888 #define MX_C_EQ  0x1
 889 #define MX_C_LT  0x4
 890
 891 void mdmx_cc_op (SIM_STATE, int cond, uint64_t op1, int vt, MX_fmtsel fmtsel);
 892 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 893
 894 uint64_t mdmx_pick_op (SIM_STATE, int tf, uint64_t op1, int vt, MX_fmtsel fmtsel);
 895 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 896
 897 #define MX_VECT_ADDA  (0)
 898 #define MX_VECT_ADDL  (1)
 899 #define MX_VECT_MULA  (2)
 900 #define MX_VECT_MULL  (3)
 901 #define MX_VECT_MULS  (4)
 902 #define MX_VECT_MULSL (5)
 903 #define MX_VECT_SUBA  (6)
 904 #define MX_VECT_SUBL  (7)
 905 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 906
 907 void mdmx_acc_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel);
 908 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 909 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 910 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 911 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 912 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 913 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 914 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 915 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 916 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 917
 918 #define MX_FMT_OB   (0)
 919 #define MX_FMT_QH   (1)
 920
 921 /* The following codes chosen to indicate the units of shift.  */
 922 #define MX_RAC_L    (0)
 923 #define MX_RAC_M    (1)
 924 #define MX_RAC_H    (2)
 925
 926 uint64_t mdmx_rac_op (SIM_STATE, int, int);
 927 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 928
 929 void mdmx_wacl (SIM_STATE, int, uint64_t, uint64_t);
 930 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 931 void mdmx_wach (SIM_STATE, int, uint64_t);
 932 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 933
 934 #define MX_RND_AS   (0)
 935 #define MX_RND_AU   (1)
 936 #define MX_RND_ES   (2)
 937 #define MX_RND_EU   (3)
 938 #define MX_RND_ZS   (4)
 939 #define MX_RND_ZU   (5)
 940
 941 uint64_t mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 942 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 943 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 944 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 945 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 946 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 947 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 948
 949 uint64_t mdmx_shuffle (SIM_STATE, int, uint64_t, uint64_t);
 950 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 951
 952
 953
 954 /* Memory accesses */
 955
 956 /* The following are generic to all versions of the MIPS architecture
 957    to date: */
 958
 959 #define isINSTRUCTION   (1 == 0) /* FALSE */
 960 #define isDATA          (1 == 1) /* TRUE */
 961 #define isLOAD          (1 == 0) /* FALSE */
 962 #define isSTORE         (1 == 1) /* TRUE */
 963 #define isREAL          (1 == 0) /* FALSE */
 964 #define isRAW           (1 == 1) /* TRUE */
 965 /* The parameter HOST (isTARGET / isHOST) is ignored */
 966 #define isTARGET        (1 == 0) /* FALSE */
 967 /* #define isHOST          (1 == 1) TRUE */
 968
 969 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 970    is the number of bytes minus 1. */
 971 #define AccessLength_BYTE       (0)
 972 #define AccessLength_HALFWORD   (1)
 973 #define AccessLength_TRIPLEBYTE (2)
 974 #define AccessLength_WORD       (3)
 975 #define AccessLength_QUINTIBYTE (4)
 976 #define AccessLength_SEXTIBYTE  (5)
 977 #define AccessLength_SEPTIBYTE  (6)
 978 #define AccessLength_DOUBLEWORD (7)
 979 #define AccessLength_QUADWORD   (15)
 980
 981 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 982                     ? AccessLength_DOUBLEWORD /*7*/ \
 983                     : AccessLength_WORD /*3*/)
 984
 985 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
 986 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
 987 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
 988
 989 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
 990 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 991 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 992
 993 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
 994 #define CacheOp(op,pAddr,vAddr,instruction) \
 995 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 996
 997 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
 998 #define SyncOperation(stype) \
 999 sync_operation (SD, CPU, cia, (stype))
1000
1001 void unpredictable_action (sim_cpu *cpu, address_word cia);
1002 #define NotWordValue(val)       not_word_value (SD_, (val))
1003 #define Unpredictable()         unpredictable (SD_)
1004 #define UnpredictableResult()   /* For now, do nothing.  */
1005
1006 INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
1007 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
1008 INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
1009 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
1010 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
1011 #define IMEM32_MICROMIPS(CIA) \
1012   (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \
1013                                                       (CIA + 2)))
1014 #define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA)))
1015
1016 #define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10)
1017
1018 #define MICROMIPS_DELAYSLOT_SIZE_ANY 0
1019 #define MICROMIPS_DELAYSLOT_SIZE_16 2
1020 #define MICROMIPS_DELAYSLOT_SIZE_32 4
1021
1022 extern int isa_mode;
1023
1024 #define ISA_MODE_MIPS32 0
1025 #define ISA_MODE_MICROMIPS 1
1026
1027 address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
1028                                            address_word cia,
1029                                            int instruction_size);
1030
1031 #if WITH_TRACE_ANY_P
1032 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, const char *comment, ...) ATTRIBUTE_PRINTF (7, 8);
1033 extern FILE *tracefh;
1034 #else
1035 #define dotrace(sd, cpu, tracefh, type, address, width, comment, ...)
1036 #endif
1037
1038 extern int DSPLO_REGNUM[4];
1039 extern int DSPHI_REGNUM[4];
1040
1041 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
1042 extern SIM_CORE_SIGNAL_FN mips_core_signal;
1043
1044 char* pr_addr (SIM_ADDR addr);
1045 char* pr_uword64 (uword64 addr);
1046
1047
1048 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
1049
1050 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
1051 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
1052 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
1053
1054 #ifdef MIPS_MACH_MULTI
1055 extern int mips_mach_multi(SIM_DESC sd);
1056 #define MIPS_MACH(SD)   mips_mach_multi(SD)
1057 #else
1058 #define MIPS_MACH(SD)   MIPS_MACH_DEFAULT
1059 #endif
1060
1061 /* Macros for determining whether a MIPS IV or MIPS V part is subject
1062    to the hi/lo restrictions described in mips.igen.  */
1063
1064 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
1065   (MIPS_MACH (SD) != bfd_mach_mips5500)
1066
1067 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1068   (MIPS_MACH (SD) != bfd_mach_mips5500)
1069
1070 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1071   (MIPS_MACH (SD) != bfd_mach_mips5500)
1072
1073 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1074 #include "sim-main.c"
1075 #endif
1076
1077 #endif