sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 #include "sim-fpu.h"
  80
  81 /* FPU registers must be one of the following types. All other values
  82    are reserved (and undefined). */
  83 typedef enum {
  84  fmt_single  = 0,
  85  fmt_double  = 1,
  86  fmt_word    = 4,
  87  fmt_long    = 5,
  88  /* The following are well outside the normal acceptable format
  89     range, and are used in the register status vector. */
  90  fmt_unknown       = 0x10000000,
  91  fmt_uninterpreted = 0x20000000,
  92  fmt_uninterpreted_32 = 0x40000000,
  93  fmt_uninterpreted_64 = 0x80000000,
  94 } FP_formats;
  95
  96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
  97 #define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
  98
  99 void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
 101
 102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 115 #define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
 116
 117 /* Macro to update FPSR condition-code field. This is complicated by
 118    the fact that there is a hole in the index range of the bits within
 119    the FCSR register. Also, the number of bits visible depends on the
 120    MIPS ISA version being supported. */
 121
 122 #define SETFCC(cc,v) {\
 123   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 124   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 125 }
 126 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 127
 128 /* This should be the COC1 value at the start of the preceding
 129    instruction: */
 130 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 131
 132 #if 1
 133 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 134 #else
 135 /* They depend on the CPU being simulated */
 136 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 137 #endif
 138
 139 /* Standard FCRS bits: */
 140 #define IR (0) /* Inexact Result */
 141 #define UF (1) /* UnderFlow */
 142 #define OF (2) /* OverFlow */
 143 #define DZ (3) /* Division by Zero */
 144 #define IO (4) /* Invalid Operation */
 145 #define UO (5) /* Unimplemented Operation */
 146
 147 /* Get masks for individual flags: */
 148 #if 1 /* SAFE version */
 149 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 150 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 151 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 152 #else
 153 #define FP_FLAGS(b)  (1 << ((b) + 2))
 154 #define FP_ENABLE(b) (1 << ((b) + 7))
 155 #define FP_CAUSE(b)  (1 << ((b) + 12))
 156 #endif
 157
 158 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 159
 160 #define FP_MASK_RM    (0x3)
 161 #define FP_SH_RM      (0)
 162 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 163 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 164 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 165 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 166 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 167
 168
 169
 170 /* Integer ALU operations: */
 171
 172 #include "sim-alu.h"
 173
 174 #define ALU32_END(ANS) \
 175   if (ALU32_HAD_OVERFLOW) \
 176     SignalExceptionIntegerOverflow (); \
 177   (ANS) = ALU32_OVERFLOW_RESULT
 178
 179
 180 #define ALU64_END(ANS) \
 181   if (ALU64_HAD_OVERFLOW) \
 182     SignalExceptionIntegerOverflow (); \
 183   (ANS) = ALU64_OVERFLOW_RESULT;
 184
 185 /* start-sanitize-r5900 */
 186
 187 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 188 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 189 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 190 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 191
 192 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 193 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 194 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 195 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 196
 197 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 198    T  - type of the sub part
 199    TC - # of T's in the mips part of the "register"
 200    I  - index (from 0) of desired sub part
 201    A  - low part of "register"
 202    A1 - high part of register
 203 */
 204 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 205 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 206    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 207       ? ((TC) - 1 - (I) % (TC)) \
 208       : ((I) % (TC)) \
 209       ) \
 210    ) \
 211  )
 212
 213 /*
 214 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 215             where <type> has two letters:
 216                   1 is S=signed or U=unsigned
 217                   2 is B=byte H=halfword W=word D=doubleword
 218 */
 219
 220 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 221 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 222 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 223 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 224
 225 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 226 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 227 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 228 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 229
 230 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 231 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 232 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 233 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 234
 235 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 236 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 237 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 238 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 239
 240
 241 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 242 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 243 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 244 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 245
 246 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 247 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 248 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 249 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 250
 251 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 252 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 253 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 254 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 255
 256 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 257 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 258 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 259 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 260
 261
 262
 263 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 264 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 265 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 266 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 267
 268 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 269 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 270 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 271 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 272
 273 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 274 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 275 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 276 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 277
 278 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 279 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 280 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 281 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 282
 283 /* end-sanitize-r5900 */
 284
 285
 286
 287
 288 struct _sim_cpu {
 289
 290
 291   /* The following are internal simulator state variables: */
 292 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 293 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 294   address_word dspc;  /* delay-slot PC */
 295 #define DSPC ((STATE_CPU (sd,0))->dspc)
 296
 297   /* Issue a delay slot instruction immediatly by re-calling
 298      idecode_issue */
 299 #define DELAY_SLOT(TARGET) \
 300   do { \
 301     address_word target = (TARGET); \
 302     instruction_word delay_insn; \
 303     sim_events_slip (sd, 1); \
 304     CIA = CIA + 4; \
 305     STATE |= simDELAYSLOT; \
 306     delay_insn = IMEM (CIA); \
 307     idecode_issue (sd, delay_insn, (CIA)); \
 308     STATE &= ~simDELAYSLOT; \
 309     NIA = target; \
 310   } while (0)
 311 #define NULLIFY_NEXT_INSTRUCTION() \
 312   do { \
 313     sim_events_slip (sd, 1); \
 314     dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
 315     NIA = CIA + 8; \
 316   } while (0)
 317
 318
 319
 320   /* State of the simulator */
 321   unsigned int state;
 322   unsigned int dsstate;
 323 #define STATE ((STATE_CPU (sd,0))->state)
 324 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 325
 326 /* Flags in the "state" variable: */
 327 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 328 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 329 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 330 #define simPCOC0        (1 << 17) /* COC[1] from current */
 331 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 332 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 333 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 334 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 335 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 336
 337 #define ENGINE_ISSUE_PREFIX_HOOK() \
 338   { \
 339     /* Set previous flag, depending on current: */ \
 340     if (STATE & simPCOC0) \
 341      STATE |= simPCOC1; \
 342     else \
 343      STATE &= ~simPCOC1; \
 344     /* and update the current value: */ \
 345     if (GETFCC(0)) \
 346      STATE |= simPCOC0; \
 347     else \
 348      STATE &= ~simPCOC0; \
 349   }
 350
 351
 352 /* This is nasty, since we have to rely on matching the register
 353    numbers used by GDB. Unfortunately, depending on the MIPS target
 354    GDB uses different register numbers. We cannot just include the
 355    relevant "gdb/tm.h" link, since GDB may not be configured before
 356    the sim world, and also the GDB header file requires too much other
 357    state. */
 358
 359 #ifndef TM_MIPS_H
 360 #define LAST_EMBED_REGNUM (89)
 361 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 362 /* start-sanitize-r5900 */
 363 #undef NUM_REGS
 364 #define NUM_REGS (128)
 365 /* end-sanitize-r5900 */
 366 #endif
 367
 368 /* To keep this default simulator simple, and fast, we use a direct
 369    vector of registers. The internal simulator engine then uses
 370    manifests to access the correct slot. */
 371
 372   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 373   int register_widths[NUM_REGS];
 374 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 375
 376 #define GPR     (&REGISTERS[0])
 377 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 378 #define FGRIDX  (38)
 379 #define FGR     (&REGISTERS[FGRIDX])
 380 #define LO      (REGISTERS[33])
 381 #define HI      (REGISTERS[34])
 382 #define PCIDX   37
 383 #define PC      (REGISTERS[PCIDX])
 384 #define CAUSE   (REGISTERS[36])
 385 #define SRIDX   (32)
 386 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 387 #define FCR0IDX  (71)
 388 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 389 #define FCR31IDX (70)
 390 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 391 #define FCSR    (FCR31)
 392 #define Debug   (REGISTERS[86])
 393 #define DEPC    (REGISTERS[87])
 394 #define EPC     (REGISTERS[88])
 395 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 396
 397   unsigned_word c0_config_reg;
 398 #define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
 399
 400 /* The following are pseudonyms for standard registers */
 401 #define ZERO    (REGISTERS[0])
 402 #define V0      (REGISTERS[2])
 403 #define A0      (REGISTERS[4])
 404 #define A1      (REGISTERS[5])
 405 #define A2      (REGISTERS[6])
 406 #define A3      (REGISTERS[7])
 407 #define SP      (REGISTERS[29])
 408 #define RA      (REGISTERS[31])
 409
 410   /* Keep the current format state for each register: */
 411   FP_formats fpr_state[32];
 412 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 413
 414
 415   /* Slots for delayed register updates. For the moment we just have a
 416      fixed number of slots (rather than a more generic, dynamic
 417      system). This keeps the simulator fast. However, we only allow
 418      for the register update to be delayed for a single instruction
 419      cycle. */
 420 #define PSLOTS (5) /* Maximum number of instruction cycles */
 421   int pending_in;
 422   int pending_out;
 423   int pending_total;
 424   int pending_slot_count[PSLOTS];
 425   int pending_slot_reg[PSLOTS];
 426   unsigned_word pending_slot_value[PSLOTS];
 427 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 428 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 429 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 430 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 431 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 432 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 433
 434   /* The following are not used for MIPS IV onwards: */
 435 #define PENDING_FILL(r,v) {\
 436 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 437                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 438                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 439                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 440                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 441                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 442 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 443                             PENDING_TOTAL++;\
 444                             PENDING_IN++;\
 445                             if (PENDING_IN == PSLOTS)\
 446                              PENDING_IN = 0;\
 447 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 448                           }
 449
 450
 451   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 452      read-write instructions. It is set when a linked load occurs. It
 453      is tested and cleared by the conditional store. It is cleared
 454      (during other CPU operations) when a store to the location would
 455      no longer be atomic. In particular, it is cleared by exception
 456      return instructions. */
 457   int llbit;
 458 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 459
 460
 461 /* The HIACCESS and LOACCESS counts are used to ensure that
 462    corruptions caused by using the HI or LO register to close to a
 463    following operation are spotted. */
 464
 465   int hiaccess;
 466   int loaccess;
 467 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 468 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 469   /* start-sanitize-r5900 */
 470   int hi1access;
 471   int lo1access;
 472 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 473 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 474   /* end-sanitize-r5900 */
 475 #if 1
 476   /* The 4300 and a few other processors have interlocks on hi/lo
 477      register reads, and hence do not have this problem.  To avoid
 478      spurious warnings, we just disable this always.  */
 479 #define CHECKHILO(s)
 480 #else
 481   unsigned_word HLPC;
 482   /* If either of the preceding two instructions have accessed the HI
 483      or LO registers, then the values they see should be
 484      undefined. However, to keep the simulator world simple, we just
 485      let them use the value read and raise a warning to notify the
 486      user: */
 487 #define CHECKHILO(s) {\
 488   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 489     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 490 }
 491   /* start-sanitize-r5900 */
 492 #undef CHECKHILO
 493 #define CHECKHILO(s) {\
 494   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 495     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 496 }
 497   /* end-sanitize-r5900 */
 498 #endif
 499
 500
 501   /* start-sanitize-r5900 */
 502   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 503      touched by multimedia (MMI) instructions.  The normal mips
 504      instructions just use the lower 64 bits.  To avoid changing the
 505      older parts of the simulator to handle this weirdness, the high
 506      64 bits of each register are kept in a separate array
 507      (registers1).  The high 64 bits of any register are by convention
 508      refered by adding a '1' to the end of the normal register's name.
 509      So LO still refers to the low 64 bits of the LO register, LO1
 510      refers to the high 64 bits of that same register.  */
 511
 512   signed_word registers1[LAST_EMBED_REGNUM + 1];
 513 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 514 #define GPR1     (&REGISTERS1[0])
 515 #define LO1      (REGISTERS1[32])
 516 #define HI1      (REGISTERS1[33])
 517 #define REGISTER_SA     (124)
 518
 519   unsigned_word sa;        /* the shift amount register */
 520 #define SA ((STATE_CPU (sd, 0))->sa)
 521
 522   /* end-sanitize-r5900 */
 523   /* start-sanitize-vr5400 */
 524
 525   /* The MDMX ISA has a very very large accumulator */
 526   unsigned8 acc[3 * 8];
 527   /* end-sanitize-vr5400 */
 528
 529   sim_cpu_base base;
 530 };
 531
 532
 533 /* MIPS specific simulator watch config */
 534
 535 void watch_options_install PARAMS ((SIM_DESC sd));
 536
 537 struct swatch {
 538   sim_event *pc;
 539   sim_event *clock;
 540   sim_event *cycles;
 541 };
 542
 543
 544 /* FIXME: At present much of the simulator is still static */
 545 struct sim_state {
 546
 547   struct swatch watch;
 548
 549   sim_cpu cpu[1];
 550 #if (WITH_SMP)
 551 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 552 #else
 553 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 554 #endif
 555
 556   sim_state_base base;
 557 };
 558
 559
 560
 561 /* Status information: */
 562
 563 /* TODO : these should be the bitmasks for these bits within the
 564    status register. At the moment the following are VR4300
 565    bit-positions: */
 566 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 567 #define status_KSU_shift (3)            /* shift for field */
 568 #define ksu_kernel       (0x0)
 569 #define ksu_supervisor   (0x1)
 570 #define ksu_user         (0x2)
 571 #define ksu_unknown      (0x3)
 572
 573 #define status_IE        (1 <<  0)      /* Interrupt enable */
 574 #define status_EXL       (1 <<  1)      /* Exception level */
 575 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 576 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 577 #define status_SR        (1 << 20)      /* soft reset or NMI */
 578 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 579 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 580 #define status_ERL       (1 <<  2)      /* Error level */
 581 #define status_RP        (1 << 27)      /* Reduced Power mode */
 582
 583 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 584
 585 /* NOTE: We keep the following status flags as bit values (1 for true,
 586    0 for false). This allows them to be used in binary boolean
 587    operations without worrying about what exactly the non-zero true
 588    value is. */
 589
 590 /* UserMode */
 591 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 592
 593 /* BigEndianMem */
 594 /* Hardware configuration. Affects endianness of LoadMemory and
 595    StoreMemory and the endianness of Kernel and Supervisor mode
 596    execution. The value is 0 for little-endian; 1 for big-endian. */
 597 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 598 /*(state & simBE) ? 1 : 0)*/
 599
 600 /* ReverseEndian */
 601 /* This mode is selected if in User mode with the RE bit being set in
 602    SR (Status Register). It reverses the endianness of load and store
 603    instructions. */
 604 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 605
 606 /* BigEndianCPU */
 607 /* The endianness for load and store instructions (0=little;1=big). In
 608    User mode this endianness may be switched by setting the state_RE
 609    bit in the SR register. Thus, BigEndianCPU may be computed as
 610    (BigEndianMem EOR ReverseEndian). */
 611 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 612
 613
 614
 615 /* Exceptions: */
 616
 617 /* NOTE: These numbers depend on the processor architecture being
 618    simulated: */
 619 #define Interrupt               (0)
 620 #define TLBModification         (1)
 621 #define TLBLoad                 (2)
 622 #define TLBStore                (3)
 623 #define AddressLoad             (4)
 624 #define AddressStore            (5)
 625 #define InstructionFetch        (6)
 626 #define DataReference           (7)
 627 #define SystemCall              (8)
 628 #define BreakPoint              (9)
 629 #define ReservedInstruction     (10)
 630 #define CoProcessorUnusable     (11)
 631 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 632 #define Trap                    (13)
 633 #define FPE                     (15)
 634 #define DebugBreakPoint         (16)
 635 #define Watch                   (23)
 636
 637 /* The following exception code is actually private to the simulator
 638    world. It is *NOT* a processor feature, and is used to signal
 639    run-time errors in the simulator. */
 640 #define SimulatorFault      (0xFFFFFFFF)
 641
 642 void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
 643 #define SignalException(exc,instruction)     signal_exception (sd, cia, (exc), (instruction))
 644 #define SignalExceptionInterrupt()           signal_exception (sd, NULL_CIA, Interrupt)
 645 #define SignalExceptionInstructionFetch()    signal_exception (sd, cia, InstructionFetch)
 646 #define SignalExceptionAddressStore()        signal_exception (sd, cia, AddressStore)
 647 #define SignalExceptionAddressLoad()         signal_exception (sd, cia, AddressLoad)
 648 #define SignalExceptionSimulatorFault(buf)   signal_exception (sd, cia, SimulatorFault, buf)
 649 #define SignalExceptionFPE()                 signal_exception (sd, cia, FPE)
 650 #define SignalExceptionIntegerOverflow()     signal_exception (sd, cia, IntegerOverflow)
 651 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
 652
 653
 654 /* Co-processor accesses */
 655
 656 void cop_lw  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 657 void cop_ld  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 658 unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 659 uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 660
 661 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
 662 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
 663 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
 664 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
 665
 666 void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
 667 #define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
 668
 669
 670
 671 /* Memory accesses */
 672
 673 /* The following are generic to all versions of the MIPS architecture
 674    to date: */
 675
 676 /* Memory Access Types (for CCA): */
 677 #define Uncached                (0)
 678 #define CachedNoncoherent       (1)
 679 #define CachedCoherent          (2)
 680 #define Cached                  (3)
 681
 682 #define isINSTRUCTION   (1 == 0) /* FALSE */
 683 #define isDATA          (1 == 1) /* TRUE */
 684 #define isLOAD          (1 == 0) /* FALSE */
 685 #define isSTORE         (1 == 1) /* TRUE */
 686 #define isREAL          (1 == 0) /* FALSE */
 687 #define isRAW           (1 == 1) /* TRUE */
 688 /* The parameter HOST (isTARGET / isHOST) is ignored */
 689 #define isTARGET        (1 == 0) /* FALSE */
 690 /* #define isHOST          (1 == 1) TRUE */
 691
 692 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 693    is the number of bytes minus 1. */
 694 #define AccessLength_BYTE       (0)
 695 #define AccessLength_HALFWORD   (1)
 696 #define AccessLength_TRIPLEBYTE (2)
 697 #define AccessLength_WORD       (3)
 698 #define AccessLength_QUINTIBYTE (4)
 699 #define AccessLength_SEXTIBYTE  (5)
 700 #define AccessLength_SEPTIBYTE  (6)
 701 #define AccessLength_DOUBLEWORD (7)
 702 #define AccessLength_QUADWORD   (15)
 703
 704 int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 705 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 706 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
 707
 708 void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 709 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 710 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
 711
 712 void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 713 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 714 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
 715
 716 void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 717 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
 718
 719 void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
 720 #define SyncOperation(stype) sync_operation (sd, cia, (stype))
 721
 722 void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 723 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
 724
 725 unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
 726 #define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
 727
 728 void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 729 FILE *tracefh;
 730
 731 #endif