sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Depreciated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Check if a value will fit within a halfword: */
  60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  61
  62
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67
  68 /* FPU registers must be one of the following types. All other values
  69    are reserved (and undefined). */
  70 typedef enum {
  71  fmt_single  = 0,
  72  fmt_double  = 1,
  73  fmt_word    = 4,
  74  fmt_long    = 5,
  75  /* The following are well outside the normal acceptable format
  76     range, and are used in the register status vector. */
  77  fmt_unknown       = 0x10000000,
  78  fmt_uninterpreted = 0x20000000,
  79  fmt_uninterpreted_32 = 0x40000000,
  80  fmt_uninterpreted_64 = 0x80000000U,
  81 } FP_formats;
  82
  83 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  84 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  85
  86 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  87 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
  88
  89 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
  90 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
  91 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  92 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  93 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
  94 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
  95 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  96 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  97 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  98 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  99 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 100 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 101 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 102 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 103 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 104 #define Convert(rm,op,from,to) \
 105 convert (SD, CPU, cia, rm, op, from, to)
 106
 107 /* Macro to update FPSR condition-code field. This is complicated by
 108    the fact that there is a hole in the index range of the bits within
 109    the FCSR register. Also, the number of bits visible depends on the
 110    MIPS ISA version being supported. */
 111
 112 #define SETFCC(cc,v) {\
 113   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 114   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 115 }
 116 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 117
 118 /* This should be the COC1 value at the start of the preceding
 119    instruction: */
 120 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 121
 122 #ifdef TARGET_ENABLE_FR
 123 /* FIXME: this should be enabled for all targets, but needs testing first. */
 124 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
 125    ? ((SR & status_FR) ? 64 : 32) \
 126    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 127 #else
 128 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 129 #endif
 130
 131 /* Standard FCRS bits: */
 132 #define IR (0) /* Inexact Result */
 133 #define UF (1) /* UnderFlow */
 134 #define OF (2) /* OverFlow */
 135 #define DZ (3) /* Division by Zero */
 136 #define IO (4) /* Invalid Operation */
 137 #define UO (5) /* Unimplemented Operation */
 138
 139 /* Get masks for individual flags: */
 140 #if 1 /* SAFE version */
 141 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 142 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 143 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 144 #else
 145 #define FP_FLAGS(b)  (1 << ((b) + 2))
 146 #define FP_ENABLE(b) (1 << ((b) + 7))
 147 #define FP_CAUSE(b)  (1 << ((b) + 12))
 148 #endif
 149
 150 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 151
 152 #define FP_MASK_RM    (0x3)
 153 #define FP_SH_RM      (0)
 154 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 155 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 156 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 157 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 158 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 159
 160
 161
 162
 163
 164
 165 /* HI/LO register accesses */
 166
 167 /* For some MIPS targets, the HI/LO registers have certain timing
 168    restrictions in that, for instance, a read of a HI register must be
 169    separated by at least three instructions from a preceeding read.
 170
 171    The struct below is used to record the last access by each of A MT,
 172    MF or other OP instruction to a HI/LO register.  See mips.igen for
 173    more details. */
 174
 175 typedef struct _hilo_access {
 176   signed64 timestamp;
 177   address_word cia;
 178 } hilo_access;
 179
 180 typedef struct _hilo_history {
 181   hilo_access mt;
 182   hilo_access mf;
 183   hilo_access op;
 184 } hilo_history;
 185
 186
 187
 188
 189 /* Integer ALU operations: */
 190
 191 #include "sim-alu.h"
 192
 193 #define ALU32_END(ANS) \
 194   if (ALU32_HAD_OVERFLOW) \
 195     SignalExceptionIntegerOverflow (); \
 196   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 197
 198
 199 #define ALU64_END(ANS) \
 200   if (ALU64_HAD_OVERFLOW) \
 201     SignalExceptionIntegerOverflow (); \
 202   (ANS) = ALU64_OVERFLOW_RESULT;
 203
 204
 205
 206
 207
 208 /* The following is probably not used for MIPS IV onwards: */
 209 /* Slots for delayed register updates. For the moment we just have a
 210    fixed number of slots (rather than a more generic, dynamic
 211    system). This keeps the simulator fast. However, we only allow
 212    for the register update to be delayed for a single instruction
 213    cycle. */
 214 #define PSLOTS (8) /* Maximum number of instruction cycles */
 215
 216 typedef struct _pending_write_queue {
 217   int in;
 218   int out;
 219   int total;
 220   int slot_delay[PSLOTS];
 221   int slot_size[PSLOTS];
 222   int slot_bit[PSLOTS];
 223   void *slot_dest[PSLOTS];
 224   unsigned64 slot_value[PSLOTS];
 225 } pending_write_queue;
 226
 227 #ifndef PENDING_TRACE
 228 #define PENDING_TRACE 0
 229 #endif
 230 #define PENDING_IN ((CPU)->pending.in)
 231 #define PENDING_OUT ((CPU)->pending.out)
 232 #define PENDING_TOTAL ((CPU)->pending.total)
 233 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 234 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 235 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 236 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 237 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 238
 239 /* Invalidate the pending write queue, all pending writes are
 240    discarded. */
 241
 242 #define PENDING_INVALIDATE() \
 243 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 244
 245 /* Schedule a write to DEST for N cycles time.  For 64 bit
 246    destinations, schedule two writes.  For floating point registers,
 247    the caller should schedule a write to both the dest register and
 248    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 249    is updated. */
 250
 251 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 252   do {                                                                  \
 253     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 254       sim_engine_abort (SD, CPU, cia,                                   \
 255                         "PENDING_SCHED - buffer overflow\n");           \
 256     if (PENDING_TRACE)                                                  \
 257       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 258                       (unsigned long) cia, (unsigned long) &(DEST),     \
 259                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 260                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 261     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 262     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 263     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 264     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 265     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 266     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 267     PENDING_TOTAL += 1;                                                 \
 268   } while (0)
 269
 270 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 271 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 272
 273 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 274
 275 #define PENDING_FLUSH() abort () /* think about this one */
 276 #define PENDING_FP() abort () /* think about this one */
 277
 278 /* For backward compatibility */
 279 #define PENDING_FILL(R,VAL)                                             \
 280 do {                                                                    \
 281   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 282     {                                                                   \
 283       PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                     \
 284       PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
 285     }                                                                   \
 286   else                                                                  \
 287     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 288 } while (0)
 289
 290
 291 enum float_operation
 292   {
 293     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 294     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 295     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 296   };
 297
 298
 299 struct _sim_cpu {
 300
 301
 302   /* The following are internal simulator state variables: */
 303 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 304 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 305   address_word dspc;  /* delay-slot PC */
 306 #define DSPC ((CPU)->dspc)
 307
 308 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 309 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 310
 311
 312   /* State of the simulator */
 313   unsigned int state;
 314   unsigned int dsstate;
 315 #define STATE ((CPU)->state)
 316 #define DSSTATE ((CPU)->dsstate)
 317
 318 /* Flags in the "state" variable: */
 319 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 320 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 321 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 322 #define simPCOC0        (1 << 17) /* COC[1] from current */
 323 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 324 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 325 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 326 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 327 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 328
 329 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 330 #define ENGINE_ISSUE_PREFIX_HOOK() \
 331   { \
 332     /* Perform any pending writes */ \
 333     PENDING_TICK(); \
 334     /* Set previous flag, depending on current: */ \
 335     if (STATE & simPCOC0) \
 336      STATE |= simPCOC1; \
 337     else \
 338      STATE &= ~simPCOC1; \
 339     /* and update the current value: */ \
 340     if (GETFCC(0)) \
 341      STATE |= simPCOC0; \
 342     else \
 343      STATE &= ~simPCOC0; \
 344   }
 345 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 346
 347
 348 /* This is nasty, since we have to rely on matching the register
 349    numbers used by GDB. Unfortunately, depending on the MIPS target
 350    GDB uses different register numbers. We cannot just include the
 351    relevant "gdb/tm.h" link, since GDB may not be configured before
 352    the sim world, and also the GDB header file requires too much other
 353    state. */
 354
 355 #ifndef TM_MIPS_H
 356 #define LAST_EMBED_REGNUM (89)
 357 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 358
 359
 360 #endif
 361
 362
 363 /* To keep this default simulator simple, and fast, we use a direct
 364    vector of registers. The internal simulator engine then uses
 365    manifests to access the correct slot. */
 366
 367   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 368
 369   int register_widths[NUM_REGS];
 370 #define REGISTERS       ((CPU)->registers)
 371
 372 #define GPR     (&REGISTERS[0])
 373 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 374
 375   /* While space is allocated for the floating point registers in the
 376      main registers array, they are stored separatly.  This is because
 377      their size may not necessarily match the size of either the
 378      general-purpose or system specific registers */
 379 #define NR_FGR  (32)
 380 #define FGRIDX  (38)
 381   fp_word fgr[NR_FGR];
 382 #define FGR     ((CPU)->fgr)
 383
 384 #define LO      (REGISTERS[33])
 385 #define HI      (REGISTERS[34])
 386 #define PCIDX   37
 387 #define PC      (REGISTERS[PCIDX])
 388 #define CAUSE   (REGISTERS[36])
 389 #define SRIDX   (32)
 390 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 391 #define FCR0IDX  (71)
 392 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 393 #define FCR31IDX (70)
 394 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 395 #define FCSR    (FCR31)
 396 #define Debug   (REGISTERS[86])
 397 #define DEPC    (REGISTERS[87])
 398 #define EPC     (REGISTERS[88])
 399
 400   /* All internal state modified by signal_exception() that may need to be
 401      rolled back for passing moment-of-exception image back to gdb. */
 402   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 403   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 404   int exc_suspended;
 405
 406 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 407 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 408 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 409
 410   unsigned_word c0_config_reg;
 411 #define C0_CONFIG ((CPU)->c0_config_reg)
 412
 413 /* The following are pseudonyms for standard registers */
 414 #define ZERO    (REGISTERS[0])
 415 #define V0      (REGISTERS[2])
 416 #define A0      (REGISTERS[4])
 417 #define A1      (REGISTERS[5])
 418 #define A2      (REGISTERS[6])
 419 #define A3      (REGISTERS[7])
 420 #define T8IDX   24
 421 #define T8      (REGISTERS[T8IDX])
 422 #define SPIDX   29
 423 #define SP      (REGISTERS[SPIDX])
 424 #define RAIDX   31
 425 #define RA      (REGISTERS[RAIDX])
 426
 427   /* While space is allocated in the main registers arrray for some of
 428      the COP0 registers, that space isn't sufficient.  Unknown COP0
 429      registers overflow into the array below */
 430
 431 #define NR_COP0_GPR     32
 432   unsigned_word cop0_gpr[NR_COP0_GPR];
 433 #define COP0_GPR        ((CPU)->cop0_gpr)
 434 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 435
 436   /* Keep the current format state for each register: */
 437   FP_formats fpr_state[32];
 438 #define FPR_STATE ((CPU)->fpr_state)
 439
 440   pending_write_queue pending;
 441
 442   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 443      read-write instructions. It is set when a linked load occurs. It
 444      is tested and cleared by the conditional store. It is cleared
 445      (during other CPU operations) when a store to the location would
 446      no longer be atomic. In particular, it is cleared by exception
 447      return instructions. */
 448   int llbit;
 449 #define LLBIT ((CPU)->llbit)
 450
 451
 452 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 453    corruptions caused by using the HI or LO register too close to a
 454    following operation is spotted. See mips.igen for more details. */
 455
 456   hilo_history hi_history;
 457 #define HIHISTORY (&(CPU)->hi_history)
 458   hilo_history lo_history;
 459 #define LOHISTORY (&(CPU)->lo_history)
 460
 461 #define check_branch_bug()
 462 #define mark_branch_bug(TARGET)
 463
 464
 465
 466   sim_cpu_base base;
 467 };
 468
 469
 470 /* MIPS specific simulator watch config */
 471
 472 void watch_options_install PARAMS ((SIM_DESC sd));
 473
 474 struct swatch {
 475   sim_event *pc;
 476   sim_event *clock;
 477   sim_event *cycles;
 478 };
 479
 480
 481 /* FIXME: At present much of the simulator is still static */
 482 struct sim_state {
 483
 484   struct swatch watch;
 485
 486   sim_cpu cpu[MAX_NR_PROCESSORS];
 487 #if (WITH_SMP)
 488 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 489 #else
 490 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 491 #endif
 492
 493
 494   sim_state_base base;
 495 };
 496
 497
 498
 499 /* Status information: */
 500
 501 /* TODO : these should be the bitmasks for these bits within the
 502    status register. At the moment the following are VR4300
 503    bit-positions: */
 504 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 505 #define status_KSU_shift (3)            /* shift for field */
 506 #define ksu_kernel       (0x0)
 507 #define ksu_supervisor   (0x1)
 508 #define ksu_user         (0x2)
 509 #define ksu_unknown      (0x3)
 510
 511 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 512
 513 #define status_IE        (1 <<  0)      /* Interrupt enable */
 514 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 515 #define status_EXL       (1 <<  1)      /* Exception level */
 516 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 517 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 518 #define status_SR        (1 << 20)      /* soft reset or NMI */
 519 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 520 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 521 #define status_ERL       (1 <<  2)      /* Error level */
 522 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 523 #define status_RP        (1 << 27)      /* Reduced Power mode */
 524
 525 /* Specializations for TX39 family */
 526 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 527 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 528 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 529 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 530 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 531 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 532 #define status_IM_mask   (0xff)         /* Interrupt mask */
 533 #define status_IM_shift  (8)
 534 #define status_NMI       (1 << 20)      /* NMI */
 535 #define status_NMI       (1 << 20)      /* NMI */
 536
 537 /* Status bits used by MIPS32/MIPS64.  */
 538 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 539 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 540 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 541 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 542 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 543 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 544 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 545 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 546 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 547 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 548
 549 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 550 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 551 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 552 #define cause_CE_shift    28
 553 #define cause_EXC2_mask   0x00070000
 554 #define cause_EXC2_shift  16
 555 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 556 #define cause_SIOP        (1 << 12)     /* SIO pending */
 557 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 558 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 559
 560 #define cause_EXC_mask  (0x1c)          /* Exception code */
 561 #define cause_EXC_shift (2)
 562
 563 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 564 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 565 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 566 #define cause_IP_shift  (10)
 567
 568 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 569 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 570
 571
 572 /* NOTE: We keep the following status flags as bit values (1 for true,
 573    0 for false). This allows them to be used in binary boolean
 574    operations without worrying about what exactly the non-zero true
 575    value is. */
 576
 577 /* UserMode */
 578 #ifdef SUBTARGET_R3900
 579 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 580 #else
 581 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 582 #endif /* SUBTARGET_R3900 */
 583
 584 /* BigEndianMem */
 585 /* Hardware configuration. Affects endianness of LoadMemory and
 586    StoreMemory and the endianness of Kernel and Supervisor mode
 587    execution. The value is 0 for little-endian; 1 for big-endian. */
 588 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 589 /*(state & simBE) ? 1 : 0)*/
 590
 591 /* ReverseEndian */
 592 /* This mode is selected if in User mode with the RE bit being set in
 593    SR (Status Register). It reverses the endianness of load and store
 594    instructions. */
 595 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 596
 597 /* BigEndianCPU */
 598 /* The endianness for load and store instructions (0=little;1=big). In
 599    User mode this endianness may be switched by setting the state_RE
 600    bit in the SR register. Thus, BigEndianCPU may be computed as
 601    (BigEndianMem EOR ReverseEndian). */
 602 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 603
 604
 605
 606 /* Exceptions: */
 607
 608 /* NOTE: These numbers depend on the processor architecture being
 609    simulated: */
 610 enum ExceptionCause {
 611   Interrupt               = 0,
 612   TLBModification         = 1,
 613   TLBLoad                 = 2,
 614   TLBStore                = 3,
 615   AddressLoad             = 4,
 616   AddressStore            = 5,
 617   InstructionFetch        = 6,
 618   DataReference           = 7,
 619   SystemCall              = 8,
 620   BreakPoint              = 9,
 621   ReservedInstruction     = 10,
 622   CoProcessorUnusable     = 11,
 623   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 624   Trap                    = 13,
 625   FPE                     = 15,
 626   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 627   MDMX                    = 22,
 628   Watch                   = 23,
 629   MCheck                  = 24,
 630   CacheErr                = 30,
 631   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 632
 633
 634 /* The following exception code is actually private to the simulator
 635    world. It is *NOT* a processor feature, and is used to signal
 636    run-time errors in the simulator. */
 637   SimulatorFault          = 0xFFFFFFFF
 638 };
 639
 640 #define TLB_REFILL  (0)
 641 #define TLB_INVALID (1)
 642
 643
 644 /* The following break instructions are reserved for use by the
 645    simulator.  The first is used to halt the simulation.  The second
 646    is used by gdb for break-points.  NOTE: Care must be taken, since
 647    this value may be used in later revisions of the MIPS ISA. */
 648 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 649
 650 #define HALT_INSTRUCTION        (0x03ff000d)
 651 #define HALT_INSTRUCTION2       (0x0000ffcd)
 652
 653
 654 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 655 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 656
 657
 658
 659 void interrupt_event (SIM_DESC sd, void *data);
 660
 661 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 662 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 663 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 664 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 665 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 666 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 667 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 668 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 669 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 670 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 671 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 672 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 673 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 674 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 675 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 676 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 677 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 678 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 679 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 680 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 681 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 682
 683 /* Co-processor accesses */
 684
 685 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 686 #define COP_Usable(coproc_num)          (coproc_num == 1)
 687
 688 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 689 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 690 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 691 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 692
 693 #define COP_LW(coproc_num,coproc_reg,memword) \
 694 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 695 #define COP_LD(coproc_num,coproc_reg,memword) \
 696 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 697 #define COP_SW(coproc_num,coproc_reg) \
 698 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 699 #define COP_SD(coproc_num,coproc_reg) \
 700 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 701
 702
 703 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 704 #define DecodeCoproc(instruction) \
 705 decode_coproc (SD, CPU, cia, (instruction))
 706
 707 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 708
 709
 710
 711 /* Memory accesses */
 712
 713 /* The following are generic to all versions of the MIPS architecture
 714    to date: */
 715
 716 /* Memory Access Types (for CCA): */
 717 #define Uncached                (0)
 718 #define CachedNoncoherent       (1)
 719 #define CachedCoherent          (2)
 720 #define Cached                  (3)
 721
 722 #define isINSTRUCTION   (1 == 0) /* FALSE */
 723 #define isDATA          (1 == 1) /* TRUE */
 724 #define isLOAD          (1 == 0) /* FALSE */
 725 #define isSTORE         (1 == 1) /* TRUE */
 726 #define isREAL          (1 == 0) /* FALSE */
 727 #define isRAW           (1 == 1) /* TRUE */
 728 /* The parameter HOST (isTARGET / isHOST) is ignored */
 729 #define isTARGET        (1 == 0) /* FALSE */
 730 /* #define isHOST          (1 == 1) TRUE */
 731
 732 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 733    is the number of bytes minus 1. */
 734 #define AccessLength_BYTE       (0)
 735 #define AccessLength_HALFWORD   (1)
 736 #define AccessLength_TRIPLEBYTE (2)
 737 #define AccessLength_WORD       (3)
 738 #define AccessLength_QUINTIBYTE (4)
 739 #define AccessLength_SEXTIBYTE  (5)
 740 #define AccessLength_SEPTIBYTE  (6)
 741 #define AccessLength_DOUBLEWORD (7)
 742 #define AccessLength_QUADWORD   (15)
 743
 744 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 745                     ? AccessLength_DOUBLEWORD /*7*/ \
 746                     : AccessLength_WORD /*3*/)
 747 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 748
 749
 750 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 751 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 752 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 753
 754 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 755 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 756 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 757
 758 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 759 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 760 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 761
 762 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 763 #define CacheOp(op,pAddr,vAddr,instruction) \
 764 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 765
 766 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 767 #define SyncOperation(stype) \
 768 sync_operation (SD, CPU, cia, (stype))
 769
 770 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 771 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 772 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 773
 774 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 775 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 776 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 777 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 778 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 779
 780 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 781 extern FILE *tracefh;
 782
 783 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 784 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 785
 786 char* pr_addr PARAMS ((SIM_ADDR addr));
 787 char* pr_uword64 PARAMS ((uword64 addr));
 788
 789
 790 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 791
 792 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 793 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 794 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 795
 796
 797 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 798 #include "sim-main.c"
 799 #endif
 800
 801 #endif