sim/mn10300/ChangeLog

   1 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
   2
   3         * interp.c (sim_open): New arg `kind'.
   4
   5         * configure: Regenerated to track ../common/aclocal.m4 changes.
   6
   7 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
   8
   9         * configure: Regenerated to track ../common/aclocal.m4 changes.
  10
  11 Thu Mar 20 11:58:02 1997  Jeffrey A Law  (law@cygnus.com)
  12
  13         * simops.c: Fix register extraction for a two "movbu" variants.
  14         Somewhat simplify "sub" instructions.
  15         Correctly sign extend operands for "mul".  Put the correct
  16         half of the result in MDR for "mul" and "mulu".
  17         Implement remaining instructions.
  18         Tweak opcode for "syscall".
  19
  20 Tue Mar 18 14:21:21 1997  Jeffrey A Law  (law@cygnus.com)
  21
  22         * simops.c: Do syscall emulation in "syscall" instruction.  Add
  23         dummy "trap" instruction.
  24
  25 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  26
  27         * configure: Regenerated to track ../common/aclocal.m4 changes.
  28
  29 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  30
  31         * configure: Re-generate.
  32
  33 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
  34
  35         * configure: Regenerate to track ../common/aclocal.m4 changes.
  36
  37 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
  38
  39         * interp.c (sim_open): New SIM_DESC result.  Argument is now
  40         in argv form.
  41         (other sim_*): New SIM_DESC argument.
  42
  43 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
  44
  45         * simops.c: Fix carry bit computation for "add" instructions.
  46
  47         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
  48         for bset imm8,(d8,an) and bclr imm8,(d8,an).
  49
  50 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
  51
  52         * simops.c: Fix register references when computing Z and N bits
  53         for lsr imm8,dn.
  54
  55 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
  56
  57         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
  58         COMMON_{PRE,POST}_CONFIG_FRAG instead.
  59         * configure.in: sinclude ../common/aclocal.m4.
  60         * configure: Regenerated.
  61
  62 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
  63
  64         * interp.c (init_system): Allocate 2^19 bytes of space for the
  65         simulator.
  66
  67 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
  68
  69         * configure configure.in Makefile.in:  Update to new configure
  70         scheme which is more compatible with WinGDB builds.
  71         * configure.in:  Improve comment on how to run autoconf.
  72         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
  73         * Makefile.in:  Use autoconf substitution to install common
  74         makefile fragment.
  75
  76 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
  77
  78         * simops.c: Undo last change to "rol" and "ror", original code
  79         was correct!
  80
  81 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
  82
  83         * simops.c: Fix "rol" and "ror".
  84
  85 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
  86
  87         * simops.c: Fix typo in last change.
  88
  89 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  90
  91         * simops.c: Use REG macros in few places not using them yet.
  92
  93 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  94
  95         * mn10300_sim.h (struct _state): Fix number of registers!
  96
  97 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
  98
  99         * mn10300_sim.h (struct _state): Put all registers into a single
 100         array to make gdb implementation easier.
 101         (REG_*): Add definitions for all registers in the state array.
 102         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
 103         * simops.c: Related changes.
 104
 105 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 106
 107         * interp.c (sim_resume): Handle 0xff as a single byte insn.
 108
 109         * simops.c: Fix overflow computation for "add" and "inc"
 110         instructions.
 111
 112 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 113
 114         * simops.c: Handle "break" instruction.
 115
 116         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
 117
 118 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
 119
 120         * gencode.c (write_opcodes): Also write out the format of the
 121         opcode.
 122         * mn10300_sim.h (simops): Add "format" field.
 123         * interp.c (sim_resume): Deal with endianness issues here.
 124
 125 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 126
 127         * simops.c (REG0_4): Define.
 128         Use REG0_4 for indexed loads/stores.
 129
 130 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 131
 132         * simops.c (REG0_16): Fix typo.
 133
 134 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 135
 136         * simops.c: Call abort for any instruction that's not currently
 137         simulated.
 138
 139         * simops.c: Define accessor macros to extract register
 140         values from instructions.  Use them consistently.
 141
 142         * interp.c: Delete unused global variable "OP".
 143         (sim_resume): Remove unused variable "opcode".
 144         * simops.c: Fix some uninitialized variable problems, add
 145         parens to fix various -Wall warnings.
 146
 147         * gencode.c (write_header): Add "insn" and "extension" arguments
 148         to the OP_* declarations.
 149         (write_template): Similarly for function templates.
 150         * interp.c (insn, extension): Remove global variables.  Instead
 151         pass them as arguments to the OP_* functions.
 152         * mn10300_sim.h: Remove decls for "insn" and "extension".
 153         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 154         instead of using globals.
 155
 156 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 157
 158         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 159
 160         * simops.c: Fix thinkos in last change to "inc dn".
 161
 162 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 163
 164         * simops.c: "add imm,sp" does not effect the condition codes.
 165         "inc dn" does effect the condition codes.
 166
 167 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 168
 169         * simops.c: Treat both operands as signed values for
 170         "div" instruction.
 171
 172         * simops.c: Fix simulation of division instructions.
 173         Fix typos/thinkos in several "cmp" and "sub" instructions.
 174
 175 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 176
 177         * simops.c: Fix carry bit handling in "sub" and "cmp"
 178         instructions.
 179
 180         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 181
 182 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 183
 184         * simops.c: Fix overflow computation for many instructions.
 185
 186         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 187
 188         * simops.c: Fix "mov am, dn".
 189
 190         * simops.c: Fix more bugs in "add imm,an" and
 191         "add imm,dn".
 192
 193 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 194
 195         * simops.c: Fix bugs in "movm" and "add imm,an".
 196
 197         * simops.c: Don't lose the upper 24 bits of the return
 198         pointer in "call" and "calls" instructions.  Rough cut
 199         at emulated system calls.
 200
 201         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 202
 203         * simops.c: Implement remaining 4 byte instructions.
 204
 205         * simops.c: Implement remaining 3 byte instructions.
 206
 207         * simops.c: Implement remaining 2 byte instructions.  Call
 208         abort for instructions we're not implementing now.
 209
 210 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 211
 212         * simops.c: Implement lots of random instructions.
 213
 214         * simops.c: Implement "movm" and "bCC" insns.
 215
 216         * mn10300_sim.h (_state): Add another register (MDR).
 217         (REG_MDR): Define.
 218         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 219         a few additional random insns.
 220
 221         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 222         (REG_D0, REG_A0, REG_SP): Define.
 223         * simops.c: Implement "add", "addc" and a few other random
 224         instructions.
 225
 226         * gencode.c, interp.c: Snapshot current simulator code.
 227
 228 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 229
 230         * Makefile.in, config.in, configure, configure.in: New files.
 231         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 232