sim/mn10300/ChangeLog

   1 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Fix "rol" and "ror".
   4
   5 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
   6
   7         * simops.c: Fix typo in last change.
   8
   9 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  10
  11         * simops.c: Use REG macros in few places not using them yet.
  12
  13 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  14
  15         * mn10300_sim.h (struct _state): Fix number of registers!
  16
  17 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
  18
  19         * mn10300_sim.h (struct _state): Put all registers into a single
  20         array to make gdb implementation easier.
  21         (REG_*): Add definitions for all registers in the state array.
  22         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
  23         * simops.c: Related changes.
  24
  25 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
  26
  27         * interp.c (sim_resume): Handle 0xff as a single byte insn.
  28
  29         * simops.c: Fix overflow computation for "add" and "inc"
  30         instructions.
  31
  32 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
  33
  34         * simops.c: Handle "break" instruction.
  35
  36         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
  37
  38 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
  39
  40         * gencode.c (write_opcodes): Also write out the format of the
  41         opcode.
  42         * mn10300_sim.h (simops): Add "format" field.
  43         * interp.c (sim_resume): Deal with endianness issues here.
  44
  45 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
  46
  47         * simops.c (REG0_4): Define.
  48         Use REG0_4 for indexed loads/stores.
  49
  50 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
  51
  52         * simops.c (REG0_16): Fix typo.
  53
  54 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
  55
  56         * simops.c: Call abort for any instruction that's not currently
  57         simulated.
  58
  59         * simops.c: Define accessor macros to extract register
  60         values from instructions.  Use them consistently.
  61
  62         * interp.c: Delete unused global variable "OP".
  63         (sim_resume): Remove unused variable "opcode".
  64         * simops.c: Fix some uninitialized variable problems, add
  65         parens to fix various -Wall warnings.
  66
  67         * gencode.c (write_header): Add "insn" and "extension" arguments
  68         to the OP_* declarations.
  69         (write_template): Similarly for function templates.
  70         * interp.c (insn, extension): Remove global variables.  Instead
  71         pass them as arguments to the OP_* functions.
  72         * mn10300_sim.h: Remove decls for "insn" and "extension".
  73         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  74         instead of using globals.
  75
  76 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  77
  78         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  79
  80         * simops.c: Fix thinkos in last change to "inc dn".
  81
  82 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
  83
  84         * simops.c: "add imm,sp" does not effect the condition codes.
  85         "inc dn" does effect the condition codes.
  86
  87 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
  88
  89         * simops.c: Treat both operands as signed values for
  90         "div" instruction.
  91
  92         * simops.c: Fix simulation of division instructions.
  93         Fix typos/thinkos in several "cmp" and "sub" instructions.
  94
  95 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  96
  97         * simops.c: Fix carry bit handling in "sub" and "cmp"
  98         instructions.
  99
 100         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 101
 102 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 103
 104         * simops.c: Fix overflow computation for many instructions.
 105
 106         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 107
 108         * simops.c: Fix "mov am, dn".
 109
 110         * simops.c: Fix more bugs in "add imm,an" and
 111         "add imm,dn".
 112
 113 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 114
 115         * simops.c: Fix bugs in "movm" and "add imm,an".
 116
 117         * simops.c: Don't lose the upper 24 bits of the return
 118         pointer in "call" and "calls" instructions.  Rough cut
 119         at emulated system calls.
 120
 121         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 122
 123         * simops.c: Implement remaining 4 byte instructions.
 124
 125         * simops.c: Implement remaining 3 byte instructions.
 126
 127         * simops.c: Implement remaining 2 byte instructions.  Call
 128         abort for instructions we're not implementing now.
 129
 130 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 131
 132         * simops.c: Implement lots of random instructions.
 133
 134         * simops.c: Implement "movm" and "bCC" insns.
 135
 136         * mn10300_sim.h (_state): Add another register (MDR).
 137         (REG_MDR): Define.
 138         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 139         a few additional random insns.
 140
 141         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 142         (REG_D0, REG_A0, REG_SP): Define.
 143         * simops.c: Implement "add", "addc" and a few other random
 144         instructions.
 145
 146         * gencode.c, interp.c: Snapshot current simulator code.
 147
 148 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 149
 150         * Makefile.in, config.in, configure, configure.in: New files.
 151         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 152