sim/mn10300/ChangeLog

   1 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Fix "mov am, dn".
   4
   5         * simops.c: Fix more bugs in "add imm,an" and
   6         "add imm,dn".
   7
   8 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
   9
  10         * simops.c: Fix bugs in "movm" and "add imm,an".
  11
  12         * simops.c: Don't lose the upper 24 bits of the return
  13         pointer in "call" and "calls" instructions.  Rough cut
  14         at emulated system calls.
  15
  16         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  17
  18         * simops.c: Implement remaining 4 byte instructions.
  19
  20         * simops.c: Implement remaining 3 byte instructions.
  21
  22         * simops.c: Implement remaining 2 byte instructions.  Call
  23         abort for instructions we're not implementing now.
  24
  25 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
  26
  27         * simops.c: Implement lots of random instructions.
  28
  29         * simops.c: Implement "movm" and "bCC" insns.
  30
  31         * mn10300_sim.h (_state): Add another register (MDR).
  32         (REG_MDR): Define.
  33         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
  34         a few additional random insns.
  35
  36         * mn10300_sim.h (PSW_*): Define for CC status tracking.
  37         (REG_D0, REG_A0, REG_SP): Define.
  38         * simops.c: Implement "add", "addc" and a few other random
  39         instructions.
  40
  41         * gencode.c, interp.c: Snapshot current simulator code.
  42
  43 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
  44
  45         * Makefile.in, config.in, configure, configure.in: New files.
  46         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
  47