sim/mn10300/ChangeLog

   1 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * gencode.c (write_header): Add "insn" and "extension" arguments
   4         to the OP_* declarations.
   5         (write_template): Similarly for function templates.
   6         * interp.c (insn, extension): Remove global variables.  Instead
   7         pass them as arguments to the OP_* functions.
   8         * mn10300_sim.h: Remove decls for "insn" and "extension".
   9         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  10         instead of using globals.
  11
  12 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  13
  14         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  15
  16         * simops.c: Fix thinkos in last change to "inc dn".
  17
  18 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
  19
  20         * simops.c: "add imm,sp" does not effect the condition codes.
  21         "inc dn" does effect the condition codes.
  22
  23 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
  24
  25         * simops.c: Treat both operands as signed values for
  26         "div" instruction.
  27
  28         * simops.c: Fix simulation of division instructions.
  29         Fix typos/thinkos in several "cmp" and "sub" instructions.
  30
  31 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  32
  33         * simops.c: Fix carry bit handling in "sub" and "cmp"
  34         instructions.
  35
  36         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
  37
  38 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
  39
  40         * simops.c: Fix overflow computation for many instructions.
  41
  42         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
  43
  44         * simops.c: Fix "mov am, dn".
  45
  46         * simops.c: Fix more bugs in "add imm,an" and
  47         "add imm,dn".
  48
  49 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
  50
  51         * simops.c: Fix bugs in "movm" and "add imm,an".
  52
  53         * simops.c: Don't lose the upper 24 bits of the return
  54         pointer in "call" and "calls" instructions.  Rough cut
  55         at emulated system calls.
  56
  57         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  58
  59         * simops.c: Implement remaining 4 byte instructions.
  60
  61         * simops.c: Implement remaining 3 byte instructions.
  62
  63         * simops.c: Implement remaining 2 byte instructions.  Call
  64         abort for instructions we're not implementing now.
  65
  66 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
  67
  68         * simops.c: Implement lots of random instructions.
  69
  70         * simops.c: Implement "movm" and "bCC" insns.
  71
  72         * mn10300_sim.h (_state): Add another register (MDR).
  73         (REG_MDR): Define.
  74         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
  75         a few additional random insns.
  76
  77         * mn10300_sim.h (PSW_*): Define for CC status tracking.
  78         (REG_D0, REG_A0, REG_SP): Define.
  79         * simops.c: Implement "add", "addc" and a few other random
  80         instructions.
  81
  82         * gencode.c, interp.c: Snapshot current simulator code.
  83
  84 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
  85
  86         * Makefile.in, config.in, configure, configure.in: New files.
  87         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
  88