sim/mn10300/ChangeLog

   1 Fri Apr  4 20:02:37 1997  Ian Lance Taylor  <ian@cygnus.com>
   2
   3         * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
   4         corresponding change in opcodes directory.
   5
   6 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
   7
   8         * interp.c (sim_open): New arg `kind'.
   9
  10         * configure: Regenerated to track ../common/aclocal.m4 changes.
  11
  12 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
  13
  14         * configure: Regenerated to track ../common/aclocal.m4 changes.
  15
  16 Thu Mar 20 11:58:02 1997  Jeffrey A Law  (law@cygnus.com)
  17
  18         * simops.c: Fix register extraction for a two "movbu" variants.
  19         Somewhat simplify "sub" instructions.
  20         Correctly sign extend operands for "mul".  Put the correct
  21         half of the result in MDR for "mul" and "mulu".
  22         Implement remaining instructions.
  23         Tweak opcode for "syscall".
  24
  25 Tue Mar 18 14:21:21 1997  Jeffrey A Law  (law@cygnus.com)
  26
  27         * simops.c: Do syscall emulation in "syscall" instruction.  Add
  28         dummy "trap" instruction.
  29
  30 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  31
  32         * configure: Regenerated to track ../common/aclocal.m4 changes.
  33
  34 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  35
  36         * configure: Re-generate.
  37
  38 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
  39
  40         * configure: Regenerate to track ../common/aclocal.m4 changes.
  41
  42 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
  43
  44         * interp.c (sim_open): New SIM_DESC result.  Argument is now
  45         in argv form.
  46         (other sim_*): New SIM_DESC argument.
  47
  48 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
  49
  50         * simops.c: Fix carry bit computation for "add" instructions.
  51
  52         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
  53         for bset imm8,(d8,an) and bclr imm8,(d8,an).
  54
  55 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
  56
  57         * simops.c: Fix register references when computing Z and N bits
  58         for lsr imm8,dn.
  59
  60 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
  61
  62         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
  63         COMMON_{PRE,POST}_CONFIG_FRAG instead.
  64         * configure.in: sinclude ../common/aclocal.m4.
  65         * configure: Regenerated.
  66
  67 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
  68
  69         * interp.c (init_system): Allocate 2^19 bytes of space for the
  70         simulator.
  71
  72 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
  73
  74         * configure configure.in Makefile.in:  Update to new configure
  75         scheme which is more compatible with WinGDB builds.
  76         * configure.in:  Improve comment on how to run autoconf.
  77         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
  78         * Makefile.in:  Use autoconf substitution to install common
  79         makefile fragment.
  80
  81 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
  82
  83         * simops.c: Undo last change to "rol" and "ror", original code
  84         was correct!
  85
  86 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
  87
  88         * simops.c: Fix "rol" and "ror".
  89
  90 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
  91
  92         * simops.c: Fix typo in last change.
  93
  94 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  95
  96         * simops.c: Use REG macros in few places not using them yet.
  97
  98 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  99
 100         * mn10300_sim.h (struct _state): Fix number of registers!
 101
 102 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
 103
 104         * mn10300_sim.h (struct _state): Put all registers into a single
 105         array to make gdb implementation easier.
 106         (REG_*): Add definitions for all registers in the state array.
 107         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
 108         * simops.c: Related changes.
 109
 110 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 111
 112         * interp.c (sim_resume): Handle 0xff as a single byte insn.
 113
 114         * simops.c: Fix overflow computation for "add" and "inc"
 115         instructions.
 116
 117 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 118
 119         * simops.c: Handle "break" instruction.
 120
 121         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
 122
 123 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
 124
 125         * gencode.c (write_opcodes): Also write out the format of the
 126         opcode.
 127         * mn10300_sim.h (simops): Add "format" field.
 128         * interp.c (sim_resume): Deal with endianness issues here.
 129
 130 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 131
 132         * simops.c (REG0_4): Define.
 133         Use REG0_4 for indexed loads/stores.
 134
 135 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 136
 137         * simops.c (REG0_16): Fix typo.
 138
 139 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 140
 141         * simops.c: Call abort for any instruction that's not currently
 142         simulated.
 143
 144         * simops.c: Define accessor macros to extract register
 145         values from instructions.  Use them consistently.
 146
 147         * interp.c: Delete unused global variable "OP".
 148         (sim_resume): Remove unused variable "opcode".
 149         * simops.c: Fix some uninitialized variable problems, add
 150         parens to fix various -Wall warnings.
 151
 152         * gencode.c (write_header): Add "insn" and "extension" arguments
 153         to the OP_* declarations.
 154         (write_template): Similarly for function templates.
 155         * interp.c (insn, extension): Remove global variables.  Instead
 156         pass them as arguments to the OP_* functions.
 157         * mn10300_sim.h: Remove decls for "insn" and "extension".
 158         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 159         instead of using globals.
 160
 161 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 162
 163         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 164
 165         * simops.c: Fix thinkos in last change to "inc dn".
 166
 167 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 168
 169         * simops.c: "add imm,sp" does not effect the condition codes.
 170         "inc dn" does effect the condition codes.
 171
 172 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 173
 174         * simops.c: Treat both operands as signed values for
 175         "div" instruction.
 176
 177         * simops.c: Fix simulation of division instructions.
 178         Fix typos/thinkos in several "cmp" and "sub" instructions.
 179
 180 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 181
 182         * simops.c: Fix carry bit handling in "sub" and "cmp"
 183         instructions.
 184
 185         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 186
 187 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 188
 189         * simops.c: Fix overflow computation for many instructions.
 190
 191         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 192
 193         * simops.c: Fix "mov am, dn".
 194
 195         * simops.c: Fix more bugs in "add imm,an" and
 196         "add imm,dn".
 197
 198 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 199
 200         * simops.c: Fix bugs in "movm" and "add imm,an".
 201
 202         * simops.c: Don't lose the upper 24 bits of the return
 203         pointer in "call" and "calls" instructions.  Rough cut
 204         at emulated system calls.
 205
 206         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 207
 208         * simops.c: Implement remaining 4 byte instructions.
 209
 210         * simops.c: Implement remaining 3 byte instructions.
 211
 212         * simops.c: Implement remaining 2 byte instructions.  Call
 213         abort for instructions we're not implementing now.
 214
 215 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 216
 217         * simops.c: Implement lots of random instructions.
 218
 219         * simops.c: Implement "movm" and "bCC" insns.
 220
 221         * mn10300_sim.h (_state): Add another register (MDR).
 222         (REG_MDR): Define.
 223         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 224         a few additional random insns.
 225
 226         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 227         (REG_D0, REG_A0, REG_SP): Define.
 228         * simops.c: Implement "add", "addc" and a few other random
 229         instructions.
 230
 231         * gencode.c, interp.c: Snapshot current simulator code.
 232
 233 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 234
 235         * Makefile.in, config.in, configure, configure.in: New files.
 236         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 237