sim/ppc/std-config.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright 1994, 1995, 2002 Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 3 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, see <http://www.gnu.org/licenses/>.
  17
  18     */
  19
  20
  21 #ifndef _PSIM_CONFIG_H_
  22 #define _PSIM_CONFIG_H_
  23
  24 #include "bfd.h"
  25
  26 /* endianness of the host/target:
  27
  28    If the build process is aware (at compile time) of the endianness
  29    of the host/target it is able to eliminate slower generic endian
  30    handling code.
  31
  32    Possible values are BFD_ENDIAN_UNKNOWN, BFD_ENDIAN_LITTLE,
  33    BFD_ENDIAN_BIG.  */
  34
  35 #ifdef WORDS_BIGENDIAN
  36 # define HOST_BYTE_ORDER BFD_ENDIAN_BIG
  37 #else
  38 # define HOST_BYTE_ORDER BFD_ENDIAN_LITTLE
  39 #endif
  40
  41 #ifndef WITH_TARGET_BYTE_ORDER
  42 #define WITH_TARGET_BYTE_ORDER          BFD_ENDIAN_UNKNOWN
  43 #endif
  44
  45 extern enum bfd_endian current_target_byte_order;
  46 #define CURRENT_TARGET_BYTE_ORDER \
  47   (WITH_TARGET_BYTE_ORDER != BFD_ENDIAN_UNKNOWN \
  48    ? WITH_TARGET_BYTE_ORDER : current_target_byte_order)
  49
  50
  51 /* PowerPC XOR endian.
  52
  53    In addition to the above, the simulator can support the PowerPC's
  54    horrible XOR endian mode.  This feature makes it possible to
  55    control the endian mode of a processor using the MSR. */
  56
  57 #ifndef WITH_XOR_ENDIAN
  58 #define WITH_XOR_ENDIAN         8
  59 #endif
  60
  61
  62 /* SMP support:
  63
  64    Sets a limit on the number of processors that can be simulated.  If
  65    WITH_SMP is set to zero (0), the simulator is restricted to
  66    suporting only on processor (and as a consequence leaves the SMP
  67    code out of the build process).
  68
  69    The actual number of processors is taken from the device
  70    /options/smp@<nr-cpu> */
  71
  72 #ifndef WITH_SMP
  73 #define WITH_SMP                        5
  74 #endif
  75 #if WITH_SMP
  76 #define MAX_NR_PROCESSORS               WITH_SMP
  77 #else
  78 #define MAX_NR_PROCESSORS               1
  79 #endif
  80
  81
  82 /* Word size of host/target:
  83
  84    Set these according to your host and target requirements.  At this
  85    point in time, I've only compiled (not run) for a 64bit and never
  86    built for a 64bit host.  This will always remain a compile time
  87    option */
  88
  89 #ifndef WITH_TARGET_WORD_BITSIZE
  90 #define WITH_TARGET_WORD_BITSIZE        32 /* compiled only */
  91 #endif
  92
  93 #ifndef WITH_HOST_WORD_BITSIZE
  94 #define WITH_HOST_WORD_BITSIZE          32 /* 64bit ready? */
  95 #endif
  96
  97
  98 /* Program environment:
  99
 100    Three environments are available - UEA (user), VEA (virtual) and
 101    OEA (perating).  The former two are environment that users would
 102    expect to see (VEA includes things like coherency and the time
 103    base) while OEA is what an operating system expects to see.  By
 104    setting these to specific values, the build process is able to
 105    eliminate non relevent environment code
 106
 107    CURRENT_ENVIRONMENT specifies which of vea or oea is required for
 108    the current runtime. */
 109
 110 #define ALL_ENVIRONMENT                 0
 111 #define USER_ENVIRONMENT                1
 112 #define VIRTUAL_ENVIRONMENT             2
 113 #define OPERATING_ENVIRONMENT           3
 114
 115 extern int current_environment;
 116 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
 117                              ? WITH_ENVIRONMENT \
 118                              : current_environment)
 119
 120
 121 /* Optional VEA/OEA code:
 122
 123    The below, required for the OEA model may also be included in the
 124    VEA model however, as far as I can tell only make things
 125    slower... */
 126
 127
 128 /* Events.  Devices modeling real H/W need to be able to efficiently
 129    schedule things to do at known times in the future.  The event
 130    queue implements this.  Unfortunatly this adds the need to check
 131    for any events once each full instruction cycle. */
 132
 133 #define WITH_EVENTS                     (WITH_ENVIRONMENT != USER_ENVIRONMENT)
 134
 135
 136 /* Time base:
 137
 138    The PowerPC architecture includes the addition of both a time base
 139    register and a decrement timer.  Like events adds to the overhead
 140    of of some instruction cycles. */
 141
 142 #ifndef WITH_TIME_BASE
 143 #define WITH_TIME_BASE                  (WITH_ENVIRONMENT != USER_ENVIRONMENT)
 144 #endif
 145
 146
 147 /* Callback/Default Memory.
 148
 149    Core includes a builtin memory type (raw_memory) that is
 150    implemented using an array.  raw_memory does not require any
 151    additional functions etc.
 152
 153    Callback memory is where the core calls a core device for the data
 154    it requires.
 155
 156    Default memory is an extenstion of this where for addresses that do
 157    not map into either a callback or core memory range a default map
 158    can be used.
 159
 160    The OEA model uses callback memory for devices and default memory
 161    for buses.
 162
 163    The VEA model uses callback memory to capture `page faults'.
 164
 165    While it may be possible to eliminate callback/default memory (and
 166    hence also eliminate an additional test per memory fetch) it
 167    probably is not worth the effort.
 168
 169    BTW, while raw_memory could have been implemented as a callback,
 170    profiling has shown that there is a biger win (at least for the
 171    x86) in eliminating a function call for the most common
 172    (raw_memory) case. */
 173
 174 #define WITH_CALLBACK_MEMORY            1
 175
 176
 177 /* Alignment:
 178
 179    The PowerPC may or may not handle miss aligned transfers.  An
 180    implementation normally handles miss aligned transfers in big
 181    endian mode but generates an exception in little endian mode.
 182
 183    This model.  Instead allows both little and big endian modes to
 184    either take exceptions or handle miss aligned transfers.
 185
 186    If 0 is specified then for big-endian mode miss alligned accesses
 187    are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
 188    processor will fault on them (STRICT_ALIGNMENT). */
 189
 190 #define NONSTRICT_ALIGNMENT             1
 191 #define STRICT_ALIGNMENT                2
 192
 193 #ifndef WITH_ALIGNMENT
 194 #define WITH_ALIGNMENT                  0
 195 #endif
 196
 197 extern int current_alignment;
 198 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
 199                            ? WITH_ALIGNMENT \
 200                            : current_alignment)
 201
 202
 203 /* Floating point suport:
 204
 205    Still under development. */
 206
 207 #define SOFT_FLOATING_POINT             1
 208 #define HARD_FLOATING_POINT             2
 209
 210 #ifndef WITH_FLOATING_POINT
 211 #define WITH_FLOATING_POINT             HARD_FLOATING_POINT
 212 #endif
 213 extern int current_floating_point;
 214 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
 215                                 ? WITH_FLOATING_POINT \
 216                                 : current_floating_point)
 217
 218
 219 /* Debugging:
 220
 221    Control the inclusion of debugging code. */
 222
 223 /* Whether to check instructions for reserved bits being set */
 224
 225 #ifndef WITH_RESERVED_BITS
 226 #define WITH_RESERVED_BITS              1
 227 #endif
 228
 229 /* include monitoring code */
 230
 231 #define MONITOR_INSTRUCTION_ISSUE       1
 232 #define MONITOR_LOAD_STORE_UNIT         2
 233 #ifndef WITH_MON
 234 #define WITH_MON                        (MONITOR_LOAD_STORE_UNIT \
 235                                          | MONITOR_INSTRUCTION_ISSUE)
 236 #endif
 237
 238 /* Current CPU model (models are in the generated models.h include file)  */
 239 #ifndef WITH_MODEL
 240 #define WITH_MODEL                      0
 241 #endif
 242
 243 #define CURRENT_MODEL (WITH_MODEL       \
 244                        ? WITH_MODEL     \
 245                        : current_model)
 246
 247 #ifndef WITH_DEFAULT_MODEL
 248 #define WITH_DEFAULT_MODEL              DEFAULT_MODEL
 249 #endif
 250
 251 #define MODEL_ISSUE_IGNORE              (-1)
 252 #define MODEL_ISSUE_PROCESS             1
 253
 254 #ifndef WITH_MODEL_ISSUE
 255 #define WITH_MODEL_ISSUE                0
 256 #endif
 257
 258 extern int current_model_issue;
 259 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE   \
 260                              ? WITH_MODEL_ISSUE \
 261                              : current_model_issue)
 262
 263 /* Whether or not input/output just uses stdio, or uses printf_filtered for
 264    output, and polling input for input.  */
 265
 266 #define DONT_USE_STDIO                  2
 267 #define DO_USE_STDIO                    1
 268
 269 extern int current_stdio;
 270 #define CURRENT_STDIO (WITH_STDIO       \
 271                        ? WITH_STDIO     \
 272                        : current_stdio)
 273
 274
 275
 276 /* INLINE CODE SELECTION:
 277
 278    GCC -O3 attempts to inline any function or procedure in scope.  The
 279    options below facilitate fine grained control over what is and what
 280    isn't made inline.  For instance it can control things down to a
 281    specific modules static routines.  Doing this allows the compiler
 282    to both eliminate the overhead of function calls and (as a
 283    consequence) also eliminate further dead code.
 284
 285    On a CISC (x86) I've found that I can achieve an order of magnitude
 286    speed improvement (x3-x5).  In the case of RISC (sparc) while the
 287    performance gain isn't as great it is still significant.
 288
 289    Each module is controled by the macro <module>_INLINE which can
 290    have the values described below
 291
 292        0  Do not inline any thing for the given module
 293
 294    The following additional values are `bit fields' and can be
 295    combined.
 296
 297       REVEAL_MODULE:
 298
 299          Include the C file for the module into the file being compiled
 300          but do not make the functions within the module inline.
 301
 302          While of no apparent benefit, this makes it possible for the
 303          included module, when compiled to inline its calls to what
 304          would otherwize be external functions.
 305
 306       INLINE_MODULE:
 307
 308          Make external functions within the module `inline'.  Thus if
 309          the module is included into a file being compiled, calls to
 310          its funtions can be eliminated. 2 implies 1.
 311
 312       INLINE_LOCALS:
 313
 314          Make internal (static) functions within the module `inline'.
 315
 316    The following abreviations are available:
 317
 318       INCLUDE_MODULE == (REVEAL_MODULE | INLINE_MODULE)
 319
 320       ALL_C_INLINE == (REVEAL_MODULE | INLINE_MODULE | INLINE_LOCALS)
 321
 322    In addition to this, modules have been put into two categories.
 323
 324          Simple modules - eg sim-endian.h bits.h
 325
 326          Because these modules are small and simple and do not have
 327          any complex interpendencies they are configured, if
 328          <module>_INLINE is so enabled, to inline themselves in all
 329          modules that include those files.
 330
 331          For the default build, this is a real win as all byte
 332          conversion and bit manipulation functions are inlined.
 333
 334          Complex modules - the rest
 335
 336          These are all handled using the files inline.h and inline.c.
 337          psim.c includes the above which in turn include any remaining
 338          code.
 339
 340    IMPLEMENTATION:
 341
 342    The inline ability is enabled by prefixing every data / function
 343    declaration and definition with one of the following:
 344
 345
 346        INLINE_<module>
 347
 348        Prefix to any global function that is a candidate for being
 349        inline.
 350
 351        values - `', `static', `static INLINE'
 352
 353
 354        EXTERN_<module>
 355
 356        Prefix to any global data structures for the module.  Global
 357        functions that are not to be inlined shall also be prefixed
 358        with this.
 359
 360        values - `', `static', `static'
 361
 362
 363        STATIC_INLINE_<module>
 364
 365        Prefix to any local (static) function that is a candidate for
 366        being made inline.
 367
 368        values - `static', `static INLINE'
 369
 370
 371        static
 372
 373        Prefix all local data structures.  Local functions that are not
 374        to be inlined shall also be prefixed with this.
 375
 376        values - `static', `static'
 377
 378        nb: will not work for modules that are being inlined for every
 379        use (white lie).
 380
 381
 382        extern
 383        #ifndef _INLINE_C_
 384        #endif
 385
 386        Prefix to any declaration of a global object (function or
 387        variable) that should not be inlined and should have only one
 388        definition.  The #ifndef wrapper goes around the definition
 389        propper to ensure that only one copy is generated.
 390
 391        nb: this will not work when a module is being inlined for every
 392        use.
 393
 394
 395        STATIC_<module>
 396
 397        Replaced by either `static' or `EXTERN_MODULE'.
 398
 399
 400    REALITY CHECK:
 401
 402    This is not for the faint hearted.  I've seen GCC get up to 500mb
 403    trying to compile what this can create.
 404
 405    Some of the modules do not yet implement the WITH_INLINE_STATIC
 406    option.  Instead they use the macro STATIC_INLINE to control their
 407    local function.
 408
 409    Because of the way that GCC parses __attribute__(), the macro's
 410    need to be adjacent to the function name rather than at the start
 411    of the line vis:
 412
 413         int STATIC_INLINE_MODULE f(void);
 414         void INLINE_MODULE *g(void);
 415
 416    */
 417
 418 #include "../common/sim-inline.h"
 419 #define REVEAL_MODULE                   H_REVEALS_MODULE
 420 #define INLINE_MODULE                   C_REVEALS_MODULE
 421 #define INCLUDE_MODULE                  (INLINE_MODULE | REVEAL_MODULE)
 422
 423 /* Your compilers inline reserved word */
 424
 425 #ifndef INLINE
 426 #if defined(__GNUC__) && defined(__OPTIMIZE__)
 427 #define INLINE __inline__
 428 #else
 429 #define INLINE /*inline*/
 430 #endif
 431 #endif
 432
 433
 434 /* Default prefix for static functions */
 435
 436 #ifndef STATIC_INLINE
 437 #define STATIC_INLINE static INLINE
 438 #endif
 439
 440 /* Default macro to simplify control several of key the inlines */
 441
 442 #ifndef DEFAULT_INLINE
 443 #define DEFAULT_INLINE                  INLINE_LOCALS
 444 #endif
 445
 446 /* Code that converts between hosts and target byte order.  Used on
 447    every memory access (instruction and data).  See sim-endian.h for
 448    additional byte swapping configuration information.  This module
 449    can inline for all callers */
 450
 451 #ifndef SIM_ENDIAN_INLINE
 452 #define SIM_ENDIAN_INLINE               (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 453 #endif
 454
 455 /* Low level bit manipulation routines. This module can inline for all
 456    callers */
 457
 458 #ifndef BITS_INLINE
 459 #define BITS_INLINE                     (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 460 #endif
 461
 462 /* Code that gives access to various CPU internals such as registers.
 463    Used every time an instruction is executed */
 464
 465 #ifndef CPU_INLINE
 466 #define CPU_INLINE                      (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 467 #endif
 468
 469 /* Code that translates between an effective and real address.  Used
 470    by every load or store. */
 471
 472 #ifndef VM_INLINE
 473 #define VM_INLINE                       DEFAULT_INLINE
 474 #endif
 475
 476 /* Code that loads/stores data to/from the memory data structure.
 477    Used by every load or store */
 478
 479 #ifndef CORE_INLINE
 480 #define CORE_INLINE                     DEFAULT_INLINE
 481 #endif
 482
 483 /* Code to check for and process any events scheduled in the future.
 484    Called once per instruction cycle */
 485
 486 #ifndef EVENTS_INLINE
 487 #define EVENTS_INLINE                   (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 488 #endif
 489
 490 /* Code monotoring the processors performance.  It counts events on
 491    every instruction cycle */
 492
 493 #ifndef MON_INLINE
 494 #define MON_INLINE                      (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 495 #endif
 496
 497 /* Code called on the rare occasions that an interrupt occures. */
 498
 499 #ifndef INTERRUPTS_INLINE
 500 #define INTERRUPTS_INLINE               DEFAULT_INLINE
 501 #endif
 502
 503 /* Code called on the rare occasion that either gdb or the device tree
 504    need to manipulate a register within a processor */
 505
 506 #ifndef REGISTERS_INLINE
 507 #define REGISTERS_INLINE                DEFAULT_INLINE
 508 #endif
 509
 510 /* Code called on the rare occasion that a processor is manipulating
 511    real hardware instead of RAM.
 512
 513    Also, most of the functions in devices.c are always called through
 514    a jump table. */
 515
 516 #ifndef DEVICE_INLINE
 517 #define DEVICE_INLINE                   (DEFAULT_INLINE ? INLINE_LOCALS : 0)
 518 #endif
 519
 520 /* Code called used while the device tree is being built.
 521
 522    Inlining this is of no benefit */
 523
 524 #ifndef TREE_INLINE
 525 #define TREE_INLINE                     (DEFAULT_INLINE ? INLINE_LOCALS : 0)
 526 #endif
 527
 528 /* Code called whenever information on a Special Purpose Register is
 529    required.  Called by the mflr/mtlr pseudo instructions */
 530
 531 #ifndef SPREG_INLINE
 532 #define SPREG_INLINE                    DEFAULT_INLINE
 533 #endif
 534
 535 /* Functions modeling the semantics of each instruction.  Two cases to
 536    consider, firstly of idecode is implemented with a switch then this
 537    allows the idecode function to inline each semantic function
 538    (avoiding a call).  The second case is when idecode is using a
 539    table, even then while the semantic functions can't be inlined,
 540    setting it to one still enables each semantic function to inline
 541    anything they call (if that code is marked for being inlined).
 542
 543    WARNING: you need lots (like 200mb of swap) of swap.  Setting this
 544    to 1 is useful when using a table as it enables the sematic code to
 545    inline all of their called functions */
 546
 547 #ifndef SEMANTICS_INLINE
 548 #define SEMANTICS_INLINE                (DEFAULT_INLINE & ~INLINE_MODULE)
 549 #endif
 550
 551 /* When using the instruction cache, code to decode an instruction and
 552    install it into the cache.  Normally called when ever there is a
 553    miss in the instruction cache. */
 554
 555 #ifndef ICACHE_INLINE
 556 #define ICACHE_INLINE                   (DEFAULT_INLINE & ~INLINE_MODULE)
 557 #endif
 558
 559 /* General functions called by semantics functions but part of the
 560    instruction table.  Although called by the semantic functions the
 561    frequency of calls is low.  Consequently the need to inline this
 562    code is reduced. */
 563
 564 #ifndef SUPPORT_INLINE
 565 #define SUPPORT_INLINE                  INLINE_LOCALS
 566 #endif
 567
 568 /* Model specific code used in simulating functional units.  Note, it actaully
 569    pays NOT to inline the PowerPC model functions (at least on the x86).  This
 570    is because if it is inlined, each PowerPC instruction gets a separate copy
 571    of the code, which is not friendly to the cache.  */
 572
 573 #ifndef MODEL_INLINE
 574 #define MODEL_INLINE                    (DEFAULT_INLINE & ~INLINE_MODULE)
 575 #endif
 576
 577 /* Code to print out what options we were compiled with.  Because this
 578    is called at process startup, it doesn't have to be inlined, but
 579    if it isn't brought in and the model routines are inline, the model
 580    routines will be pulled in twice.  */
 581
 582 #ifndef OPTIONS_INLINE
 583 #define OPTIONS_INLINE                  MODEL_INLINE
 584 #endif
 585
 586 /* idecode acts as the hub of the system, everything else is imported
 587    into this file */
 588
 589 #ifndef IDECOCE_INLINE
 590 #define IDECODE_INLINE                  INLINE_LOCALS
 591 #endif
 592
 593 /* psim, isn't actually inlined */
 594
 595 #ifndef PSIM_INLINE
 596 #define PSIM_INLINE                     INLINE_LOCALS
 597 #endif
 598
 599 /* Code to emulate os or rom compatibility.  This code is called via a
 600    table and hence there is little benefit in making it inline */
 601
 602 #ifndef OS_EMUL_INLINE
 603 #define OS_EMUL_INLINE                  0
 604 #endif
 605
 606 #endif /* _PSIM_CONFIG_H */