sim/riscv/machs.c

   1 /* RISC-V simulator.
   2
   3    Copyright (C) 2005-2022 Free Software Foundation, Inc.
   4    Contributed by Mike Frysinger.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25
  26 static void
  27 riscv_model_init (SIM_CPU *cpu)
  28 {
  29 }
  30
  31 static void
  32 riscv_init_cpu (SIM_CPU *cpu)
  33 {
  34 }
  35
  36 static void
  37 riscv_prepare_run (SIM_CPU *cpu)
  38 {
  39 }
  40
  41 static const SIM_MACH_IMP_PROPERTIES riscv_imp_properties =
  42 {
  43   sizeof (SIM_CPU),
  44   0,
  45 };
  46
  47 #if WITH_TARGET_WORD_BITSIZE >= 32
  48
  49 static const SIM_MACH rv32i_mach;
  50
  51 static const SIM_MODEL rv32_models[] =
  52 {
  53 #define M(ext) { "RV32"#ext, &rv32i_mach, MODEL_RV32##ext, NULL, riscv_model_init },
  54 #include "model_list.def"
  55 #undef M
  56   { 0, NULL, 0, NULL, NULL, }
  57 };
  58
  59 static const SIM_MACH rv32i_mach =
  60 {
  61   "rv32i", "riscv:rv32", MACH_RV32I,
  62   32, 32, &rv32_models[0], &riscv_imp_properties,
  63   riscv_init_cpu,
  64   riscv_prepare_run
  65 };
  66
  67 #endif
  68
  69 #if WITH_TARGET_WORD_BITSIZE >= 64
  70
  71 static const SIM_MACH rv64i_mach;
  72
  73 static const SIM_MODEL rv64_models[] =
  74 {
  75 #define M(ext) { "RV64"#ext, &rv64i_mach, MODEL_RV64##ext, NULL, riscv_model_init },
  76 #include "model_list.def"
  77 #undef M
  78   { 0, NULL, 0, NULL, NULL, }
  79 };
  80
  81 static const SIM_MACH rv64i_mach =
  82 {
  83   "rv64i", "riscv:rv64", MACH_RV64I,
  84   64, 64, &rv64_models[0], &riscv_imp_properties,
  85   riscv_init_cpu,
  86   riscv_prepare_run
  87 };
  88
  89 #endif
  90
  91 #if WITH_TARGET_WORD_BITSIZE >= 128
  92
  93 static const SIM_MACH rv128i_mach;
  94
  95 static const SIM_MODEL rv128_models[] =
  96 {
  97 #define M(ext) { "RV128"#ext, &rv128i_mach, MODEL_RV128##ext, NULL, riscv_model_init },
  98 #include "model_list.def"
  99 #undef M
 100   { 0, NULL, 0, NULL, NULL, }
 101 };
 102
 103 static const SIM_MACH rv128i_mach =
 104 {
 105   "rv128i", "riscv:rv128", MACH_RV128I,
 106   128, 128, &rv128_models[0], &riscv_imp_properties,
 107   riscv_init_cpu,
 108   riscv_prepare_run
 109 };
 110
 111 #endif
 112
 113 /* Order matters here.  */
 114 const SIM_MACH * const riscv_sim_machs[] =
 115 {
 116 #if WITH_TARGET_WORD_BITSIZE >= 128
 117   &rv128i_mach,
 118 #endif
 119 #if WITH_TARGET_WORD_BITSIZE >= 64
 120   &rv64i_mach,
 121 #endif
 122 #if WITH_TARGET_WORD_BITSIZE >= 32
 123   &rv32i_mach,
 124 #endif
 125   NULL
 126 };