1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 /* This must come before any other includes. */
34 # define MAP_FAILED -1
36 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
37 # define MAP_ANONYMOUS MAP_ANON
43 #ifdef HAVE_SYS_STAT_H
54 #include "sim/callback.h"
56 #include "gdb/sim-sh.h"
60 #include "sim-options.h"
62 #include "targ-vals.h"
67 #include <float.h> /* Needed for _isnan() */
72 #define SIGBUS SIGSEGV
76 #define SIGQUIT SIGTERM
83 /* TODO: Stop using these names. */
87 extern unsigned short sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
89 #define O_RECOMPILE 85
91 #define DISASSEMBLER_TABLE
93 /* Define the rate at which the simulator should poll the host
95 #define POLL_QUIT_INTERVAL 0x60000
97 /* TODO: Move into sim_cpu. */
98 saved_state_type saved_state
;
100 struct loop_bounds
{ unsigned char *start
, *end
; };
102 /* These variables are at file scope so that functions other than
103 sim_resume can use the fetch/store macros */
105 #define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
106 static int global_endianw
, endianb
;
107 static int target_dsp
;
108 #define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE)
110 static int maskw
= 0;
111 static int maskl
= 0;
113 /* Short hand definitions of the registers */
115 #define SBIT(x) ((x)&sbit)
116 #define R0 saved_state.asregs.regs[0]
117 #define Rn saved_state.asregs.regs[n]
118 #define Rm saved_state.asregs.regs[m]
119 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
120 #define UR (unsigned int) R
121 #define UR (unsigned int) R
122 #define SR0 saved_state.asregs.regs[0]
123 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
124 #define GBR saved_state.asregs.cregs.named.gbr
125 #define VBR saved_state.asregs.cregs.named.vbr
126 #define DBR saved_state.asregs.cregs.named.dbr
127 #define TBR saved_state.asregs.cregs.named.tbr
128 #define IBCR saved_state.asregs.cregs.named.ibcr
129 #define IBNR saved_state.asregs.cregs.named.ibnr
130 #define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
131 #define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
132 #define SSR saved_state.asregs.cregs.named.ssr
133 #define SPC saved_state.asregs.cregs.named.spc
134 #define SGR saved_state.asregs.cregs.named.sgr
135 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
136 #define MACH saved_state.asregs.sregs.named.mach
137 #define MACL saved_state.asregs.sregs.named.macl
138 #define PR saved_state.asregs.sregs.named.pr
139 #define FPUL saved_state.asregs.sregs.named.fpul
145 /* Alternate bank of registers r0-r7 */
147 /* Note: code controling SR handles flips between BANK0 and BANK1 */
148 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
149 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
154 #define SR_MASK_BO (1 << 14)
155 #define SR_MASK_CS (1 << 13)
156 #define SR_MASK_DMY (1 << 11)
157 #define SR_MASK_DMX (1 << 10)
158 #define SR_MASK_M (1 << 9)
159 #define SR_MASK_Q (1 << 8)
160 #define SR_MASK_I (0xf << 4)
161 #define SR_MASK_S (1 << 1)
162 #define SR_MASK_T (1 << 0)
164 #define SR_MASK_BL (1 << 28)
165 #define SR_MASK_RB (1 << 29)
166 #define SR_MASK_MD (1 << 30)
167 #define SR_MASK_RC 0x0fff0000
168 #define SR_RC_INCREMENT -0x00010000
170 #define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
171 #define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
172 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
173 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
174 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
175 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
176 #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
178 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
179 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
180 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
181 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
182 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
183 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
185 /* Note: don't use this for privileged bits */
186 #define SET_SR_BIT(EXP, BIT) \
189 saved_state.asregs.cregs.named.sr |= (BIT); \
191 saved_state.asregs.cregs.named.sr &= ~(BIT); \
194 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
195 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
196 #define SET_BANKN(EXP) \
198 IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
200 #define SET_ME(EXP) \
202 IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
204 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
205 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
206 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
207 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
208 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
210 /* stc currently relies on being able to read SR without modifications. */
211 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
213 #define SET_SR(x) set_sr (x)
216 (saved_state.asregs.cregs.named.sr \
217 = (saved_state.asregs.cregs.named.sr & 0xf000ffff) | ((x) & 0xfff) << 16)
219 /* Manipulate FPSCR */
221 #define FPSCR_MASK_FR (1 << 21)
222 #define FPSCR_MASK_SZ (1 << 20)
223 #define FPSCR_MASK_PR (1 << 19)
225 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
226 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
227 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
232 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
233 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
234 /* swap the floating point register banks */
235 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
236 /* Ignore bit change if simulating sh-dsp. */
239 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
240 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
241 saved_state
.asregs
.fregs
[1] = tmpf
;
245 /* sts relies on being able to read fpscr directly. */
246 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
247 #define SET_FPSCR(x) \
252 #define DSR (saved_state.asregs.sregs.named.fpscr)
254 #define RAISE_EXCEPTION(x) \
255 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
257 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
258 if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
260 /* This function exists mainly for the purpose of setting a breakpoint to
261 catch simulated bus errors when running the simulator under GDB. */
264 raise_exception (int x
)
270 raise_buserror (void)
272 raise_exception (SIGBUS
);
275 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
276 forbidden_addr_bits, data, retval) \
278 if (addr & forbidden_addr_bits) \
283 else if ((addr & saved_state.asregs.xyram_select) \
284 == saved_state.asregs.xram_start) \
285 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
286 else if ((addr & saved_state.asregs.xyram_select) \
287 == saved_state.asregs.yram_start) \
288 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
289 else if ((unsigned) addr >> 24 == 0xf0 \
290 && bits_written == 32 && (data & 1) == 0) \
291 /* This invalidates (if not associative) or might invalidate \
292 (if associative) an instruction cache line. This is used for \
293 trampolines. Since we don't simulate the cache, this is a no-op \
294 as far as the simulator is concerned. */ \
298 if (bits_written == 8 && addr > 0x5000000) \
299 IOMEM (addr, 1, data); \
300 /* We can't do anything useful with the other stuff, so fail. */ \
306 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
307 being implemented by ../common/sim_resume.c and the below should
308 make a call to sim_engine_halt */
310 #define BUSERROR(addr, mask) ((addr) & (mask))
312 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
317 addr_func (addr, data); \
323 #define READ_BUSERROR(addr, mask, addr_func) \
327 return addr_func (addr); \
331 /* Define this to enable register lifetime checking.
332 The compiler generates "add #0,rn" insns to mark registers as invalid,
333 the simulator uses this info to call fail if it finds a ref to an invalid
334 register before a def
341 #define CREF(x) if (!valid[x]) fail ();
342 #define CDEF(x) valid[x] = 1;
343 #define UNDEF(x) valid[x] = 0;
350 static void parse_and_set_memory_size (SIM_DESC sd
, const char *str
);
351 static int IOMEM (int addr
, int write
, int value
);
352 static struct loop_bounds
get_loop_bounds (int, int, unsigned char *,
353 unsigned char *, int, int);
354 static void process_wlat_addr (int, int);
355 static void process_wwat_addr (int, int);
356 static void process_wbat_addr (int, int);
357 static int process_rlat_addr (int);
358 static int process_rwat_addr (int);
359 static int process_rbat_addr (int);
361 /* Floating point registers */
363 #define DR(n) (get_dr (n))
368 if (host_little_endian
)
375 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
376 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
380 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
383 #define SET_DR(n, EXP) set_dr ((n), (EXP))
385 set_dr (int n
, double exp
)
388 if (host_little_endian
)
396 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
397 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
400 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
403 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
404 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
406 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
407 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
409 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
410 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
411 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
413 #define RS saved_state.asregs.cregs.named.rs
414 #define RE saved_state.asregs.cregs.named.re
415 #define MOD (saved_state.asregs.cregs.named.mod)
418 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
419 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
421 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
422 #define DSP_GRD(n) DSP_R ((n) + 8)
423 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
428 #define Y0 DSP_R (10)
429 #define Y1 DSP_R (11)
430 #define M0 DSP_R (12)
431 #define A1G DSP_R (13)
432 #define M1 DSP_R (14)
433 #define A0G DSP_R (15)
434 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
435 #define MOD_ME DSP_GRD (17)
436 #define MOD_DELTA DSP_GRD (18)
438 #define FP_OP(n, OP, m) \
442 if (((n) & 1) || ((m) & 1)) \
443 RAISE_EXCEPTION (SIGILL); \
445 SET_DR (n, (DR (n) OP DR (m))); \
448 SET_FR (n, (FR (n) OP FR (m))); \
451 #define FP_UNARY(n, OP) \
456 RAISE_EXCEPTION (SIGILL); \
458 SET_DR (n, (OP (DR (n)))); \
461 SET_FR (n, (OP (FR (n)))); \
464 #define FP_CMP(n, OP, m) \
468 if (((n) & 1) || ((m) & 1)) \
469 RAISE_EXCEPTION (SIGILL); \
471 SET_SR_T (DR (n) OP DR (m)); \
474 SET_SR_T (FR (n) OP FR (m)); \
480 /* do we need to swap banks */
481 int old_gpr
= SR_MD
&& SR_RB
;
482 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
483 if (old_gpr
!= new_gpr
)
486 for (i
= 0; i
< 8; i
++)
488 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
489 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
490 saved_state
.asregs
.regs
[i
] = tmp
;
493 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
498 wlat_fast (unsigned char *memory
, int x
, int value
, int maskl
)
501 unsigned int *p
= (unsigned int *) (memory
+ x
);
502 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
507 wwat_fast (unsigned char *memory
, int x
, int value
, int maskw
, int endianw
)
510 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
511 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
516 wbat_fast (unsigned char *memory
, int x
, int value
, int maskb
)
518 unsigned char *p
= memory
+ (x
^ endianb
);
519 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
527 rlat_fast (unsigned char *memory
, int x
, int maskl
)
529 unsigned int *p
= (unsigned int *) (memory
+ x
);
530 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
536 rwat_fast (unsigned char *memory
, int x
, int maskw
, int endianw
)
538 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
539 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
545 riat_fast (unsigned char *insn_ptr
, int endianw
)
547 unsigned short *p
= (unsigned short *) ((uintptr_t) insn_ptr
^ endianw
);
553 rbat_fast (unsigned char *memory
, int x
, int maskb
)
555 unsigned char *p
= memory
+ (x
^ endianb
);
556 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
561 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
562 #define RLAT(x) (rlat_fast (memory, x, maskl))
563 #define RBAT(x) (rbat_fast (memory, x, maskb))
564 #define RIAT(p) (riat_fast ((p), endianw))
565 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
566 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
567 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
569 #define RUWAT(x) (RWAT (x) & 0xffff)
570 #define RSWAT(x) ((short) (RWAT (x)))
571 #define RSLAT(x) ((long) (RLAT (x)))
572 #define RSBAT(x) (SEXT (RBAT (x)))
574 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
576 do_rdat (unsigned char *memory
, int x
, int n
, int maskl
)
582 f0
= rlat_fast (memory
, x
+ 0, maskl
);
583 f1
= rlat_fast (memory
, x
+ 4, maskl
);
584 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
585 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
589 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
591 do_wdat (unsigned char *memory
, int x
, int n
, int maskl
)
597 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
598 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
599 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
600 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
605 process_wlat_addr (int addr
, int value
)
609 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
614 process_wwat_addr (int addr
, int value
)
618 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
623 process_wbat_addr (int addr
, int value
)
627 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
632 process_rlat_addr (int addr
)
636 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
641 process_rwat_addr (int addr
)
645 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
650 process_rbat_addr (int addr
)
654 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
658 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
659 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
660 #define SEXTW(y) ((int) ((short) y))
662 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
664 #define SEXT32(x) ((int) (x))
666 #define SIGN32(x) (SEXT32 (x) >> 31)
668 /* convert pointer from target to host value. */
669 #define PT2H(x) ((x) + memory)
670 /* convert pointer from host to target value. */
671 #define PH2T(x) ((x) - memory)
673 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
675 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
677 static int in_delay_slot
= 0;
678 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
680 #define CHECK_INSN_PTR(p) \
682 if (saved_state.asregs.exception || PH2T (p) & maskw) \
683 saved_state.asregs.insn_end = 0; \
684 else if (p < loop.end) \
685 saved_state.asregs.insn_end = loop.end; \
687 saved_state.asregs.insn_end = mem_end; \
700 do { memstalls += ((((long) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
702 #define L(x) thislock = x;
703 #define TL(x) if ((x) == prevlock) stalls++;
704 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
708 #if defined(__GO32__)
709 int sim_memory_size
= 19;
711 int sim_memory_size
= 30;
714 static int sim_profile_size
= 17;
720 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
721 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
722 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
723 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
724 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
725 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
727 #define SCI_RDRF 0x40 /* Recieve data register full */
728 #define SCI_TDRE 0x80 /* Transmit data register empty */
731 IOMEM (int addr
, int write
, int value
)
760 return time ((long *) 0);
769 static FILE *profile_file
;
771 static INLINE
unsigned
775 n
= (n
<< 24 | (n
& 0xff00) << 8
776 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
780 static INLINE
unsigned short
781 swap16 (unsigned short n
)
784 n
= n
<< 8 | (n
& 0xff00) >> 8;
793 union { char b
[4]; int n
; } u
;
795 fwrite (u
.b
, 4, 1, profile_file
);
802 union { char b
[4]; int n
; } u
;
804 fwrite (u
.b
, 2, 1, profile_file
);
807 /* Turn a pointer in a register into a pointer into real memory. */
812 return (char *) (x
+ saved_state
.asregs
.memory
);
815 /* STR points to a zero-terminated string in target byte order. Return
816 the number of bytes that need to be converted to host byte order in order
817 to use this string as a zero-terminated string on the host.
818 (Not counting the rounding up needed to operate on entire words.) */
822 unsigned char *memory
= saved_state
.asregs
.memory
;
824 int endian
= endianb
;
829 for (end
= str
; memory
[end
^ endian
]; end
++) ;
830 return end
- str
+ 1;
834 strnswap (int str
, int len
)
838 if (! endianb
|| ! len
)
840 start
= (int *) ptr (str
& ~3);
841 end
= (int *) ptr (str
+ len
);
845 *start
= (old
<< 24 | (old
& 0xff00) << 8
846 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
852 /* Simulate a monitor trap, put the result into r0 and errno into r1
853 return offset by which to adjust pc. */
856 trap (SIM_DESC sd
, int i
, int *regs
, unsigned char *insn_ptr
,
857 unsigned char *memory
, int maskl
, int maskw
, int endianw
)
859 host_callback
*callback
= STATE_CALLBACK (sd
);
860 char **prog_argv
= STATE_PROG_ARGV (sd
);
865 printf ("%c", regs
[0]);
868 raise_exception (SIGQUIT
);
870 case 3: /* FIXME: for backwards compat, should be removed */
873 unsigned int countp
= * (unsigned int *) (insn_ptr
+ 4);
875 WLAT (countp
, RLAT (countp
) + 1);
887 #if !defined(__GO32__) && !defined(_WIN32)
888 case TARGET_SYS_fork
:
891 /* This would work only if endianness matched between host and target.
892 Besides, it's quite dangerous. */
894 case TARGET_SYS_execve
:
895 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]),
896 (char **) ptr (regs
[7]));
898 case TARGET_SYS_execv
:
899 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]), 0);
902 case TARGET_SYS_pipe
:
904 regs
[0] = (BUSERROR (regs
[5], maskl
)
906 : pipe ((int *) ptr (regs
[5])));
910 case TARGET_SYS_wait
:
911 regs
[0] = wait ((int *) ptr (regs
[5]));
913 #endif /* !defined(__GO32__) && !defined(_WIN32) */
915 case TARGET_SYS_read
:
916 strnswap (regs
[6], regs
[7]);
918 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
919 strnswap (regs
[6], regs
[7]);
921 case TARGET_SYS_write
:
922 strnswap (regs
[6], regs
[7]);
924 regs
[0] = (int) callback
->write_stdout (callback
,
925 ptr (regs
[6]), regs
[7]);
927 regs
[0] = (int) callback
->write (callback
, regs
[5],
928 ptr (regs
[6]), regs
[7]);
929 strnswap (regs
[6], regs
[7]);
931 case TARGET_SYS_lseek
:
932 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
934 case TARGET_SYS_close
:
935 regs
[0] = callback
->close (callback
,regs
[5]);
937 case TARGET_SYS_open
:
939 int len
= strswaplen (regs
[5]);
940 strnswap (regs
[5], len
);
941 regs
[0] = callback
->open (callback
, ptr (regs
[5]), regs
[6]);
942 strnswap (regs
[5], len
);
945 case TARGET_SYS_exit
:
946 /* EXIT - caller can look in r5 to work out the reason */
947 raise_exception (SIGQUIT
);
951 case TARGET_SYS_stat
: /* added at hmsi */
952 /* stat system call */
954 struct stat host_stat
;
956 int len
= strswaplen (regs
[5]);
958 strnswap (regs
[5], len
);
959 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
960 strnswap (regs
[5], len
);
964 WWAT (buf
, host_stat
.st_dev
);
966 WWAT (buf
, host_stat
.st_ino
);
968 WLAT (buf
, host_stat
.st_mode
);
970 WWAT (buf
, host_stat
.st_nlink
);
972 WWAT (buf
, host_stat
.st_uid
);
974 WWAT (buf
, host_stat
.st_gid
);
976 WWAT (buf
, host_stat
.st_rdev
);
978 WLAT (buf
, host_stat
.st_size
);
980 WLAT (buf
, host_stat
.st_atime
);
984 WLAT (buf
, host_stat
.st_mtime
);
988 WLAT (buf
, host_stat
.st_ctime
);
1000 case TARGET_SYS_chown
:
1002 int len
= strswaplen (regs
[5]);
1004 strnswap (regs
[5], len
);
1005 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1006 strnswap (regs
[5], len
);
1010 case TARGET_SYS_chmod
:
1012 int len
= strswaplen (regs
[5]);
1014 strnswap (regs
[5], len
);
1015 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1016 strnswap (regs
[5], len
);
1019 case TARGET_SYS_utime
:
1021 /* Cast the second argument to void *, to avoid type mismatch
1022 if a prototype is present. */
1023 int len
= strswaplen (regs
[5]);
1025 strnswap (regs
[5], len
);
1026 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1027 strnswap (regs
[5], len
);
1030 case TARGET_SYS_argc
:
1031 regs
[0] = countargv (prog_argv
);
1033 case TARGET_SYS_argnlen
:
1034 if (regs
[5] < countargv (prog_argv
))
1035 regs
[0] = strlen (prog_argv
[regs
[5]]);
1039 case TARGET_SYS_argn
:
1040 if (regs
[5] < countargv (prog_argv
))
1042 /* Include the termination byte. */
1043 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1044 regs
[0] = sim_write (0, regs
[6], (void *) prog_argv
[regs
[5]], i
);
1049 case TARGET_SYS_time
:
1050 regs
[0] = get_now ();
1052 case TARGET_SYS_ftruncate
:
1053 regs
[0] = callback
->ftruncate (callback
, regs
[5], regs
[6]);
1055 case TARGET_SYS_truncate
:
1057 int len
= strswaplen (regs
[5]);
1058 strnswap (regs
[5], len
);
1059 regs
[0] = callback
->truncate (callback
, ptr (regs
[5]), regs
[6]);
1060 strnswap (regs
[5], len
);
1067 regs
[1] = callback
->get_errno (callback
);
1072 case 13: /* Set IBNR */
1073 IBNR
= regs
[0] & 0xffff;
1075 case 14: /* Set IBCR */
1076 IBCR
= regs
[0] & 0xffff;
1080 raise_exception (SIGTRAP
);
1089 div1 (int *R
, int iRn2
, int iRn1
/*, int T*/)
1092 unsigned char old_q
, tmp1
;
1095 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1097 R
[iRn1
] |= (unsigned long) T
;
1107 tmp1
= (R
[iRn1
] > tmp0
);
1114 SET_SR_Q ((unsigned char) (tmp1
== 0));
1121 tmp1
= (R
[iRn1
] < tmp0
);
1125 SET_SR_Q ((unsigned char) (tmp1
== 0));
1140 tmp1
= (R
[iRn1
] < tmp0
);
1147 SET_SR_Q ((unsigned char) (tmp1
== 0));
1154 tmp1
= (R
[iRn1
] > tmp0
);
1158 SET_SR_Q ((unsigned char) (tmp1
== 0));
1174 dmul_s (uint32_t rm
, uint32_t rn
)
1176 int64_t res
= (int64_t)(int32_t)rm
* (int64_t)(int32_t)rn
;
1177 MACH
= (uint32_t)((uint64_t)res
>> 32);
1178 MACL
= (uint32_t)res
;
1182 dmul_u (uint32_t rm
, uint32_t rn
)
1184 uint64_t res
= (uint64_t)(uint32_t)rm
* (uint64_t)(uint32_t)rn
;
1185 MACH
= (uint32_t)(res
>> 32);
1186 MACL
= (uint32_t)res
;
1190 macw (int *regs
, unsigned char *memory
, int n
, int m
, int endianw
)
1193 long prod
, macl
, sum
;
1195 tempm
=RSWAT (regs
[m
]); regs
[m
]+=2;
1196 tempn
=RSWAT (regs
[n
]); regs
[n
]+=2;
1199 prod
= (long) (short) tempm
* (long) (short) tempn
;
1203 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1205 /* MACH's lsb is a sticky overflow bit. */
1207 /* Store the smallest negative number in MACL if prod is
1208 negative, and the largest positive number otherwise. */
1209 sum
= 0x7fffffff + (prod
< 0);
1215 /* Add to MACH the sign extended product, and carry from low sum. */
1216 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1217 /* Sign extend at 10:th bit in MACH. */
1218 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1224 macl (int *regs
, unsigned char *memory
, int n
, int m
)
1231 tempm
= RSLAT (regs
[m
]);
1234 tempn
= RSLAT (regs
[n
]);
1240 mac64
= ((long long) macl
& 0xffffffff) |
1241 ((long long) mach
& 0xffffffff) << 32;
1243 ans
= (long long) tempm
* (long long) tempn
; /* Multiply 32bit * 32bit */
1245 mac64
+= ans
; /* Accumulate 64bit + 64 bit */
1247 macl
= (long) (mac64
& 0xffffffff);
1248 mach
= (long) ((mac64
>> 32) & 0xffffffff);
1250 if (S
) /* Store only 48 bits of the result */
1252 if (mach
< 0) /* Result is negative */
1254 mach
= mach
& 0x0000ffff; /* Mask higher 16 bits */
1255 mach
|= 0xffff8000; /* Sign extend higher 16 bits */
1258 mach
= mach
& 0x00007fff; /* Postive Result */
1289 /* Do extended displacement move instructions. */
1291 do_long_move_insn (int op
, int disp12
, int m
, int n
, int *thatlock
)
1294 int thislock
= *thatlock
;
1295 int endianw
= global_endianw
;
1296 int *R
= &(saved_state
.asregs
.regs
[0]);
1297 unsigned char *memory
= saved_state
.asregs
.memory
;
1298 int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1299 unsigned char *insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1302 case MOVB_RM
: /* signed */
1303 WBAT (disp12
* 1 + R
[n
], R
[m
]);
1306 WWAT (disp12
* 2 + R
[n
], R
[m
]);
1309 WLAT (disp12
* 4 + R
[n
], R
[m
]);
1311 case FMOV_RM
: /* floating point */
1315 WDAT (R
[n
] + 8 * disp12
, m
);
1318 WLAT (R
[n
] + 4 * disp12
, FI (m
));
1321 R
[n
] = RSBAT (disp12
* 1 + R
[m
]);
1325 R
[n
] = RSWAT (disp12
* 2 + R
[m
]);
1329 R
[n
] = RLAT (disp12
* 4 + R
[m
]);
1335 RDAT (R
[m
] + 8 * disp12
, n
);
1338 SET_FI (n
, RLAT (R
[m
] + 4 * disp12
));
1340 case MOVU_BMR
: /* unsigned */
1341 R
[n
] = RBAT (disp12
* 1 + R
[m
]);
1345 R
[n
] = RWAT (disp12
* 2 + R
[m
]);
1349 RAISE_EXCEPTION (SIGINT
);
1352 saved_state
.asregs
.memstalls
+= memstalls
;
1353 *thatlock
= thislock
;
1356 /* Do binary logical bit-manipulation insns. */
1358 do_blog_insn (int imm
, int addr
, int binop
,
1359 unsigned char *memory
, int maskb
)
1361 int oldval
= RBAT (addr
);
1364 case B_BCLR
: /* bclr.b */
1365 WBAT (addr
, oldval
& ~imm
);
1367 case B_BSET
: /* bset.b */
1368 WBAT (addr
, oldval
| imm
);
1370 case B_BST
: /* bst.b */
1372 WBAT (addr
, oldval
| imm
);
1374 WBAT (addr
, oldval
& ~imm
);
1376 case B_BLD
: /* bld.b */
1377 SET_SR_T ((oldval
& imm
) != 0);
1379 case B_BAND
: /* band.b */
1380 SET_SR_T (T
&& ((oldval
& imm
) != 0));
1382 case B_BOR
: /* bor.b */
1383 SET_SR_T (T
|| ((oldval
& imm
) != 0));
1385 case B_BXOR
: /* bxor.b */
1386 SET_SR_T (T
^ ((oldval
& imm
) != 0));
1388 case B_BLDNOT
: /* bldnot.b */
1389 SET_SR_T ((oldval
& imm
) == 0);
1391 case B_BANDNOT
: /* bandnot.b */
1392 SET_SR_T (T
&& ((oldval
& imm
) == 0));
1394 case B_BORNOT
: /* bornot.b */
1395 SET_SR_T (T
|| ((oldval
& imm
) == 0));
1401 fsca_s (int in
, double (*f
) (double))
1403 double rad
= ldexp ((in
& 0xffff), -15) * 3.141592653589793238462643383;
1404 double result
= (*f
) (rad
);
1405 double error
, upper
, lower
, frac
;
1408 /* Search the value with the maximum error that is still within the
1409 architectural spec. */
1410 error
= ldexp (1., -21);
1411 /* compensate for calculation inaccuracy by reducing error. */
1412 error
= error
- ldexp (1., -50);
1413 upper
= result
+ error
;
1414 frac
= frexp (upper
, &exp
);
1415 upper
= ldexp (floor (ldexp (frac
, 24)), exp
- 24);
1416 lower
= result
- error
;
1417 frac
= frexp (lower
, &exp
);
1418 lower
= ldexp (ceil (ldexp (frac
, 24)), exp
- 24);
1419 return abs (upper
- result
) >= abs (lower
- result
) ? upper
: lower
;
1425 double result
= 1. / sqrt (in
);
1427 double frac
, upper
, lower
, error
, eps
;
1430 result
= result
- (result
* result
* in
- 1) * 0.5 * result
;
1431 /* Search the value with the maximum error that is still within the
1432 architectural spec. */
1433 frac
= frexp (result
, &exp
);
1434 frac
= ldexp (frac
, 24);
1435 error
= 4.0; /* 1 << 24-1-21 */
1436 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1437 eps
= ldexp (1., -29);
1438 upper
= floor (frac
+ error
- eps
);
1439 if (upper
> 16777216.)
1440 upper
= floor ((frac
+ error
- eps
) * 0.5) * 2.;
1441 lower
= ceil ((frac
- error
+ eps
) * 2) * .5;
1442 if (lower
> 8388608.)
1443 lower
= ceil (frac
- error
+ eps
);
1444 upper
= ldexp (upper
, exp
- 24);
1445 lower
= ldexp (lower
, exp
- 24);
1446 return upper
- result
>= result
- lower
? upper
: lower
;
1450 /* GET_LOOP_BOUNDS {EXTENDED}
1451 These two functions compute the actual starting and ending point
1452 of the repeat loop, based on the RS and RE registers (repeat start,
1453 repeat stop). The extended version is called for LDRC, and the
1454 regular version is called for SETRC. The difference is that for
1455 LDRC, the loop start and end instructions are literally the ones
1456 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1458 static struct loop_bounds
1459 get_loop_bounds_ext (int rs
, int re
, unsigned char *memory
,
1460 unsigned char *mem_end
, int maskw
, int endianw
)
1462 struct loop_bounds loop
;
1464 /* FIXME: should I verify RS < RE? */
1465 loop
.start
= PT2H (RS
); /* FIXME not using the params? */
1466 loop
.end
= PT2H (RE
& ~1); /* Ignore bit 0 of RE. */
1467 SKIP_INSN (loop
.end
);
1468 if (loop
.end
>= mem_end
)
1469 loop
.end
= PT2H (0);
1473 static struct loop_bounds
1474 get_loop_bounds (int rs
, int re
, unsigned char *memory
, unsigned char *mem_end
,
1475 int maskw
, int endianw
)
1477 struct loop_bounds loop
;
1483 loop
.start
= PT2H (RE
- 4);
1484 SKIP_INSN (loop
.start
);
1485 loop
.end
= loop
.start
;
1487 SKIP_INSN (loop
.end
);
1489 SKIP_INSN (loop
.end
);
1490 SKIP_INSN (loop
.end
);
1494 loop
.start
= PT2H (RS
);
1495 loop
.end
= PT2H (RE
- 4);
1496 SKIP_INSN (loop
.end
);
1497 SKIP_INSN (loop
.end
);
1498 SKIP_INSN (loop
.end
);
1499 SKIP_INSN (loop
.end
);
1501 if (loop
.end
>= mem_end
)
1502 loop
.end
= PT2H (0);
1505 loop
.end
= PT2H (0);
1510 static void ppi_insn ();
1514 /* Provide calloc / free versions that use an anonymous mmap. This can
1515 significantly cut the start-up time when a large simulator memory is
1516 required, because pages are only zeroed on demand. */
1517 #ifdef MAP_ANONYMOUS
1519 mcalloc (size_t nmemb
, size_t size
)
1525 return mmap (0, size
, PROT_READ
| PROT_WRITE
, MAP_PRIVATE
| MAP_ANONYMOUS
,
1529 #define mfree(start,length) munmap ((start), (length))
1531 #define mcalloc calloc
1532 #define mfree(start,length) free(start)
1535 /* Set the memory size to the power of two provided. */
1538 sim_size (int power
)
1540 sim_memory_size
= power
;
1542 if (saved_state
.asregs
.memory
)
1544 mfree (saved_state
.asregs
.memory
, saved_state
.asregs
.msize
);
1547 saved_state
.asregs
.msize
= 1 << power
;
1549 saved_state
.asregs
.memory
=
1550 (unsigned char *) mcalloc (1, saved_state
.asregs
.msize
);
1552 if (!saved_state
.asregs
.memory
)
1555 "Not enough VM for simulation of %d bytes of RAM\n",
1556 saved_state
.asregs
.msize
);
1558 saved_state
.asregs
.msize
= 1;
1559 saved_state
.asregs
.memory
= (unsigned char *) mcalloc (1, 1);
1564 init_dsp (struct bfd
*abfd
)
1566 int was_dsp
= target_dsp
;
1567 unsigned long mach
= bfd_get_mach (abfd
);
1569 if (mach
== bfd_mach_sh_dsp
||
1570 mach
== bfd_mach_sh4al_dsp
||
1571 mach
== bfd_mach_sh3_dsp
)
1573 int ram_area_size
, xram_start
, yram_start
;
1577 if (mach
== bfd_mach_sh_dsp
)
1579 /* SH7410 (orig. sh-sdp):
1580 4KB each for X & Y memory;
1581 On-chip X RAM 0x0800f000-0x0800ffff
1582 On-chip Y RAM 0x0801f000-0x0801ffff */
1583 xram_start
= 0x0800f000;
1584 ram_area_size
= 0x1000;
1586 if (mach
== bfd_mach_sh3_dsp
|| mach
== bfd_mach_sh4al_dsp
)
1589 8KB each for X & Y memory;
1590 On-chip X RAM 0x1000e000-0x1000ffff
1591 On-chip Y RAM 0x1001e000-0x1001ffff */
1592 xram_start
= 0x1000e000;
1593 ram_area_size
= 0x2000;
1595 yram_start
= xram_start
+ 0x10000;
1596 new_select
= ~(ram_area_size
- 1);
1597 if (saved_state
.asregs
.xyram_select
!= new_select
)
1599 saved_state
.asregs
.xyram_select
= new_select
;
1600 free (saved_state
.asregs
.xmem
);
1601 free (saved_state
.asregs
.ymem
);
1602 saved_state
.asregs
.xmem
=
1603 (unsigned char *) calloc (1, ram_area_size
);
1604 saved_state
.asregs
.ymem
=
1605 (unsigned char *) calloc (1, ram_area_size
);
1607 /* Disable use of X / Y mmeory if not allocated. */
1608 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1610 saved_state
.asregs
.xyram_select
= 0;
1611 if (saved_state
.asregs
.xmem
)
1612 free (saved_state
.asregs
.xmem
);
1613 if (saved_state
.asregs
.ymem
)
1614 free (saved_state
.asregs
.ymem
);
1617 saved_state
.asregs
.xram_start
= xram_start
;
1618 saved_state
.asregs
.yram_start
= yram_start
;
1619 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1620 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1625 if (saved_state
.asregs
.xyram_select
)
1627 saved_state
.asregs
.xyram_select
= 0;
1628 free (saved_state
.asregs
.xmem
);
1629 free (saved_state
.asregs
.ymem
);
1633 if (! saved_state
.asregs
.xyram_select
)
1635 saved_state
.asregs
.xram_start
= 1;
1636 saved_state
.asregs
.yram_start
= 1;
1639 if (saved_state
.asregs
.regstack
== NULL
)
1640 saved_state
.asregs
.regstack
=
1641 calloc (512, sizeof *saved_state
.asregs
.regstack
);
1643 if (target_dsp
!= was_dsp
)
1647 for (i
= ARRAY_SIZE (sh_dsp_table
) - 1; i
>= 0; i
--)
1649 tmp
= sh_jump_table
[0xf000 + i
];
1650 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1651 sh_dsp_table
[i
] = tmp
;
1657 init_pointers (void)
1659 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1661 sim_size (sim_memory_size
);
1664 if (saved_state
.asregs
.profile
&& !profile_file
)
1666 profile_file
= fopen ("gmon.out", "wb");
1667 /* Seek to where to put the call arc data */
1668 nsamples
= (1 << sim_profile_size
);
1670 fseek (profile_file
, nsamples
* 2 + 12, 0);
1674 fprintf (stderr
, "Can't open gmon.out\n");
1678 saved_state
.asregs
.profile_hist
=
1679 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1692 p
= saved_state
.asregs
.profile_hist
;
1694 maxpc
= (1 << sim_profile_size
);
1696 fseek (profile_file
, 0L, 0);
1697 swapout (minpc
<< PROFILE_SHIFT
);
1698 swapout (maxpc
<< PROFILE_SHIFT
);
1699 swapout (nsamples
* 2 + 12);
1700 for (i
= 0; i
< nsamples
; i
++)
1701 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1706 gotcall (int from
, int to
)
1713 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1716 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1718 register unsigned char *insn_ptr
;
1719 unsigned char *mem_end
;
1720 struct loop_bounds loop
;
1721 register int cycles
= 0;
1722 register int stalls
= 0;
1723 register int memstalls
= 0;
1724 register int insts
= 0;
1725 register int prevlock
;
1729 register int thislock
;
1731 register unsigned int doprofile
;
1732 register int pollcount
= 0;
1733 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1734 endianb is used less often. */
1735 register int endianw
= global_endianw
;
1737 int tick_start
= get_now ();
1738 void (*prev_fpe
) ();
1740 register unsigned short *jump_table
= sh_jump_table
;
1742 register int *R
= &(saved_state
.asregs
.regs
[0]);
1748 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1749 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1750 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1751 register unsigned char *memory
;
1752 register unsigned int sbit
= ((unsigned int) 1 << 31);
1754 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1757 saved_state
.asregs
.exception
= 0;
1759 memory
= saved_state
.asregs
.memory
;
1760 mem_end
= memory
+ saved_state
.asregs
.msize
;
1763 loop
= get_loop_bounds_ext (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1765 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1767 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1768 CHECK_INSN_PTR (insn_ptr
);
1771 PR
= saved_state
.asregs
.sregs
.named
.pr
;
1773 /*T = GET_SR () & SR_MASK_T;*/
1774 prevlock
= saved_state
.asregs
.prevlock
;
1775 thislock
= saved_state
.asregs
.thislock
;
1776 doprofile
= saved_state
.asregs
.profile
;
1778 /* If profiling not enabled, disable it by asking for
1779 profiles infrequently. */
1784 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1786 if (saved_state
.asregs
.exception
)
1787 /* This can happen if we've already been single-stepping and
1788 encountered a loop end. */
1789 saved_state
.asregs
.insn_end
= insn_ptr
;
1792 saved_state
.asregs
.exception
= SIGTRAP
;
1793 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1797 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1799 register unsigned int iword
= RIAT (insn_ptr
);
1800 register unsigned int ult
;
1801 register unsigned char *nip
= insn_ptr
+ 2;
1814 if (--pollcount
< 0)
1816 host_callback
*callback
= STATE_CALLBACK (sd
);
1818 pollcount
= POLL_QUIT_INTERVAL
;
1819 if ((*callback
->poll_quit
) != NULL
1820 && (*callback
->poll_quit
) (callback
))
1827 prevlock
= thislock
;
1831 if (cycles
>= doprofile
)
1834 saved_state
.asregs
.cycles
+= doprofile
;
1835 cycles
-= doprofile
;
1836 if (saved_state
.asregs
.profile_hist
)
1838 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1841 int i
= saved_state
.asregs
.profile_hist
[n
];
1843 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1850 if (saved_state
.asregs
.insn_end
== loop
.end
)
1852 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
1854 insn_ptr
= loop
.start
;
1857 saved_state
.asregs
.insn_end
= mem_end
;
1858 loop
.end
= PT2H (0);
1863 if (saved_state
.asregs
.exception
== SIGILL
1864 || saved_state
.asregs
.exception
== SIGBUS
)
1868 /* Check for SIGBUS due to insn fetch. */
1869 else if (! saved_state
.asregs
.exception
)
1870 saved_state
.asregs
.exception
= SIGBUS
;
1872 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1873 saved_state
.asregs
.cycles
+= cycles
;
1874 saved_state
.asregs
.stalls
+= stalls
;
1875 saved_state
.asregs
.memstalls
+= memstalls
;
1876 saved_state
.asregs
.insts
+= insts
;
1877 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1879 saved_state
.asregs
.sregs
.named
.pr
= PR
;
1882 saved_state
.asregs
.prevlock
= prevlock
;
1883 saved_state
.asregs
.thislock
= thislock
;
1890 signal (SIGFPE
, prev_fpe
);
1894 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1900 for (i
= 0; i
< size
; i
++)
1902 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
1908 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1914 for (i
= 0; i
< size
; i
++)
1916 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1921 static int gdb_bank_number
;
1931 sh_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1936 val
= swap (* (int *) memory
);
1939 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
1940 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
1941 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
1942 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
1943 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
1944 case SIM_SH_R15_REGNUM
:
1945 saved_state
.asregs
.regs
[rn
] = val
;
1947 case SIM_SH_PC_REGNUM
:
1948 saved_state
.asregs
.pc
= val
;
1950 case SIM_SH_PR_REGNUM
:
1953 case SIM_SH_GBR_REGNUM
:
1956 case SIM_SH_VBR_REGNUM
:
1959 case SIM_SH_MACH_REGNUM
:
1962 case SIM_SH_MACL_REGNUM
:
1965 case SIM_SH_SR_REGNUM
:
1968 case SIM_SH_FPUL_REGNUM
:
1971 case SIM_SH_FPSCR_REGNUM
:
1974 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
1975 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
1976 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
1977 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
1978 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
1979 case SIM_SH_FR15_REGNUM
:
1980 SET_FI (rn
- SIM_SH_FR0_REGNUM
, val
);
1982 case SIM_SH_DSR_REGNUM
:
1985 case SIM_SH_A0G_REGNUM
:
1988 case SIM_SH_A0_REGNUM
:
1991 case SIM_SH_A1G_REGNUM
:
1994 case SIM_SH_A1_REGNUM
:
1997 case SIM_SH_M0_REGNUM
:
2000 case SIM_SH_M1_REGNUM
:
2003 case SIM_SH_X0_REGNUM
:
2006 case SIM_SH_X1_REGNUM
:
2009 case SIM_SH_Y0_REGNUM
:
2012 case SIM_SH_Y1_REGNUM
:
2015 case SIM_SH_MOD_REGNUM
:
2018 case SIM_SH_RS_REGNUM
:
2021 case SIM_SH_RE_REGNUM
:
2024 case SIM_SH_SSR_REGNUM
:
2027 case SIM_SH_SPC_REGNUM
:
2030 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2031 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2032 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2033 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2034 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2035 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2036 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2038 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2039 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
] = val
;
2043 Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
) = val
;
2045 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
] = val
;
2047 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2048 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2049 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2050 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2051 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2053 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2054 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8] = val
;
2058 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
] = val
;
2060 Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
) = val
;
2062 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2063 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2064 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2065 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2066 SET_Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
, val
);
2068 case SIM_SH_TBR_REGNUM
:
2071 case SIM_SH_IBNR_REGNUM
:
2074 case SIM_SH_IBCR_REGNUM
:
2077 case SIM_SH_BANK_REGNUM
:
2078 /* This is a pseudo-register maintained just for gdb.
2079 It tells us what register bank gdb would like to read/write. */
2080 gdb_bank_number
= val
;
2082 case SIM_SH_BANK_MACL_REGNUM
:
2083 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
] = val
;
2085 case SIM_SH_BANK_GBR_REGNUM
:
2086 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
] = val
;
2088 case SIM_SH_BANK_PR_REGNUM
:
2089 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
] = val
;
2091 case SIM_SH_BANK_IVN_REGNUM
:
2092 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
] = val
;
2094 case SIM_SH_BANK_MACH_REGNUM
:
2095 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
] = val
;
2104 sh_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
2111 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2112 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2113 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2114 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2115 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2116 case SIM_SH_R15_REGNUM
:
2117 val
= saved_state
.asregs
.regs
[rn
];
2119 case SIM_SH_PC_REGNUM
:
2120 val
= saved_state
.asregs
.pc
;
2122 case SIM_SH_PR_REGNUM
:
2125 case SIM_SH_GBR_REGNUM
:
2128 case SIM_SH_VBR_REGNUM
:
2131 case SIM_SH_MACH_REGNUM
:
2134 case SIM_SH_MACL_REGNUM
:
2137 case SIM_SH_SR_REGNUM
:
2140 case SIM_SH_FPUL_REGNUM
:
2143 case SIM_SH_FPSCR_REGNUM
:
2146 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2147 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2148 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2149 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2150 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2151 case SIM_SH_FR15_REGNUM
:
2152 val
= FI (rn
- SIM_SH_FR0_REGNUM
);
2154 case SIM_SH_DSR_REGNUM
:
2157 case SIM_SH_A0G_REGNUM
:
2160 case SIM_SH_A0_REGNUM
:
2163 case SIM_SH_A1G_REGNUM
:
2166 case SIM_SH_A1_REGNUM
:
2169 case SIM_SH_M0_REGNUM
:
2172 case SIM_SH_M1_REGNUM
:
2175 case SIM_SH_X0_REGNUM
:
2178 case SIM_SH_X1_REGNUM
:
2181 case SIM_SH_Y0_REGNUM
:
2184 case SIM_SH_Y1_REGNUM
:
2187 case SIM_SH_MOD_REGNUM
:
2190 case SIM_SH_RS_REGNUM
:
2193 case SIM_SH_RE_REGNUM
:
2196 case SIM_SH_SSR_REGNUM
:
2199 case SIM_SH_SPC_REGNUM
:
2202 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2203 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2204 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2205 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2206 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2207 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2208 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2210 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2211 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
];
2214 val
= (SR_MD
&& SR_RB
2215 ? Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
)
2216 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
]);
2218 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2219 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2220 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2221 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2222 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2224 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2225 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8];
2228 val
= (! SR_MD
|| ! SR_RB
2229 ? Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
)
2230 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
]);
2232 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2233 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2234 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2235 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2236 val
= Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
);
2238 case SIM_SH_TBR_REGNUM
:
2241 case SIM_SH_IBNR_REGNUM
:
2244 case SIM_SH_IBCR_REGNUM
:
2247 case SIM_SH_BANK_REGNUM
:
2248 /* This is a pseudo-register maintained just for gdb.
2249 It tells us what register bank gdb would like to read/write. */
2250 val
= gdb_bank_number
;
2252 case SIM_SH_BANK_MACL_REGNUM
:
2253 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
];
2255 case SIM_SH_BANK_GBR_REGNUM
:
2256 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
];
2258 case SIM_SH_BANK_PR_REGNUM
:
2259 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
];
2261 case SIM_SH_BANK_IVN_REGNUM
:
2262 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
];
2264 case SIM_SH_BANK_MACH_REGNUM
:
2265 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
];
2270 * (int *) memory
= swap (val
);
2275 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
2277 /* The SH simulator uses SIGQUIT to indicate that the program has
2278 exited, so we must check for it here and translate it to exit. */
2279 if (saved_state
.asregs
.exception
== SIGQUIT
)
2281 *reason
= sim_exited
;
2282 *sigrc
= saved_state
.asregs
.regs
[5];
2286 *reason
= sim_stopped
;
2287 *sigrc
= saved_state
.asregs
.exception
;
2292 sim_info (SIM_DESC sd
, int verbose
)
2295 (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2296 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2298 sim_io_printf (sd
, "\n\n# instructions executed %10d\n",
2299 saved_state
.asregs
.insts
);
2300 sim_io_printf (sd
, "# cycles %10d\n",
2301 saved_state
.asregs
.cycles
);
2302 sim_io_printf (sd
, "# pipeline stalls %10d\n",
2303 saved_state
.asregs
.stalls
);
2304 sim_io_printf (sd
, "# misaligned load/store %10d\n",
2305 saved_state
.asregs
.memstalls
);
2306 sim_io_printf (sd
, "# real time taken %10.4f\n", timetaken
);
2307 sim_io_printf (sd
, "# virtual time taken %10.4f\n", virttime
);
2308 sim_io_printf (sd
, "# profiling size %10d\n", sim_profile_size
);
2309 sim_io_printf (sd
, "# profiling frequency %10d\n",
2310 saved_state
.asregs
.profile
);
2311 sim_io_printf (sd
, "# profile maxpc %10x\n",
2312 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2316 sim_io_printf (sd
, "# cycles/second %10d\n",
2317 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2318 sim_io_printf (sd
, "# simulation ratio %10.4f\n",
2319 virttime
/ timetaken
);
2324 sh_pc_get (sim_cpu
*cpu
)
2326 return saved_state
.asregs
.pc
;
2330 sh_pc_set (sim_cpu
*cpu
, sim_cia pc
)
2332 saved_state
.asregs
.pc
= pc
;
2336 free_state (SIM_DESC sd
)
2338 if (STATE_MODULES (sd
) != NULL
)
2339 sim_module_uninstall (sd
);
2340 sim_cpu_free_all (sd
);
2341 sim_state_free (sd
);
2345 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
2346 struct bfd
*abfd
, char * const *argv
)
2358 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
2359 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
2361 /* Set default options before parsing user options. */
2362 current_alignment
= STRICT_ALIGNMENT
;
2364 /* The cpu data is kept in a separately allocated chunk of memory. */
2365 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
2371 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
2377 /* The parser will print an error message for us, so we silently return. */
2378 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
2384 /* Check for/establish the a reference program image. */
2385 if (sim_analyze_program (sd
,
2386 (STATE_PROG_ARGV (sd
) != NULL
2387 ? *STATE_PROG_ARGV (sd
)
2388 : NULL
), abfd
) != SIM_RC_OK
)
2394 /* Configure/verify the target byte order and other runtime
2395 configuration options. */
2396 if (sim_config (sd
) != SIM_RC_OK
)
2398 sim_module_uninstall (sd
);
2402 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
2404 /* Uninstall the modules to avoid memory leaks,
2405 file descriptor leaks, etc. */
2406 sim_module_uninstall (sd
);
2410 /* CPU specific initialization. */
2411 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
2413 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
2415 CPU_REG_FETCH (cpu
) = sh_reg_fetch
;
2416 CPU_REG_STORE (cpu
) = sh_reg_store
;
2417 CPU_PC_FETCH (cpu
) = sh_pc_get
;
2418 CPU_PC_STORE (cpu
) = sh_pc_set
;
2421 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2424 parse_and_set_memory_size (sd
, *p
);
2430 for (i
= 4; (i
-= 2) >= 0; )
2431 mem_word
.s
[i
>> 1] = i
;
2432 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2434 for (i
= 4; --i
>= 0; )
2436 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2442 parse_and_set_memory_size (SIM_DESC sd
, const char *str
)
2446 n
= strtol (str
, NULL
, 10);
2447 if (n
> 0 && n
<= 31)
2448 sim_memory_size
= n
;
2450 sim_io_printf (sd
, "Bad memory size %d; must be 1 to 31, inclusive\n", n
);
2454 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
2455 char * const *argv
, char * const *env
)
2457 /* Clear the registers. */
2458 memset (&saved_state
, 0,
2459 (char*) &saved_state
.asregs
.end_of_registers
- (char*) &saved_state
);
2462 if (prog_bfd
!= NULL
)
2463 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2465 /* Set the bfd machine type. */
2466 if (prog_bfd
!= NULL
)
2467 saved_state
.asregs
.bfd_mach
= bfd_get_mach (prog_bfd
);
2469 if (prog_bfd
!= NULL
)
2470 init_dsp (prog_bfd
);
2476 sim_do_command (SIM_DESC sd
, const char *cmd
)
2478 const char *sms_cmd
= "set-memory-size";
2481 if (cmd
== NULL
|| *cmd
== '\0')
2486 cmdsize
= strlen (sms_cmd
);
2487 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0
2488 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2490 parse_and_set_memory_size (sd
, cmd
+ cmdsize
+ 1);
2492 else if (strcmp (cmd
, "help") == 0)
2494 sim_io_printf (sd
, "List of SH simulator commands:\n\n");
2495 sim_io_printf (sd
, "set-memory-size <n> -- Set the number of address bits to use\n");
2496 sim_io_printf (sd
, "\n");
2500 sim_io_printf (sd
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);