sim/sh/interp.c

   1 /* Simulator for the Hitachi SH architecture.
   2
   3    Written by Steve Chamberlain of Cygnus Support.
   4    sac@cygnus.com
   5
   6    This file is part of SH sim
   7
   8
   9                 THIS SOFTWARE IS NOT COPYRIGHTED
  10
  11    Cygnus offers the following for use in the public domain.  Cygnus
  12    makes no warranty with regard to the software or it's performance
  13    and the user accepts the software "AS IS" with all faults.
  14
  15    CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
  16    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18
  19 */
  20
  21 #include "config.h"
  22
  23 #include <signal.h>
  24 #ifdef HAVE_UNISTD_H
  25 #include <unistd.h>
  26 #endif
  27
  28 #include "sysdep.h"
  29 #include "bfd.h"
  30 #include "gdb/callback.h"
  31 #include "gdb/remote-sim.h"
  32
  33 /* This file is local - if newlib changes, then so should this.  */
  34 #include "syscall.h"
  35
  36 #include <math.h>
  37
  38 #ifdef _WIN32
  39 #include <float.h>              /* Needed for _isnan() */
  40 #define isnan _isnan
  41 #endif
  42
  43 #ifndef SIGBUS
  44 #define SIGBUS SIGSEGV
  45 #endif
  46
  47 #ifndef SIGQUIT
  48 #define SIGQUIT SIGTERM
  49 #endif
  50
  51 #ifndef SIGTRAP
  52 #define SIGTRAP 5
  53 #endif
  54
  55 extern unsigned char sh_jump_table[], sh_dsp_table[0x1000], ppi_table[];
  56
  57 int sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size);
  58
  59 #define O_RECOMPILE 85
  60 #define DEFINE_TABLE
  61 #define DISASSEMBLER_TABLE
  62
  63 /* Define the rate at which the simulator should poll the host
  64    for a quit. */
  65 #define POLL_QUIT_INTERVAL 0x60000
  66
  67 typedef union
  68 {
  69
  70   struct
  71   {
  72     int regs[16];
  73     int pc;
  74
  75     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
  76        which are located in fregs, i.e. strictly speaking, these are
  77        out-of-bounds accesses of sregs.i .  This wart of the code could be
  78        fixed by making fregs part of sregs, and including pc too - to avoid
  79        alignment repercussions - but this would cause very onerous union /
  80        structure nesting, which would only be managable with anonymous
  81        unions and structs.  */
  82     union
  83       {
  84         struct
  85           {
  86             int mach;
  87             int macl;
  88             int pr;
  89             int dummy3, dummy4;
  90             int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
  91             int fpscr; /* dsr for sh-dsp */
  92           } named;
  93         int i[7];
  94       } sregs;
  95
  96     /* sh3e / sh-dsp */
  97     union fregs_u
  98       {
  99         float f[16];
 100         double d[8];
 101         int i[16];
 102       }
 103     fregs[2];
 104
 105     /* Control registers; on the SH4, ldc / stc is privileged, except when
 106        accessing gbr.  */
 107     union
 108       {
 109         struct
 110           {
 111             int sr;
 112             int gbr;
 113             int vbr;
 114             int ssr;
 115             int spc;
 116             int mod;
 117             /* sh-dsp */
 118             int rs;
 119             int re;
 120             /* sh3 */
 121             int bank[8];
 122           } named;
 123         int i[16];
 124       } cregs;
 125
 126     unsigned char *insn_end;
 127
 128     int ticks;
 129     int stalls;
 130     int memstalls;
 131     int cycles;
 132     int insts;
 133
 134     int prevlock;
 135     int thislock;
 136     int exception;
 137
 138     int end_of_registers;
 139
 140     int msize;
 141 #define PROFILE_FREQ 1
 142 #define PROFILE_SHIFT 2
 143     int profile;
 144     unsigned short *profile_hist;
 145     unsigned char *memory;
 146     int xyram_select, xram_start, yram_start;
 147     unsigned char *xmem;
 148     unsigned char *ymem;
 149     unsigned char *xmem_offset;
 150     unsigned char *ymem_offset;
 151   }
 152   asregs;
 153   int asints[40];
 154 } saved_state_type;
 155
 156 saved_state_type saved_state;
 157
 158 struct loop_bounds { unsigned char *start, *end; };
 159
 160 /* These variables are at file scope so that functions other than
 161    sim_resume can use the fetch/store macros */
 162
 163 static int target_little_endian;
 164 static int global_endianw, endianb;
 165 static int target_dsp;
 166 static int host_little_endian;
 167 static char **prog_argv;
 168
 169 #if 1
 170 static int maskw = 0;
 171 #endif
 172
 173 static SIM_OPEN_KIND sim_kind;
 174 static char *myname;
 175
 176
 177 /* Short hand definitions of the registers */
 178
 179 #define SBIT(x) ((x)&sbit)
 180 #define R0      saved_state.asregs.regs[0]
 181 #define Rn      saved_state.asregs.regs[n]
 182 #define Rm      saved_state.asregs.regs[m]
 183 #define UR0     (unsigned int)(saved_state.asregs.regs[0])
 184 #define UR      (unsigned int)R
 185 #define UR      (unsigned int)R
 186 #define SR0     saved_state.asregs.regs[0]
 187 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
 188 #define GBR     saved_state.asregs.cregs.named.gbr
 189 #define VBR     saved_state.asregs.cregs.named.vbr
 190 #define SSR     saved_state.asregs.cregs.named.ssr
 191 #define SPC     saved_state.asregs.cregs.named.spc
 192 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
 193 #define MACH    saved_state.asregs.sregs.named.mach
 194 #define MACL    saved_state.asregs.sregs.named.macl
 195 #define PR      saved_state.asregs.sregs.named.pr
 196 #define FPUL    saved_state.asregs.sregs.named.fpul
 197
 198 #define PC insn_ptr
 199
 200
 201
 202 /* Alternate bank of registers r0-r7 */
 203
 204 /* Note: code controling SR handles flips between BANK0 and BANK1 */
 205 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
 206 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
 207
 208
 209 /* Manipulate SR */
 210
 211 #define SR_MASK_DMY (1 << 11)
 212 #define SR_MASK_DMX (1 << 10)
 213 #define SR_MASK_M (1 << 9)
 214 #define SR_MASK_Q (1 << 8)
 215 #define SR_MASK_I (0xf << 4)
 216 #define SR_MASK_S (1 << 1)
 217 #define SR_MASK_T (1 << 0)
 218
 219 #define SR_MASK_BL (1 << 28)
 220 #define SR_MASK_RB (1 << 29)
 221 #define SR_MASK_MD (1 << 30)
 222 #define SR_MASK_RC 0x0fff0000
 223 #define SR_RC_INCREMENT -0x00010000
 224
 225 #define M       ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
 226 #define Q       ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
 227 #define S       ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
 228 #define T       ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
 229
 230 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
 231 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
 232 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
 233 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
 234 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
 235 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
 236
 237 /* Note: don't use this for privileged bits */
 238 #define SET_SR_BIT(EXP, BIT) \
 239 do { \
 240   if ((EXP) & 1) \
 241     saved_state.asregs.cregs.named.sr |= (BIT); \
 242   else \
 243     saved_state.asregs.cregs.named.sr &= ~(BIT); \
 244 } while (0)
 245
 246 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
 247 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
 248 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
 249 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
 250
 251 /* stc currently relies on being able to read SR without modifications.  */
 252 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
 253
 254 #define SET_SR(x) set_sr (x)
 255
 256 #define SET_RC(x) \
 257   (saved_state.asregs.cregs.named.sr \
 258    = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
 259
 260 /* Manipulate FPSCR */
 261
 262 #define FPSCR_MASK_FR (1 << 21)
 263 #define FPSCR_MASK_SZ (1 << 20)
 264 #define FPSCR_MASK_PR (1 << 19)
 265
 266 #define FPSCR_FR  ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
 267 #define FPSCR_SZ  ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
 268 #define FPSCR_PR  ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
 269
 270 /* Count the number of arguments in an argv.  */
 271 static int
 272 count_argc (char **argv)
 273 {
 274   int i;
 275
 276   if (! argv)
 277     return -1;
 278
 279   for (i = 0; argv[i] != NULL; ++i)
 280     continue;
 281   return i;
 282 }
 283
 284 static void
 285 set_fpscr1 (x)
 286         int x;
 287 {
 288   int old = saved_state.asregs.sregs.named.fpscr;
 289   saved_state.asregs.sregs.named.fpscr = (x);
 290   /* swap the floating point register banks */
 291   if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
 292       /* Ignore bit change if simulating sh-dsp.  */
 293       && ! target_dsp)
 294     {
 295       union fregs_u tmpf = saved_state.asregs.fregs[0];
 296       saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
 297       saved_state.asregs.fregs[1] = tmpf;
 298     }
 299 }
 300
 301 /* sts relies on being able to read fpscr directly.  */
 302 #define GET_FPSCR()  (saved_state.asregs.sregs.named.fpscr)
 303 #define SET_FPSCR(x) \
 304 do { \
 305   set_fpscr1 (x); \
 306 } while (0)
 307
 308 #define DSR  (saved_state.asregs.sregs.named.fpscr)
 309
 310 int
 311 fail ()
 312 {
 313   abort ();
 314 }
 315
 316 #define RAISE_EXCEPTION(x) \
 317   (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
 318
 319 /* This function exists mainly for the purpose of setting a breakpoint to
 320    catch simulated bus errors when running the simulator under GDB.  */
 321
 322 void
 323 raise_exception (x)
 324      int x;
 325 {
 326   RAISE_EXCEPTION(x);
 327 }
 328
 329 void
 330 raise_buserror ()
 331 {
 332   raise_exception (SIGBUS);
 333 }
 334
 335 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
 336                                 forbidden_addr_bits, data, retval) \
 337 do { \
 338   if (addr & forbidden_addr_bits) \
 339     { \
 340       raise_buserror (); \
 341       return retval; \
 342     } \
 343   else if ((addr & saved_state.asregs.xyram_select) \
 344            == saved_state.asregs.xram_start) \
 345     ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
 346   else if ((addr & saved_state.asregs.xyram_select) \
 347            == saved_state.asregs.yram_start) \
 348     ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
 349   else if ((unsigned) addr >> 24 == 0xf0 \
 350            && bits_written == 32 && (data & 1) == 0) \
 351     /* This invalidates (if not associative) or might invalidate \
 352        (if associative) an instruction cache line.  This is used for \
 353        trampolines.  Since we don't simulate the cache, this is a no-op \
 354        as far as the simulator is concerned.  */ \
 355     return retval; \
 356   else \
 357     { \
 358       if (bits_written == 8 && addr > 0x5000000) \
 359         IOMEM (addr, 1, data); \
 360       /* We can't do anything useful with the other stuff, so fail.  */ \
 361       raise_buserror (); \
 362       return retval; \
 363     } \
 364 } while (0)
 365
 366 /* FIXME: sim_resume should be renamed to sim_engine_run.  sim_resume
 367    being implemented by ../common/sim_resume.c and the below should
 368    make a call to sim_engine_halt */
 369
 370 #define BUSERROR(addr, mask) ((addr) & (mask))
 371
 372 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
 373   do \
 374     { \
 375       if (addr & mask) \
 376         { \
 377           addr_func (addr, data); \
 378           return; \
 379         } \
 380     } \
 381   while (0)
 382
 383 #define READ_BUSERROR(addr, mask, addr_func) \
 384   do \
 385     { \
 386       if (addr & mask) \
 387         return addr_func (addr); \
 388     } \
 389   while (0)
 390
 391 /* Define this to enable register lifetime checking.
 392    The compiler generates "add #0,rn" insns to mark registers as invalid,
 393    the simulator uses this info to call fail if it finds a ref to an invalid
 394    register before a def
 395
 396    #define PARANOID
 397 */
 398
 399 #ifdef PARANOID
 400 int valid[16];
 401 #define CREF(x)  if(!valid[x]) fail();
 402 #define CDEF(x)  valid[x] = 1;
 403 #define UNDEF(x) valid[x] = 0;
 404 #else
 405 #define CREF(x)
 406 #define CDEF(x)
 407 #define UNDEF(x)
 408 #endif
 409
 410 static void parse_and_set_memory_size PARAMS ((char *str));
 411 static int IOMEM PARAMS ((int addr, int write, int value));
 412 static struct loop_bounds get_loop_bounds PARAMS((int, int, unsigned char *,
 413                                                   unsigned char *, int, int));
 414 static void process_wlat_addr PARAMS((int, int));
 415 static void process_wwat_addr PARAMS((int, int));
 416 static void process_wbat_addr PARAMS((int, int));
 417 static int process_rlat_addr PARAMS((int));
 418 static int process_rwat_addr PARAMS((int));
 419 static int process_rbat_addr PARAMS((int));
 420 static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int));
 421 static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int));
 422 static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int));
 423 static int INLINE rlat_fast PARAMS ((unsigned char *, int, int));
 424 static int INLINE rwat_fast PARAMS ((unsigned char *, int, int, int));
 425 static int INLINE rbat_fast PARAMS ((unsigned char *, int, int));
 426
 427 static host_callback *callback;
 428
 429
 430
 431 /* Floating point registers */
 432
 433 #define DR(n) (get_dr (n))
 434 static double
 435 get_dr (n)
 436      int n;
 437 {
 438   n = (n & ~1);
 439   if (host_little_endian)
 440     {
 441       union
 442       {
 443         int i[2];
 444         double d;
 445       } dr;
 446       dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
 447       dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
 448       return dr.d;
 449     }
 450   else
 451     return (saved_state.asregs.fregs[0].d[n >> 1]);
 452 }
 453
 454 #define SET_DR(n, EXP) set_dr ((n), (EXP))
 455 static void
 456 set_dr (n, exp)
 457      int n;
 458      double exp;
 459 {
 460   n = (n & ~1);
 461   if (host_little_endian)
 462     {
 463       union
 464       {
 465         int i[2];
 466         double d;
 467       } dr;
 468       dr.d = exp;
 469       saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
 470       saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
 471     }
 472   else
 473     saved_state.asregs.fregs[0].d[n >> 1] = exp;
 474 }
 475
 476 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
 477 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
 478
 479 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
 480 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
 481
 482 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
 483 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
 484 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
 485
 486 #define RS saved_state.asregs.cregs.named.rs
 487 #define RE saved_state.asregs.cregs.named.re
 488 #define MOD (saved_state.asregs.cregs.named.mod)
 489 #define SET_MOD(i) \
 490 (MOD = (i), \
 491  MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
 492  MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
 493
 494 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
 495 #define DSP_GRD(n) DSP_R ((n) + 8)
 496 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
 497 #define A1 DSP_R (5)
 498 #define A0 DSP_R (7)
 499 #define X0 DSP_R (8)
 500 #define X1 DSP_R (9)
 501 #define Y0 DSP_R (10)
 502 #define Y1 DSP_R (11)
 503 #define M0 DSP_R (12)
 504 #define A1G DSP_R (13)
 505 #define M1 DSP_R (14)
 506 #define A0G DSP_R (15)
 507 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp.  */
 508 #define MOD_ME DSP_GRD (17)
 509 #define MOD_DELTA DSP_GRD (18)
 510
 511 #define FP_OP(n, OP, m) \
 512 { \
 513   if (FPSCR_PR) \
 514     { \
 515       if (((n) & 1) || ((m) & 1)) \
 516         RAISE_EXCEPTION (SIGILL); \
 517       else \
 518         SET_DR(n, (DR(n) OP DR(m))); \
 519     } \
 520   else \
 521     SET_FR(n, (FR(n) OP FR(m))); \
 522 } while (0)
 523
 524 #define FP_UNARY(n, OP) \
 525 { \
 526   if (FPSCR_PR) \
 527     { \
 528       if ((n) & 1) \
 529         RAISE_EXCEPTION (SIGILL); \
 530       else \
 531         SET_DR(n, (OP (DR(n)))); \
 532     } \
 533   else \
 534     SET_FR(n, (OP (FR(n)))); \
 535 } while (0)
 536
 537 #define FP_CMP(n, OP, m) \
 538 { \
 539   if (FPSCR_PR) \
 540     { \
 541       if (((n) & 1) || ((m) & 1)) \
 542         RAISE_EXCEPTION (SIGILL); \
 543       else \
 544         SET_SR_T (DR(n) OP DR(m)); \
 545     } \
 546   else \
 547     SET_SR_T (FR(n) OP FR(m)); \
 548 } while (0)
 549
 550 static void
 551 set_sr (new_sr)
 552      int new_sr;
 553 {
 554   /* do we need to swap banks */
 555   int old_gpr = SR_MD && SR_RB;
 556   int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB);
 557   if (old_gpr != new_gpr)
 558     {
 559       int i, tmp;
 560       for (i = 0; i < 8; i++)
 561         {
 562           tmp = saved_state.asregs.cregs.named.bank[i];
 563           saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i];
 564           saved_state.asregs.regs[i] = tmp;
 565         }
 566     }
 567   saved_state.asregs.cregs.named.sr = new_sr;
 568   SET_MOD (MOD);
 569 }
 570
 571 static void INLINE
 572 wlat_fast (memory, x, value, maskl)
 573      unsigned char *memory;
 574 {
 575   int v = value;
 576   unsigned int *p = (unsigned int *)(memory + x);
 577   WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
 578   *p = v;
 579 }
 580
 581 static void INLINE
 582 wwat_fast (memory, x, value, maskw, endianw)
 583      unsigned char *memory;
 584 {
 585   int v = value;
 586   unsigned short *p = (unsigned short *)(memory + (x ^ endianw));
 587   WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
 588   *p = v;
 589 }
 590
 591 static void INLINE
 592 wbat_fast (memory, x, value, maskb)
 593      unsigned char *memory;
 594 {
 595   unsigned char *p = memory + (x ^ endianb);
 596   WRITE_BUSERROR (x, maskb, value, process_wbat_addr);
 597
 598   p[0] = value;
 599 }
 600
 601 /* Read functions */
 602
 603 static int INLINE
 604 rlat_fast (memory, x, maskl)
 605      unsigned char *memory;
 606 {
 607   unsigned int *p = (unsigned int *)(memory + x);
 608   READ_BUSERROR (x, maskl, process_rlat_addr);
 609
 610   return *p;
 611 }
 612
 613 static int INLINE
 614 rwat_fast (memory, x, maskw, endianw)
 615      unsigned char *memory;
 616      int x, maskw, endianw;
 617 {
 618   unsigned short *p = (unsigned short *)(memory + (x ^ endianw));
 619   READ_BUSERROR (x, maskw, process_rwat_addr);
 620
 621   return *p;
 622 }
 623
 624 static int INLINE
 625 riat_fast (insn_ptr, endianw)
 626      unsigned char *insn_ptr;
 627 {
 628   unsigned short *p = (unsigned short *)((size_t) insn_ptr ^ endianw);
 629
 630   return *p;
 631 }
 632
 633 static int INLINE
 634 rbat_fast (memory, x, maskb)
 635      unsigned char *memory;
 636 {
 637   unsigned char *p = memory + (x ^ endianb);
 638   READ_BUSERROR (x, maskb, process_rbat_addr);
 639
 640   return *p;
 641 }
 642
 643 #define RWAT(x)         (rwat_fast (memory, x, maskw, endianw))
 644 #define RLAT(x)         (rlat_fast (memory, x, maskl))
 645 #define RBAT(x)         (rbat_fast (memory, x, maskb))
 646 #define RIAT(p)         (riat_fast ((p), endianw))
 647 #define WWAT(x,v)       (wwat_fast (memory, x, v, maskw, endianw))
 648 #define WLAT(x,v)       (wlat_fast (memory, x, v, maskl))
 649 #define WBAT(x,v)       (wbat_fast (memory, x, v, maskb))
 650
 651 #define RUWAT(x)  (RWAT(x) & 0xffff)
 652 #define RSWAT(x)  ((short)(RWAT(x)))
 653 #define RSBAT(x)  (SEXT(RBAT(x)))
 654
 655 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
 656 static int
 657 do_rdat (memory, x, n, maskl)
 658      char *memory;
 659      int x;
 660      int n;
 661      int maskl;
 662 {
 663   int f0;
 664   int f1;
 665   int i = (n & 1);
 666   int j = (n & ~1);
 667   f0 = rlat_fast (memory, x + 0, maskl);
 668   f1 = rlat_fast (memory, x + 4, maskl);
 669   saved_state.asregs.fregs[i].i[(j + 0)] = f0;
 670   saved_state.asregs.fregs[i].i[(j + 1)] = f1;
 671   return 0;
 672 }
 673
 674 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
 675 static int
 676 do_wdat (memory, x, n, maskl)
 677      char *memory;
 678      int x;
 679      int n;
 680      int maskl;
 681 {
 682   int f0;
 683   int f1;
 684   int i = (n & 1);
 685   int j = (n & ~1);
 686   f0 = saved_state.asregs.fregs[i].i[(j + 0)];
 687   f1 = saved_state.asregs.fregs[i].i[(j + 1)];
 688   wlat_fast (memory, (x + 0), f0, maskl);
 689   wlat_fast (memory, (x + 4), f1, maskl);
 690   return 0;
 691 }
 692
 693 static void
 694 process_wlat_addr (addr, value)
 695      int addr;
 696      int value;
 697 {
 698   unsigned int *ptr;
 699
 700   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, );
 701   *ptr = value;
 702 }
 703
 704 static void
 705 process_wwat_addr (addr, value)
 706      int addr;
 707      int value;
 708 {
 709   unsigned short *ptr;
 710
 711   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, );
 712   *ptr = value;
 713 }
 714
 715 static void
 716 process_wbat_addr (addr, value)
 717      int addr;
 718      int value;
 719 {
 720   unsigned char *ptr;
 721
 722   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, );
 723   *ptr = value;
 724 }
 725
 726 static int
 727 process_rlat_addr (addr)
 728      int addr;
 729 {
 730   unsigned char *ptr;
 731
 732   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0);
 733   return *ptr;
 734 }
 735
 736 static int
 737 process_rwat_addr (addr)
 738      int addr;
 739 {
 740   unsigned char *ptr;
 741
 742   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0);
 743   return *ptr;
 744 }
 745
 746 static int
 747 process_rbat_addr (addr)
 748      int addr;
 749 {
 750   unsigned char *ptr;
 751
 752   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0);
 753   return *ptr;
 754 }
 755
 756 #define SEXT(x)         (((x &  0xff) ^ (~0x7f))+0x80)
 757 #define SEXT12(x)       (((x & 0xfff) ^ 0x800) - 0x800)
 758 #define SEXTW(y)        ((int)((short)y))
 759 #if 0
 760 #define SEXT32(x)       ((int)((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
 761 #else
 762 #define SEXT32(x)       ((int)(x))
 763 #endif
 764 #define SIGN32(x)       (SEXT32 (x) >> 31)
 765
 766 /* convert pointer from target to host value.  */
 767 #define PT2H(x) ((x) + memory)
 768 /* convert pointer from host to target value.  */
 769 #define PH2T(x) ((x) - memory)
 770
 771 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
 772
 773 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
 774
 775 #define Delay_Slot(TEMPPC)      iword = RIAT (TEMPPC); goto top;
 776
 777 #define CHECK_INSN_PTR(p) \
 778 do { \
 779   if (saved_state.asregs.exception || PH2T (p) & maskw) \
 780     saved_state.asregs.insn_end = 0; \
 781   else if (p < loop.end) \
 782     saved_state.asregs.insn_end = loop.end; \
 783   else \
 784     saved_state.asregs.insn_end = mem_end; \
 785 } while (0)
 786
 787 #ifdef ACE_FAST
 788
 789 #define MA(n)
 790 #define L(x)
 791 #define TL(x)
 792 #define TB(x)
 793
 794 #else
 795
 796 #define MA(n) \
 797   do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
 798
 799 #define L(x)   thislock = x;
 800 #define TL(x)  if ((x) == prevlock) stalls++;
 801 #define TB(x,y)  if ((x) == prevlock || (y)==prevlock) stalls++;
 802
 803 #endif
 804
 805 #if defined(__GO32__) || defined(_WIN32)
 806 int sim_memory_size = 19;
 807 #else
 808 int sim_memory_size = 24;
 809 #endif
 810
 811 static int sim_profile_size = 17;
 812 static int nsamples;
 813
 814 #undef TB
 815 #define TB(x,y)
 816
 817 #define SMR1 (0x05FFFEC8)       /* Channel 1  serial mode register */
 818 #define BRR1 (0x05FFFEC9)       /* Channel 1  bit rate register */
 819 #define SCR1 (0x05FFFECA)       /* Channel 1  serial control register */
 820 #define TDR1 (0x05FFFECB)       /* Channel 1  transmit data register */
 821 #define SSR1 (0x05FFFECC)       /* Channel 1  serial status register */
 822 #define RDR1 (0x05FFFECD)       /* Channel 1  receive data register */
 823
 824 #define SCI_RDRF         0x40   /* Recieve data register full */
 825 #define SCI_TDRE        0x80    /* Transmit data register empty */
 826
 827 static int
 828 IOMEM (addr, write, value)
 829      int addr;
 830      int write;
 831      int value;
 832 {
 833   if (write)
 834     {
 835       switch (addr)
 836         {
 837         case TDR1:
 838           if (value != '\r')
 839             {
 840               putchar (value);
 841               fflush (stdout);
 842             }
 843           break;
 844         }
 845     }
 846   else
 847     {
 848       switch (addr)
 849         {
 850         case RDR1:
 851           return getchar ();
 852         }
 853     }
 854   return 0;
 855 }
 856
 857 static int
 858 get_now ()
 859 {
 860   return time ((long *) 0);
 861 }
 862
 863 static int
 864 now_persec ()
 865 {
 866   return 1;
 867 }
 868
 869 static FILE *profile_file;
 870
 871 static unsigned INLINE
 872 swap (n)
 873      unsigned n;
 874 {
 875   if (endianb)
 876     n = (n << 24 | (n & 0xff00) << 8
 877          | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24);
 878   return n;
 879 }
 880
 881 static unsigned short INLINE
 882 swap16 (n)
 883      unsigned short n;
 884 {
 885   if (endianb)
 886     n = n << 8 | (n & 0xff00) >> 8;
 887   return n;
 888 }
 889
 890 static void
 891 swapout (n)
 892      int n;
 893 {
 894   if (profile_file)
 895     {
 896       union { char b[4]; int n; } u;
 897       u.n = swap (n);
 898       fwrite (u.b, 4, 1, profile_file);
 899     }
 900 }
 901
 902 static void
 903 swapout16 (n)
 904      int n;
 905 {
 906   union { char b[4]; int n; } u;
 907   u.n = swap16 (n);
 908   fwrite (u.b, 2, 1, profile_file);
 909 }
 910
 911 /* Turn a pointer in a register into a pointer into real memory. */
 912
 913 static char *
 914 ptr (x)
 915      int x;
 916 {
 917   return (char *) (x + saved_state.asregs.memory);
 918 }
 919
 920 static int
 921 strswaplen (str)
 922      int str;
 923 {
 924   unsigned char *memory = saved_state.asregs.memory;
 925   int start, end;
 926   int endian = endianb;
 927
 928   if (! endian)
 929     return 0;
 930   end = str;
 931   for (end = str; memory[end ^ endian]; end++) ;
 932   return end - str;
 933 }
 934
 935 static void
 936 strnswap (str, len)
 937      int str;
 938      int len;
 939 {
 940   int *start, *end;
 941
 942   if (! endianb || ! len)
 943     return;
 944   start = (int *) ptr (str & ~3);
 945   end = (int *) ptr (str + len);
 946   do
 947     {
 948       int old = *start;
 949       *start = (old << 24 | (old & 0xff00) << 8
 950                 | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24);
 951       start++;
 952     }
 953   while (start < end);
 954 }
 955
 956 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
 957
 958 static void
 959 trap (i, regs, memory, maskl, maskw, endianw)
 960      int i;
 961      int *regs;
 962      unsigned char *memory;
 963 {
 964   switch (i)
 965     {
 966     case 1:
 967       printf ("%c", regs[0]);
 968       break;
 969     case 2:
 970       raise_exception (SIGQUIT);
 971       break;
 972     case 3:                     /* FIXME: for backwards compat, should be removed */
 973     case 34:
 974       {
 975         extern int errno;
 976         int perrno = errno;
 977         errno = 0;
 978
 979         switch (regs[4])
 980           {
 981
 982 #if !defined(__GO32__) && !defined(_WIN32)
 983           case SYS_fork:
 984             regs[0] = fork ();
 985             break;
 986 /* This would work only if endianness matched between host and target.
 987    Besides, it's quite dangerous.  */
 988 #if 0
 989           case SYS_execve:
 990             regs[0] = execve (ptr (regs[5]), (char **)ptr (regs[6]), (char **)ptr (regs[7]));
 991             break;
 992           case SYS_execv:
 993             regs[0] = execve (ptr (regs[5]),(char **) ptr (regs[6]), 0);
 994             break;
 995 #endif
 996           case SYS_pipe:
 997             {
 998               regs[0] = (BUSERROR (regs[5], maskl)
 999                          ? -EINVAL
1000                          : pipe ((int *) ptr (regs[5])));
1001             }
1002             break;
1003
1004           case SYS_wait:
1005             regs[0] = wait (ptr (regs[5]));
1006             break;
1007 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1008
1009           case SYS_read:
1010             strnswap (regs[6], regs[7]);
1011             regs[0]
1012               = callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
1013             strnswap (regs[6], regs[7]);
1014             break;
1015           case SYS_write:
1016             strnswap (regs[6], regs[7]);
1017             if (regs[5] == 1)
1018               regs[0] = (int)callback->write_stdout (callback, ptr(regs[6]), regs[7]);
1019             else
1020               regs[0] = (int)callback->write (callback, regs[5], ptr (regs[6]), regs[7]);
1021             strnswap (regs[6], regs[7]);
1022             break;
1023           case SYS_lseek:
1024             regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
1025             break;
1026           case SYS_close:
1027             regs[0] = callback->close (callback,regs[5]);
1028             break;
1029           case SYS_open:
1030             {
1031               int len = strswaplen (regs[5]);
1032               strnswap (regs[5], len);
1033               regs[0] = callback->open (callback,ptr (regs[5]), regs[6]);
1034               strnswap (regs[5], len);
1035               break;
1036             }
1037           case SYS_exit:
1038             /* EXIT - caller can look in r5 to work out the reason */
1039             raise_exception (SIGQUIT);
1040             regs[0] = regs[5];
1041             break;
1042
1043           case SYS_stat:        /* added at hmsi */
1044             /* stat system call */
1045             {
1046               struct stat host_stat;
1047               int buf;
1048               int len = strswaplen (regs[5]);
1049
1050               strnswap (regs[5], len);
1051               regs[0] = stat (ptr (regs[5]), &host_stat);
1052               strnswap (regs[5], len);
1053
1054               buf = regs[6];
1055
1056               WWAT (buf, host_stat.st_dev);
1057               buf += 2;
1058               WWAT (buf, host_stat.st_ino);
1059               buf += 2;
1060               WLAT (buf, host_stat.st_mode);
1061               buf += 4;
1062               WWAT (buf, host_stat.st_nlink);
1063               buf += 2;
1064               WWAT (buf, host_stat.st_uid);
1065               buf += 2;
1066               WWAT (buf, host_stat.st_gid);
1067               buf += 2;
1068               WWAT (buf, host_stat.st_rdev);
1069               buf += 2;
1070               WLAT (buf, host_stat.st_size);
1071               buf += 4;
1072               WLAT (buf, host_stat.st_atime);
1073               buf += 4;
1074               WLAT (buf, 0);
1075               buf += 4;
1076               WLAT (buf, host_stat.st_mtime);
1077               buf += 4;
1078               WLAT (buf, 0);
1079               buf += 4;
1080               WLAT (buf, host_stat.st_ctime);
1081               buf += 4;
1082               WLAT (buf, 0);
1083               buf += 4;
1084               WLAT (buf, 0);
1085               buf += 4;
1086               WLAT (buf, 0);
1087               buf += 4;
1088             }
1089             break;
1090
1091 #ifndef _WIN32
1092           case SYS_chown:
1093             {
1094               int len = strswaplen (regs[5]);
1095
1096               strnswap (regs[5], len);
1097               regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
1098               strnswap (regs[5], len);
1099               break;
1100             }
1101 #endif /* _WIN32 */
1102           case SYS_chmod:
1103             {
1104               int len = strswaplen (regs[5]);
1105
1106               strnswap (regs[5], len);
1107               regs[0] = chmod (ptr (regs[5]), regs[6]);
1108               strnswap (regs[5], len);
1109               break;
1110             }
1111           case SYS_utime:
1112             {
1113               /* Cast the second argument to void *, to avoid type mismatch
1114                  if a prototype is present.  */
1115               int len = strswaplen (regs[5]);
1116
1117               strnswap (regs[5], len);
1118               regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6]));
1119               strnswap (regs[5], len);
1120               break;
1121             }
1122           case SYS_argc:
1123             regs[0] = count_argc (prog_argv);
1124             break;
1125           case SYS_argnlen:
1126             if (regs[5] < count_argc (prog_argv))
1127               regs[0] = strlen (prog_argv[regs[5]]);
1128             else
1129               regs[0] = -1;
1130             break;
1131           case SYS_argn:
1132             if (regs[5] < count_argc (prog_argv))
1133               {
1134                 /* Include the termination byte.  */
1135                 int i = strlen (prog_argv[regs[5]]) + 1;
1136                 regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], i);
1137               }
1138             else
1139               regs[0] = -1;
1140             break;
1141           case SYS_time:
1142             regs[0] = get_now ();
1143             break;
1144           default:
1145             regs[0] = -1;
1146             break;
1147           }
1148         regs[1] = callback->get_errno (callback);
1149         errno = perrno;
1150       }
1151       break;
1152
1153     case 0xc3:
1154     case 255:
1155       raise_exception (SIGTRAP);
1156       break;
1157     }
1158
1159 }
1160
1161 void
1162 control_c (sig, code, scp, addr)
1163      int sig;
1164      int code;
1165      char *scp;
1166      char *addr;
1167 {
1168   raise_exception (SIGINT);
1169 }
1170
1171 static int
1172 div1 (R, iRn2, iRn1/*, T*/)
1173      int *R;
1174      int iRn1;
1175      int iRn2;
1176      /* int T;*/
1177 {
1178   unsigned long tmp0;
1179   unsigned char old_q, tmp1;
1180
1181   old_q = Q;
1182   SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0));
1183   R[iRn1] <<= 1;
1184   R[iRn1] |= (unsigned long) T;
1185
1186   switch (old_q)
1187     {
1188     case 0:
1189       switch (M)
1190         {
1191         case 0:
1192           tmp0 = R[iRn1];
1193           R[iRn1] -= R[iRn2];
1194           tmp1 = (R[iRn1] > tmp0);
1195           switch (Q)
1196             {
1197             case 0:
1198               SET_SR_Q (tmp1);
1199               break;
1200             case 1:
1201               SET_SR_Q ((unsigned char) (tmp1 == 0));
1202               break;
1203             }
1204           break;
1205         case 1:
1206           tmp0 = R[iRn1];
1207           R[iRn1] += R[iRn2];
1208           tmp1 = (R[iRn1] < tmp0);
1209           switch (Q)
1210             {
1211             case 0:
1212               SET_SR_Q ((unsigned char) (tmp1 == 0));
1213               break;
1214             case 1:
1215               SET_SR_Q (tmp1);
1216               break;
1217             }
1218           break;
1219         }
1220       break;
1221     case 1:
1222       switch (M)
1223         {
1224         case 0:
1225           tmp0 = R[iRn1];
1226           R[iRn1] += R[iRn2];
1227           tmp1 = (R[iRn1] < tmp0);
1228           switch (Q)
1229             {
1230             case 0:
1231               SET_SR_Q (tmp1);
1232               break;
1233             case 1:
1234               SET_SR_Q ((unsigned char) (tmp1 == 0));
1235               break;
1236             }
1237           break;
1238         case 1:
1239           tmp0 = R[iRn1];
1240           R[iRn1] -= R[iRn2];
1241           tmp1 = (R[iRn1] > tmp0);
1242           switch (Q)
1243             {
1244             case 0:
1245               SET_SR_Q ((unsigned char) (tmp1 == 0));
1246               break;
1247             case 1:
1248               SET_SR_Q (tmp1);
1249               break;
1250             }
1251           break;
1252         }
1253       break;
1254     }
1255   /*T = (Q == M);*/
1256   SET_SR_T (Q == M);
1257   /*return T;*/
1258 }
1259
1260 static void
1261 dmul (sign, rm, rn)
1262      int sign;
1263      unsigned int rm;
1264      unsigned int rn;
1265 {
1266   unsigned long RnL, RnH;
1267   unsigned long RmL, RmH;
1268   unsigned long temp0, temp1, temp2, temp3;
1269   unsigned long Res2, Res1, Res0;
1270
1271   RnL = rn & 0xffff;
1272   RnH = (rn >> 16) & 0xffff;
1273   RmL = rm & 0xffff;
1274   RmH = (rm >> 16) & 0xffff;
1275   temp0 = RmL * RnL;
1276   temp1 = RmH * RnL;
1277   temp2 = RmL * RnH;
1278   temp3 = RmH * RnH;
1279   Res2 = 0;
1280   Res1 = temp1 + temp2;
1281   if (Res1 < temp1)
1282     Res2 += 0x00010000;
1283   temp1 = (Res1 << 16) & 0xffff0000;
1284   Res0 = temp0 + temp1;
1285   if (Res0 < temp0)
1286     Res2 += 1;
1287   Res2 += ((Res1 >> 16) & 0xffff) + temp3;
1288
1289   if (sign)
1290     {
1291       if (rn & 0x80000000)
1292         Res2 -= rm;
1293       if (rm & 0x80000000)
1294         Res2 -= rn;
1295     }
1296
1297   MACH = Res2;
1298   MACL = Res0;
1299 }
1300
1301 static void
1302 macw (regs, memory, n, m, endianw)
1303      int *regs;
1304      unsigned char *memory;
1305      int m, n;
1306      int endianw;
1307 {
1308   long tempm, tempn;
1309   long prod, macl, sum;
1310
1311   tempm=RSWAT(regs[m]); regs[m]+=2;
1312   tempn=RSWAT(regs[n]); regs[n]+=2;
1313
1314   macl = MACL;
1315   prod = (long)(short) tempm * (long)(short) tempn;
1316   sum = prod + macl;
1317   if (S)
1318     {
1319       if ((~(prod ^ macl) & (sum ^ prod)) < 0)
1320         {
1321           /* MACH's lsb is a sticky overflow bit.  */
1322           MACH |= 1;
1323           /* Store the smallest negative number in MACL if prod is
1324              negative, and the largest positive number otherwise.  */
1325           sum = 0x7fffffff + (prod < 0);
1326         }
1327     }
1328   else
1329     {
1330       long mach;
1331       /* Add to MACH the sign extended product, and carry from low sum.  */
1332       mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
1333       /* Sign extend at 10:th bit in MACH.  */
1334       MACH = (mach & 0x1ff) | -(mach & 0x200);
1335     }
1336   MACL = sum;
1337 }
1338
1339 static struct loop_bounds
1340 get_loop_bounds (rs, re, memory, mem_end, maskw, endianw)
1341      int rs, re;
1342      unsigned char *memory, *mem_end;
1343      int maskw, endianw;
1344 {
1345   struct loop_bounds loop;
1346
1347   if (SR_RC)
1348     {
1349       if (RS >= RE)
1350         {
1351           loop.start = PT2H (RE - 4);
1352           SKIP_INSN (loop.start);
1353           loop.end = loop.start;
1354           if (RS - RE == 0)
1355             SKIP_INSN (loop.end);
1356           if (RS - RE <= 2)
1357             SKIP_INSN (loop.end);
1358           SKIP_INSN (loop.end);
1359         }
1360       else
1361         {
1362           loop.start = PT2H (RS);
1363           loop.end = PT2H (RE - 4);
1364           SKIP_INSN (loop.end);
1365           SKIP_INSN (loop.end);
1366           SKIP_INSN (loop.end);
1367           SKIP_INSN (loop.end);
1368         }
1369       if (loop.end >= mem_end)
1370         loop.end = PT2H (0);
1371     }
1372   else
1373     loop.end = PT2H (0);
1374
1375   return loop;
1376 }
1377
1378 static void
1379 ppi_insn();
1380
1381 #include "ppi.c"
1382
1383 /* Set the memory size to the power of two provided. */
1384
1385 void
1386 sim_size (power)
1387      int power;
1388
1389 {
1390   saved_state.asregs.msize = 1 << power;
1391
1392   sim_memory_size = power;
1393
1394   if (saved_state.asregs.memory)
1395     {
1396       free (saved_state.asregs.memory);
1397     }
1398
1399   saved_state.asregs.memory =
1400     (unsigned char *) calloc (64, saved_state.asregs.msize / 64);
1401
1402   if (!saved_state.asregs.memory)
1403     {
1404       fprintf (stderr,
1405                "Not enough VM for simulation of %d bytes of RAM\n",
1406                saved_state.asregs.msize);
1407
1408       saved_state.asregs.msize = 1;
1409       saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
1410     }
1411 }
1412
1413 static void
1414 init_dsp (abfd)
1415      struct _bfd *abfd;
1416 {
1417   int was_dsp = target_dsp;
1418   unsigned long mach = bfd_get_mach (abfd);
1419
1420   if (mach == bfd_mach_sh_dsp || mach == bfd_mach_sh3_dsp)
1421     {
1422       int ram_area_size, xram_start, yram_start;
1423       int new_select;
1424
1425       target_dsp = 1;
1426       if (mach == bfd_mach_sh_dsp)
1427         {
1428           /* SH7410 (orig. sh-sdp):
1429              4KB each for X & Y memory;
1430              On-chip X RAM 0x0800f000-0x0800ffff
1431              On-chip Y RAM 0x0801f000-0x0801ffff  */
1432           xram_start = 0x0800f000;
1433           ram_area_size = 0x1000;
1434         }
1435       if (mach == bfd_mach_sh3_dsp)
1436         {
1437           /* SH7612:
1438              8KB each for X & Y memory;
1439              On-chip X RAM 0x1000e000-0x1000ffff
1440              On-chip Y RAM 0x1001e000-0x1001ffff  */
1441           xram_start = 0x1000e000;
1442           ram_area_size = 0x2000;
1443         }
1444       yram_start = xram_start + 0x10000;
1445       new_select = ~(ram_area_size - 1);
1446       if (saved_state.asregs.xyram_select != new_select)
1447         {
1448           saved_state.asregs.xyram_select = new_select;
1449           free (saved_state.asregs.xmem);
1450           free (saved_state.asregs.ymem);
1451           saved_state.asregs.xmem = (unsigned char *) calloc (1, ram_area_size);
1452           saved_state.asregs.ymem = (unsigned char *) calloc (1, ram_area_size);
1453
1454           /* Disable use of X / Y mmeory if not allocated.  */
1455           if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
1456             {
1457               saved_state.asregs.xyram_select = 0;
1458               if (saved_state.asregs.xmem)
1459                 free (saved_state.asregs.xmem);
1460               if (saved_state.asregs.ymem)
1461                 free (saved_state.asregs.ymem);
1462             }
1463         }
1464       saved_state.asregs.xram_start = xram_start;
1465       saved_state.asregs.yram_start = yram_start;
1466       saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
1467       saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
1468     }
1469   else
1470     {
1471       target_dsp = 0;
1472       if (saved_state.asregs.xyram_select)
1473         {
1474           saved_state.asregs.xyram_select = 0;
1475           free (saved_state.asregs.xmem);
1476           free (saved_state.asregs.ymem);
1477         }
1478     }
1479
1480   if (! saved_state.asregs.xyram_select)
1481     {
1482       saved_state.asregs.xram_start = 1;
1483       saved_state.asregs.yram_start = 1;
1484     }
1485
1486   if (target_dsp != was_dsp)
1487     {
1488       int i, tmp;
1489
1490       for (i = sizeof sh_dsp_table - 1; i >= 0; i--)
1491         {
1492           tmp = sh_jump_table[0xf000 + i];
1493           sh_jump_table[0xf000 + i] = sh_dsp_table[i];
1494           sh_dsp_table[i] = tmp;
1495         }
1496     }
1497 }
1498
1499 static void
1500 init_pointers ()
1501 {
1502   host_little_endian = 0;
1503   *(char*)&host_little_endian = 1;
1504   host_little_endian &= 1;
1505
1506   if (saved_state.asregs.msize != 1 << sim_memory_size)
1507     {
1508       sim_size (sim_memory_size);
1509     }
1510
1511   if (saved_state.asregs.profile && !profile_file)
1512     {
1513       profile_file = fopen ("gmon.out", "wb");
1514       /* Seek to where to put the call arc data */
1515       nsamples = (1 << sim_profile_size);
1516
1517       fseek (profile_file, nsamples * 2 + 12, 0);
1518
1519       if (!profile_file)
1520         {
1521           fprintf (stderr, "Can't open gmon.out\n");
1522         }
1523       else
1524         {
1525           saved_state.asregs.profile_hist =
1526             (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
1527         }
1528     }
1529 }
1530
1531 static void
1532 dump_profile ()
1533 {
1534   unsigned int minpc;
1535   unsigned int maxpc;
1536   unsigned short *p;
1537   int i;
1538
1539   p = saved_state.asregs.profile_hist;
1540   minpc = 0;
1541   maxpc = (1 << sim_profile_size);
1542
1543   fseek (profile_file, 0L, 0);
1544   swapout (minpc << PROFILE_SHIFT);
1545   swapout (maxpc << PROFILE_SHIFT);
1546   swapout (nsamples * 2 + 12);
1547   for (i = 0; i < nsamples; i++)
1548     swapout16 (saved_state.asregs.profile_hist[i]);
1549
1550 }
1551
1552 static void
1553 gotcall (from, to)
1554      int from;
1555      int to;
1556 {
1557   swapout (from);
1558   swapout (to);
1559   swapout (1);
1560 }
1561
1562 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1563
1564 int
1565 sim_stop (sd)
1566      SIM_DESC sd;
1567 {
1568   raise_exception (SIGINT);
1569   return 1;
1570 }
1571
1572 void
1573 sim_resume (sd, step, siggnal)
1574      SIM_DESC sd;
1575      int step, siggnal;
1576 {
1577   register unsigned char *insn_ptr;
1578   unsigned char *mem_end;
1579   struct loop_bounds loop;
1580   register int cycles = 0;
1581   register int stalls = 0;
1582   register int memstalls = 0;
1583   register int insts = 0;
1584   register int prevlock;
1585   register int thislock;
1586   register unsigned int doprofile;
1587   register int pollcount = 0;
1588   /* endianw is used for every insn fetch, hence it makes sense to cache it.
1589      endianb is used less often.  */
1590   register int endianw = global_endianw;
1591
1592   int tick_start = get_now ();
1593   void (*prev) ();
1594   void (*prev_fpe) ();
1595
1596   register unsigned char *jump_table = sh_jump_table;
1597
1598   register int *R = &(saved_state.asregs.regs[0]);
1599   /*register int T;*/
1600 #ifndef PR
1601   register int PR;
1602 #endif
1603
1604   register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1605   register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
1606   register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
1607   register unsigned char *memory;
1608   register unsigned int sbit = ((unsigned int) 1 << 31);
1609
1610   prev = signal (SIGINT, control_c);
1611   prev_fpe = signal (SIGFPE, SIG_IGN);
1612
1613   init_pointers ();
1614   saved_state.asregs.exception = 0;
1615
1616   memory = saved_state.asregs.memory;
1617   mem_end = memory + saved_state.asregs.msize;
1618
1619   loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
1620   insn_ptr = PT2H (saved_state.asregs.pc);
1621   CHECK_INSN_PTR (insn_ptr);
1622
1623 #ifndef PR
1624   PR = saved_state.asregs.sregs.named.pr;
1625 #endif
1626   /*T = GET_SR () & SR_MASK_T;*/
1627   prevlock = saved_state.asregs.prevlock;
1628   thislock = saved_state.asregs.thislock;
1629   doprofile = saved_state.asregs.profile;
1630
1631   /* If profiling not enabled, disable it by asking for
1632      profiles infrequently. */
1633   if (doprofile == 0)
1634     doprofile = ~0;
1635
1636  loop:
1637   if (step && insn_ptr < saved_state.asregs.insn_end)
1638     {
1639       if (saved_state.asregs.exception)
1640         /* This can happen if we've already been single-stepping and
1641            encountered a loop end.  */
1642         saved_state.asregs.insn_end = insn_ptr;
1643       else
1644         {
1645           saved_state.asregs.exception = SIGTRAP;
1646           saved_state.asregs.insn_end = insn_ptr + 2;
1647         }
1648     }
1649
1650   while (insn_ptr < saved_state.asregs.insn_end)
1651     {
1652       register unsigned int iword = RIAT (insn_ptr);
1653       register unsigned int ult;
1654       register unsigned char *nip = insn_ptr + 2;
1655
1656 #ifndef ACE_FAST
1657       insts++;
1658 #endif
1659     top:
1660
1661 #include "code.c"
1662
1663
1664       insn_ptr = nip;
1665
1666       if (--pollcount < 0)
1667         {
1668           pollcount = POLL_QUIT_INTERVAL;
1669           if ((*callback->poll_quit) != NULL
1670               && (*callback->poll_quit) (callback))
1671             {
1672               sim_stop (sd);
1673             }
1674         }
1675
1676 #ifndef ACE_FAST
1677       prevlock = thislock;
1678       thislock = 30;
1679       cycles++;
1680
1681       if (cycles >= doprofile)
1682         {
1683
1684           saved_state.asregs.cycles += doprofile;
1685           cycles -= doprofile;
1686           if (saved_state.asregs.profile_hist)
1687             {
1688               int n = PH2T (insn_ptr) >> PROFILE_SHIFT;
1689               if (n < nsamples)
1690                 {
1691                   int i = saved_state.asregs.profile_hist[n];
1692                   if (i < 65000)
1693                     saved_state.asregs.profile_hist[n] = i + 1;
1694                 }
1695
1696             }
1697         }
1698 #endif
1699     }
1700   if (saved_state.asregs.insn_end == loop.end)
1701     {
1702       saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
1703       if (SR_RC)
1704         insn_ptr = loop.start;
1705       else
1706         {
1707           saved_state.asregs.insn_end = mem_end;
1708           loop.end = PT2H (0);
1709         }
1710       goto loop;
1711     }
1712
1713   if (saved_state.asregs.exception == SIGILL
1714       || saved_state.asregs.exception == SIGBUS)
1715     {
1716       insn_ptr -= 2;
1717     }
1718   /* Check for SIGBUS due to insn fetch.  */
1719   else if (! saved_state.asregs.exception)
1720     saved_state.asregs.exception == SIGBUS;
1721
1722   saved_state.asregs.ticks += get_now () - tick_start;
1723   saved_state.asregs.cycles += cycles;
1724   saved_state.asregs.stalls += stalls;
1725   saved_state.asregs.memstalls += memstalls;
1726   saved_state.asregs.insts += insts;
1727   saved_state.asregs.pc = PH2T (insn_ptr);
1728 #ifndef PR
1729   saved_state.asregs.sregs.named.pr = PR;
1730 #endif
1731
1732   saved_state.asregs.prevlock = prevlock;
1733   saved_state.asregs.thislock = thislock;
1734
1735   if (profile_file)
1736     {
1737       dump_profile ();
1738     }
1739
1740   signal (SIGFPE, prev_fpe);
1741   signal (SIGINT, prev);
1742 }
1743
1744 int
1745 sim_write (sd, addr, buffer, size)
1746      SIM_DESC sd;
1747      SIM_ADDR addr;
1748      unsigned char *buffer;
1749      int size;
1750 {
1751   int i;
1752
1753   init_pointers ();
1754
1755   for (i = 0; i < size; i++)
1756     {
1757       saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i];
1758     }
1759   return size;
1760 }
1761
1762 int
1763 sim_read (sd, addr, buffer, size)
1764      SIM_DESC sd;
1765      SIM_ADDR addr;
1766      unsigned char *buffer;
1767      int size;
1768 {
1769   int i;
1770
1771   init_pointers ();
1772
1773   for (i = 0; i < size; i++)
1774     {
1775       buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
1776     }
1777   return size;
1778 }
1779
1780 int
1781 sim_store_register (sd, rn, memory, length)
1782      SIM_DESC sd;
1783      int rn;
1784      unsigned char *memory;
1785      int length;
1786 {
1787   unsigned val;
1788
1789   init_pointers ();
1790   val = swap (* (int *)memory);
1791   switch (rn)
1792     {
1793     case  0: case  1: case  2: case  3: case  4: case  5: case  6: case  7:
1794     case  8: case  9: case 10: case 11: case 12: case 13: case 14: case 15:
1795       saved_state.asregs.regs[rn] = val;
1796       break;
1797     case 16:
1798       saved_state.asregs.pc = val;
1799       break;
1800     case 17:
1801       PR = val;
1802       break;
1803     case 18:
1804       GBR = val;
1805       break;
1806     case 19:
1807       VBR = val;
1808       break;
1809     case 20:
1810       MACH = val;
1811       break;
1812     case 21:
1813       MACL = val;
1814       break;
1815     case 22:
1816       SET_SR (val);
1817       break;
1818     case 23:
1819       FPUL = val;
1820       break;
1821     case 24:
1822       SET_FPSCR (val);
1823       break;
1824     case 25:
1825       if (target_dsp)
1826         A0G = val;
1827     else case 26:
1828       if (target_dsp)
1829         A0 = val;
1830     else case 27:
1831       if (target_dsp)
1832         A1G = val;
1833     else case 28:
1834       if (target_dsp)
1835         A1 = val;
1836     else case 29:
1837       if (target_dsp)
1838         M0 = val;
1839     else case 30:
1840       if (target_dsp)
1841         M1 = val;
1842     else case 31:
1843       if (target_dsp)
1844         X0 = val;
1845     else case 32:
1846       if (target_dsp)
1847         X1 = val;
1848     else case 33:
1849       if (target_dsp)
1850         Y0 = val;
1851     else case 34:
1852       if (target_dsp)
1853         Y1 = val;
1854     else case 40:
1855       if (target_dsp)
1856         SET_MOD (val);
1857     else case 35: case 36: case 37: case 38: case 39:
1858         SET_FI (rn - 25, val);
1859       break;
1860     case 41:
1861       SSR = val;
1862       break;
1863     case 42:
1864       SPC = val;
1865       break;
1866     /* The rn_bank idiosyncracies are not due to hardware differences, but to
1867        a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
1868     case 43:
1869       if (target_dsp)
1870         RS = val;
1871     else case 44:
1872       if (target_dsp)
1873         RE = val;
1874     else case 45: case 46: case 47: case 48: case 49: case 50:
1875       if (SR_MD && SR_RB)
1876         Rn_BANK (rn - 43) = val;
1877       else
1878         saved_state.asregs.regs[rn - 43] = val;
1879       break;
1880     case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
1881       if (target_dsp || ! SR_MD || ! SR_RB)
1882         SET_Rn_BANK (rn - 51, val);
1883       else
1884         saved_state.asregs.regs[rn - 51] = val;
1885       break;
1886     default:
1887       return 0;
1888     }
1889   return -1;
1890 }
1891
1892 int
1893 sim_fetch_register (sd, rn, memory, length)
1894      SIM_DESC sd;
1895      int rn;
1896      unsigned char *memory;
1897      int length;
1898 {
1899   int val;
1900
1901   init_pointers ();
1902   switch (rn)
1903     {
1904     case  0: case  1: case  2: case  3: case  4: case  5: case  6: case  7:
1905     case  8: case  9: case 10: case 11: case 12: case 13: case 14: case 15:
1906       val = saved_state.asregs.regs[rn];
1907       break;
1908     case 16:
1909       val = saved_state.asregs.pc;
1910       break;
1911     case 17:
1912       val = PR;
1913       break;
1914     case 18:
1915       val = GBR;
1916       break;
1917     case 19:
1918       val = VBR;
1919       break;
1920     case 20:
1921       val = MACH;
1922       break;
1923     case 21:
1924       val = MACL;
1925       break;
1926     case 22:
1927       val = GET_SR ();
1928       break;
1929     case 23:
1930       val = FPUL;
1931       break;
1932     case 24:
1933       val = GET_FPSCR ();
1934       break;
1935     case 25:
1936       val = target_dsp ? SEXT (A0G) : FI (0);
1937       break;
1938     case 26:
1939       val = target_dsp ? A0 : FI (1);
1940       break;
1941     case 27:
1942       val = target_dsp ? SEXT (A1G) : FI (2);
1943       break;
1944     case 28:
1945       val = target_dsp ? A1 : FI (3);
1946       break;
1947     case 29:
1948       val = target_dsp ? M0 : FI (4);
1949       break;
1950     case 30:
1951       val = target_dsp ? M1 : FI (5);
1952       break;
1953     case 31:
1954       val = target_dsp ? X0 : FI (6);
1955       break;
1956     case 32:
1957       val = target_dsp ? X1 : FI (7);
1958       break;
1959     case 33:
1960       val = target_dsp ? Y0 : FI (8);
1961       break;
1962     case 34:
1963       val = target_dsp ? Y1 : FI (9);
1964       break;
1965     case 35: case 36: case 37: case 38: case 39:
1966       val = FI (rn - 25);
1967       break;
1968     case 40:
1969       val = target_dsp ? MOD : FI (15);
1970       break;
1971     case 41:
1972       val = SSR;
1973       break;
1974     case 42:
1975       val = SPC;
1976       break;
1977     /* The rn_bank idiosyncracies are not due to hardware differences, but to
1978        a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
1979     case 43:
1980       if (target_dsp)
1981         val = RS;
1982     else case 44:
1983       if (target_dsp)
1984         val = RE;
1985     else case 45: case 46: case 47: case 48: case 49: case 50:
1986         val = (SR_MD && SR_RB
1987                ? Rn_BANK (rn - 43)
1988                : saved_state.asregs.regs[rn - 43]);
1989       break;
1990     case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
1991       val = (target_dsp || ! SR_MD || ! SR_RB
1992              ? Rn_BANK (rn - 51)
1993              : saved_state.asregs.regs[rn - 51]);
1994       break;
1995     default:
1996       return 0;
1997     }
1998   * (int *) memory = swap (val);
1999   return -1;
2000 }
2001
2002 int
2003 sim_trace (sd)
2004      SIM_DESC sd;
2005 {
2006   return 0;
2007 }
2008
2009 void
2010 sim_stop_reason (sd, reason, sigrc)
2011      SIM_DESC sd;
2012      enum sim_stop *reason;
2013      int *sigrc;
2014 {
2015   /* The SH simulator uses SIGQUIT to indicate that the program has
2016      exited, so we must check for it here and translate it to exit.  */
2017   if (saved_state.asregs.exception == SIGQUIT)
2018     {
2019       *reason = sim_exited;
2020       *sigrc = saved_state.asregs.regs[5];
2021     }
2022   else
2023     {
2024       *reason = sim_stopped;
2025       *sigrc = saved_state.asregs.exception;
2026     }
2027 }
2028
2029 void
2030 sim_info (sd, verbose)
2031      SIM_DESC sd;
2032      int verbose;
2033 {
2034   double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
2035   double virttime = saved_state.asregs.cycles / 36.0e6;
2036
2037   callback->printf_filtered (callback, "\n\n# instructions executed  %10d\n",
2038                              saved_state.asregs.insts);
2039   callback->printf_filtered (callback, "# cycles                 %10d\n",
2040                              saved_state.asregs.cycles);
2041   callback->printf_filtered (callback, "# pipeline stalls        %10d\n",
2042                              saved_state.asregs.stalls);
2043   callback->printf_filtered (callback, "# misaligned load/store  %10d\n",
2044                              saved_state.asregs.memstalls);
2045   callback->printf_filtered (callback, "# real time taken        %10.4f\n",
2046                              timetaken);
2047   callback->printf_filtered (callback, "# virtual time taken     %10.4f\n",
2048                              virttime);
2049   callback->printf_filtered (callback, "# profiling size         %10d\n",
2050                              sim_profile_size);
2051   callback->printf_filtered (callback, "# profiling frequency    %10d\n",
2052                              saved_state.asregs.profile);
2053   callback->printf_filtered (callback, "# profile maxpc          %10x\n",
2054                              (1 << sim_profile_size) << PROFILE_SHIFT);
2055
2056   if (timetaken != 0)
2057     {
2058       callback->printf_filtered (callback, "# cycles/second          %10d\n",
2059                                  (int) (saved_state.asregs.cycles / timetaken));
2060       callback->printf_filtered (callback, "# simulation ratio       %10.4f\n",
2061                                  virttime / timetaken);
2062     }
2063 }
2064
2065 void
2066 sim_set_profile (n)
2067      int n;
2068 {
2069   saved_state.asregs.profile = n;
2070 }
2071
2072 void
2073 sim_set_profile_size (n)
2074      int n;
2075 {
2076   sim_profile_size = n;
2077 }
2078
2079 SIM_DESC
2080 sim_open (kind, cb, abfd, argv)
2081      SIM_OPEN_KIND kind;
2082      host_callback *cb;
2083      struct _bfd *abfd;
2084      char **argv;
2085 {
2086   char **p;
2087   int endian_set = 0;
2088   int i;
2089   union
2090     {
2091       int i;
2092       short s[2];
2093       char c[4];
2094     }
2095   mem_word;
2096
2097   sim_kind = kind;
2098   myname = argv[0];
2099   callback = cb;
2100
2101   for (p = argv + 1; *p != NULL; ++p)
2102     {
2103       if (strcmp (*p, "-E") == 0)
2104         {
2105           ++p;
2106           if (*p == NULL)
2107             {
2108               /* FIXME: This doesn't use stderr, but then the rest of the
2109                  file doesn't either.  */
2110               callback->printf_filtered (callback, "Missing argument to `-E'.\n");
2111               return 0;
2112             }
2113           target_little_endian = strcmp (*p, "big") != 0;
2114           endian_set = 1;
2115         }
2116       else if (isdigit (**p))
2117         parse_and_set_memory_size (*p);
2118     }
2119
2120   if (abfd != NULL && ! endian_set)
2121       target_little_endian = ! bfd_big_endian (abfd);
2122
2123   if (abfd)
2124     init_dsp (abfd);
2125
2126   for (i = 4; (i -= 2) >= 0; )
2127     mem_word.s[i >> 1] = i;
2128   global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;
2129
2130   for (i = 4; --i >= 0; )
2131     mem_word.c[i] = i;
2132   endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;
2133
2134   /* fudge our descriptor for now */
2135   return (SIM_DESC) 1;
2136 }
2137
2138 static void
2139 parse_and_set_memory_size (str)
2140      char *str;
2141 {
2142   int n;
2143
2144   n = strtol (str, NULL, 10);
2145   if (n > 0 && n <= 24)
2146     sim_memory_size = n;
2147   else
2148     callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
2149 }
2150
2151 void
2152 sim_close (sd, quitting)
2153      SIM_DESC sd;
2154      int quitting;
2155 {
2156   /* nothing to do */
2157 }
2158
2159 SIM_RC
2160 sim_load (sd, prog, abfd, from_tty)
2161      SIM_DESC sd;
2162      char *prog;
2163      bfd *abfd;
2164      int from_tty;
2165 {
2166   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
2167   bfd *prog_bfd;
2168
2169   prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
2170                             sim_kind == SIM_OPEN_DEBUG,
2171                             0, sim_write);
2172   if (prog_bfd == NULL)
2173     return SIM_RC_FAIL;
2174   if (abfd == NULL)
2175     bfd_close (prog_bfd);
2176   return SIM_RC_OK;
2177 }
2178
2179 SIM_RC
2180 sim_create_inferior (sd, prog_bfd, argv, env)
2181      SIM_DESC sd;
2182      struct _bfd *prog_bfd;
2183      char **argv;
2184      char **env;
2185 {
2186   /* Clear the registers. */
2187   memset (&saved_state, 0,
2188           (char*)&saved_state.asregs.end_of_registers - (char*)&saved_state);
2189
2190   /* Set the PC.  */
2191   if (prog_bfd != NULL)
2192     saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
2193
2194   /* Record the program's arguments. */
2195   prog_argv = argv;
2196
2197   return SIM_RC_OK;
2198 }
2199
2200 void
2201 sim_do_command (sd, cmd)
2202      SIM_DESC sd;
2203      char *cmd;
2204 {
2205   char *sms_cmd = "set-memory-size";
2206   int cmdsize;
2207
2208   if (cmd == NULL || *cmd == '\0')
2209     {
2210       cmd = "help";
2211     }
2212
2213   cmdsize = strlen (sms_cmd);
2214   if (strncmp (cmd, sms_cmd, cmdsize) == 0 && strchr (" \t", cmd[cmdsize]) != NULL)
2215     {
2216       parse_and_set_memory_size (cmd + cmdsize + 1);
2217     }
2218   else if (strcmp (cmd, "help") == 0)
2219     {
2220       (callback->printf_filtered) (callback, "List of SH simulator commands:\n\n");
2221       (callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
2222       (callback->printf_filtered) (callback, "\n");
2223     }
2224   else
2225     {
2226       (callback->printf_filtered) (callback, "Error: \"%s\" is not a valid SH simulator command.\n", cmd);
2227     }
2228 }
2229
2230 void
2231 sim_set_callbacks (p)
2232      host_callback *p;
2233 {
2234   callback = p;
2235 }