sim/sh/sim-main.h

   1 /* Moxie Simulator definition.
   2    Copyright (C) 2009-2022 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, the GNU debugger.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef SIM_MAIN_H
  20 #define SIM_MAIN_H
  21
  22 #include "sim-basics.h"
  23 #include "sim-base.h"
  24
  25 typedef struct
  26 {
  27   int regs[20];
  28 } regstacktype;
  29
  30 typedef union
  31 {
  32
  33   struct
  34   {
  35     int regs[16];
  36     int pc;
  37
  38     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
  39        which are located in fregs.  Probably should include pc too - to avoid
  40        alignment repercussions.  */
  41     union {
  42       struct {
  43         int mach;
  44         int macl;
  45         int pr;
  46         int dummy3, dummy4;
  47         int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
  48         int fpscr; /* dsr for sh-dsp */
  49
  50         /* sh3e / sh-dsp */
  51         union fregs_u {
  52           float f[16];
  53           double d[8];
  54           int i[16];
  55         } fregs[2];
  56       };
  57       int sregs[39];
  58     };
  59
  60     /* Control registers; on the SH4, ldc / stc is privileged, except when
  61        accessing gbr.  */
  62     union
  63       {
  64         struct
  65           {
  66             int sr;
  67             int gbr;
  68             int vbr;
  69             int ssr;
  70             int spc;
  71             int mod;
  72             /* sh-dsp */
  73             int rs;
  74             int re;
  75             /* sh3 */
  76             int bank[8];
  77             int dbr;            /* debug base register */
  78             int sgr;            /* saved gr15 */
  79             int ldst;           /* load/store flag (boolean) */
  80             int tbr;
  81             int ibcr;           /* sh2a bank control register */
  82             int ibnr;           /* sh2a bank number register */
  83           };
  84         int cregs[16];
  85       };
  86
  87     unsigned char *insn_end;
  88
  89     int ticks;
  90     int stalls;
  91     int memstalls;
  92     int cycles;
  93     int insts;
  94
  95     int prevlock;
  96     int thislock;
  97     int exception;
  98
  99     int end_of_registers;
 100
 101     int msize;
 102 #define PROFILE_FREQ 1
 103 #define PROFILE_SHIFT 2
 104     int profile;
 105     unsigned short *profile_hist;
 106     unsigned char *memory;
 107     int xyram_select, xram_start, yram_start;
 108     unsigned char *xmem;
 109     unsigned char *ymem;
 110     unsigned char *xmem_offset;
 111     unsigned char *ymem_offset;
 112     unsigned long bfd_mach;
 113     regstacktype *regstack;
 114   } asregs;
 115   int asints[40];
 116 } saved_state_type;
 117
 118 /* TODO: Move into sim_cpu.  */
 119 extern saved_state_type saved_state;
 120
 121 struct _sim_cpu {
 122
 123   sim_cpu_base base;
 124 };
 125
 126 #endif