sim/testsuite/sim/bfin/a11.S

   1 //  Test ALU   RND RND12 RND20
   2 # mach: bfin
   3
   4 #include "test.h"
   5 .include "testutils.inc"
   6         start
   7
   8
   9         R7 = 0;
  10         ASTAT = R7;
  11
  12 //    7ffffff0
  13 // +  00008000
  14 // -> 7fff0000
  15         R0 = 0xfff0 (Z);
  16         R0.H = 0x7fff;
  17         R7.L = R0 (RND);
  18         R0 = ASTAT;
  19         CHECKREG R7, 0x7fff;
  20         CHECKREG R0, (_VS|_V|_V_COPY);
  21
  22 //    7ffffff0
  23 // +  00008000
  24 // -> 7fff0000
  25         R0.L = 0xfff0;
  26         R0.H = 0x7fff;
  27         R7.H = R0 (RND);
  28         R0 = ASTAT;
  29         CHECKREG R7, 0x7fff7fff;
  30         CHECKREG R0, (_VS|_V|_V_COPY);
  31
  32 //    7ff0fff0
  33 // +  00008000
  34 // -> 7ff10000
  35         R0.L = 0xfff0;
  36         R0.H = 0x7ff0;
  37         R7.L = R0 (RND);
  38         R0 = ASTAT;
  39         CHECKREG R7, 0x7fff7ff1
  40         CHECKREG R0, (_VS);
  41
  42 //    7ff0fff0
  43 // +  00008000
  44 // -> 7ff10000
  45 // 7ff0fff0
  46 // +   8000
  47 // -> 7ff1
  48         R0.L = 0xfff0;
  49         R0.H = 0x7ff0;
  50         R7.H = R0 (RND);
  51         R0 = ASTAT;
  52         CHECKREG R7, 0x7ff17ff1
  53         CHECKREG R0, (_VS);
  54
  55 //    fffffff0
  56 // +  00008000
  57 // -> 00000000
  58         R0.L = 0xfff0;
  59         R0.H = 0xffff;
  60         R7.L = R0 (RND);
  61         R0 = ASTAT;
  62         CHECKREG R7, 0x7ff10000;
  63         CHECKREG R0, (_VS|_AZ);
  64
  65 //    fffffff0
  66 // +  00008000
  67 // -> 00000000
  68         R0.L = 0xfff0;
  69         R0.H = 0xffff;
  70         R7.H = R0 (RND);
  71         R0 = ASTAT;
  72         DBGA ( R7.H , 0 );
  73         CHECKREG R0, (_VS|_AZ);
  74
  75 //    00fffff0
  76 // +  00008000
  77 // -> 0100
  78         R0.L = 0xfff0;
  79         R0.H = 0x00ff;
  80         R7.L = R0 (RND);
  81         R0 = ASTAT;
  82         DBGA ( R7.L , 0x0100 );
  83         CHECKREG R0, (_VS);
  84
  85 // RND12
  86
  87 //    07ffe000
  88 // +  00000000
  89 // =  07ffe000
  90 // +  00000800
  91 // ->  7ffe
  92         R0.L = 0xe000;
  93         R0.H = 0x07ff;
  94         R1 = 0x0000 (Z);
  95         R1.H = 0x0000;
  96         R7.L = R0 + R1 (RND12);
  97         R0 = ASTAT;
  98         DBGA ( R7.L , 0x7ffe );
  99         CHECKREG R0, (_VS);
 100
 101 //    07ffff00
 102 // +  00000000
 103 // =  07ffff00
 104 // +  00000800
 105 // ->  7fff
 106         R0.L = 0xff00;
 107         R0.H = 0x07ff;
 108         R1.L = 0x0000;
 109         R1.H = 0x0000;
 110         R7.L = R0 + R1 (RND12);
 111         R0 = ASTAT;
 112         DBGA ( R7.L , 0x7fff );
 113         CHECKREG R0, (_VS|_V|_V_COPY);
 114
 115 //    07fffc00
 116 // +  00000f00
 117 // =  08000b00
 118 // +  00000800
 119 // ->  7fff
 120         R0.L = 0xfc00;
 121         R0.H = 0x07ff;
 122         R1.L = 0x0f00;
 123         R1.H = 0x0000;
 124         R7.L = R0 + R1 (RND12);
 125         R0 = ASTAT;
 126         DBGA ( R7.L , 0x7fff );
 127         CHECKREG R0, (_VS|_V|_V_COPY);
 128
 129 //    07ff c000
 130 // +  0000 1000
 131 // =  07ff d000
 132 // +  0000 0800
 133 // ->  7ff d
 134         R0.L = 0xc000;
 135         R0.H = 0x07ff;
 136         R1.L = 0x1000;
 137         R1.H = 0x0000;
 138         _DBG ASTAT;
 139         R7.L = R0 + R1 (RND12);
 140         _DBG ASTAT;
 141         R0 = ASTAT;
 142         _DBG R0;
 143         DBGA ( R7.L , 0x7ffd );
 144         CHECKREG R0, (_VS);
 145
 146 //    ffff ffea
 147 // +  07ff fe00
 148 // = 107ff fdea
 149 // +  0000 0800
 150 // ->  7ff f
 151         R0.L = 0xffea;
 152         R0.H = 0xffff;
 153         R1.L = 0xfe00;
 154         R1.H = 0x07ff;
 155         _DBG ASTAT;
 156         R7.L = R0 + R1 (RND12);
 157         _DBG ASTAT;
 158         R0 = ASTAT;
 159         _DBG R0;
 160         DBGA ( R7.L , 0x7fff );
 161         CHECKREG R0, (_VS|_V|_V_COPY);
 162
 163 // Small negative plus small negative should give zero
 164 //    ffff ffff
 165 // +  ffff ffff
 166 // +  0000 0800
 167 // ->  000 0
 168         R0.L = 0xffff;
 169         R0.H = 0xffff;
 170         R1.L = 0xffff;
 171         R1.H = 0xffff;
 172         _DBG ASTAT;
 173         R7.L = R0 + R1 (RND12);
 174         R0 = ASTAT;
 175         _DBG R0;
 176         DBGA ( R7.L , 0x0000 );
 177         CHECKREG R0, (_VS|_AZ);
 178
 179 // Small negative minus small positive should give zero
 180 //    ffff ffff
 181 // +  0000 0001
 182 // -  0000 0800
 183 // ->  000 0
 184         R0.L = 0xffff;
 185         R0.H = 0xffff;
 186         R1.L = 0x0001;
 187         R1.H = 0x0000;
 188         R7.L = R0 - R1 (RND12);
 189         R0 = ASTAT;
 190         DBGA ( R7.L , 0x0000 );
 191         CHECKREG R0, (_VS|_AZ);
 192
 193 // Large positive plus large positive should give maxpos
 194 //    07ff ffff
 195 // +  07ff ffff
 196 // +  0000 0800
 197 // ->  7ff f
 198         R0.L = 0xffff;
 199         R0.H = 0x07ff;
 200         R1.L = 0xffff;
 201         R1.H = 0x07ff;
 202         R7.L = R0 + R1 (RND12);
 203         R0 = ASTAT;
 204         DBGA ( R7.L , 0x7fff );
 205         CHECKREG R0, (_VS|_V|_V_COPY);
 206
 207 // Large negative plus large negative should give maxneg
 208 //    0800 0000
 209 // +  0800 0000
 210 // +  0000 0800
 211 // ->  800 0
 212         R0.L = 0x0000;
 213         R0.H = 0x0800;
 214         R1.L = 0x0000;
 215         R1.H = 0x0800;
 216         R7.L = R0 + R1 (RND12);
 217         R0 = ASTAT;
 218         DBGA ( R7.L , 0x7fff );
 219         CHECKREG R0, (_VS|_V|_V_COPY);
 220
 221 // Large positive minus large negative should give maxpos
 222 //    07ff ffff
 223 // -  0800 0000
 224 // +  0000 0800
 225 // ->  800 0
 226         R0.L = 0xffff;
 227         R0.H = 0x07ff;
 228         R1.L = 0x0000;
 229         R1.H = 0x0800;
 230         R7.L = R0 - R1 (RND12);
 231         R0 = ASTAT;
 232         _DBG ASTAT;
 233         DBGA ( R7.L , 0x0 );
 234         CHECKREG R0, (_VS|_AZ);
 235
 236 // Large negative minus large positive should give maxneg
 237 //    0800 0000
 238 // -  07ff ffff
 239 // +  0000 0800
 240 // ->  800 0
 241         R0.L = 0x0000;
 242         R0.H = 0x0800;
 243         R1.L = 0xffff;
 244         R1.H = 0x07ff;
 245         R7.L = R0 - R1 (RND12);
 246         R0 = ASTAT;
 247         _DBG ASTAT;
 248         DBGA ( R7.L , 0x0000 );
 249         CHECKREG R0, (_VS|_AZ);
 250
 251 //    cef4 3ed6
 252 // -  56f4 417a
 253 // +  0000 0800
 254 // ->  800 0
 255         R0.L = 0x3ed6;
 256         R0.H = 0xcef4;
 257         R1.L = 0x417a;
 258         R1.H = 0x56f4;
 259         R7.L = R0 - R1 (RND12);
 260         R0 = ASTAT;
 261         DBGA ( R7.L , 0x8000 );
 262         CHECKREG R0, (_VS|_V|_V_COPY|_AN);
 263
 264 // RND20
 265
 266 //    00ff 0000
 267 // +  0000 0000
 268 // +  0008 0000
 269 // ->0010
 270         R0.L = 0x0000;
 271         R0.H = 0x00ff;
 272         R1.L = 0x0000;
 273         R1.H = 0x0000;
 274         R7.L = R0 + R1 (RND20);
 275         R0 = ASTAT;
 276         DBGA ( R7.L , 0x0010 );
 277         CHECKREG R0, (_VS);
 278
 279 //    00f0 0000
 280 // +  000f 0000
 281 // +  0008 0000
 282 // ->0010
 283         R0.L = 0x0000;
 284         R0.H = 0x00f0;
 285         R1.L = 0x0000;
 286         R1.H = 0x000f;
 287         R7.L = R0 + R1 (RND20);
 288         R0 = ASTAT;
 289         DBGA ( R7.L , 0x0010 );
 290         CHECKREG R0, (_VS);
 291
 292 //    7ff0 0000
 293 // +  0000 0000
 294 // +  0008 0000
 295 // ->07ff
 296         R0.L = 0x0000;
 297         R0.H = 0x7ff0;
 298         R1.L = 0x0000;
 299         R1.H = 0x0000;
 300         R7.L = R0 + R1 (RND20);
 301         R0 = ASTAT;
 302         DBGA ( R7.L , 0x07ff );
 303         CHECKREG R0, (_VS);
 304
 305 //    7fff 0000
 306 // +  0000 0000
 307 // +  0008 0000
 308 // ->0800
 309         R0.L = 0x0000;
 310         R0.H = 0x7fff;
 311         R1.L = 0x0000;
 312         R1.H = 0x0000;
 313         R7.L = R0 + R1 (RND20);
 314         R0 = ASTAT;
 315         DBGA ( R7.L , 0x0800 );
 316         CHECKREG R0, (_VS);
 317
 318 //    ffff 0000
 319 // +  0000 0000
 320 // +  0008 0000
 321 // ->0000
 322         R0.L = 0x0000;
 323         R0.H = 0xffff;
 324         R1.L = 0x0000;
 325         R1.H = 0x0000;
 326         R7.L = R0 + R1 (RND20);
 327         R0 = ASTAT;
 328         DBGA ( R7.L , 0x0000 );
 329         DBGA ( R0.H , 0x0200 );
 330         DBGA ( R0.L , 0x0001 );
 331
 332 //    ff00 0000
 333 // +  0010 0000
 334 // +  0008 0000
 335 // ->fff1
 336         R0.L = 0x0000;
 337         R0.H = 0xff00;
 338         R1.L = 0x0000;
 339         R1.H = 0x0010;
 340         R7.L = R0 + R1 (RND20);
 341         R0 = ASTAT;
 342         DBGA ( R7.L , 0xfff1 );
 343         CHECKREG R0, (_VS|_AN);
 344
 345 //    ff00 0000
 346 // +  0018 0000
 347 // +  0008 0000
 348 // ->fff2
 349         R0.L = 0x0000;
 350         R0.H = 0xff00;
 351         R1.L = 0x0000;
 352         R1.H = 0x0018;
 353         R7.L = R0 + R1 (RND20);
 354         R0 = ASTAT;
 355         DBGA ( R7.L , 0xfff2 );
 356         CHECKREG R0, (_VS|_AN);
 357
 358 // Small negative plus small negative should give zero
 359 //    ffff ffff
 360 // +  ffff ffff
 361 // +  0008 0000
 362 // ->0000
 363         R0.L = 0xffff;
 364         R0.H = 0xffff;
 365         R1.L = 0xffff;
 366         R1.H = 0xffff;
 367         R7.L = R0 + R1 (RND20);
 368         R0 = ASTAT;
 369         DBGA ( R7.L , 0x0000 );
 370         CHECKREG R0, (_VS|_AZ);
 371
 372 // Small negative minus small positive should give zero
 373 //    ffff ffff
 374 // +  0000 0010
 375 // +  0008 0000
 376 // ->0000
 377         R0.L = 0xffff;
 378         R0.H = 0xffff;
 379         R1.L = 0x0010;
 380         R1.H = 0x0000;
 381         R7.L = R0 - R1 (RND20);
 382         R0 = ASTAT;
 383         DBGA ( R7.L , 0x0000 );
 384         CHECKREG R0, (_VS|_AZ);
 385
 386         pass