sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s

   1 //Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp
   2 // Spec Reference: dsp32alu a0a1s
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 A1 = A0 = 0;
  11
  12 imm32 r0, 0x15678911;
  13 imm32 r1, 0xa789ab1d;
  14 imm32 r2, 0xd4445515;
  15 imm32 r3, 0xf6667717;
  16 imm32 r4, 0xe567891b;
  17 imm32 r5, 0x6789ab1d;
  18 imm32 r6, 0xb4445515;
  19 imm32 r7, 0x86667777;
  20 // A0 & A1 types
  21 A0 = R0;
  22 A1 = R1;
  23  R6 = A0.w;
  24  R7 = A1.w;
  25 A0 = 0;
  26 A1 = 0;
  27  R0 = A0.w;
  28  R1 = A1.w;
  29 A0 = R2;
  30 A1 = R3;
  31 A0 = A0 (S);
  32 A1 = A1 (S);
  33  R4 = A0.w;
  34  R5 = A1.w;
  35 A0 = A1;
  36  R2 = A0.w;
  37 A0 = R3;
  38 A1 = A0;
  39  R3 = A1.w;
  40 CHECKREG r0, 0x00000000;
  41 CHECKREG r1, 0x00000000;
  42 CHECKREG r2, 0xF6667717;
  43 CHECKREG r3, 0xF6667717;
  44 CHECKREG r4, 0xD4445515;
  45 CHECKREG r5, 0xF6667717;
  46 CHECKREG r6, 0x15678911;
  47 CHECKREG r7, 0xA789AB1D;
  48
  49 A1 = A0 = 0;
  50  R0 = A0.w;
  51  R1 = A1.w;
  52 CHECKREG r0, 0x00000000;
  53 CHECKREG r1, 0x00000000;
  54
  55 imm32 r0, 0xa1567891;
  56 imm32 r1, 0xba789abd;
  57 imm32 r2, 0xcd412355;
  58 imm32 r3, 0xdf646777;
  59 imm32 r4, 0xe567891b;
  60 imm32 r5, 0x6789ab1d;
  61 imm32 r6, 0xb4445515;
  62 imm32 r7, 0xf666aeb7;
  63
  64 A0 = R4;
  65 A1 = R5;
  66  R0 = A0.w;
  67  R1 = A1.w;
  68 A0 = R6;
  69 A1 = R7;
  70  R2 = A0.w;
  71  R3 = A1.w;
  72 CHECKREG r0, 0xE567891B;
  73 CHECKREG r1, 0x6789AB1D;
  74 CHECKREG r2, 0xB4445515;
  75 CHECKREG r3, 0xF666AEB7;
  76 CHECKREG r4, 0xE567891B;
  77 CHECKREG r5, 0x6789AB1D;
  78 CHECKREG r6, 0xB4445515;
  79 CHECKREG r7, 0xF666AEB7;
  80
  81
  82 pass