sim/testsuite/sim/bfin/c_dsp32alu_awx.s

   1 //Original:/testcases/core/c_dsp32alu_awx/c_dsp32alu_awx.dsp
   2 // Spec Reference: dsp32alu awx
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0x15678911;
  12 imm32 r1, 0x2789ab1d;
  13 imm32 r2, 0x34445515;
  14 imm32 r3, 0x46667717;
  15 imm32 r4, 0x5567891b;
  16 imm32 r5, 0x6789ab1d;
  17 imm32 r6, 0x74445515;
  18 imm32 r7, 0x86667777;
  19 // A0 & A1 types
  20 A0 = 0;
  21 A1 = 0;
  22
  23 A0.L = R0.L;
  24 A0.H = R0.H;
  25 A0.x = R2.L;
  26 R3 = A0.w;
  27 R4 = A1.w;
  28 R5.L = A0.x;
  29 //rl6 = a1x;
  30 CHECKREG r3, 0x15678911;
  31 CHECKREG r4, 0x00000000;
  32 CHECKREG r5, 0x67890015;
  33 //CHECKREG r6, 0x74440000;
  34
  35 R5 = ( A0 += A1 );
  36 R6.L = ( A0 += A1 );
  37 R7.H = ( A0 += A1 );
  38 CHECKREG r5, 0x7FFFFFFF;
  39 CHECKREG r6, 0x74447FFF;
  40 CHECKREG r7, 0x7FFF7777;
  41
  42 A0 += A1;
  43 R0 = A0.w;
  44 CHECKREG r0, 0x15678911;
  45
  46 A0 -= A1;
  47 R1 = A0.w;
  48 CHECKREG r1, 0x15678911;
  49
  50 R2 = A1.L + A1.H, R3 = A0.L + A0.H; /* 0x */
  51 CHECKREG r2, 0x00000000;
  52 CHECKREG r3, 0xFFFF9E78;
  53
  54 A0 = A1;
  55 R4 = A0.w;
  56 R5 = A1.w;
  57 CHECKREG r4, 0x00000000;
  58 CHECKREG r5, 0x00000000;
  59
  60
  61 pass