sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s

   1 //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp
   2 // Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         R0 = 0;
   9         ASTAT = R0;
  10
  11         imm32 r0, 0x35678911;
  12         imm32 r1, 0x2489ab1d;
  13         imm32 r2, 0x34545515;
  14         imm32 r3, 0x46667717;
  15         imm32 r0, 0x5567891b;
  16         imm32 r1, 0x67889b1d;
  17         imm32 r2, 0x74445915;
  18         imm32 r3, 0x86667797;
  19         R0 = R0 +|- R0 , R7 = R0 -|+ R0 (CO , ASR);
  20         R1 = R0 +|- R1 , R6 = R0 -|+ R1 (CO , ASR);
  21         R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR);
  22         R3 = R0 +|- R3 , R4 = R0 -|+ R3 (CO , ASR);
  23         R4 = R0 +|- R4 , R3 = R0 -|+ R4 (CO , ASR);
  24         R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR);
  25         R6 = R0 +|- R6 , R1 = R0 -|+ R6 (CO , ASR);
  26         R7 = R0 +|- R7 , R0 = R0 -|+ R7 (CO , ASR);
  27         CHECKREG r0, 0x00006626;
  28         CHECKREG r1, 0xfb7743ec;
  29         CHECKREG r2, 0xf848146e;
  30         CHECKREG r3, 0x33c00cce;
  31         CHECKREG r4, 0x4899cc40;
  32         CHECKREG r5, 0x40f807b7;
  33         CHECKREG r6, 0x117a0488;
  34         CHECKREG r7, 0xef410000;
  35
  36         imm32 r0, 0xe5678911;
  37         imm32 r1, 0x2e89ab1d;
  38         imm32 r2, 0x34e45515;
  39         imm32 r3, 0x466e7717;
  40         imm32 r0, 0x5567ee1b;
  41         imm32 r1, 0x6789abed;
  42         imm32 r2, 0x7444551e;
  43         imm32 r3, 0x86e67777;
  44         R0 = R1 +|- R0 , R7 = R1 -|+ R0 (CO , ASR);
  45         R1 = R1 +|- R1 , R6 = R1 -|+ R1 (CO , ASR);
  46         R2 = R1 +|- R2 , R5 = R1 -|+ R2 (CO , ASR);
  47         R3 = R1 +|- R3 , R4 = R1 -|+ R3 (CO , ASR);
  48         R4 = R1 +|- R4 , R3 = R1 -|+ R4 (CO , ASR);
  49         R5 = R1 +|- R5 , R2 = R1 -|+ R5 (CO , ASR);
  50         R6 = R1 +|- R6 , R1 = R1 -|+ R6 (CO , ASR);
  51         R7 = R1 +|- R7 , R0 = R1 -|+ R7 (CO , ASR);
  52         CHECKREG r0, 0x336f197e;
  53         CHECKREG r1, 0x00005dce;
  54         CHECKREG r2, 0xfcd11e7d;
  55         CHECKREG r3, 0x382815e7;
  56         CHECKREG r4, 0x51a2c7d7;
  57         CHECKREG r5, 0x490c032f;
  58         CHECKREG r6, 0x09bb0000;
  59         CHECKREG r7, 0xe6822a5e;
  60
  61         imm32 r0, 0x15678911;
  62         imm32 r1, 0x2789ab1d;
  63         imm32 r2, 0x34445515;
  64         imm32 r3, 0x46667717;
  65         imm32 r0, 0x5567891b;
  66         imm32 r1, 0x6789ab1d;
  67         imm32 r2, 0x74445515;
  68         imm32 r3, 0x86667777;
  69         R0 = R2 +|- R0 , R7 = R2 -|+ R0 (CO , ASR);
  70         R1 = R2 +|- R1 , R6 = R2 -|+ R1 (CO , ASR);
  71         R2 = R2 +|- R2 , R5 = R2 -|+ R2 (CO , ASR);
  72         R3 = R2 +|- R3 , R4 = R2 -|+ R3 (CO , ASR);
  73         R4 = R2 +|- R4 , R3 = R2 -|+ R4 (CO , ASR);
  74         R5 = R2 +|- R5 , R2 = R2 -|+ R5 (CO , ASR);
  75         R6 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR);
  76         R7 = R2 +|- R7 , R0 = R2 -|+ R7 (CO , ASR);
  77         CHECKREG r0, 0x0f820874;
  78         CHECKREG r1, 0x0afafff3;
  79         CHECKREG r2, 0x00000f97;
  80         CHECKREG r3, 0x3b771c44;
  81         CHECKREG r4, 0x57ffc488;
  82         CHECKREG r5, 0x64ac0000;
  83         CHECKREG r6, 0x000c049d;
  84         CHECKREG r7, 0xf78c0014;
  85
  86         imm32 r0, 0x85678911;
  87         imm32 r1, 0x2889ab1d;
  88         imm32 r2, 0x34445515;
  89         imm32 r3, 0x46667717;
  90         imm32 r0, 0x5587891b;
  91         imm32 r1, 0x6788ab1d;
  92         imm32 r2, 0x74448515;
  93         imm32 r3, 0x86667877;
  94         R0 = R3 +|- R0 , R7 = R3 -|+ R0 (CO , ASR);
  95         R1 = R3 +|- R1 , R6 = R3 -|+ R1 (CO , ASR);
  96         R2 = R3 +|- R2 , R5 = R3 -|+ R2 (CO , ASR);
  97         R3 = R3 +|- R3 , R4 = R3 -|+ R3 (CO , ASR);
  98         R4 = R3 +|- R4 , R3 = R3 -|+ R4 (CO , ASR);
  99         R5 = R3 +|- R5 , R2 = R3 -|+ R5 (CO , ASR);
 100         R6 = R3 +|- R6 , R1 = R3 -|+ R6 (CO , ASR);
 101         R7 = R3 +|- R7 , R0 = R3 -|+ R7 (CO , ASR);
 102         CHECKREG r0, 0x8fb3ff9b;
 103         CHECKREG r1, 0x8b33f71b;
 104         CHECKREG r2, 0x8804009d;
 105         CHECKREG r3, 0x000086f7;
 106         CHECKREG r4, 0xff6e0000;
 107         CHECKREG r5, 0xff63fef3;
 108         CHECKREG r6, 0x08e5fbc4;
 109         CHECKREG r7, 0x0064f744;
 110
 111         imm32 r0, 0x15678911;
 112         imm32 r1, 0x2789ab1d;
 113         imm32 r2, 0x34445515;
 114         imm32 r3, 0x46667717;
 115         imm32 r0, 0x5567891b;
 116         imm32 r1, 0x6789ab1d;
 117         imm32 r2, 0x74445515;
 118         imm32 r3, 0x86667777;
 119         R0 = R4 +|- R0 , R7 = R4 -|+ R0 (CO , ASR);
 120         R1 = R4 +|- R1 , R6 = R4 -|+ R1 (CO , ASR);
 121         R2 = R4 +|- R2 , R5 = R4 -|+ R2 (CO , ASR);
 122         R3 = R4 +|- R3 , R4 = R4 -|+ R3 (CO , ASR);
 123         R4 = R4 +|- R4 , R3 = R4 -|+ R4 (CO , ASR);
 124         R5 = R4 +|- R5 , R2 = R4 -|+ R5 (CO , ASR);
 125         R6 = R4 +|- R6 , R1 = R4 -|+ R6 (CO , ASR);
 126         R7 = R4 +|- R7 , R0 = R4 -|+ R7 (CO , ASR);
 127         CHECKREG r0, 0xEA813B97;
 128         CHECKREG r1, 0xE5F93316;
 129         CHECKREG r2, 0xe2ca0898;
 130         CHECKREG r3, 0x3C840000;
 131         CHECKREG r4, 0x3BBB0000;
 132         CHECKREG r5, 0x33221D35;
 133         CHECKREG r6, 0x08A41A07;
 134         CHECKREG r7, 0x0024157E;
 135
 136         imm32 r0, 0x95678911;
 137         imm32 r1, 0x2789ab1d;
 138         imm32 r2, 0x39445515;
 139         imm32 r3, 0x46967717;
 140         imm32 r0, 0x5567891b;
 141         imm32 r1, 0x6789ab1d;
 142         imm32 r2, 0x74495515;
 143         imm32 r3, 0x86669777;
 144         R0 = R5 +|- R0 , R7 = R5 -|+ R0 (CO , ASR);
 145         R1 = R5 +|- R1 , R6 = R5 -|+ R1 (CO , ASL);
 146         R2 = R5 +|- R2 , R5 = R5 -|+ R2 (CO , ASR);
 147         R3 = R5 +|- R3 , R4 = R5 -|+ R3 (CO , ASL);
 148         R4 = R5 +|- R4 , R3 = R5 -|+ R4 (CO , ASR);
 149         R5 = R5 +|- R5 , R2 = R5 -|+ R5 (CO , ASR);
 150         R6 = R5 +|- R6 , R1 = R5 -|+ R6 (CO , ASR);
 151         R7 = R5 +|- R7 , R0 = R5 -|+ R7 (CO , ASL);
 152         CHECKREG r0, 0xDDBACBFA;
 153         CHECKREG r1, 0xCB995440;
 154         CHECKREG r2, 0xDF6C0000;
 155         CHECKREG r3, 0x227525AF;
 156         CHECKREG r4, 0x1375bCF7;
 157         CHECKREG r5, 0x39250000;
 158         CHECKREG r6, 0xE4E43467;
 159         CHECKREG r7, 0x189A2246;
 160
 161         imm32 r0, 0x15678911;
 162         imm32 r1, 0x2789ab1d;
 163         imm32 r2, 0x34445515;
 164         imm32 r3, 0x46667717;
 165         imm32 r0, 0x5567891b;
 166         imm32 r1, 0x6789ab1d;
 167         imm32 r2, 0x74445515;
 168         imm32 r3, 0x86667777;
 169         R0 = R6 +|- R0 , R7 = R6 -|+ R0 (CO , ASR);
 170         R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL);
 171         R2 = R6 +|- R2 , R5 = R6 -|+ R2 (CO , ASL);
 172         R3 = R6 +|- R3 , R4 = R6 -|+ R3 (CO , ASR);
 173         R4 = R6 +|- R4 , R3 = R6 -|+ R4 (CO , ASR);
 174         R5 = R6 +|- R5 , R2 = R6 -|+ R5 (CO , ASR);
 175         R6 = R6 +|- R6 , R1 = R6 -|+ R6 (CO , ASL);
 176         R7 = R6 +|- R7 , R0 = R6 -|+ R7 (CO , ASR);
 177         CHECKREG r0, 0xE3DF0EAF;
 178         CHECKREG r1, 0xEAD80000;
 179         CHECKREG r2, 0xC81F0FB9;
 180         CHECKREG r3, 0x0B83C2F9;
 181         CHECKREG r4, 0xFC0FEF32;
 182         CHECKREG r5, 0xaF4F3297;
 183         CHECKREG r6, 0xFC200000;
 184         CHECKREG r7, 0xED701C21;
 185
 186         imm32 r0, 0x67898911;
 187         imm32 r1, 0xb789ab1d;
 188         imm32 r2, 0x3b445515;
 189         imm32 r3, 0x46b67717;
 190         imm32 r0, 0x5567891b;
 191         imm32 r1, 0x678bab1d;
 192         imm32 r2, 0x7444b515;
 193         imm32 r3, 0x86667b77;
 194         R0 = R7 +|- R0 , R7 = R7 -|+ R0 (CO , ASR);
 195         R1 = R7 +|- R1 , R6 = R7 -|+ R1 (CO , ASR);
 196         R2 = R7 +|- R2 , R5 = R7 -|+ R2 (CO , ASL);
 197         R3 = R7 +|- R3 , R4 = R7 -|+ R3 (CO , ASR);
 198         R4 = R7 +|- R4 , R3 = R7 -|+ R4 (CO , ASL);
 199         R5 = R7 +|- R5 , R2 = R7 -|+ R5 (CO , ASL);
 200         R6 = R7 +|- R6 , R1 = R7 -|+ R6 (CO , ASL);
 201         R7 = R7 +|- R7 , R0 = R7 -|+ R7 (CO , ASR);
 202         CHECKREG r0, 0xCC040000;
 203         CHECKREG r1, 0x031A2E1C;
 204         CHECKREG r2, 0x1170A0D8;
 205         CHECKREG r3, 0xE4405DC2;
 206         CHECKREG r4, 0xECB64BD0;
 207         CHECKREG r5, 0xA9A01EA0;
 208         CHECKREG r6, 0x1C5C2CF6;
 209         CHECKREG r7, 0xD29E0000;
 210
 211         imm32 r0, 0xe5678911;
 212         imm32 r1, 0x2e89ab1d;
 213         imm32 r2, 0x34ee5515;
 214         imm32 r3, 0x4666e717;
 215         imm32 r0, 0x5567891b;
 216         imm32 r1, 0x6789ae1d;
 217         imm32 r2, 0x744455e5;
 218         imm32 r3, 0x8666777e;
 219         R4 = R2 +|- R5 , R3 = R2 -|+ R5 (CO , ASR);
 220         R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO , ASL);
 221         R2 = R6 +|- R2 , R0 = R6 -|+ R2 (CO , ASR);
 222         R3 = R4 +|- R0 , R2 = R4 -|+ R0 (CO , ASR);
 223         R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO , ASR);
 224         R6 = R1 +|- R7 , R1 = R1 -|+ R7 (CO , ASL);
 225         R5 = R0 +|- R4 , R7 = R0 -|+ R4 (CO , ASR);
 226         R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO , ASL);
 227         CHECKREG r0, 0x416dd40c;
 228         CHECKREG r1, 0xaEE68766;
 229         CHECKREG r2, 0xF7D7e6C2;
 230         CHECKREG r3, 0x282F23CB;
 231         CHECKREG r4, 0x07C6f1D6;
 232         CHECKREG r5, 0x282FDC35;
 233         CHECKREG r6, 0xBE0C8930;
 234         CHECKREG r7, 0xF7D7193D;
 235
 236         imm32 r0, 0xff678911;
 237         imm32 r1, 0x2789ab1d;
 238         imm32 r2, 0x3f445515;
 239         imm32 r3, 0x46f67717;
 240         imm32 r0, 0x556f891b;
 241         imm32 r1, 0x6789fb1d;
 242         imm32 r2, 0x74445f15;
 243         imm32 r3, 0x866677f7;
 244         R4 = R3 +|- R3 , R5 = R3 -|+ R3 (CO , ASR);
 245         R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL);
 246         R6 = R1 +|- R4 , R4 = R1 -|+ R4 (CO , ASR);
 247         R7 = R4 +|- R2 , R0 = R4 -|+ R2 (CO , ASL);
 248         R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR);
 249         R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO , ASL);
 250         R5 = R7 +|- R7 , R3 = R7 -|+ R7 (CO , ASR);
 251         R0 = R0 +|- R0 , R2 = R0 -|+ R0 (CO , ASR);
 252         CHECKREG r0, 0x82EE0000;
 253         CHECKREG r1, 0x369445BE;
 254         CHECKREG r2, 0x339E0000;
 255         CHECKREG r3, 0x00000000;
 256         CHECKREG r4, 0x0E136262;
 257         CHECKREG r5, 0x00000000;
 258         CHECKREG r6, 0xe8C80E13;
 259         CHECKREG r7, 0x00000000;
 260
 261         pass