sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp
   2 // Spec Reference: dsp32mac dr_a0 m
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0xab235675;
  12 imm32 r1, 0xcfba5127;
  13 imm32 r2, 0x13246705;
  14 imm32 r3, 0x00060007;
  15 imm32 r4, 0x90abcd09;
  16 imm32 r5, 0x10acefdb;
  17 imm32 r6, 0x000c000d;
  18 imm32 r7, 0x1246700f;
  19
  20 A1 = A0 = 0;
  21
  22 // The result accumulated in A1 , and stored to a reg half
  23 imm32 r0, 0x13545abd;
  24 imm32 r1, 0xadbcfec7;
  25 imm32 r2, 0xa1245679;
  26 imm32 r3, 0x00060007;
  27 imm32 r4, 0xefbc4569;
  28 imm32 r5, 0x1235000b;
  29 imm32 r6, 0x000c000d;
  30 imm32 r7, 0x678e000f;
  31 A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
  32 R1 = A0.w;
  33 A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L );
  34 R3 = A0.w;
  35 A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H );
  36 R5 = A0.w;
  37 A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H );
  38 R7 = A0.w;
  39 CHECKREG r0, 0x1354FF22;
  40 CHECKREG r1, 0xFF221DD6;
  41 CHECKREG r2, 0xA124FF27;
  42 CHECKREG r3, 0xFF274DDE;
  43 CHECKREG r4, 0xEFBCFCD7;
  44 CHECKREG r5, 0xFCD701B6;
  45 CHECKREG r6, 0x000C000B;
  46 CHECKREG r7, 0x000A846C;
  47
  48 // The result accumulated in A1, and stored to a reg half (MNOP)
  49 imm32 r0, 0x13545abd;
  50 imm32 r1, 0xadbcfec7;
  51 imm32 r2, 0xa1245679;
  52 imm32 r3, 0x00060007;
  53 imm32 r4, 0xefbc4569;
  54 imm32 r5, 0x1235000b;
  55 imm32 r6, 0x000c000d;
  56 imm32 r7, 0x678e000f;
  57 R0.L = ( A0 += R6.L * R7.L );
  58 R1 = A0.w;
  59 R2.L = ( A0 -= R2.L * R3.H );
  60 R3 = A0.w;
  61 R4.L = ( A0 += R4.H * R5.L );
  62 R5 = A0.w;
  63 R6.L = ( A0 = R0.H * R1.H );
  64 R7 = A0.w;
  65 CHECKREG r0, 0x1354000B;
  66 CHECKREG r1, 0x000A85F2;
  67 CHECKREG r2, 0xA1240006;
  68 CHECKREG r3, 0x00067846;
  69 CHECKREG r4, 0xEFBC0005;
  70 CHECKREG r5, 0x0005126E;
  71 CHECKREG r6, 0x000C0002;
  72 CHECKREG r7, 0x00018290;
  73
  74 // The result accumulated in A1 , and stored to a reg half (MNOP)
  75 imm32 r0, 0x13545abd;
  76 imm32 r1, 0xadbcfec7;
  77 imm32 r2, 0xa1245679;
  78 imm32 r3, 0x00060007;
  79 imm32 r4, 0xefbc4569;
  80 imm32 r5, 0x1235000b;
  81 imm32 r6, 0x000c000d;
  82 imm32 r7, 0x678e000f;
  83 R0.L = ( A0 = R1.L * R0.L );
  84 R1 = A0.w;
  85 R2.L = ( A0 += R2.H * R3.L );
  86 R3 = A0.w;
  87 R4.L = ( A0 += R4.H * R5.H );
  88 R5 = A0.w;
  89 R6.L = ( A0 += R6.L * R7.H );
  90 R7 = A0.w;
  91 CHECKREG r0, 0x1354FF22;
  92 CHECKREG r1, 0xFF221DD6;
  93 CHECKREG r2, 0xA124FF1D;
  94 CHECKREG r3, 0xFF1CEDCE;
  95 CHECKREG r4, 0xEFBCFCCD;
  96 CHECKREG r5, 0xFCCCA1A6;
  97 CHECKREG r6, 0x000CFCD7;
  98 CHECKREG r7, 0xFCD72612;
  99
 100 // The result accumulated in A1 , and stored to a reg half
 101 imm32 r0, 0x13545abd;
 102 imm32 r1, 0xadbcfec7;
 103 imm32 r2, 0xa1245679;
 104 imm32 r3, 0x00060007;
 105 imm32 r4, 0xefbc4569;
 106 imm32 r5, 0x1235000b;
 107 imm32 r6, 0x000c000d;
 108 imm32 r7, 0x678e000f;
 109 A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L );
 110 R7 = A0.w;
 111 A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L );
 112 R3 = A0.w;
 113 A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H );
 114 R5 = A0.w;
 115 A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H );
 116 R1 = A0.w;
 117 CHECKREG r0, 0x1354000B;
 118 CHECKREG r1, 0x000A83F2;
 119 CHECKREG r2, 0xA124FDB0;
 120 CHECKREG r3, 0xFDAFD834;
 121 CHECKREG r4, 0xEFBCFDB0;
 122 CHECKREG r5, 0xFDAFB3D8;
 123 CHECKREG r6, 0x000CFDB5;
 124 CHECKREG r7, 0xFDB5083C;
 125
 126
 127 pass