sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s

   1 //Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp
   2 // Spec Reference: dsp32shift ashift/ashift s
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 // ashift/ashift s : positive data, count (+)=left (half reg)
  11 // d_reg = ashift/ashift (d BY d_lo) saturation
  12 // Rx by RLx
  13 imm32 r0, 0x01230000;
  14 imm32 r1, 0x12345678;
  15 imm32 r2, 0x23456789;
  16 imm32 r3, 0x3456789a;
  17 imm32 r4, 0x456789ab;
  18 imm32 r5, 0x56789abc;
  19 imm32 r6, 0x6789abcd;
  20 imm32 r7, 0x789abcde;
  21 R5 = ASHIFT R0 BY R0.L (V , S);
  22 R0 = ASHIFT R1 BY R0.L (V , S);
  23 R1 = ASHIFT R2 BY R0.L (V , S);
  24 R2 = ASHIFT R3 BY R0.L (V , S);
  25 R3 = ASHIFT R4 BY R0.L (V , S);
  26 R4 = ASHIFT R5 BY R0.L (V , S);
  27 R7 = ASHIFT R6 BY R0.L (V , S);
  28 R6 = ASHIFT R7 BY R0.L (V , S);
  29 CHECKREG r0, 0x12345678;
  30 CHECKREG r1, 0x00230067;
  31 CHECKREG r2, 0x00340078;
  32 CHECKREG r3, 0x0045FF89;
  33 CHECKREG r4, 0x00010000;
  34 CHECKREG r5, 0x01230000;
  35 CHECKREG r6, 0x0000FFFF;
  36 CHECKREG r7, 0x0067FFAB;
  37
  38 imm32 r0, 0x01230002;
  39 imm32 r1, 0x12345678;
  40 imm32 r2, 0x23456789;
  41 imm32 r3, 0x3456789a;
  42 imm32 r4, 0x456789ab;
  43 imm32 r5, 0x56789abc;
  44 imm32 r6, 0x6789abcd;
  45 imm32 r7, 0x789abcde;
  46 R1.L = 5;
  47 R2 = ASHIFT R0 BY R1.L (V , S);
  48 R3 = ASHIFT R1 BY R1.L (V , S);
  49 R4 = ASHIFT R2 BY R1.L (V , S);
  50 R5 = ASHIFT R3 BY R1.L (V , S);
  51 R6 = ASHIFT R4 BY R1.L (V , S);
  52 R7 = ASHIFT R5 BY R1.L (V , S);
  53 R0 = ASHIFT R6 BY R1.L (V , S);
  54 R1 = ASHIFT R7 BY R1.L (V , S);
  55 CHECKREG r0, 0x7FFF7FFF;
  56 CHECKREG r1, 0x7FFF7FFF;
  57 CHECKREG r2, 0x24600040;
  58 CHECKREG r3, 0x7FFF00A0;
  59 CHECKREG r4, 0x7FFF0800;
  60 CHECKREG r5, 0x7FFF1400;
  61 CHECKREG r6, 0x7FFF7FFF;
  62 CHECKREG r7, 0x7FFF7FFF;
  63
  64 imm32 r0, 0x01230002;
  65 imm32 r1, 0x12345678;
  66 imm32 r2, 0x23456789;
  67 imm32 r3, 0x3456789a;
  68 imm32 r4, 0x456789ab;
  69 imm32 r5, 0x56789abc;
  70 imm32 r6, 0x6789abcd;
  71 imm32 r7, 0x789abcde;
  72 R2 = 15;
  73 R3 = ASHIFT R0 BY R2.L (V , S);
  74 R4 = ASHIFT R1 BY R2.L (V , S);
  75 R5 = ASHIFT R2 BY R2.L (V , S);
  76 R6 = ASHIFT R3 BY R2.L (V , S);
  77 R7 = ASHIFT R4 BY R2.L (V , S);
  78 R0 = ASHIFT R5 BY R2.L (V , S);
  79 R1 = ASHIFT R6 BY R2.L (V , S);
  80 R2 = ASHIFT R7 BY R2.L (V , S);
  81 CHECKREG r0, 0x00007FFF;
  82 CHECKREG r1, 0x7FFF7FFF;
  83 CHECKREG r2, 0x7FFF7FFF;
  84 CHECKREG r3, 0x7FFF7FFF;
  85 CHECKREG r4, 0x7FFF7FFF;
  86 CHECKREG r5, 0x00007FFF;
  87 CHECKREG r6, 0x7FFF7FFF;
  88 CHECKREG r7, 0x7FFF7FFF;
  89
  90 imm32 r0, 0x01230002;
  91 imm32 r1, 0x12345678;
  92 imm32 r2, 0x23456789;
  93 imm32 r3, 0x3456789a;
  94 imm32 r4, 0x456789ab;
  95 imm32 r5, 0x56789abc;
  96 imm32 r6, 0x6789abcd;
  97 imm32 r7, 0x789abcde;
  98 R3.L = 16;
  99 R4 = ASHIFT R0 BY R3.L (V , S);
 100 R5 = ASHIFT R1 BY R3.L (V , S);
 101 R6 = ASHIFT R2 BY R3.L (V , S);
 102 R7 = ASHIFT R3 BY R3.L (V , S);
 103 R0 = ASHIFT R4 BY R3.L (V , S);
 104 R1 = ASHIFT R5 BY R3.L (V , S);
 105 R2 = ASHIFT R6 BY R3.L (V , S);
 106 R3 = ASHIFT R7 BY R3.L (V , S);
 107 CHECKREG r0, 0x7FFF7FFF;
 108 CHECKREG r1, 0x7FFF7FFF;
 109 CHECKREG r2, 0x7FFF7FFF;
 110 CHECKREG r3, 0x7FFF7FFF;
 111 CHECKREG r4, 0x7FFF7FFF;
 112 CHECKREG r5, 0x7FFF7FFF;
 113 CHECKREG r6, 0x7FFF7FFF;
 114 CHECKREG r7, 0x7FFF7FFF;
 115
 116 imm32 r0, 0x01230002;
 117 imm32 r1, 0x12345678;
 118 imm32 r2, 0x23456789;
 119 imm32 r3, 0x3456789a;
 120 imm32 r4, 0x456789ab;
 121 imm32 r5, 0x56789abc;
 122 imm32 r6, 0x6789abcd;
 123 imm32 r7, 0x789abcde;
 124 R4.L = -1;
 125 R0 = ASHIFT R0 BY R4.L (V , S);
 126 R1 = ASHIFT R1 BY R4.L (V , S);
 127 R2 = ASHIFT R2 BY R4.L (V , S);
 128 R3 = ASHIFT R3 BY R4.L (V , S);
 129 R4 = ASHIFT R4 BY R4.L (V , S);
 130 R5 = ASHIFT R5 BY R4.L (V , S);
 131 R6 = ASHIFT R6 BY R4.L (V , S);
 132 R7 = ASHIFT R7 BY R4.L (V , S);
 133 CHECKREG r0, 0x00910001;
 134 CHECKREG r1, 0x091A2B3C;
 135 CHECKREG r2, 0x11A233C4;
 136 CHECKREG r3, 0x1A2B3C4D;
 137 CHECKREG r4, 0x22B3FFFF;
 138 CHECKREG r5, 0x2B3CCD5E;
 139 CHECKREG r6, 0x33C4D5E6;
 140 CHECKREG r7, 0x3C4DDE6F;
 141
 142 imm32 r0, 0x01230002;
 143 imm32 r1, 0x12345678;
 144 imm32 r2, 0x23456789;
 145 imm32 r3, 0x3456789a;
 146 imm32 r4, 0x456789ab;
 147 imm32 r5, 0x56789abc;
 148 imm32 r6, 0x6789abcd;
 149 imm32 r7, 0x789abcde;
 150 R5.L = -6;
 151 R6 = ASHIFT R0 BY R5.L (V , S);
 152 R7 = ASHIFT R1 BY R5.L (V , S);
 153 R0 = ASHIFT R2 BY R5.L (V , S);
 154 R1 = ASHIFT R3 BY R5.L (V , S);
 155 R2 = ASHIFT R4 BY R5.L (V , S);
 156 R3 = ASHIFT R5 BY R5.L (V , S);
 157 R4 = ASHIFT R6 BY R5.L (V , S);
 158 R5 = ASHIFT R7 BY R5.L (V , S);
 159 CHECKREG r0, 0x008D019E;
 160 CHECKREG r1, 0x00D101E2;
 161 CHECKREG r2, 0x0115FE26;
 162 CHECKREG r3, 0x0159FFFF;
 163 CHECKREG r4, 0x00000000;
 164 CHECKREG r5, 0x00010005;
 165 CHECKREG r6, 0x00040000;
 166 CHECKREG r7, 0x00480159;
 167
 168 imm32 r0, 0x01230002;
 169 imm32 r1, 0x12345678;
 170 imm32 r2, 0x23456789;
 171 imm32 r3, 0x3456789a;
 172 imm32 r4, 0x456789ab;
 173 imm32 r5, 0x56789abc;
 174 imm32 r6, 0x6789abcd;
 175 imm32 r7, 0x789abcde;
 176 R6.L = -15;
 177 R7 = ASHIFT R0 BY R6.L (V , S);
 178 R0 = ASHIFT R1 BY R6.L (V , S);
 179 R1 = ASHIFT R2 BY R6.L (V , S);
 180 R2 = ASHIFT R3 BY R6.L (V , S);
 181 R3 = ASHIFT R4 BY R6.L (V , S);
 182 R4 = ASHIFT R5 BY R6.L (V , S);
 183 R5 = ASHIFT R6 BY R6.L (V , S);
 184 R6 = ASHIFT R7 BY R6.L (V , S);
 185 CHECKREG r0, 0x00000000;
 186 CHECKREG r1, 0x00000000;
 187 CHECKREG r2, 0x00000000;
 188 CHECKREG r3, 0x0000FFFF;
 189 CHECKREG r4, 0x0000FFFF;
 190 CHECKREG r5, 0x0000FFFF;
 191 CHECKREG r6, 0x00000000;
 192 CHECKREG r7, 0x00000000;
 193
 194 imm32 r0, 0x01230002;
 195 imm32 r1, 0x12345678;
 196 imm32 r2, 0x23456789;
 197 imm32 r3, 0x3456789a;
 198 imm32 r4, 0x456789ab;
 199 imm32 r5, 0x56789abc;
 200 imm32 r6, 0x6789abcd;
 201 imm32 r7, 0x789abcde;
 202 R7.L = -16;
 203 R0 = ASHIFT R0 BY R7.L (V , S);
 204 R1 = ASHIFT R1 BY R7.L (V , S);
 205 R2 = ASHIFT R2 BY R7.L (V , S);
 206 R3 = ASHIFT R3 BY R7.L (V , S);
 207 R4 = ASHIFT R4 BY R7.L (V , S);
 208 R5 = ASHIFT R5 BY R7.L (V , S);
 209 R6 = ASHIFT R6 BY R7.L (V , S);
 210 R7 = ASHIFT R7 BY R7.L (V , S);
 211 CHECKREG r0, 0x00000000;
 212 CHECKREG r1, 0x00000000;
 213 CHECKREG r2, 0x00000000;
 214 CHECKREG r3, 0x00000000;
 215 CHECKREG r4, 0x0000FFFF;
 216 CHECKREG r5, 0x0000FFFF;
 217 CHECKREG r6, 0x0000FFFF;
 218 CHECKREG r7, 0x0000FFFF;
 219
 220 imm32 r0, 0x01230002;
 221 imm32 r1, 0x12345678;
 222 imm32 r2, 0x23456789;
 223 imm32 r3, 0x3456789a;
 224 imm32 r4, 0x456789ab;
 225 imm32 r5, 0x56789abc;
 226 imm32 r6, 0x6789abcd;
 227 imm32 r7, 0x789abcde;
 228 R0.L = 4;
 229 //r0 = ashift/ashift (r0 by rl0);
 230 R1 = ASHIFT R1 BY R0.L (V , S);
 231 R2 = ASHIFT R2 BY R0.L (V , S);
 232 R3 = ASHIFT R3 BY R0.L (V , S);
 233 R4 = ASHIFT R4 BY R0.L (V , S);
 234 R5 = ASHIFT R5 BY R0.L (V , S);
 235 R6 = ASHIFT R6 BY R0.L (V , S);
 236 R7 = ASHIFT R7 BY R0.L (V , S);
 237 CHECKREG r0, 0x01230004;
 238 CHECKREG r1, 0x7FFF7FFF;
 239 CHECKREG r2, 0x7FFF7FFF;
 240 CHECKREG r3, 0x7FFF7FFF;
 241 CHECKREG r4, 0x7FFF8000;
 242 CHECKREG r5, 0x7FFF8000;
 243 CHECKREG r6, 0x7FFF8000;
 244 CHECKREG r7, 0x7FFF8000;
 245
 246 imm32 r0, 0x01230002;
 247 imm32 r1, 0x12345678;
 248 imm32 r2, 0x23456789;
 249 imm32 r3, 0x3456789a;
 250 imm32 r4, 0x456789ab;
 251 imm32 r5, 0x56789abc;
 252 imm32 r6, 0x6789abcd;
 253 imm32 r7, 0x789abcde;
 254 R1.L = 6;
 255 R0 = ASHIFT R0 BY R1.L (V , S);
 256 //r1 = ashift/ashift (r1 by rl1);
 257 R2 = ASHIFT R2 BY R1.L (V , S);
 258 R3 = ASHIFT R3 BY R1.L (V , S);
 259 R4 = ASHIFT R4 BY R1.L (V , S);
 260 R5 = ASHIFT R5 BY R1.L (V , S);
 261 R6 = ASHIFT R6 BY R1.L (V , S);
 262 R7 = ASHIFT R7 BY R1.L (V , S);
 263 CHECKREG r0, 0x48C00080;
 264 CHECKREG r1, 0x12340006;
 265 CHECKREG r2, 0x7FFF7FFF;
 266 CHECKREG r3, 0x7FFF7FFF;
 267 CHECKREG r4, 0x7FFF8000;
 268 CHECKREG r5, 0x7FFF8000;
 269 CHECKREG r6, 0x7FFF8000;
 270 CHECKREG r7, 0x7FFF8000;
 271
 272
 273 imm32 r0, 0x01230002;
 274 imm32 r1, 0x12345678;
 275 imm32 r2, 0x23456789;
 276 imm32 r3, 0x3456789a;
 277 imm32 r4, 0x456789ab;
 278 imm32 r5, 0x56789abc;
 279 imm32 r6, 0x6789abcd;
 280 imm32 r7, 0x789abcde;
 281 R2.L = 15;
 282 R0 = ASHIFT R0 BY R2.L (V , S);
 283 R1 = ASHIFT R1 BY R2.L (V , S);
 284 //r2 = ashift/ashift (r2 by rl2) s;
 285 R3 = ASHIFT R3 BY R2.L (V , S);
 286 R4 = ASHIFT R4 BY R2.L (V , S);
 287 R5 = ASHIFT R5 BY R2.L (V , S);
 288 R6 = ASHIFT R6 BY R2.L (V , S);
 289 R7 = ASHIFT R7 BY R2.L (V , S);
 290 CHECKREG r0, 0x7FFF7FFF;
 291 CHECKREG r1, 0x7FFF7FFF;
 292 CHECKREG r2, 0x2345000F;
 293 CHECKREG r3, 0x7FFF7FFF;
 294 CHECKREG r4, 0x7FFF8000;
 295 CHECKREG r5, 0x7FFF8000;
 296 CHECKREG r6, 0x7FFF8000;
 297 CHECKREG r7, 0x7FFF8000;
 298
 299 imm32 r0, 0x01230002;
 300 imm32 r1, 0x12345678;
 301 imm32 r2, 0x23456789;
 302 imm32 r3, 0x3456789a;
 303 imm32 r4, 0x456789ab;
 304 imm32 r5, 0x56789abc;
 305 imm32 r6, 0x6789abcd;
 306 imm32 r7, 0x789abcde;
 307 R3.L = 16;
 308 R0 = ASHIFT R0 BY R3.L (V , S);
 309 R1 = ASHIFT R1 BY R3.L (V , S);
 310 R2 = ASHIFT R2 BY R3.L (V , S);
 311 //r3 = ashift/ashift (r3 by rl3) s;
 312 R4 = ASHIFT R4 BY R3.L (V , S);
 313 R5 = ASHIFT R5 BY R3.L (V , S);
 314 R6 = ASHIFT R6 BY R3.L (V , S);
 315 R7 = ASHIFT R7 BY R3.L (V , S);
 316 CHECKREG r0, 0x7FFF7FFF;
 317 CHECKREG r1, 0x7FFF7FFF;
 318 CHECKREG r2, 0x7FFF7FFF;
 319 CHECKREG r3, 0x34560010;
 320 CHECKREG r4, 0x7FFF8000;
 321 CHECKREG r5, 0x7FFF8000;
 322 CHECKREG r6, 0x7FFF8000;
 323 CHECKREG r7, 0x7FFF8000;
 324
 325 imm32 r0, 0x01230002;
 326 imm32 r1, 0x12345678;
 327 imm32 r2, 0x23456789;
 328 imm32 r3, 0x3456789a;
 329 imm32 r4, 0x456789ab;
 330 imm32 r5, 0x56789abc;
 331 imm32 r6, 0x6789abcd;
 332 imm32 r7, 0x789abcde;
 333 R4.L = -9;
 334 R0 = ASHIFT R0 BY R4.L (V , S);
 335 R1 = ASHIFT R1 BY R4.L (V , S);
 336 R2 = ASHIFT R2 BY R4.L (V , S);
 337 R3 = ASHIFT R3 BY R4.L (V , S);
 338 //r4 = ashift/ashift (r4 by rl4) s;
 339 R5 = ASHIFT R5 BY R4.L (V , S);
 340 R6 = ASHIFT R6 BY R4.L (V , S);
 341 R7 = ASHIFT R7 BY R4.L (V , S);
 342 CHECKREG r0, 0x00000000;
 343 CHECKREG r1, 0x0009002B;
 344 CHECKREG r2, 0x00110033;
 345 CHECKREG r3, 0x001A003C;
 346 CHECKREG r4, 0x4567FFF7;
 347 CHECKREG r5, 0x002BFFCD;
 348 CHECKREG r6, 0x0033FFD5;
 349 CHECKREG r7, 0x003CFFDE;
 350
 351 imm32 r0, 0x01230002;
 352 imm32 r1, 0x12345678;
 353 imm32 r2, 0x23456789;
 354 imm32 r3, 0x3456789a;
 355 imm32 r4, 0x456789ab;
 356 imm32 r5, 0x56789abc;
 357 imm32 r6, 0x6789abcd;
 358 imm32 r7, 0x789abcde;
 359 R5.L = -14;
 360 R0 = ASHIFT R0 BY R5.L (V , S);
 361 R1 = ASHIFT R1 BY R5.L (V , S);
 362 R2 = ASHIFT R2 BY R5.L (V , S);
 363 R3 = ASHIFT R3 BY R5.L (V , S);
 364 R4 = ASHIFT R4 BY R5.L (V , S);
 365 //r5 = ashift/ashift (r5 by rl5) s;
 366 R6 = ASHIFT R6 BY R5.L (V , S);
 367 R7 = ASHIFT R7 BY R5.L (V , S);
 368 CHECKREG r0, 0x00000000;
 369 CHECKREG r1, 0x00000001;
 370 CHECKREG r2, 0x00000001;
 371 CHECKREG r3, 0x00000001;
 372 CHECKREG r4, 0x0001FFFE;
 373 CHECKREG r5, 0x5678FFF2;
 374 CHECKREG r6, 0x0001FFFE;
 375 CHECKREG r7, 0x0001FFFE;
 376
 377
 378 imm32 r0, 0x01230002;
 379 imm32 r1, 0x12345678;
 380 imm32 r2, 0x23456789;
 381 imm32 r3, 0x3456789a;
 382 imm32 r4, 0x456789ab;
 383 imm32 r5, 0x56789abc;
 384 imm32 r6, 0x6789abcd;
 385 imm32 r7, 0x789abcde;
 386 R6.L = -15;
 387 R0 = ASHIFT R0 BY R6.L (V , S);
 388 R1 = ASHIFT R1 BY R6.L (V , S);
 389 R2 = ASHIFT R2 BY R6.L (V , S);
 390 R3 = ASHIFT R3 BY R6.L (V , S);
 391 R4 = ASHIFT R4 BY R6.L (V , S);
 392 R5 = ASHIFT R5 BY R6.L (V , S);
 393 //r6 = ashift/ashift (r6 by rl6) s;
 394 R7 = ASHIFT R7 BY R6.L (V , S);
 395 CHECKREG r0, 0x00000000;
 396 CHECKREG r1, 0x00000000;
 397 CHECKREG r2, 0x00000000;
 398 CHECKREG r3, 0x00000000;
 399 CHECKREG r4, 0x0000FFFF;
 400 CHECKREG r5, 0x0000FFFF;
 401 CHECKREG r6, 0x6789FFF1;
 402 CHECKREG r7, 0x0000FFFF;
 403
 404 imm32 r0, 0x01230002;
 405 imm32 r1, 0x12345678;
 406 imm32 r2, 0x23456789;
 407 imm32 r3, 0x3456789a;
 408 imm32 r4, 0x456789ab;
 409 imm32 r5, 0x56789abc;
 410 imm32 r6, 0x6789abcd;
 411 imm32 r7, 0x789abcde;
 412 R7.L = -16;
 413 R0 = ASHIFT R0 BY R7.L (V , S);
 414 R1 = ASHIFT R1 BY R7.L (V , S);
 415 R2 = ASHIFT R2 BY R7.L (V , S);
 416 R3 = ASHIFT R3 BY R7.L (V , S);
 417 R4 = ASHIFT R4 BY R7.L (V , S);
 418 R5 = ASHIFT R5 BY R7.L (V , S);
 419 R6 = ASHIFT R6 BY R7.L (V , S);
 420 R7 = ASHIFT R7 BY R7.L (V , S);
 421 CHECKREG r0, 0x00000000;
 422 CHECKREG r1, 0x00000000;
 423 CHECKREG r2, 0x00000000;
 424 CHECKREG r3, 0x00000000;
 425 CHECKREG r4, 0x0000ffff;
 426 CHECKREG r5, 0x0000ffff;
 427 CHECKREG r6, 0x0000ffff;
 428 CHECKREG r7, 0x0000ffff;
 429
 430 pass