sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s

   1 //Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp
   2 # mach: bfin
   3
   4 .include "testutils.inc"
   5         start
   6
   7
   8 // Spec Reference: dsp32shiftimm ashift: ashift / ashift
   9
  10
  11
  12 imm32 r0, 0x01230abc;
  13 imm32 r1, 0x12345678;
  14 imm32 r2, 0x23456789;
  15 imm32 r3, 0x3456789a;
  16 imm32 r4, 0x456789ab;
  17 imm32 r5, 0x56789abc;
  18 imm32 r6, 0x6789abcd;
  19 imm32 r7, 0x789abcde;
  20 R0 = R0 << 0 (V);
  21 R1 = R1 << 3 (V);
  22 R2 = R2 << 5 (V);
  23 R3 = R3 << 8 (V);
  24 R4 = R4 << 9 (V);
  25 R5 = R5 << 15 (V);
  26 R6 = R6 << 7 (V);
  27 R7 = R7 << 13 (V);
  28 CHECKREG r0, 0x01230ABC;
  29 CHECKREG r1, 0x91A0B3C0;
  30 CHECKREG r2, 0x68A0F120;
  31 CHECKREG r3, 0x56009A00;
  32 CHECKREG r4, 0xCE005600;
  33 CHECKREG r5, 0x00000000;
  34 CHECKREG r6, 0xC480E680;
  35 CHECKREG r7, 0x4000C000;
  36
  37 imm32 r0, 0x01230000;
  38 imm32 r1, 0x12345678;
  39 imm32 r2, 0x23456789;
  40 imm32 r3, 0x3456789a;
  41 imm32 r4, 0x456789ab;
  42 imm32 r5, 0x56789abc;
  43 imm32 r6, 0x6789abcd;
  44 imm32 r7, 0x789abcde;
  45 R7 = R0 >>> 1 (V);
  46 R0 = R1 >>> 8 (V);
  47 R1 = R2 >>> 14 (V);
  48 R2 = R3 >>> 15 (V);
  49 R3 = R4 >>> 11 (V);
  50 R4 = R5 >>> 4 (V);
  51 R5 = R6 >>> 9 (V);
  52 R6 = R7 >>> 6 (V);
  53 CHECKREG r0, 0x00120056;
  54 CHECKREG r1, 0x00000001;
  55 CHECKREG r2, 0x00000000;
  56 CHECKREG r3, 0x0008FFF1;
  57 CHECKREG r4, 0x0567F9AB;
  58 CHECKREG r5, 0x0033FFD5;
  59 CHECKREG r6, 0x00020000;
  60 CHECKREG r7, 0x00910000;
  61
  62
  63
  64
  65 pass