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sim: bfin: import testsuite
[thirdparty/binutils-gdb.git] / sim / testsuite / sim / bfin / c_ptr2op_pr_neg_pr.s
1 //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp
2 // Spec Reference: ptr2op preg -= preg
3 # mach: bfin
4
5 .include "testutils.inc"
6 start
7
8 // check p-reg to p-reg move
9 imm32 p1, 0xf0021003;
10 imm32 p2, 0x2e041005;
11 imm32 p3, 0x20d61007;
12 imm32 p4, 0x200a1009;
13 imm32 p5, 0x200a300b;
14 imm32 sp, 0x200c180d;
15 imm32 fp, 0x200e109f;
16 P1 -= P1;
17 P2 -= P1;
18 P3 -= P1;
19 P4 -= P1;
20 P5 -= P1;
21 SP -= P1;
22 FP -= P1;
23 CHECKREG p1, 0x00000000;
24 CHECKREG p2, 0x2E041005;
25 CHECKREG p3, 0x20D61007;
26 CHECKREG p4, 0x200A1009;
27 CHECKREG p5, 0x200A300B;
28 CHECKREG sp, 0x200C180D;
29 CHECKREG fp, 0x200E109F;
30
31 imm32 p1, 0x50021003;
32 imm32 p2, 0x26041005;
33 imm32 p3, 0x20761007;
34 imm32 p4, 0x20081009;
35 imm32 p5, 0x200a900b;
36 imm32 sp, 0x200c1a0d;
37 imm32 fp, 0x200e10bf;
38 P1 -= P2;
39 P2 -= P2;
40 P3 -= P2;
41 P4 -= P2;
42 P5 -= P2;
43 SP -= P2;
44 FP -= P2;
45 CHECKREG p1, 0x29FDFFFE;
46 CHECKREG p2, 0x00000000;
47 CHECKREG p3, 0x20761007;
48 CHECKREG p4, 0x20081009;
49 CHECKREG p5, 0x200A900B;
50 CHECKREG sp, 0x200C1A0D;
51 CHECKREG fp, 0x200E10BF;
52
53 imm32 p1, 0x20021003;
54 imm32 p2, 0x20041005;
55 imm32 p3, 0x20061007;
56 imm32 p4, 0x20081009;
57 imm32 p5, 0x200a100b;
58 imm32 sp, 0x200c100d;
59 imm32 fp, 0x200e100f;
60 P1 -= P3;
61 P2 -= P3;
62 P3 -= P3;
63 P4 -= P3;
64 P5 -= P3;
65 SP -= P3;
66 FP -= P3;
67 CHECKREG p1, 0xFFFBFFFC;
68 CHECKREG p2, 0xFFFDFFFE;
69 CHECKREG p3, 0x00000000;
70 CHECKREG p4, 0x20081009;
71 CHECKREG p5, 0x200A100B;
72 CHECKREG sp, 0x200C100D;
73 CHECKREG fp, 0x200E100F;
74
75 imm32 p1, 0xa0021003;
76 imm32 p2, 0x2c041005;
77 imm32 p3, 0x20b61007;
78 imm32 p4, 0x200d1009;
79 imm32 p5, 0x200ae00b;
80 imm32 sp, 0x200c110d;
81 imm32 fp, 0x200e104f;
82 P1 -= P4;
83 P2 -= P4;
84 P3 -= P4;
85 P4 -= P4;
86 P5 -= P4;
87 SP -= P4;
88 FP -= P4;
89 CHECKREG p1, 0x7FF4FFFA;
90 CHECKREG p2, 0x0BF6FFFC;
91 CHECKREG p3, 0x00A8FFFE;
92 CHECKREG p4, 0x00000000;
93 CHECKREG p5, 0x200AE00B;
94 CHECKREG sp, 0x200C110D;
95 CHECKREG fp, 0x200E104F;
96
97 imm32 p1, 0x10021003;
98 imm32 p2, 0x22041005;
99 imm32 p3, 0x20361007;
100 imm32 p4, 0x20041009;
101 imm32 p5, 0x200aa00b;
102 imm32 sp, 0x200c1b0d;
103 imm32 fp, 0x200e10cf;
104 P1 -= P5;
105 P2 -= P5;
106 P3 -= P5;
107 P4 -= P5;
108 P5 -= P5;
109 SP -= P5;
110 FP -= P5;
111 CHECKREG p1, 0xEFF76FF8;
112 CHECKREG p2, 0x01F96FFA;
113 CHECKREG p3, 0x002B6FFC;
114 CHECKREG p4, 0xFFF96FFE;
115 CHECKREG p5, 0x00000000;
116 CHECKREG sp, 0x200C1B0D;
117 CHECKREG fp, 0x200E10CF;
118
119 imm32 p1, 0x20021003;
120 imm32 p2, 0x20041005;
121 imm32 p3, 0x20061007;
122 imm32 p4, 0x20081009;
123 imm32 p5, 0x200a100b;
124 imm32 sp, 0x200c100d;
125 imm32 fp, 0x200e100f;
126 P1 -= SP;
127 P2 -= SP;
128 P3 -= SP;
129 P4 -= SP;
130 P5 -= SP;
131 SP -= SP;
132 FP -= SP;
133 CHECKREG p1, 0xFFF5FFF6;
134 CHECKREG p2, 0xFFF7FFF8;
135 CHECKREG p3, 0xFFF9FFFA;
136 CHECKREG p4, 0xFFFBFFFC;
137 CHECKREG p5, 0xFFFDFFFE;
138 CHECKREG sp, 0x00000000;
139 CHECKREG fp, 0x200E100F;
140
141 imm32 p1, 0x20021003;
142 imm32 p2, 0x20041005;
143 imm32 p3, 0x20061007;
144 imm32 p4, 0x20081009;
145 imm32 p5, 0x200a100b;
146 imm32 sp, 0x200c100d;
147 imm32 fp, 0x200e100f;
148 P1 -= FP;
149 P2 -= FP;
150 P3 -= FP;
151 P4 -= FP;
152 P5 -= FP;
153 SP -= FP;
154 FP -= FP;
155 CHECKREG p1, 0xFFF3FFF4;
156 CHECKREG p2, 0xFFF5FFF6;
157 CHECKREG p3, 0xFFF7FFF8;
158 CHECKREG p4, 0xFFF9FFFA;
159 CHECKREG p5, 0xFFFBFFFC;
160 CHECKREG sp, 0xFFFDFFFE;
161 CHECKREG fp, 0x00000000;
162
163 pass