sim/testsuite/sim/bfin/c_regmv_dr_pr.s

   1 //Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp
   2 // Spec Reference: regmv dreg-to-preg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 // check R-reg to R-reg move
   9         imm32 r0, 0x20001001;
  10         imm32 r1, 0x20021003;
  11         imm32 r2, 0x20041005;
  12         imm32 r3, 0x20061007;
  13         imm32 r4, 0x20081009;
  14         imm32 r5, 0x200a100b;
  15         imm32 r6, 0x200c100d;
  16         imm32 r7, 0x200e100f;
  17
  18         P1 = R0;
  19         P2 = R0;
  20         P4 = R0;
  21         P5 = R0;
  22         FP = R0;
  23         CHECKREG p1, 0x20001001;
  24         CHECKREG p2, 0x20001001;
  25         CHECKREG p4, 0x20001001;
  26         CHECKREG p5, 0x20001001;
  27         CHECKREG fp, 0x20001001;
  28
  29         P1 = R1;
  30         P2 = R1;
  31         P4 = R1;
  32         P5 = R1;
  33         FP = R1;
  34         CHECKREG p1, 0x20021003;
  35         CHECKREG p2, 0x20021003;
  36         CHECKREG p4, 0x20021003;
  37         CHECKREG p5, 0x20021003;
  38         CHECKREG fp, 0x20021003;
  39
  40         P1 = R2;
  41         P2 = R2;
  42         P4 = R2;
  43         P5 = R2;
  44         FP = R2;
  45         CHECKREG p1, 0x20041005;
  46         CHECKREG p2, 0x20041005;
  47         CHECKREG p4, 0x20041005;
  48         CHECKREG p5, 0x20041005;
  49         CHECKREG fp, 0x20041005;
  50
  51         P1 = R3;
  52         P2 = R3;
  53         P4 = R3;
  54         P5 = R3;
  55         FP = R3;
  56         CHECKREG p1, 0x20061007;
  57         CHECKREG p2, 0x20061007;
  58         CHECKREG p4, 0x20061007;
  59         CHECKREG p5, 0x20061007;
  60         CHECKREG fp, 0x20061007;
  61
  62         P1 = R4;
  63         P2 = R4;
  64         P4 = R4;
  65         P5 = R4;
  66         FP = R4;
  67         CHECKREG p1, 0x20081009;
  68         CHECKREG p2, 0x20081009;
  69         CHECKREG p4, 0x20081009;
  70         CHECKREG p5, 0x20081009;
  71         CHECKREG fp, 0x20081009;
  72
  73         P1 = R5;
  74         P2 = R5;
  75         P4 = R5;
  76         P5 = R5;
  77         FP = R5;
  78         CHECKREG p1, 0x200a100b;
  79         CHECKREG p2, 0x200a100b;
  80         CHECKREG p4, 0x200a100b;
  81         CHECKREG p5, 0x200a100b;
  82         CHECKREG fp, 0x200a100b;
  83
  84         P1 = R6;
  85         P2 = R6;
  86         P4 = R6;
  87         P5 = R6;
  88         FP = R6;
  89         CHECKREG p1, 0x200c100d;
  90         CHECKREG p2, 0x200c100d;
  91         CHECKREG p4, 0x200c100d;
  92         CHECKREG p5, 0x200c100d;
  93         CHECKREG fp, 0x200c100d;
  94
  95         P1 = R7;
  96         P2 = R7;
  97         P4 = R7;
  98         P5 = R7;
  99         FP = R7;
 100         CHECKREG p1, 0x200e100f;
 101         CHECKREG p2, 0x200e100f;
 102         CHECKREG p4, 0x200e100f;
 103         CHECKREG p5, 0x200e100f;
 104         CHECKREG fp, 0x200e100f;
 105
 106 End:
 107         pass