sim/testsuite/sim/bfin/cec-multi-pending.S

   1 # Blackfin testcase for multiple pending IVGs vs masked state
   2 # mach: bfin
   3 # sim: --environment operating
   4
   5 #include "test.h"
   6         .include "testutils.inc"
   7
   8         # This test keeps P5 as the base of the EVT table
   9
  10         .macro set_evt lvl:req, sym:req
  11         loadsym R1, \sym;
  12         [P5 + 4 * \lvl\()] = R1;
  13         .endm
  14
  15         .macro check_cec mmr:req, valid:req
  16         imm32 P3, \mmr;
  17         R0 = [P3];
  18         R1 = ~0x1f;
  19         R0 = R0 & R1;
  20         imm32 R1, \valid;
  21         CC = R1 == R0;
  22         IF CC JUMP 1f;
  23         dbg_fail
  24 1:
  25         .endm
  26
  27         .macro delay cnt:req
  28         imm32 P2, \cnt
  29         LSETUP (1f, 1f) LC1 = P2;
  30 1:      mnop;
  31         .endm
  32
  33         start
  34
  35         # First mark all EVTs as fails (they shouldn't be activated)
  36         imm32 P5, EVT0;
  37         P1 = P5;
  38         loadsym R1, fail_lvl
  39         imm32 P2, 16
  40         LSETUP (1f, 1f) LC0 = P2;
  41 1:      [P1++] = R1;
  42
  43         # Lower ourselves to EVT15
  44         set_evt 15, evt15;
  45         R7 = 0 (x);
  46         BITSET (R7, 15);
  47         sti R7;
  48         loadsym R1, wait;
  49         RETI = R1;
  50         RAISE 15;
  51         RTI;
  52
  53 wait:
  54         jump wait;
  55
  56 evt15:
  57         # We shouldn't come back here
  58         set_evt 15, fail_lvl;
  59
  60         # Activate interrupt nesting early
  61         [--SP] = RETI;
  62
  63         # Raise some higher levels, but they should be masked and so
  64         # they should never be activated ...
  65         RAISE 6;
  66         RAISE 5;
  67         RAISE 9;
  68         RAISE 12;
  69
  70         # Only IVG15 should be pending
  71         check_cec IPEND, (1<<15);
  72
  73         # But all should be latched
  74         check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<12);
  75
  76         # Delay a little in case a higher level wrongly activates
  77         delay 30
  78
  79         # If we're still here, things are still good.  So let's
  80         # transition up *slightly*, but not to the highest latched.
  81         set_evt 12, evt12;
  82         cli R7;
  83         BITSET (R7, 12);
  84         sti R7;
  85
  86         # Let CEC raise us to IVG12
  87         delay 30
  88         # CEC should have been faster than this ...
  89         dbg_fail
  90
  91 evt12:
  92         # We shouldn't come back here
  93         set_evt 12, fail_lvl;
  94
  95         # Raise some higher levels, but they should be masked and so
  96         # they should never be activated ...
  97         RAISE 11;
  98
  99         # Both IVG15 and IVG12 should be pending
 100         check_cec IPEND, (1<<15) | (1<<12);
 101
 102         # But all should be latched
 103         check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<11);
 104
 105         # Activate interrupt nesting a little later
 106         [--SP] = RETI;
 107
 108         # Still here, so unmask a higher IVG again to move up
 109         set_evt 9, evt9;
 110         cli R7;
 111         BITSET (R7, 9);
 112         sti R7;
 113         delay 30
 114
 115         # CEC should have been faster than this ...
 116         dbg_fail
 117
 118 evt9:
 119         # We shouldn't come back here
 120         set_evt 9, fail_lvl;
 121
 122         # IVG9 should also be pending now
 123         check_cec IPEND, (1<<15) | (1<<12) | (1<<9);
 124
 125         # But all should be latched
 126         check_cec ILAT, (1<<5) | (1<<6) | (1<<11);
 127
 128         # Unmask the next level, but IPEND[4] is set, so we should stay here
 129         set_evt 6, evt6;
 130         cli R7;
 131         BITSET (R7, 6);
 132         sti R7;
 133
 134         # Delay a little in case a higher level wrongly activates
 135         delay 30
 136
 137         # Good, now unmask things globally
 138         [--SP] = RETI;
 139         delay 30
 140
 141         # CEC should have been faster than this ...
 142         dbg_fail
 143
 144 evt6:
 145         # We shouldn't come back here
 146         set_evt 6, fail_lvl;
 147
 148         # IVG6 should also be pending now
 149         check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6);
 150
 151         # But all should be latched
 152         check_cec ILAT, (1<<5) | (1<<11);
 153
 154         # Activate interrupt nesting a little later
 155         [--SP] = RETI;
 156
 157         # Unmask the next level, but do it via IMASK
 158         set_evt 5, evt5;
 159         imm32 P2, IMASK;
 160         R7 = [P2];
 161         BITSET (R7, 5);
 162         [P2] = R7;
 163         delay 30
 164
 165         # CEC should have been faster than this ...
 166         dbg_fail
 167
 168 evt5:
 169         # We shouldn't come back here
 170         set_evt 5, fail_lvl;
 171
 172         # IVG5 should also be pending now
 173         check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<5);
 174
 175         # But all should be latched
 176         check_cec ILAT, (1<<11);
 177
 178         # All good!
 179         dbg_pass;
 180
 181 fail_lvl:
 182         dbg_fail;