sim/testsuite/sim/bfin/hwloop-branch-in.s

   1 # Blackfin testcase for branching into the middle of a hardware loop
   2 # mach: bfin
   3
   4         .include "testutils.inc"
   5
   6         .macro test_prep lc:req
   7         loadsym P5, 1f;
   8         dmm32 LC0, \lc
   9         R5 = 0;
  10         R6 = 0;
  11         R7 = 0;
  12         .endm
  13
  14         .macro test_check exp5:req, exp6:req, exp7:req, expLC:req
  15 1:
  16         imm32 R4, \exp5;
  17         CC = R4 == R5;
  18         IF !CC JUMP 2f;
  19         imm32 R4, \exp6;
  20         CC = R4 == R6;
  21         IF !CC JUMP 2f;
  22         imm32 R4, \exp7;
  23         CC = R4 == R7;
  24         IF !CC JUMP 2f;
  25         R3 = LC0;
  26         imm32 R4, \expLC;
  27         CC = R4 == R3;
  28         IF !CC JUMP 2f;
  29         JUMP 3f;
  30 2:      fail
  31 3:
  32         .endm
  33
  34         .macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
  35         loadsym R1, \entry;
  36         RETS = R1;
  37         test_prep \lc
  38         RTS;
  39         test_check \exp5, \exp6, \exp7, \expLC
  40         .endm
  41
  42         .macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
  43         loadsym P1, \entry;
  44         test_prep \lc
  45         JUMP (P1);
  46         test_check \exp5, \exp6, \exp7, \expLC
  47         .endm
  48
  49         start
  50
  51         loadsym R1, hws;
  52         LT0 = R1;
  53         loadsym R1, hwe;
  54         LB0 = R1;
  55
  56         test_rts hws, 0, 1, 1, 1, 0
  57         test_rts hws, 1, 1, 1, 1, 0
  58         test_rts hws, 2, 2, 2, 2, 0
  59         test_rts hws, 20, 20, 20, 20, 0
  60
  61         test_rts hwm, 0, 0, 1, 1, 0
  62         test_rts hwm, 1, 0, 1, 1, 0
  63         test_rts hwm, 2, 1, 2, 2, 0
  64         test_rts hwm, 20, 19, 20, 20, 0
  65
  66         test_rts hwe, 0, 0, 0, 1, 0
  67         test_rts hwe, 1, 0, 0, 1, 0
  68         test_rts hwe, 2, 1, 1, 2, 0
  69         test_rts hwe, 20, 19, 19, 20, 0
  70
  71         test_rts hwp, 0, 0, 0, 0, 0
  72         test_rts hwp, 1, 0, 0, 0, 1
  73         test_rts hwp, 2, 0, 0, 0, 2
  74
  75         test_jump hws, 0, 1, 1, 1, 0
  76         test_jump hws, 1, 1, 1, 1, 0
  77         test_jump hws, 2, 2, 2, 2, 0
  78         test_jump hws, 20, 20, 20, 20, 0
  79
  80         test_jump hwm, 0, 0, 1, 1, 0
  81         test_jump hwm, 1, 0, 1, 1, 0
  82         test_jump hwm, 2, 1, 2, 2, 0
  83         test_jump hwm, 20, 19, 20, 20, 0
  84
  85         test_jump hwe, 0, 0, 0, 1, 0
  86         test_jump hwe, 1, 0, 0, 1, 0
  87         test_jump hwe, 2, 1, 1, 2, 0
  88         test_jump hwe, 20, 19, 19, 20, 0
  89
  90         test_jump hwp, 0, 0, 0, 0, 0
  91         test_jump hwp, 1, 0, 0, 0, 1
  92         test_jump hwp, 2, 0, 0, 0, 2
  93
  94         pass
  95
  96 hws:    R5 += 1;
  97 hwm:    R6 += 1;
  98 hwe:    R7 += 1;
  99 hwp:    JUMP (P5);