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* interp.c (do_format_3): Get operands correctly and call
[thirdparty/binutils-gdb.git] / sim / v850 / ChangeLog
1 Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
2
3 * interp.c (do_format_3): Get operands correctly and call
4 the target function.
5 * simops.c: Handle bCC instructions.
6
7 * simops.c: Add condition code handling to shift insns.
8 Fix minor typos in condition code handling for other insns.
9
10 * Makefile.in: Fix typo.
11 * simops.c: Add condition code handling to "sub" "subr" and
12 "divh" instructions.
13
14 * interp.c (hash): Update to be more accurate.
15 (lookup_hash): Call hash rather than computing the hash
16 code here.
17 (do_format_1_2): Handle format 1 and format 2 instructions.
18 Get operands correctly and call the target function.
19 (do_format_6): Get operands correctly and call the target
20 function.
21 (do_formats_9_10): Rough cut so shift ops will work.
22 (sim_resume): Tweak to deal with format 1 and format 2
23 handling in a single funtion. Don't update the PC
24 for format 3 insns. Fix typos.
25 * simops.c: Slightly reorganize. Add condition code handling
26 to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
27 and "not" instructions.
28 * v850_sim.h (reg_t): Registers are 32bits.
29 (_state): The V850 has 32 general registers. Add a 32bit
30 psw and pc register too. Add accessor macros
31
32 * Makefile.in, interp.c, v850_sim.h: Bring over endianness
33 changes from the d10v simulator.
34
35 * simops.c: Add shift support.
36
37 * simops.c: Add multiply & divide support. Abort for system
38 instructions.
39
40 * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
41 and subr. No condition codes yet.
42
43 Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
44
45 * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
46 gencode.c, interp.c, simops.c: Created.
47